EVB-LAN9354
Evaluation Board
User’s Guide
2015 Microchip Technology Inc.
DS50002394A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck,
MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and
UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK,
MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial
Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-588-7
QUALITYMANAGEMENTSYSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS50002394A-page 2
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2015 Microchip Technology Inc.
EVB-LAN9354 Evaluation Board User’s Guide
Object of Declaration: EVB-LAN9354
2015 Microchip Technology Inc.
DS50002394A-page 3
EVB-LAN9354 Evaluation Board User’s Guide
NOTES:
2015 Microchip Technology Inc.
DS50002394A-page 4
EVB-LAN9354
EVALUATION BOARD
USER’S GUIDE
Table of Contents
Preface ........................................................................................................................... 7
Introduction............................................................................................................ 7
Document Layout .................................................................................................. 7
Conventions Used in this Guide ............................................................................ 8
The Microchip Web Site ........................................................................................ 9
Development Systems Customer Change Notification Service ............................ 9
Customer Support ................................................................................................. 9
Document Revision History ................................................................................. 10
Chapter 1. Overview
1.1 Introduction ................................................................................................... 11
1.1.1 References ................................................................................................ 12
1.1.2 Terms and Abbreviations .......................................................................... 12
Chapter 2. Board Details
2.1 Board Details ................................................................................................ 14
2.1.1 Power ........................................................................................................ 14
2.1.2 Power-on Reset ......................................................................................... 15
2.1.3 Clock .......................................................................................................... 15
Chapter 3. Board Configuration
3.1 Strap Options ............................................................................................... 16
3.1.1 Jumpers J4:J15 ......................................................................................... 16
3.1.1.1 GPIO/LED POL/LED Configurations ......................................... 17
3.1.1.2 Serial Management Mode Configuration ................................... 18
3.1.1.3 EEPROM Size Configuration ..................................................... 18
3.1.1.4 Energy-Efficient Ethernet Configuration .................................... 18
3.1.1.5 1588 Enable Configuration ........................................................ 19
3.1.1.6 PHY Address Configuration ....................................................... 19
3.1.2 GPIO 6 & GPIO 7 Input and Output Configurations .................................. 19
3.1.3 Link Partner Duplex/Speed Configurations ............................................... 19
3.1.4 P0 Configurations ...................................................................................... 20
3.1.5 RMII RX Clock Configurations ................................................................... 20
3.1.6 GPIO Header ............................................................................................. 21
3.1.7 I2C Aardvark Header ................................................................................. 21
3.1.8 Copper and Fiber Mode Selections ........................................................... 21
3.1.8.1 Copper Mode ............................................................................. 23
3.1.8.2 Fiber Mode ................................................................................ 22
3.1.8.3 FX-LOS Fiber Mode Strap ......................................................... 23
3.2 LEDs ............................................................................................................. 23
3.3 Test Points ................................................................................................... 23
3.4 Mechanicals ................................................................................................. 24
2015 Microchip Technology Inc.
DS50002394A-page 5
EVB-LAN9354 Evaluation Board User’s Guide
Appendix A. EVB-LAN9354 Evaluation Board
A.1 Introduction .................................................................................................. 25
Appendix B. EVB-LAN9354 Evaluation Board Schematics
B.1 Introduction .................................................................................................. 26
Appendix C. Bill of Materials (BOM)
C.1 Introduction .................................................................................................. 34
Wordwide Sales and Service ......................................................................................38
DS50002394A-page 6
2015 Microchip Technology Inc.
EVB-LAN9354
EVALUATION BOARD
USER’S GUIDE
Preface
NOTICE TO CUSTOMERS
All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our web site
(www.microchip.com) to obtain the latest documentation available.
Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the
document.
For the most up-to-date information on development tools, see the MPLAB® IDE online help.
Select the Help menu, and then Topics to open a list of available online help files.
INTRODUCTION
This chapter contains general information that will be useful to know before using the
EVB-LAN9354. Items discussed in this chapter include:
•
•
•
•
•
•
Document Layout
Conventions Used in this Guide
The Microchip Web Site
Development Systems Customer Change Notification Service
Customer Support
Document Revision History
DOCUMENT LAYOUT
This document describes how to use the EVB-LAN9354 Evaluation Board as a
development tool for the LAN9354 three-port 10/100 managed Ethernet switch. The
manual layout is as follows:
• Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9354 Evaluation Board.
• Chapter 2. “Getting Started” – Includes instructions on how to get started with
the EVB-LAN9354 Evaluation Board.
• Chapter 3. “Board Configuration” – Provides information about the
EVB-LAN9354 Evaluation Board battery charging features.
• Appendix A. “EVB-LAN9354 Evaluation Board” – This appendix shows the
EVB-LAN9354 Evaluation Board.
• Appendix B. “EVB-LAN9354 Evaluation Board Schematics” – This appendix
shows the EVB-LAN9354 Evaluation Board schematics.
• Appendix C. “Bill of Materials (BOM)” – This appendix includes the
EVB-LAN9354 Evaluation Board Bill of Materials (BOM).
2015 Microchip Technology Inc.
DS50002394A-page 7
EVB-LAN9354 Evaluation Board User’s Guide
CONVENTIONS USED IN THIS GUIDE
This manual uses the following documentation conventions:
DOCUMENTATION CONVENTIONS
Description
Arial font:
Italic characters
Represents
Referenced books
Emphasized text
A window
A dialog
A menu selection
A field name in a window or
dialog
A menu path
MPLAB® IDE User’s Guide
...is the only compiler...
the Output window
the Settings dialog
select Enable Programmer
“Save project before build”
A dialog button
A tab
A number in verilog format,
where N is the total number of
digits, R is the radix and n is a
digit.
A key on the keyboard
Click OK
Click the Power tab
4‘b0010, 2‘hF1
Italic Courier New
Sample source code
Filenames
File paths
Keywords
Command-line options
Bit values
Constants
A variable argument
Square brackets [ ]
Optional arguments
Curly brackets and pipe
character: { | }
Ellipses...
Choice of mutually exclusive
arguments; an OR selection
Replaces repeated text
#define START
autoexec.bat
c:\mcc18\h
_asm, _endasm, static
-Opa+, -Opa0, 1
0xFF, ‘A’
file.o, where file can be
any valid filename
mcc18 [options] file
[options]
errorlevel {0|1}
Initial caps
Quotes
Underlined, italic text with
right angle bracket
Bold characters
N‘Rnnnn
Text in angle brackets < >
Courier New font:
Plain Courier New
Represents code supplied by
user
DS50002394A-page 8
Examples
File>Save
Press <Enter>, <F1>
var_name [,
var_name...]
void main (void)
{ ...
}
2015 Microchip Technology Inc.
Preface
THE MICROCHIP WEB SITE
Microchip provides online support via our web site at www.microchip.com. This web
site is used as a means to make files and information easily available to customers.
Accessible by using your favorite Internet browser, the web site contains the following
information:
• Product Support – Data sheets and errata, application notes and sample
programs, design resources, user’s guides and hardware support documents,
latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical
support requests, online discussion groups, Microchip consultant program
member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip
press releases, listing of seminars and events, listings of Microchip sales offices,
distributors and factory representatives
DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip
products. Subscribers will receive e-mail notification whenever there are changes,
updates, revisions or errata related to a specified product family or development tool of
interest.
To register, access the Microchip web site at www.microchip.com, click on Customer
Change Notification and follow the registration instructions.
The Development Systems product group categories are:
• Compilers – The latest information on Microchip C compilers, assemblers, linkers
and other language tools. These include all MPLAB C compilers; all MPLAB
assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK
object linker); and all MPLAB librarians (including MPLIB object librarian).
• Emulators – The latest information on Microchip in-circuit emulators.This
includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators.
• In-Circuit Debuggers – The latest information on the Microchip in-circuit
debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug
express.
• MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows
Integrated Development Environment for development systems tools. This list is
focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and
MPLAB SIM simulator, as well as general editing and debugging features.
• Programmers – The latest information on Microchip programmers. These include
production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB
ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included
are nonproduction development programmers such as PICSTART Plus and
PIC-kit 2 and 3.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
2015 Microchip Technology Inc.
DS50002394A-page 9
EVB-LAN9354 Evaluation Board User’s Guide
Customers should contact their distributor, representative or field application engineer
(FAE) for support. Local sales offices are also available to help customers. A listing of
sales offices and locations is included in the back of this document.
Technical support is available through the web site at:
http://www.microchip.com/support
DOCUMENT REVISION HISTORY
Revision A (July 2015)
• Initial Release of this Document.
DS50002394A-page 10
2015 Microchip Technology Inc.
EVB-LAN9354
EVALUATION BOARD
USER’S GUIDE
Chapter 1. Overview
1.1
INTRODUCTION
The LAN9354 is a fully featured, three-port 10/100 managed Ethernet switch designed
for industrial and embedded applications where performance, flexibility, ease of integration and system cost control are required.
The LAN9354 combines all the functions of a 10/100 switch system, including the
switch fabric, packet buffers, buffer manager, media access controllers (MACs), PHY
transceivers, and serial management. IEEE 1588v2 is supported via the integrated
IEEE 1588v2 hard-ware time stamp unit, which supports end-to-end and peer-to-peer
transparent clocks.
The LAN9354 complies with the IEEE 802.3 (full/half-duplex 10BASE-T and
100BASE-TX) Ethernet protocol, IEEE 802.3az Energy Efficient Ethernet (EEE)
(100Mbps only), and 802.1D/802.1Q management protocol specifications, enabling
compatibility with industry standard Ethernet and Fast Ethernet applications.
100BASE-FX is supported via an external fiber transceiver and cable diagnostics
(short, open and length) is included on the internal twisted pair copper interface.
The EVB-LAN9354 is an Evaluation Board (EVB) that utilizes the LAN9354 to provide
a fully-functional three-port Ethernet switch with Single RMII. The EVB-LAN9354 provides two fully integrated MAC/PHY internet ports (Ports 1 & 2) via on-board RJ45 connectors. Port 0 provides two MII port connectors which support the following:
• An external RMII-Capable MAC (with LAN9354 in PHY mode), via the on-board
40-pin male MII connector
• An external RMII-Capable PHY (with LAN9354 in MAC mode), via the on-board
40-pin female MII connector
Power is supplied to the board via a +5V external wall mount power supply.
The EVB-LAN9354 includes a 64K x 8 I2C EEPROM that may be used to automatically
load configuration settings from the EEPROM into the device at reset. An I2C host
adapter interface header (10-pin, 2x5) is provided to simplify I2C based configuration.
A simplified block diagram of the EVB-LAN9354 can be seen in Figure 1-1.
2015 Microchip Technology Inc.
DS50002394A-page 11
EVB-LAN9354 Evaluation Board User’s Guide
FIGURE 1-1:
EVB-LAN9354 BLOCK DIAGRAM
To External
PHY
To External
MAC
40 pin MII
Connector
(Female)
40 pin MII
Connector
(Male)
RMII
Port 0
Mode
Switch
Microchip
LAN9354
I2C EEPROM
Straps
Jumpers
Fiber
Transceiver
(SFP)
5V
Reset
Crystal
Port 1
Port 2
10/100
Ethernet
Magnetics &
RJ45
10/100
Ethernet
Magnetics &
RJ45
Ethernet
1.1.1
Power Supply
Module
Fiber
Transceiver
(SFP)
Ethernet
References
Concepts and material available in the following documents may be helpful when reading this document. Visit www.microchip.com for the latest documentation.
Document
LAN9354 datasheet
Location
Visit www.microchip.com
AN8-13 Suggested Mag- http://www.microchip.com/wwwApnetics
pNotes/AppNotes.aspx?appnote=en562793
EVB-LAN9354 Evaluation Board Schematic
DS50002394A-page 12
Visit www.microchip.com
2015 Microchip Technology Inc.
1.1.2
•
•
•
•
•
•
•
•
•
•
Terms and Abbreviations
EVB - Evaluation Board
DNP - Do Not Populate
100BASE-TX - 100 Mbps Fast Ethernet, IEEE802.3u Compliant
GPIO - General Purpose I/O
MII - Media Independent Interface
RMII - Reduced Media Independent Interface
EEE - Energy-Efficient Ethernet
SFP - Small Form-factor Pluggable
SFF - Small Form Factor
SMI - Serial Management Interface
2015 Microchip Technology Inc.
DS50002394A-page 13
EVB-LAN9354
EVALUATION BOARD
USER’S GUIDE
Chapter 2. Board Details
2.1
BOARD DETAILS
The following sections describe the various board features, including jumpers, LEDs,
test points, system connections, and switches. A top view of the EVB-LAN9354 is
shown in Figure 2-1.
FIGURE 2-1:
LAN9354 BOARD REV-A
Port 0 (Female)
MII Connector
Port 0 (Male)
MII Connector
EEPROM
Power
Strap
Reset
Microchip
LAN9354
Mode Switch
Port 1
(with integrated
magnetics & LEDs)
2.1.1
Port 2
(with integrated
magnetics & LEDs)
Power
DC 5V is applied through (J1) DC Socket, powered by a +5V external wall adapter
switch (SW1) need to be ON position for the 5V to reach the 3.3V regulator. Glowing of
Green LED (D1) indicates successful generation of 3.3V o/p. This Power is supplied to
the LAN9354 and it has internal 1.2 V regulator which supplies power to the internal
core logic.
2015 Microchip Technology Inc.
DS50002394A-page 14
EVB-LAN9354 Evaluation Board User’s Guide
2.1.2
Power-on Reset
A power-on reset occurs whenever power is initially applied to the LAN9354 or if the
power is removed and reapplied to the LAN9354. This event resets all circuitry within
the LAN9354. After initial power-on, the LAN9354 can be reset by pressing the reset
switch (SW2). The reset LED D2 will assert (red) when the LAN9354 is in reset condition.
For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset
release.
2.1.3
Clock
The LAN9354 requires a fixed-frequency 25 MHz clock (±50 ppm) source for use by
the internal clock oscillator and PLL. This is typically provided by attaching a 25 MHz
crystal to the OSCI and OSCO pins. Optionally, this clock can be provided by driving
the OSCI input pin with a single-ended 25 MHz clock source.
DS50002394A-page 15
2015 Microchip Technology Inc.
EVB-LAN9354
EVALUATION BOARD
USER’S GUIDE
Chapter 3. Board Configuration
3.1
STRAP OPTIONS
The following tables describe the default settings and jumper descriptions for the
EVB-LAN9354. These defaults are the recommended configurations for evaluation of
the LAN9354. These settings may be changed as needed, however, any deviation from
the defaults settings should be approached with care and knowledge of the schematics
and datasheet. An incorrect jumper setting may disable the board.
3.1.1
Jumpers J4:J15
Jumpers J4 through J15 set various functions of the LAN9354. They can also be used
as GPIOs, LED drivers. When used as LED drivers, as they are on the EVB-LAN9354,
they are connected a specific way to set the strap value to a “1”, and another way to
set the strap value to a “0”. Figure 3-1 illustrates the schematics connections with the
D3 circuit as a pull-up, and the D4 circuit as a pull-down. To illuminate D3, the LAN9354
will drive the cathode of the D3 low. To illuminate D4, the LAN9354 will drive the cathode of the D4 high.
The J4 - J15 jumpers must be configured in pairs to identical settings in order to realize
the D3 circuit or the D4 circuit. The pairings are as follows:
-
J4 & J7
J6 & J9
J5 & J8
J11 & J14
J10 & J13
J12 & J15
The following subsections detail the jumper pair settings, their associated strap settings, and the functional effects of setting the straps. All strap values are read during
power-up and on the rising edge of nRST signal. Once the strap value is set, the
LAN9354 will drive the LED’s high or low for illumination according the strap value. For
other designs which may use these pins as GPIOs refer to LAN9354 datasheet for
additional information. In those cases, internal default straps must be changed by an
I2C or SMI master or through EEPROM fields.
2015 Microchip Technology Inc.
DS50002394A-page 16
EVB-LAN9354 Evaluation Board User’s Guide
FIGURE 3-1:
3.1.1.1
LED STRAP CIRCUIT
GPIO/LED POL/LED CONFIGURATIONS:
GPIO/LED POL/LED configuration straps are used to configure the default polarity of
LEDs, GPIOs through jumpers as shown below in Table 3-1.
TABLE 3-1:
GPIO/LED POL/LED CONFIGURATIONS
Header
Pin Settings
Signal Name
Strap Value
Description
J4 & J7
1-2(default)
LEDPOL0
/GPIO0
/LED0
1
The LED (D3) is
set as active
LOW.
0
The LED (D3) is
set as active
HIGH.
1
The LED (D4) is
set as active
LOW.
0
The LED (D4) is
set as active
HIGH.
1
The LED (D5) is
set as active
LOW.
0
The LED (D5) is
set as active
HIGH.
1
The LED (D6) is
set as active
LOW.
0
The LED (D6) is
set as active
HIGH.
2 -3
J5 & J8
1-2(default)
LEDPOL1
/GPIO1
/LED1
2 -3
J6 & J9
1-2(default)
LEDPOL2
/GPIO2
/LED2
2 -3
J10 & J13
1-2(default)
2 -3
DS50002394A-page 17
LEDPOL3
/GPIO3
/LED3
2015 Microchip Technology Inc.
TABLE 3-1:
GPIO/LED POL/LED CONFIGURATIONS (CONTINUED)
Header
Pin Settings
Signal Name
Strap Value
Description
J11 & J14
1-2(default)
LEDPOL4
/GPIO4
/LED4
1
The LED (D7) is
set as active
LOW.
0
The LED (D7) is
set as active
HIGH.
1
The LED (D8) is
set as active
LOW.
0
The LED (D8) is
set as active
HIGH.
2 -3
J12 & J15
1-2(default)
LEDPOL5
/GPIO5
/LED5
2 -3
3.1.1.2
SERIAL MANAGEMENT MODE CONFIGURATION
Serial Management Mode selection strap is used to configure the default value of the
Serial Management Mode Strap hard-strap (serial_mngt_mode_strap) through jumpers as shown below in Table 3-2.
TABLE 3-2:
Header
3.1.1.3
SERIAL MANAGEMENT MODE CONFIGURATION
Pin Settings
serial_mngt_mode_
strap
Description
J4 & J7
2-3
0
SMI Managed Mode
J4 & J7
1-2 (default)
1
I2C Managed Mode
EEPROM SIZE CONFIGURATION:
The EEPROM size configuration strap (J6 & J9) determines the supported EEPROM
size range. A low selects 1Kbits (128 x 8) through 16Kbits (2K x 8)_24C16. A high
selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512 as
shown below in Table 3-3.
TABLE 3-3:
3.1.1.4
EEPROM SIZE CONFIGURATION
Header
Pin Settings
eeprom_size_strap
Value
J6 & J9
1-2 (default)
1
EEPROM size = 32K
bits (4k x 8) through
512K bits (64K x 8)
2 -3
0
EEPROM size = 1K
bits (128 x 8) through
16K bits (2K x 8)
Description
ENERGY-EFFICIENT ETHERNET CONFIGURATION
EEE_EN configuration strap is used to configure the default value of the EEE Enable
2-1 soft-straps (EEE_enable_strap_[2:1]) through jumpers as shown below in
Table 3-4.
TABLE 3-4:
EEE_EN CONFIGURATION
Header
Pin Settings
EEE_enable_strap_[
2:1] Value
J10 & J13
1-2(default)
1
EEE Enable
2 -3
0
EEE Disable
2015 Microchip Technology Inc.
Description
DS50002394A-page 18
EVB-LAN9354 Evaluation Board User’s Guide
3.1.1.5
1588 ENABLE CONFIGURATION
Energy Efficient Ethernet configuration strap is used to configure the default value of
the 1588 Enable soft-strap (1588_enable_strap) through jumpers as shown below in
Table 3-5.
TABLE 3-5:
1588 ENABLE CONFIGURATION
Header
Pin Settings
1588_enable_strap
Value
J11 & J14
1-2 (default)
1
1588 Enable
2 -3
0
1588 Disable
3.1.1.6
Description
PHY ADDRESS CONFIGURATION
PHY Address selection strap is used to configure the default value of the Switch PHY
Address Select soft-strap (phy_addr_sel_strap) through jumpers as shown below in
Table 3-6.
TABLE 3-6:
PHY ADDRESSING
VIRTUAL
PHY 0 AND 1
PHY_ADDR_SEL
DEFAULT
_STRAP Value
ADDRESS
VALUE
PHY A
DEFAULT
ADDRESS
VALUE
PHY B
DEFAULT
ADDRESS
VALUE
Header
Pin
Settings
J12 & J15
1-2
1
1
2
3
2-3 (default)
0
0
1
2
3.1.2
GPIO 6 & GPIO 7 Input and Output Configurations
GPIO 6 & 7 configuration straps are used to configure the default input value of the
GPIO 6 and 7 through jumpers as shown below in Table 3-7 and Table 3-8.
TABLE 3-7:
Header
Pin Settings
Input
Signal Name
J16
1-2
1
GPIO6
J17
TABLE 3-8:
2-3
0
1-2
1
2-3
0
GPIO7
GPIO 6 & 7 OUTPUT CONFIGURATION
Header
Pin
Output
Signal Name
J16
2
Push Pull
GPIO6
J17
2
Push Pull
GPIO7
Note:
3.1.3
GPIO 6 & 7 INPUT CONFIGURATION
By default, the jumpers settings for J16 & J17 will be OPEN.
Link Partner Duplex/Speed Configurations
The “duplex_strap_0” strap is used to determine the link partners duplex ability when
in Port 0 RMII MAC mode through jumpers (J22) as shown below in Table 3-9.
DS50002394A-page 19
2015 Microchip Technology Inc.
The “speed_strap_0” strap is used to determine the link partners speed ability and to
determine the parallel detect speed when in Port 0 RMII MAC mode through jumpers
(J23) as shown below in Table 3-9.
TABLE 3-9:
J28
(P0_DUPLEX)
EMULATED LINK PARTNER DEFAULT ADVERTISED ABILITY
FOR PORT 0
J23 (P0_SPEED) duplex_strap_0
speed_strap_0
ADVERTISED
LINK PARTNER
ABILITY
1-2
2-3
1
0
10BASE-T
full-duplex
(0010)
1-2
1-2
1
1
100BASE-X
full-duplex
(1000)
2-3
2-3
0
0
10BASE-T
half-duplex
(0001)
2-3
1-2
0
1
100BASE-X
half-duplex
(0100)
Note:
3.1.4
By default, the jumpers settings for J22 & J23 will be OPEN.
Port 0 Mode Configurations
Port 0 Mode configuration straps from switches (SW3, SW4 & SW5) are used to configure the hard-straps such as Switch Port 0 Mode Strap (P0_mode_strap[1:0]), Switch
Port 0 RMII Clock Direction Strap (P0_rmii_clock_dir_strap) and Switch Port 0 Clock
Strength Strap (P0_clock_strength_strap) as shown in Table 3-10.
TABLE 3-10:
PORT 0 MODE STRAP MAPPING
P0_MODE2 (SW5)
P0_MODE1 (SW4)
P0_MODE0 (SW3)
1-3
1-3
X
1-3
1-2
1-3
RMII MAC clock out
12ma
1-3
1-2
1-2
RMII MAC clock out
16ma (Default)
1-2
1-3
X
1-2
1-2
1-3
RMII PHY clock out
12ma
1-2
1-2
1-2
RMII PHY clock out
16ma
Note:
3.1.5
MODE
RMII MAC clock in
RMII PHY clock in
For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
RMII RX Clock Configurations
When LAN9354 is in MAC/PHY mode the reference clock routed either through TX or
RX Clock as shown in Table 3-11 for Port 0.
TABLE 3-11:
RX CLOCK CONFIGURATIONS FOR PORT 0
Switch Settings
SW6 (1-3) (Default)
2015 Microchip Technology Inc.
DESCRIPTION
TX Clock used as a Reference Clock
Mode
RMII MAC
DS50002394A-page 20
EVB-LAN9354 Evaluation Board User’s Guide
TABLE 3-11:
RX CLOCK CONFIGURATIONS FOR PORT 0
Switch Settings
DESCRIPTION
Mode
SW6 (1-2)
RX Clock used as a Reference Clock
SW7 (1-3) (Default)
Reference clock used as a TX RMII PHY
clock
SW7 (1-2)
Reference clock used as a RX RMII PHY
clock
Note:
For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
3.1.6
RMII MAC
GPIO Header
J18 connector is used for GPIO header. Respective pin details are given below in
Table 3-12.
TABLE 3-12:
3.1.7
PIN NAMES FOR GPIO HEADER
Signal Name
Pin Number
GPIO0
J18.1
GPIO1
J18.2
GPIO2
J18.3
GPIO3
J18.4
GPIO4
J18.5
GPIO5
J18.6
GPIO6
J18.7
GPIO7
J18.8
I2C Aardvark® Header
J21 connector is used for I2C Aardvark header. Respective pin details are given below
in Table 3-13.
TABLE 3-13:
3.1.8
PIN NAMES FOR I2C AARDVARK HEADER
Signal Name
Pin Number
I2C2_SCL
J21.1
I2C2_SDA
J21.3
GND
J21.2 & J21.10
Copper and Fiber Mode Selections
The LAN9354 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In
100BASE-FX operation, the presence of the receive signal is indicated by the external
transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL
Signal Detect (SFF).
This EVB supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) in SFP mode. By
default Copper Mode is active. Fiber Mode is supported as an assembly option. To
select the Copper or Fiber Mode, the respective strap and signal routing resister
assembly options must to be configured.
Note:
DS50002394A-page 21
Vendor part number for SFP Transceiver: Finisar/FTLF1217P2.
2015 Microchip Technology Inc.
3.1.8.1
COPPER MODE
The EVB-LAN9354 is set to Copper Mode by default. Table 3-14 details the required
strap resistors settings for Copper Mode operation.
TABLE 3-14:
COPPER MODE STRAP RESISTORS
Resistors
Signal Names
R79 (10K)
FXLOSEN
Description
Copper twisted pair for ports A and B further determined
by FXSDENA and FXSDENB
R76, R80 (10K) FXSDA/FXSDB Configures Port 0 and Port 1 to Copper Mode
Note:
R75, R77, and R78 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 3-15 must be assembled for
Copper Mode operation.
TABLE 3-15:
COPPER MODE SIGNAL ROUTING RESISTORS
Resistors
Description
R17, R19, R21, R23
Port 0 Copper mode is Enabled
R31, R33, R35, R37
Port 1 Copper mode is Enabled
Note:
3.1.8.2
R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be
populated (DNP).
FIBER MODE
The LAN9354 supports SFP type 100BASE-FX mode. To enable Fiber Mode, the
respective strap and signal routing resisters must be configured.
Note:
Copper Mode related resistors must be DNP while Fiber Mode is active
(See Section 3.1.8.1 “Copper Mode”).
Table 3-16 details the required strap resistor settings for Fiber Mode operation.
TABLE 3-16:
FIBER MODE STRAP RESISTORS
Resistors
Description
R77 (10K)
Configures Port 0 & 1 to FX_LOS Mode
R75, R78 (10K)
Configures Port 0 & 1 to Fiber mode, respectively
Note:
R76, R79, and R80 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 3-17 must be assembled for
Fiber Mode operation.
TABLE 3-17:
FIBER MODE SIGNAL ROUTING RESISTORS
Resistors
Description
R16, R18, R20, R22
Port 0 Fiber mode Enabled
R30, R32, R34, R36
Port 1 Fiber mode Enabled
Note:
2015 Microchip Technology Inc.
R17, R19, R21, R23, R31, R33, R35, and R37 (0402 package) must not be
populated (DNP).
DS50002394A-page 22
EVB-LAN9354 Evaluation Board User’s Guide
3.1.8.3
FX-LOS FIBER MODE STRAP
FX-LOS strap details are shown in Table 3-18. These strap settings determine if the
ports are to operate in FX-LOS Fiber Mode or FX-SD/Copper Mode.
TABLE 3-18:
R77 (10K) R79 (10K)
Reference
Voltage (v)
Populate
DNP
3.3
A level above 2V selects FX-LOS for Port 0 and Port 1
Populate
Populate
1.5
A level of 1.5V selects FX-LOS for Port 0 and FX-SD /
Copper twisted pair for Port 1, further determined by
FXSDB
DNP
Populate
0 (Default)
A level of 0V selects FX-SD / Copper twisted pair for
Ports 0 and 1, further determined by FXSDA, FXSDB
Note:
3.2
FX-LOS MODE STRAP SETTINGS
Function
The above strap details describe the LAN9354 function. This EVB does not
support SFF Fiber Mode. Therefore, FX-SD related straps are not applicable.
LEDS
Table 3-19 describes the different LED references and their corresponding colors and
indications
TABLE 3-19:
LEDS
Reference
Indication
D1
Green
3.3V Power active
D2
Red
LAN9354 is in reset condition
D4
Green
Full-duplex / Collision Port 1
D6
Green
Full-duplex / Collision Port 2
Note:
3.3
Color
Assumes the LED_FUN field of the LED_CFG register is 00b.
TEST POINTS
Table 3-20 describes the different test points and their corresponding connections.
TABLE 3-20:
Test Points
DS50002394A-page 23
TEST POINTS
Description
Connection
TP1
Single pin populated 5V
5V_EXT
TP2
Single pin populated 3V3
3V3
TP3
Single pin unpopulated VDDCR
VDDCR
TP4
Single pin unpopulated IRQ
IRQ
TP5
Single pin unpopulated P0_MDC
P0_MDC
TP6
Single pin unpopulated P0_MDIO
P0_MDIO
TP7
Single pin unpopulated P1_MDC
P1_MDC
TP8
Single pin unpopulated P1_MDIO
P1_MDIO
TP9
Single pin populated GND
GND
TP10
Single pin populated GND
GND
2015 Microchip Technology Inc.
3.4
MECHANICALS
Figure 3-2 displays details for EVB-LAN9354 mechanical dimensions. Dimensions are
in mm.
FIGURE 3-2:
2015 Microchip Technology Inc.
LAN9354 EVB MECHANICAL DIMENSIONS
DS50002394A-page 24
EVB-LAN9354
EVALUATION BOARD
USER’S GUIDE
Appendix A. EVB-LAN9354 Evaluation Board
A.1
INTRODUCTION
This appendix shows the EVB-LAN9354 Evaluation Board.
FIGURE A-1:
EVB-LAN9354 EVALUATION BOARD
2015 Microchip Technology Inc.
DS50002394A-page 25
EVB-LAN9354
EVALUATION BOARD
USER’S GUIDE
Appendix B. EVB-LAN9354 Evaluation Board Schematics
B.1
INTRODUCTION
This appendix shows the EVB-LAN9354 Evaluation Board Schematics.
2015 Microchip Technology Inc.
DS50002394A-page 26
EVB-LAN9354 EVALUATION BOARD SCHEMATIC 1
EVB-LAN9354 Block Diagram
40 Pin MII
Connector
(Male)
40 Pin MII
Connector
(Female)
RMII
I2C
EEPROM/
Header
Power
Supply
Module
Port 0
Mode
Switch
Microchip
LAN9354
Straps
Jumpers
Crystal
Port 1
Fiber
Trasnceiver(SFP) Port 1
Reset
Switch
10/100
Ethernet
Magnetics &
RJ45
Port 2
10/100
Ethernet
Magnetics &
RJ45
Fiber
Trasnceiver(SFP) Port 2
EVB-LAN9354 Evaluation Board User’s Guide
DS50002394A-page 27
FIGURE B-1:
2015 Microchip Technology Inc.
EVB-LAN9354 EVALUATION BOARD SCHEMATIC 2
POWER SUPPLY
1
FB1
2
EN12_1
R1
2A/0.05DCR
2
Switch, SPDT, Slide
P/N:1101M2S3CQE2
J1 3-$+
2
1
5V_SW
3
0E
C2
10uF
25V
VIN
ENABLE
C3
3_Amp
VOUT
TRIM
GND
4
5
C1
OKR-T/3-W12-C
0.1uF
R2
1K
VOUT_3V3
3
R3
3.30K
1%
R4
470E
1%
(Ra)
(Rb)
R4A
33E
1%
C4
C5
10uF
0.1uF
4.7uF
DNP
1
5V_EXT
3
3V3
3V3
U1
A
1
TP2
ORANGE
3.3 V REGULATOR, 3A
( 3V3 fixed when Rb=470E)
D1
GRN
C
SW1
2
TP1
RED
5V
"3V3 Present"
2015 Microchip Technology Inc.
FIGURE B-2:
3V3
5
RESET#
RESET
NDS355AN_NMOS
1
D
RST#
Q1
3
R8
1K
1
G
5
MR#
2
3V3
VDD
4
2
5HVHW6ZLWFK
U2
2
1/10W
1%
3
sw_pb_2P
1
R7
100
R5
4.75K
1%
0.1uF
GND
SW2
R6
10.0K
1/10W
1%
2
1
C6
S
U3
2
4
1
R9
TPS3125
74LVC1G14
1
3
SOT23_5
Threshold = 2.64V
Delay = 180ms
2.2K
A
C
D2
RED
"Reset"
Reset Generator
2
DS50002394A-page 28
EVB-LAN9354 Evaluation Board User’s Guide
3V3
3V3
EVB-LAN9354 EVALUATION BOARD SCHEMATIC 3
3V3
Power Supply Filtering
VDD33TXRX1
FB2
3V3
2A/0.05DCR
VDDCR
VDD12TX1
VDD12TX2
7
49
11
38
8
35
I2C2_SCL
I2C2_SDA
37
36
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
42
40
39
29
16
15
13
12
RST#
ATEST/FXLOSEN
TESTMODE
I2CSCL/EESCL/TCK
I2CSDA/EESDA/TMS
48
51
VDD12TX1
VDD12TX2
VDDCR_1
VDDCR_2
VDDCR_3
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
RBIAS
IRQ
6
22
32
14
18
28
31
41
50
5
VDD33BIAS
VDD33
REG_EN
TXNA
TXPA
RXNA
RXPA
TXNB
TXPB
RXNB
RXPB
FXSDENB/FXSDB/FXLOSB
GPIO0/LED0/TDO/LEDPOL0/MNGT0
GPIO1/LED1/TDI/LEDPOL1
GPIO2/LED2/LEDPOL2/E2PSIZE
GPIO3/LED3/LEDPOL3/EEEEN
GPIO4/LED4/LEDPOL4/1588EN
GPIO5/LED5/LEDPOL5/PHYADD
GPIO6
GPIO7
2015 Microchip Technology Inc.
LAN9354_QFN56
GND
RST#
IRQ
TP4
WHITE
DNP ATEST/FXLOSEN
RBIAS
Reserved
12.1K
1%
57
R10
27
REG_EN
18pF
FXSDENA/FXSDA/FXLOSA
INT PORT0
C27
OSCVDD12
OSCI
OSCO
OSCVSS
INT PORT1
1
3V3
3
1
2
4
I2C
OSCI
OSCO
OTHER
SIGNALS
25.000MHz
25ppm
Y1
OSC
43
56
POWER
18pF
2
C26
VDD33TXRX1
VDD33TXRX2
U4A
Note:
OSCVSS need to connect to Chip gnd.
9
FXSDA/FXLOSA
44
45
46
47
TXNA
TXPA
RXNA
RXPA
55
54
53
52
TXNB
TXPB
RXNB
RXPB
10
FXSDB/FXLOSB
C20
C21
C22
470pF
0.1uF
0.1uF
C19
1uF
Low ESR
C16
C17
0.1uF
0.1uF
C14
C15
0.1uF
0.1uF
0.1uF
C12
DNP
C13
C18
FB5
2A/0.05DCR
BLM18EG221SN1D
VDD12TX1
VDD12TX2
0.1uF
0.1uF
C25
0.1uF
C24
VDD33TXRX1
VDD33TXRX2
BLM18EG221SN1D
C23
1.0uF
DNP
1.0uF
TP3
SMT
VDDCR
C11
3V3
2A/0.05DCR
2A/0.05DCR
0.1uF
3V3
FB4
FB3
0.1uF
3V3
C9
0.1uF
VDD33TXRX2
C10
C8
DNP
1.0uF
C7
1.0uF
DNP
EVB-LAN9354 Evaluation Board User’s Guide
DS50002394A-page 29
FIGURE B-3:
EVB-LAN9354 EVALUATION BOARD SCHEMATIC 4
/,1.$&7
LED2_ANODE
10
T1
Pulse J0011D01BNL
TXNA
R11
49.9
1/10W
1%
DNP
R16
R17
0E
0E
FX_SFP-TXPA
DNP
R18
R19
0E
0E
FX_SFP-TXNA
R12
49.9
1/10W
1%
R13
49.9
1/10W
1%
R14
49.9
1/10W
1%
A
C
TXPA
330E
0E
9
FB6
3257
R61
LED2_CATHODE
VDD33TXRX1
R15
0E
GRN
1
COP-TXPA
4
2
COP-TXNA
RJ45
XMIT
TD+
75
1
75
TXCT
4&5
TD-
2
'HIDXOWDVVHPEO\
LED1 (Green) = LINK/ACT
DNP
C29
10pF
50V
5%
DNP
C30
10pF
50V
5%
DNP
C31
10pF
50V
5%
C32
0.022uF
7
8
50V
10%
6
RD-
2 kV
1000 pF
NC
CHS GND
Note:
Capacitors C28 through C31 are optional for EMI purposes
and are not populated on the EVB9354 evaluation board.
These capacitors are required for operation in an EMI
constrained environment.
14
13
GND
DNP
C28
10pF
50V
5%
7&8
RXCT
YEL
A1
6
COP-RXNA
3
75
12
FX_SFP-RXNA
75
C1
0E
0E
RD+
11
5
MTG1
3
COP-RXPA
MTG
DNP
R22
R23
LED2 (Yellow) = SPEED
RCV
FX_SFP-RXPA
16
RXNA
0E
0E
15
RXPA
DNP
R20
R21
GND1
2015 Microchip Technology Inc.
FIGURE B-4:
R62
R24
330E
LED0_CATHODE
0E
LED0_ANODE
63(('
/,1.$&7
FB7
LED5_ANODE
0E
10
T2
Pulse J0011D01BNL
0E
0E
FX_SFP-TXPB
DNP
R32
R33
0E
0E
FX_SFP-TXNB
RXPB
DNP
R34
R35
0E
0E
FX_SFP-RXPB
RXNB
DNP
R36
R37
TXNB
R26
49.9
1/10W
1%
R27
49.9
1/10W
1%
R28
49.9
1/10W
1%
A
C
R25
49.9
1/10W
1%
DNP
R30
R31
TXPB
330E
9
3257
R63
LED5_CATHODE
VDD33TXRX2
R29
0E
GRN
1
COP-TXPB
4
COP-TXNB
2
COP-RXPB
3
RJ45
XMIT
TD+
75
75
1
TXCT
4&5
TD-
2
LED1 (Green) = LINK/ACT
CHS GND
A1
12
DS50002394A-page 30
Note:
Capacitors C33 through C36 are optional for EMI purposes
and are not populated on the EVB9354 evaluation board.
These capacitors are required for operation in an EMI
constrained environment.
YEL
C1
8
6
2 kV
1000 pF
NC
11
50V
10%
7
MTG1
C37
0.022uF
GND
1RWH)%DQG)%WREH]HURRKPV
DNP
C36
10pF
50V
5%
MTG
DNP
C35
10pF
50V
5%
16
DNP
C34
10pF
50V
5%
3
7&8
RD-
15
DNP
C33
10pF
50V
5%
75
RXCT
GND1
6
COP-RXNB
75
13
FX_SFP-RXNB
RD+
14
5
0E
0E
LED2 (Yellow) = SPEED
RCV
R64
R38
0E
RES1210
LED3_CATHODE
63(('
330E
LED3_ANODE
EVB-LAN9354 Evaluation Board User’s Guide
RES1210
EVB-LAN9354 EVALUATION BOARD SCHEMATIC 5
R39
82
R40
82
R41
49.9
R42
49.9
Note:Place
capacitors,
and resistors
close to FOT
Note:Place
capacitors,
and resistors
close to FOT
3V3
Fiber Port 1 :SFP Interface
R43
82
R44
82
R45
49.9
R46
49.9
Assemble 0E at C38,C40,C42,C44
C38
FX_SFP-RXPA
C40
0.1uF
FX_SFP-TXPA
C42
0.1uF
DNP
R47
100
C44
FX_SFP-TXNA
Assemble 0E at C39,C41,C43,C45
0.1uF
C39
0.1uF
FX_SFP-RXPB
C41
0.1uF
FX_SFP-TXPB
C43
0.1uF
DNP
R48
100
3V3
SFP_VCCT
L2
SFP_VCCR
0.1uF
FX_SFP-RXNB
C45
C48 +
10uF
16V
C47
0.1uF
0.1uF
R51
130
R52
130
1uH
J2
FTLF1217P2
R53
4.7K
R54
4.7K
VeeT1
TDTD+
VeeT2
VccT
VccR
VeeR2
RD+
RDVeeR3
C55
Note:Place
0.1uF
resistors
close to
ASIC
J3
FTLF1217P2
SFP_VCCT2
1
2
3
4
5
6
7
8
9
10
SFP_VCCT
VeeT
TXFault
TX Disable
MOD-DEF(2)
MOD-DEF (1)
MOD-DEF (0)
Rate Select
LOS
VeeR
VeeR1
ASIC
31
30
29
28
27
26
25
24
23
22
21
C54 +
10uF
16V
1
2
3
4
5
6
7
8
9
10
resistors
close to
31
30
29
28
27
26
25
24
23
22
21
R55
4.7K
R57
4.7K
R56
4.7K
FXSDA/FXLOSA
R58
4.7K
R59
4.7K
R60
4.7K
FXSDB/FXLOSB
2015 Microchip Technology Inc.
Note: Fiber mode related components are Not Populated on EVB (Default)
31
30
29
28
27
26
25
24
23
22
21
31
30
29
28
27
26
25
24
23
22
21
C56 +
10uF
16V
1uH
C51
0.1uF
L3
20
19
18
17
16
15
14
13
12
11
VeeT1
TDTD+
VeeT2
VccT
VccR
VeeR2
RD+
RDVeeR3
Note:Place
DNP
C50 +
10uF
16V
20
19
18
17
16
15
14
13
12
11
L4
C49
L1
SFP_VCCR2
0.1uF
SFP_TD2SFP_TD2+
R50
130
SFP_RD+
SFP_RD-
R49
130
SFP_TDSFP_TD+
FX_SFP-TXNB
DNP
C46 +
10uF
16V
3V3
SFP_VCCT2
1uH
VeeT
TXFault
TX Disable
MOD-DEF(2)
MOD-DEF (1)
MOD-DEF (0)
Rate Select
LOS
VeeR
VeeR1
FX_SFP-RXNA
Fiber Port 2 :SFP Interface
SFP_RD2+
SFP_RD2-
3V3
C57
0.1uF
C52 +
10uF
16V
1uH
C53
0.1uF
EVB-LAN9354 Evaluation Board User’s Guide
DS50002394A-page 31
FIGURE B-5:
EVB-LAN9354 EVALUATION BOARD SCHEMATIC 6
GPIO [0:5] & LED_POL_Strap
I2C EEPROM
3V3
3V3
GPIO3
R67
GPIO4
GPIO5
1
2
3
7
A0
A1
A2
GPIO0
GPIO1
WP
I2C2_SDA
6
I2C2_SCL
Note: U5: IC DIP Socket. Different sizes can be mounted
I2C EEPROM Lower size Below 16K(2K X 8)
I2C EEPROM Higher size
Above 16K(2K X 8)
[Default-512KBIT]
GPIO3
3
1
3
J15
1
3
GPIO4
5
2
2
2
R86
0E
J13
1
3
1
3
GPIO2
R85
0E
J14
J8
1
3
J9
1
J7
R84
1K
2
R74
1K
2
2
R73
0E
SDA
SCL
2
2
2
LED3_CATHODE
LED5_CATHODE
2
VCC
4.7K
R83
10.0K
24FC512-I/P
R72
0E
0.1uF
3
1
2
2
R66
LED3_ANODE
LED5_ANODE
R82
10.0K
LED1_CATHODE
LED4_CATHODE
2
LED0_CATHODE
LED2_CATHODE
R81
10.0K
1
R71
10.0K
3
1
3
1
2
J12
1
R70
10.0K
1
LED1_ANODE
LED4_ANODE
1
1
1
LED0_ANODE
LED2_ANODE
R69
10.0K
J10
2
J11
2
J5
2
J6
3
1
3
1
3
1
U5
J4
2K
GPIO1
3V3
2K
GPIO2
3V3
8
GPIO0
3V3
GND
3V3
4
3V3
R68
C58
3V3
2
2015 Microchip Technology Inc.
FIGURE B-6:
GPIO5
FX_Los_Strap_1 & 2
3V3
Port 1 LEDs
LED0_ANODE
LED0_CATHODE
DNP
D3 1
GRN A
SPEED
LED3_ANODE
2
C
LED3_CATHODE
LED3_ANODE
LED3_CATHODE
DNP
D6 1
GRN A
5
SPEED
3RXSXODWH
2
FULL DUPLEX / Collision
LED1_CATHODE
D4 1
GRN A
FULL DUPLEX / Collision
LED4_ANODE
2
LED4_CATHODE
C
D7 1
GRN A
2
C
3RXSXODWH
LED2_ANODE
LED2_CATHODE
LED2_ANODE
LED2_CATHODE
LED5_ANODE
2
LED5_CATHODE
LED5_ANODE
LED5_CATHODE
3RXSXODWH
)XQFWLRQ
9
$ERYH9VHOHFWV);/26IRUSRUWVDQG
9
/HYHORI9VHOHFWV);/26IRUSRUWDQG
);6'FRSSHUWZLVWHGSDLUIRUSRUW
IXUWKHUGHWHUPLQHGE\);6'%
R77
10K
DNP
ATEST/FXLOSEN
1
GPIO6
R87
2
'13
3
10K
'HIDXOW
LINK/ACT
DNP
D5 1
C
GRN A
'13
5HI9ROWDJH
C
3V3
LED1_ANODE
5
J16
LINK/ACT
DNP
2
D8 1
C
GRN A
3RXSXODWH
'HIDXOW
'HIDXOW
/HYHORI96HOHFWV);6'FRSSHUWZLVWHGSDLU
IRUSRUWV$DQG%
IXUWKHUGHWHUPLQHGE\);6'$DQG);6'%
R79
10K
3V3
1
Strap Name
Logic
LED Polarity Strap
Connector
0
J4,J7 (2&3)
The LED is set as active high.
1
J4,J7 (1&2)
(Default)
The LED is set as active low,
0
J5,J8 (2&3)
The LED is set as active high.
1
J5,J8 (1&2)
(Default)
The LED is set as active low,
0
J6,J9 (2&3)
The LED is set as active high.
EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8)
1
J6,J9 (1&2)
(Default)
The LED is set as active low,
EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only)
0
J10,J13 (2&3)
The LED is set as active high.
EEE Disable
GPIO7
R88
2
3
10K
J17
LED0/GPIO0/MNGT0
FX_Mode_Strap_1 & 2
3V3
LED1/GPIO1
LED2/GPIO2/E2PSIZE
LED3/GPIO3/EEEEN
FXSDA/FXLOSA
J10,J13 (1&2)
(Default)
The LED is set as active low,
EEE Enable
0
J11,J14 (2&3)
The LED is set as active high.
1588 Disable
1
J11,J14 (1&2)
(Default)
The LED is set as active low,
0
J12,J15 (2&3)
(Default)
The LED is set as active high.
PHYADD=0,1,2
J12,J15 (1&2)
The LED is set as active low,
PHYADD =1,2,3
1
LED4/GPIO4/1588EN
DS50002394A-page 32
LED5/GPIO5/PHYADD
1
1588 Enable
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
1
2
3
4
5
6
7
8
DNP 10K
R76
10K
3257
3257
02'(
3RXSXODWH
'13
&RSSHU
'HIDXOW
5
5
)LEHU
5
5
&RSSHU
'HIDXOW
5
5
)LEHU
5
5
3V3
FXSDB/FXLOSB
J18
HEADER 8
GPIO0 = LED0/TDO/LEDPOL0/MNGT0
GPIO1 = LED1/TDI/LEDPOL1
GPIO2 = LED2/LEDPOL2/E2PSIZE
GPIO3 = LED3/LEDPOL3/EEEEN
GPIO4 = LED4/LEDPOL4/1588EN
GPIO5 = LED5/LEDPOL5/PHYADD
R75
R78
DNP 10K
R80
10K
3257
EVB-LAN9354 Evaluation Board User’s Guide
LED0_ANODE
LED0_CATHODE
Port 2 LEDs
EVB-LAN9354 EVALUATION BOARD SCHEMATIC 7
10uF
5V
0.1uF
P0_MDIO
P0_MDC
P0_REF_CLK_MODE0_RES
P0_OUTD1_MODE2_RES
P0_OUTD0_MODE1_RES
P0_OUTDV
R94
0E MAC_TXCLK0
MAC_RXCLK0
P0_INDV
P0_IND0
P0_IND1
CRS
C60
+5V[3]
MDIO
MDC
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_CLK
RX_ER
TX_ER
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
COL
CRS
+5V[4]
+5V[1]
COMMON[1]
COMMON[2]
COMMON[3]
COMMON[4]
COMMON[5]
COMMON[6]
COMMON[7]
COMMON[8]
COMMON[9]
COMMON[10]
COMMON[11]
COMMON[12]
COMMON[13]
COMMON[14]
COMMON[15]
COMMON[16]
COMMON[17]
COMMON[18]
+5V[2]
P0_OUTD1_MODE2_RES
P0_OUTD0_MODE1_RES
R89
R90
P0_REF_CLK_MODE0_RES
R91
P0_IND0
P0_IND1
MAC 1
J19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
3ODFHQHDUWR,&
C59
U4B
P0_SPEED
P0_OUTD1_MODE2
P0_OUTD0_MODE1
P0_OUTDV
P0_REF_CLK_MODE0
P0_INDV
33
33
33
33
33
R92
R93
P0_DUPLEX
P0_MDC
P0_MDIO
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
17
19
20
21
23
24
25
26
30
33
34
3V3
SW3
P0_SPEED
P0_OUTD1/P0_MODE2
P0_OUTD0/P0_MODE1
P0_OUTDV
P0_REFCLK/P0_MODE0
P0_INDV
P0_IND0
P0_IND1
P0_DUPLEX
P0_MDC
P0_MDIO
2
R96
3
10K
JS102011CQN
3V3
SW4
2
P0_MODE1
1
P0_OUTD0_MODE1_RES
R97
LAN9354_QFN56
3
10K
JS102011CQN
3V3
3V3
J23 1
J22
2
P0_SPEED
R100
2
P0_DUPLEX
3
10K
R99
Default - Open
10K
3V3
SW5
1
3
2
P0_MODE2
1
P0_OUTD1_MODE2_RES
R98
3
10K
JS102011CQN
Default - Open
Note: The P0_SPEED & P0_DUPLEX pins are typically
connected to the speed & duplex indication of the external PHY
Emulated Link Partner Default Advertised Ability for Port 0
J22
AMP - 6-5174218-2
MII Male for External MAC Board
PORT0
Duplex
Strap_0
J23
(P0_DUPLEX)
MII_RA
(P0_SPEED)
Speed
Strap_0
ADVERTISED LINK PARTNER ABILITY
(Bits 8,7,6,5)
1-2
2-3
1
0
1-2
1-2
1
1
100BASE-X full-duplex (1000) (Default)
2-3
2-3
0
0
10BASE-T half-duplex (0001)
2-3
1-2
0
1
100BASE-X half-duplex (0100)
10BASE-T full-duplex (0010)
5V
C61
P0_MODE0
1
P0_REF_CLK_MODE0_RES
10uF
C62 0.1uF
RMII RX Clock Configurations
WŽƌƚϬDŽĚĞƐƚƌĂƉDĂƉƉŝŶŐ
WϬͺDKϮ
;^tϱͿ
WϬͺDKϮ
;^tϰͿ
WϬͺDKϬ
;^tϯͿ
DK
!"#$
1RWH)RU6ZLWFKHVWRVKRUW.QRE3RVLWLRQVKRXOGEHDWDQGYLFHYHUVD
Chassis2
Chassis1
J20
P0_MDIO
P0_MDC
P0_IND1
P0_IND0
P0_INDV
PHY_RXCLK0
P0_REF_CLK_MODE0_RES R95
0E PHY_TXCLK0
P0_OUTDV
P0_OUTD0_MODE1_RES
P0_OUTD1_MODE2_RES
2015 Microchip Technology Inc.
P0_INDV
CRS
For RMII
CRS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FEMALE MII CONN
AMP - 749069-4
MII Female for External PHY Board
PORT0
3V3
R103
10K
P0_INDV
SW6
2
Aardvark - I2C Connector
MAC_RXCLK0
MAC_TXCLK0 1
3
1
3
5
7
9
I2C2_SCL
I2C2_SDA
Default Short 1-3
JS102011CQN
SW7
2
PHY_RXCLK0
2
4
6
8
10
PHY_TXCLK0 1
3
HEADER 5X2
J21
Default Short 1-3
JS102011CQN
Switch
Settings
SW6 (1-3)
Default
TP5 TP6
Description
Mode
RMII MAC
SW6 (1-2)
RX Clock used as a Reference Clock
SW7 (1-3)
Default
Reference clock used as a TX clock
RMII MAC
SW7 (1-2)
3V3
TX Clock used as a Reference Clock
P0_MDIO
1.5K
R101
P0_MDC
10K
R102
RMII PHY
Pullup for MDIO(common for all PHY) signal
Reference clock used as a RX clock
RMII PHY
Note: 1. For Switches to short 1-3, Knob Position should be
at 1-2 and vice versa .
2. External PHY considered LAN8742
EVB-LAN9354 Evaluation Board User’s Guide
DS50002394A-page 33
FIGURE B-7:
EVB-LAN9354
EVALUATION BOARD
USER’S GUIDE
Appendix C. Bill of Materials (BOM)
C.1
INTRODUCTION
This appendix includes the EVB-LAN9354 Evaluation Board Bill of Materials (BOM).
2015 Microchip Technology Inc.
DS50002394A-page 34
TABLE C-1:
Item
EVB-LAN9354 EVALUATION BOARD BILL OF MATERIALS
Qty
Reference Designator(s)
Part
PCB Footprint
Manufacturer
Manufacturer Part Number
1
2
C2,C4
10uF
CAP0805
Murata
GRM21BR61E106KA73L
2
19
C3,C5,C6,C8,C10,C11,C13,C14,C15,C16,C17 0.1uF
,C18,C21,C22,C24,C25,C58,C60,C62
CAP0603
Murata
GRM155R61E104KA7D
3
1
C19
1uF
CAP0603
Murata
GRM188R61C105KA93D
4
1
C20
470pF
CAP0603
Murata
GRM033R71E471KA01D
5
2
C26,C27
18pF
CAP0603
Murata
GRM1885C1H180JA01D
6
2
C32,C37
0.022uF
CAP0603
Kemet
C0603C223K5RACTU
7
2
C59,C61
10uF
CAP0603
TDK
C1608X5R0J106K080AB
8
3
D1,D4,D7
GRN
LED0603
Wurth electronics
150 060 GS7 500 0
9
1
D2
RED
LED0603
Wurth electronics
150 060 RS7 500 0
Murata
2015 Microchip Technology Inc.
10
5
FB1,FB2,FB3,FB4,FB5
2A/0.05DCR
RES0603
11
1
J1
SKT_PWR_2R0mm_4A_THRU_R
A
th_conn_pwrjack_dc-210_rt Cui Stack
PJ-002AH
BLM18EG221SN1D
12
16
J4,J5,J6,J7,J8,J9,J10,J11,J12,J13,J14,J15,J1
6,J17,J22,J23
HDR_1x3
TH_CONN_1X3P
FCI
68000-103HLF
13
1
J18
HEADER 8
TH_CONN_1X8P
FCI
68000-108HLF
14
1
J19
MII_RA
TH_CONN_TE-5173278_40P
TE
5173278-2-ND
15
1
J20
FEMALE MII CONN
TH_CONN_MII-749069-4
TE
749069-4-ND
16
1
J21
HEADER 5X2
th_conn_2x5p_BOX
FCI
67997-210HLF
17
1
Q1
NDS355AN_NMOS
sot23-NDS
Fairchild
NDS355AN
18
7
R1,R94,R95,R72,R73,R85,R86
0E
RES0603
Panasonic
ERJ-3GEY0R00V
19
4
R2,R8,R74,R84
1K
RES0603
Panasonic
ERJ-3GEYJ102V
20
1
R3
3.30K
RES0603
Yageo America
9C06031A3301FKHFT
21
1
R4
470E
RES0603
BOURNS
CR0603-FX-4700ELF
CR0603-FX-33R0ELF
22
1
R4A
33E
RES0603
BOURNS
23
1
R5
4.75K
RES0603
Panasonic
ERJ-3EKF4751V
24
7
R6,R69,R70,R71,R81,R82,R83
10.0K
RES0603
Panasonic
ERJ-3EKF1002V
25
1
R7
100
RES0603
Panasonic
ERJ-3EKF1000V
26
1
R9
2.2K
RES0603
Panasonic
ERJ-3GEYJ222V
27
1
R10
12.1K
RES0603
Rohm
MCR01MZPF1202
28
8
R11,R12,R13,R14,R25,R26,R27,R28
49.9
RES0603
Yageo America
9C06031A49R9FKHFT
EVB-LAN9354 Evaluation Board User’s Guide
DS50002394A-page 35
Configuration: Two internal copper mode with higher size EEPROM (24FC512)
2015 Microchip Technology Inc.
TABLE C-1:
Item
EVB-LAN9354 EVALUATION BOARD BILL OF MATERIALS (CONTINUED)
Qty
Reference Designator(s)
Part
PCB Footprint
Manufacturer
Manufacturer Part Number
29
4
R15,R29, FB6,FB7
0E
RES0603
Panasonic
ERJ-3GEY0R00V
30
8
R17,R19,R21,R23,R31,R33,R35,R37
0E
RES0402
Panasonic
ERJ-2GE0R00X
31
2
R24,R38
0E
RES1210
Vishay
CRCW12100000Z0EA
ERJ-3GEYJ331V
32
4
R61,R62,R63,R64
330E
RES0603
Panasonic
33
2
R67,R68
2K
RES0603
Panasonic
ERJ-3GEYJ202V
34
12
R76,R79,R80,R87,R88,R96,R97,R98,R99,R1
00,R102,R103
10K
RES0603
Panasonic
ERJ-3EKF1002V
35
5
R89,R90,R91,R92,R93
33
RES0603
BOURNS
CR0603-FX-33R0ELF
36
1
R101
1.5K
RES0603
Panasonic
ERJ-3GEYJ152V
37
1
SW1
SW-SPDT-SLIDE
sw_ck_1101m2s3cqe2
C&K
1101M2S3CQE2
38
1
SW2
sw_pb_2P
sw_pb_2P
Panasonic
39
5
SW3,SW4,SW5,SW6,SW7
JS102011CQN
TH_SW_SPST_3P_10x2p5 Wurth electronics
450301014042
40
1
TP1
RED
TH_TP_60D40
Keystone
5000
41
1
TP2
ORANGE
TH_TP_60D40
Keystone
5003
42
2
T1,T2
Pulse - J0011D01BNL
th_conn_pulse_rj45_j0026
Pulse Electronics
553-1483-ND
43
1
U1
3_Amp
TH_DC-DC_VERT_5PIN_P Murata
67
OKR-T/3-W12-C
44
1
U2
TPS3125
SOT23_5
TI
TPS3125L30DBVR
45
1
U3
74LVC1G14
SOT23_5
TI
SN74LVC1G14DCKR
46
1
U4
LAN9354_QFN56
IC_QFN56_8X8MM
Microchip
LAN9354
47
1
U5
IC Base
IC_DIP8_300
Assmann WSW Compo- AR08-HZL-TT-R
nents
48
1
U5
24C512
IC_DIP8_300
Microchip
24FC512-I/P
49
1
Y1
25.000MHz
XTAL_HCM49
Cardinal Components
Inc.
CSM1Z-A5B2C5-40-25.0D18-F
EVQ-PJU04K
DS50002394A-page 36
EVB-LAN9354 Evaluation Board User’s Guide
NOTES:
DS50002394A-page 37
2015 Microchip Technology Inc.
Worldwide Sales and Service
AMERICAS
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Fax: 480-792-7277
Technical Support:
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Web Address:
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Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 86-592-2388138
Fax: 86-592-2388130
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Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 91-80-3090-4444
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Tel: 33-1-69-53-63-20
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Duluth, GA
Tel: 678-957-9614
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Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
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Tel: 86-10-8569-7000
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Tel: 512-257-3370
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Tel: 86-28-8665-5511
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Westborough, MA
Tel: 774-760-0087
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Tel: 86-23-8980-9588
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Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
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Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
01/27/15
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