Data Sheet

74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
Rev. 1 — 8 November 2013
Product data sheet
1. General description
The 74AHC132-Q100; 74AHCT132-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A.
The 74AHC132-Q100; 74AHCT132-Q100 contains four 2-input NAND gates which accept
standard input signals. They can transform slowly changing input signals into sharply
defined, jitter free output signals. The gate switches at different points for positive-going
and negative-going signals. The difference between the positive voltage VT+ and the
negative VT is defined as the hysteresis voltage VH.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Balanced propagation delays
 Inputs accept voltages higher than VCC
 Input levels:
 For 74AHC132-Q100: CMOS level
 For 74AHCT132-Q100: TTL level
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM EIA/JESD22-A115-A exceeds 200 V
 Multiple package options
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
3. Ordering information
Table 1.
Ordering information
Type number
Package
74AHC132D-Q100
Temperature range
Name
Description
Version
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
14 terminals; body 2.5  3  0.85 mm
74AHCT132D-Q100
74AHC132PW-Q100
74AHCT132PW-Q100
74AHC132BQ-Q100
74AHCT132BQ-Q100
SOT762-1
4. Functional diagram
1
1A
1Y
2
4
2A
2Y
5
3
1B
1
6
2B
4
9
3A
3
&
6
&
8
&
11
5
3Y
10
&
2
8
3B
9
10
12
4A
4Y
13
12
11
13
4B
mna407
Fig 1.
mna408
Logic symbol
Fig 2.
IEC logic symbol
A
Y
B
mna409
Fig 3.
Logic diagram (one Schmitt trigger)
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
2 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
5. Pinning information
5.1 Pinning
$
WHUPLQDO
LQGH[DUHD
$+&4
$+&74
<
$
$
<
%
%
<
$
*1'
<
%
<
$
$
%
<
<
*1'
%
%
%
9&&
%
<
*1'
$
9&&
$+&4
$+&74
$
DDD
7UDQVSDUHQWWRSYLHZ
DDD
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A, 2A, 3A, 4A
1, 4, 9, 12
data input nA
1B, 2B, 3B, 4B
2, 5, 10, 13
data input nB
1Y, 2Y, 3Y, 4Y
3, 6, 8, 11
data output nY
GND
7
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
Output
nA
nB
nY
L
L
H
L
H
H
H
L
H
H
H
L
[1]
H = HIGH voltage level;
L = LOW voltage level.
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
3 of 18
NXP Semiconductors
74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
VI
input voltage
IIK
input clamping current
Conditions
Min
Max
Unit
0.5
+7.0
V
0.5
+7.0
V
VI < 0.5 V
[1]
20
-
mA
[1]
20
+20
mA
25
+25
mA
IOK
output clamping current
VO <0.5 V or VO > VCC + 0.5 V
IO
output current
VO =0.5 V to (VCC + 0.5 V)
ICC
supply current
-
+75
mA
IGND
ground current
75
-
mA
Tstg
storage temperature
65
+150
C
-
500
mW
total power dissipation
Ptot
[1]
[2]
Tamb = 40 C to +125 C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 package: above 70 C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 package: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 package: above 60 C the value of Ptot derates linearly at 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
2.0
5.0
5.5
V
74AHC132-Q100
VCC
supply voltage
VI
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
C
t/V
input transition rise and fall rate
VCC = 3.0 V to 3.6 V
-
-
100
ns/V
VCC = 4.5 V to 5.5 V
-
-
20
ns/V
74AHCT132-Q100
VCC
supply voltage
4.5
5.0
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
C
t/V
input transition rise and fall rate
-
-
20
ns/V
74AHC_AHCT132_Q100
Product data sheet
VCC = 4.5 V to 5.5 V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
4 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
HIGH-level
VI = VT+ or VT
output voltage
IO = 50 A; VCC = 2.0 V
1.9
2.0
-
1.9
2.2
1.9
-
V
IO = 50 A; VCC = 3.0 V
2.9
3.0
-
2.9
3.15
2.9
-
V
IO = 50 A; VCC = 4.5 V
4.4
4.5
-
4.4
3.85
4.4
-
V
IO = 4.0 mA; VCC = 3.0 V
2.58
-
-
2.48
-
2.40
-
V
IO = 8.0 mA; VCC = 4.5 V
3.94
-
-
3.80
-
3.70
-
V
LOW-level
VI = VT+ or VT
output voltage
IO = 50 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
74AHC132-Q100
VOH
VOL
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
A
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
A
CI
input
capacitance
-
3
10
-
10
-
10
pF
CO
output
capacitance
-
4
-
-
-
-
-
pF
4.4
4.5
-
4.4
-
4.4
-
V
3.94
-
-
3.80
-
3.70
-
V
-
0
0.1
-
0.1
-
0.1
V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
A
II
input leakage
current
ICC
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
VI = VCC or GND
74AHCT132-Q100
VOH
HIGH-level
VI = VT+ or VT; VCC = 4.5 V
output voltage
IO = 50 A
IO = 8.0 mA
VOL
LOW-level
VI = VT+ or VT; VCC = 4.5 V
output voltage
IO = 50 A
IO = 8.0 mA
II
input leakage
current
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
A
ICC
additional
per input pin;
supply current VI = VCC  2.1 V; other pins
at VCC or GND; IO = 0 A;
VCC = 4.5 V to 5.5 V
-
-
1.35
-
1.5
-
1.5
mA
CI
input
capacitance
-
3
10
-
10
-
10
pF
CO
output
capacitance
-
4
-
-
-
-
-
pF
74AHC_AHCT132_Q100
Product data sheet
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
VI = VCC or GND
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
5 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 7.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
Min
Max
CL = 15 pF
-
4.4
11.9
1.0
14.0
1.0
15.0
ns
CL = 50 pF
-
6.2
15.4
1.0
17.5
1.0
19.5
ns
-
3.3
7.7
1.0
9.0
1.0
10.0
ns
-
4.7
9.7
1.0
11.0
1.0
12.5
ns
-
11
-
-
-
-
-
pF
-
3.5
7.0
1.0
8.0
1.0
9.0
ns
-
5.0
8.0
1.0
9.0
1.0
10.0
ns
-
14
-
-
-
-
-
pF
74AHC132-Q100
tpd
propagation nA, nB to nY; see Figure 6
delay
VCC = 3.0 V to 3.6 V
[2]
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
CPD
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
[3]
74AHCT132-Q100
tpd
propagation nA, nB to nY; see Figure 6
delay
VCC = 4.5 V to 5.5 V
[2]
CL = 15 pF
CL = 50 pF
CPD
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
[3]
[1]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2]
tpd is the same as tPLH and tPHL.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of the outputs.
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
6 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
11. Waveforms
VI
VM
nA, nB input
GND
t PHL
t PLH
VOH
VM
nY output
VOL
001aaa662
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Table 8.
Input to output propagation delays
Measurement points
Type
Input
Output
VM
VM
74AHC132-Q100
0.5  VCC
0.5  VCC
74AHCT132-Q100
1.5 V
0.5  VCC
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
7 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
VI
negative
pulse
tW
90 %
VM
VM
10 %
GND
tr
tf
tr
tf
VI
90 %
positive
pulse
GND
VM
VM
10 %
tW
VCC
G
VI
VO
DUT
RT
CL
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 7.
Table 9.
Test circuit for measuring switching times
Test data
Type
Input
Load
Test
VI
tr, tf
CL
74AHC132-Q100
VCC
 3.0 ns
50 pF, 15 pF
tPLH, tPHL
74AHCT132-Q100
3.0 V
 3.0 ns
50 pF, 15 pF
tPLH, tPHL
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
8 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
12. Transfer characteristics
Table 10. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 3.0 V
-
-
2.2
-
2.2
-
2.2
V
VCC = 4.5 V
-
-
3.15
-
3.15
-
3.15
V
VCC = 5.5 V
-
-
3.85
-
3.85
-
3.85
V
VCC = 3.0 V
0.9
-
-
0.9
-
0.9
-
V
VCC = 4.5 V
1.35
-
-
1.35
-
1.35
-
V
VCC = 5.5 V
1.65
-
-
1.65
-
1.65
-
V
VCC = 3.0 V
0.3
-
1.2
0.3
1.2
0.25
1.2
V
VCC = 4.5 V
0.4
-
1.4
0.4
1.4
0.35
1.4
V
VCC = 5.5 V
0.5
-
1.6
0.5
1.6
0.45
1.6
V
-
-
1.9
-
1.9
-
1.9
V
74AHC132-Q100
VT+
VT
VH
positive-going threshold
voltage
negative-going threshold
voltage
hysteresis voltage
74AHCT132-Q100
VT+
positive-going threshold
voltage
VCC = 4.5 V
VCC = 5.5 V
-
-
2.1
-
2.1
-
2.1
V
VT
negative-going threshold
voltage
VCC = 4.5 V
0.5
-
-
0.5
-
0.5
-
V
VCC = 5.5 V
0.6
-
-
0.6
-
0.6
-
V
hysteresis voltage
VCC = 4.5 V
0.3
-
1.4
0.3
1.4
0.3
1.4
V
VCC = 5.5 V
0.3
-
1.5
0.3
1.5
0.3
1.5
V
VH
13. Transfer characteristics waveforms
VO
VT+
VI
VT−
VI
VH
VT−
Fig 8.
VT+
Transfer characteristics
74AHC_AHCT132_Q100
Product data sheet
VH
VO
mna207
mna208
Fig 9.
Definition of VT+, VT and VH
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
9 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
mna411
1.5
mna412
5
I CC
I CC
(mA)
(mA)
4
1
3
2
0.5
1
0
0
0
1
2
VI (V)
3
1
0
a. VCC = 3.0 V
2
3
4 V (V) 5
I
b. VCC = 4.5 V
mna413
6
I CC
(mA)
4
2
0
0
c.
2
4
VI (V)
6
VCC = 5.5 V
Fig 10. Typical 74AHC132-Q100 transfer characteristics
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
10 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
mna414
6
mna415
8
I CC
I CC
(mA)
(mA)
6
4
4
2
2
0
0
0
1
2
4 V (V) 5
I
3
0
a. VCC = 4.5 V.
2
4
VI (V)
6
b. VCC = 5.5 V.
Fig 11. Typical 74AHCT132-Q100 transfer characteristics
14. Application information
VCC
R
VCC
A
Y
B
C
001aac440
1
T
1
0.55  RC
For 74AHC132-Q100: f = ---  ------------------------
1
T
1
0.60  RC
For 74AHCT132-Q100: f = ---  ------------------------
Fig 12. Relaxation oscillator
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
11 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
15. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 13. Package outline SOT108-1 (SO14)
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
12 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 14. Package outline SOT402-1 (TSSOP14)
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
13 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
6
y
y1 C
v M C A B
w M C
b
L
1
7
Eh
e
14
8
13
9
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 15. Package outline SOT762-1 (DHVQFN14)
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
14 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
16. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
Low-power Schottky Transistor-Transistor Logic
MIL
Military
MM
Machine Model
17. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
74AHC_AHCT132_Q100 v.1
20131108
Product data sheet
-
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
-
© NXP B.V. 2013. All rights reserved.
15 of 18
74AHC132-Q100; 74AHCT132-Q100
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AHC_AHCT132_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
16 of 18
NXP Semiconductors
74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 November 2013
© NXP B.V. 2013. All rights reserved.
17 of 18
NXP Semiconductors
74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
20. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Transfer characteristics . . . . . . . . . . . . . . . . . . 9
Transfer characteristics waveforms. . . . . . . . . 9
Application information. . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 November 2013
Document identifier: 74AHC_AHCT132_Q100