5 4 3 2 1 REVISION HISTORY DATE: DESCRIPTION 08/16/10 01/31/11 D REVISION Initial 1.0 Pull up Pin EROEN make WRSTO active low. Invert the WRSTO before it generates the G_RESETN. 1.1 D SoC Test Board C C B B A A CONFIDENTIAL & PROPRIETARY MICREL SEMICONDUCTOR Title SoC Test Board 5 4 3 2 Size Custom Document Number Revision History Date: Monday, January 31, 2011 Rev 1.1 Sheet 1 1 of 20 5 4 3 2 1 GPIO Port D D SPI/I2C SoC SPI/I2C <=>USB 10/100 GPIO Female MII Connector On-Board Derived Power: SPI/I2C MII Port1 MDC/MDIO Female MII Connector USB 5 V Input Reset KSZ9692PB JTAG/ICE 3.3 V 2.5V 1.2V RGMII Port0 10/100/1000 WAN HOST MODE C S/W Test LED DDR Bus C UART Static Memory Bus 4M x 16 bit NOR FLASH DDR 64 MB 16 Bit Generic Bus Header B B A A CONFIDENTIAL & PROPRIETARY MICREL SEMICONDUCTOR Title SoC Test Board Micrel Confidential 5 4 3 2 Size Custom Document Number Block Diagram Date: Monday, January 31, 2011 Rev 1.0 Sheet 1 2 of 20 5 4 3 2 1 Note: Support DDR 32-bit data width. DDR RDATA[31:0] 8 DATA[31:0] DATA0 DATA1 DATA2 DATA3 D NOR 7 SDATA[15:0] SADDR0 SADDR1 SADDR2 SADDR3 SADDR4 SADDR5 SADDR6 SADDR7 SADDR8 SADDR9 SADDR10 SADDR11 SADDR12 SADDR13 SADDR14 SADDR15 SADDR16 SADDR17 SADDR18 SADDR19 SADDR20 SADDR21 SADDR22 SADDR23 C 6,7 SADDR[23:0] V3.3 7 R89 10K RCSN0 ECSN0 ECS0 R188 R189 R190 0 0 0 EROEN ERWEN0 R192 0 EWAITN 6,7 6,7 EROEN ERWEN0 NAND B V2.5 K4 P1 M3 L4 R1 P2 N3 K5 M4 T1 R2 P3 N4 L5 U1 T2 SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 E3 E2 E1 F4 F5 F3 F2 G1 F1 G2 G4 G3 H1 G5 H2 J1 H3 J2 H4 H5 J3 K2 K1 L2 SADDR0 SADDR1 SADDR2 SADDR3 SADDR4 SADDR5 SADDR6 SADDR7 SADDR8 SADDR9 SADDR10 SADDR11 SADDR12 SADDR13 SADDR14 SADDR15 SADDR16 SADDR17 SADDR18 SADDR19 SADDR20 SADDR21 SADDR22 SADDR23 L1 K3 RCSN0 RCSN1 M2 N1 L3 N2 ECSN0 ECSN1 ECSN2 EWAITN M1 J4 J5 EROEN ERWEN0 ERWEN1 V3 T3 R4 T4 U2 R3 P4 U4 U3 NCEN0 NCEN1 NREN NWEN NALE NCLE NRBN1 NRBN0 NWPN R212 100 1% C175 0.1uF T7 U7 8 RCKE C180 0.1uF R228 33 R106 100 1% 33 VREF VREF DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 W4 V4 Y4 T5 U5 W5 V5 Y5 V6 W6 Y6 V7 W7 Y7 Y8 W8 Y9 W9 V9 Y10 U9 W10 Y11 V10 U10 V11 W12 Y13 W13 V12 U11 V13 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DQS0 DQS1 DQS2 DQS3 U6 V8 W11 U12 DQS0 DQS1 DQS2 DQS3 DM0 DM1 DM2 DM3 T6 U8 Y12 T12 DM0 DM1 DM2 DM3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 V16 Y18 T15 U16 V17 W18 Y19 Y20 W19 W20 T16 U17 V18 T17 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 BA0 BA1 V14 T13 BA0 BA1 CSN WEN RASN CASN U14 V15 T14 U15 CSN WEN RASN CASN CLK0 CLKN0 Y14 W14 CLK0 CLKN0 R110 R111 0 0 CLK1 CLKN1 Y15 W15 CLK1 CLKN1 R112 R113 0 0 CKE U13 CKE CLK2 CLKN2 Y16 W16 SDICLK SDOCLK Y3 W3 SDICLK SDOCLK CLK3 CLKN3 Y17 W17 R208 RDATA0 RDATA1 RDATA2 RDATA3 D 33 U7B SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 7 RN4D RN13A RN4C RN13B DATA4 DATA5 DATA6 DATA7 RN13C RN4B RN13D RN4A RDATA4 RDATA5 RDATA6 RDATA7 RN14A RN5D RN5C RN14B RDATA8 RDATA9 RDATA10 RDATA11 RN5B RN5A RN6C RN6D RDATA12 RDATA13 RDATA14 RDATA15 33 DATA8 DATA9 DATA10 DATA11 DQS0 DQS1 R219 RN14C 33 33 RDQS0 RDQS1 DQS2 DQS3 RN7A R220 33 33 RDQS2 RDQS3 DM0 DM1 R218 RN14D 33 33 RDM0 RDM1 DM2 DM3 RN8D R221 33 33 RDM2 RDM3 RDQS[3:0] 8 RDM[3:0] 8 33 DATA12 DATA13 DATA14 DATA15 RADDR[13:0] 8 33 DATA16 DATA17 DATA18 DATA19 RN6A RN6B RN15A RN7D ADDR0 ADDR1 ADDR2 ADDR3 RDATA16 RDATA17 RDATA18 RDATA19 RN9D RN9B RN18A RN18B RADDR0 RADDR1 RADDR2 RADDR3 RN9C RN9A RN10D RN10B RADDR4 RADDR5 RADDR6 RADDR7 RN10C RN10A RN18C RN18D RADDR8 RADDR9 RADDR10 RADDR11 RN19B RN19A RN19C RN19D RADDR12 RADDR13 33 33 DATA20 DATA21 DATA22 DATA23 DQS[3:0] RN15B RN7C RN7B RN15C ADDR4 ADDR5 ADDR6 ADDR7 RDATA20 RDATA21 RDATA22 RDATA23 C 33 33 DATA24 DATA25 DATA26 DATA27 DM[3:0] RN15D RN16B RN8C RN8B ADDR8 ADDR9 ADDR10 ADDR11 RDATA24 RDATA25 RDATA26 RDATA27 33 33 ADDR12 ADDR13 ADDR[13:0] DATA28 DATA29 DATA30 DATA31 RN8A RN16C RN16A RN16D RDATA28 RDATA29 RDATA30 RDATA31 33 33 33 R222 RN17A 33 RBA0 RBA1 8 8 RCSN RWEN RRASN RCASN 8 8 8 8 B RN17B RN17C R223 33 RN17D 33 RCLK0 RCLKN0 8 8 RCLK1 RCLKN1 8 8 KSZ9692PB A A MICREL SEMICONDUCTOR Title SoC Test Board 5 4 3 2 Size Custom Document Number Memory Bus Date: Tuesday, February 01, 2011 Rev 1.0 Sheet 1 3 of 20 5 4 3 2 1 +5V V3.3 AMP 787170-4 U7A STEWARD HI1206N101R-00 E5 D2 D1 F6 PCLKOUT0 PCLKOUT1 PCLKOUT2 PCLKOUT3 B2 C3 C1 E6 D3 B1 D4 E4 D5 C4 C2 B8 E9 D9 A9 B9 C9 A10 A8 B7 C8 C10 E10 A7 A6 A1 PCLK PRSTN REQ1N REQ2N REQ3N GNT1N GNT2N GNT3N PMBS M66EN MPCIACTN IRDYN TRDYN FRAMEN DEVSELN STOPN SERRN PERRN CLKRUNN IDSEL PAR CBEN0 CBEN1 CBEN2 CBEN3 PMEN R270 10K D R273 4.7K V3.3 R155 R263 A20 A19 B19 B20 C19 C20 D20 1K SCKIN 10K I2S_SDI I2S_SDO I2S_LRCLK I2S_BCLK I2S_MCLK SCKIN SCKOUT JP1 RSPI_RDY 1 2 3 4 5 6 CS_SoC 1 2 3 4 5 6 CS_SoC RSPI_RDY MISO_SoC MOSI_SoC CK_SoC MISO_SoC MOSI_SoC CK_SoC SPI/I2C<=>SoC C R272 V3.3 R261 1K D15 F13 D16 D17 E14 SPI_CS SPI_RDY SPI_MISO SPI_MOSI_SDA SPI_CK_SCL C17 E13 C16 C15 C18 D14 C14 D13 KDATA0 KDATA1 KDATA2 KDATA3 KCLK KCMD KSDCDN KSDWP W2 Y2 V1 V2 P5 TEST1 TEST2 TESTEN1 TESTEN SCANEN PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 E12 D12 C13 F12 B13 C12 A13 B12 D11 E11 A12 C11 B11 A11 B10 D10 D8 C7 E8 B6 A5 A4 B5 C6 C5 D7 A3 B4 A2 D6 E7 B3 GPIO0/EINT0 GPIO1/EINT1 GPIO2/EINT2 GPIO3/EINT3 GPIO4/TOUT0 GPIO5/TOUT1 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 U18 V19 T18 V20 U19 U20 E18 E20 E19 E17 E16 F14 D19 E15 D18 B18 B17 B16 B15 B14 TDI TDO TRSTN TCK TMS A16 A15 A14 A18 A17 U1_CTSN U1_DSRN U1_DCDN U1_TXD U1_RXD U2_TXD U2_RXD U3_TXD U3_RXD U4_TXD U4_RXD R19 P15 R20 R16 P16 R17 R15 N15 R18 T20 T19 10K R211 R101 R97 R93 R199 V3.3 V3.3 R276 10K R275 10K R253 0 Host G16 G15 R274 3.4K 1% H16 F18 F15 F17 F16 USB_U1P G19 USB_U1M G20 F19 F20 Y6 G17 G18 C108 USB_V3.3 R277 1K 0 0 0 0 0 USB_V3.3 C107 USB_TEST USB_CFG USB_REXT USB_HOVC0 USB_HOVC1 USB_HPWR0 USB_HPWR1 USB_U1P USB_U1M USB_U2P USB_U2M USB_XI USB_XO RESETN WRSTO R5 N5 XCLK2 XCLK1 W1 Y1 FB12 1 R271 10K 22PF 48MHZ Crystal CLK25MHZ H19 MDIO MDC H17 H18 P1_TXD0 P1_TXD1 P1_TXD2 P1_TXD3 P1_RXD0 P1_RXD1 P1_RXD2 P1_RXD3 P1_TXC P1_TXEN P1_RXC P1_RXER P1_RXDV P1_COL P1_CRS R195 MDIO MDC R191 0 J20 J18 J19 H20 M20 L18 L19 L20 J17 J16 K19 K17 K16 K20 K18 R63 R67 R70 R75 33 Ohm 33 Ohm 33 Ohm 33 Ohm N19 N20 M19 L17 N16 P17 N17 P18 M18 L16 M16 P19 N18 P20 M17 R91 R95 R98 R102 33 Ohm 33 Ohm 33 Ohm 33 Ohm R103 R108 33 Ohm 33 Ohm R78 R85 MDIO MDC P1_RXD3 P1_RXD2 P1_RXD1 P1_RXD0 P1_RXDV P1_RXC P1_RXER 33 Ohm J4 33 Ohm 33 Ohm P1_TXD0 P1_TXD1 P1_TXD2 P1_TXD3 P1_RXD0 P1_RXD1 P1_RXD2 P1_RXD3 P1_TXC P1_TXEN P1_RXC P1_RXER P1_RXDV P1_COL P1_CRS P1_TXC P1_TXEN P1_TXD0 P1_TXD1 P1_TXD2 P1_TXD3 P1_COL P1_CRS R88 R72 R117 R116 R131 R92 R133 0 0 0 0 0 0 0 R151 0 R153 R152 R132 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GPIO[19:0] GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 7,10,11 P0_TXD0 P0_TXD1 P0_TXD2 P0_TXD3 P0_RXD0 P0_RXD1 P0_RXD2 P0_RXD3 P0_TXC P0_TXEN P0_RXC P0_RXER P0_RXDV P0_COL P0_CRS 16 16 16 16 16 U1_CTSN U1_DSRN 10 10 U1_TXD U1_RXD U2_TXD U2_RXD 10 10 10 10 +5V 33 Ohm 33 Ohm 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D AMP 787170-4 STEWARD HI1206N101R-00 FB13 1 2 FBEAD U20 P0_TXC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 R167 0 P0_RXC R161 0 P0_RXD0 R162 0 P0_RXD1 R157 0 P0_RXD2 R154 0 P0_RXD3 R156 0 P0_RXDV R163 0 NC TXC NC NC NC RXC NC NC NC RXD0 NC RXD1 NC RXD2 NC RXD3 NC RXDV NC NC NC TXD0 NC TXD1 NC TXD2 NC TXD3 NC TXEN NC TXER NC RXER MDC COL MDIO CRS NC NC 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P0_TXD0 P0_TXD1 C P0_TXD2 P0_TXD3 P0_TXEN DNI P0_TXER R169 49.9 P0_RXER R171 49.9 P0_COL R170 49.9 P0_CRS MDC MDIO RGMII Female Connector UART 3,and 4 R201 R197 VCC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCC Female MII Connector P0_TXD0 P0_TXD1 P0_TXD2 P0_TXD3 P0_RXD0 P0_RXD1 P0_RXD2 P0_RXD3 P0_TXC P0_TXEN P0_RXC P0_RXER P0_RXDV P0_COL P0_CRS KSZ9692PB TDI TDO TRSTN TCK TMS VCC MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL CRS VCC MAC Mode MII MII Port RESETN WRSTO 16 16 RGMII Port R100 22PF 2 FBEAD U7D 1M KSZ9692PB Y2 R260 10K FB22 C244 C249 4.7uF/10V USB_V3.3 R262 12K 1% USB_U1M USB_U1P 0.01uF 7,16 G_RESETN R269 FB23 1K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND OSCI OSCO VPHY GND REF DM DP VPLL AGND GND VCORE TEST RESET# GND SK_A FBEAD C250 C251 FT2232H 4.7uF/10V C253 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCORE EECS EECLK EEDATA PWREN# GPIOH7_B GPIOH6_B GPIOH5_B VCCIO GPIOH4_B GPIOH3_B GPIOH2_B GPIOH1_B GND VREGIN VREGOUT USB_V3.3 FBEAD U19 22PF 12MHZ Crystal 22PF C65 25MHZ Crystal 22PF C252 DO_A DI_A CS_A VCCIO GPIOL0_A GPIOL1_A GPIOL2_A GPIOL3_A GND GPIOH0_A GPIOH1_A GPIOH2_A GPIOH3_A GPIOH4_A VCCIO GPIOH5_A 22PF C106 USB_V1.8 C254 C255 B 3.3uF/10V 0.01uF GPIOH0_B GND GPIOL3_B GPIOL2_B GPIOL1_B GPIOL0_B VCCIO CS_B DI_B DO_B SK_B VCORE GN GND GPIOH7_A GPIOH6_A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 0.01uF 0.01uF USB_V3.3 C256 0.01uF C257 0.01uF C258 0.01uF C259 0.01uF C260 0.01uF 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C105 B C68 USB_V1.8 Y5 0.01uF JP3 CS_USB MISO_USB MOSI_USB CK_USB A 1 2 3 4 5 6 CS_USB 1 2 3 4 5 6 MISO_USB MOSI_USB CK_USB A SPI/I2C<=>USB MICREL SEMICONDUCTOR Title SoC Tset Board 5 4 3 2 Size Custom Document Number Peripherals Date: Tuesday, February 01, 2011 1 Rev 1.0 Sheet 4 of 20 5 4 3 2 V1.2 SOC_V3.3 C125 Place V1.2 bypass caps next to BGA power pins D C151 0.01uF 0.1uF U7C V1.2 V1.2 C123 C148 C124 C152 0.1uF 0.01uF 0.01uF 0.1uF 1 C132 C149 C150 0.01uF 0.01uF C131 C147 C160 0.1uF USB1VDD1.2 USB2VDD1.2 M5 PLLSVDD1.2 P6 PLLDVDD1.2 PLLVDDA3.3 0.1uF M7 M6 N6 G7 G8 G9 P11 P12 P13 P14 N14 M14 M15 G12 G14 G13 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 K6 J6 H6 G6 F7 F8 F9 F10 F11 G10 G11 H14 J14 K14 K15 L15 VDD1.2 VDD1.2 VDD1.2 VDD1.2 VDD1.2 VDD1.2 VDD1.2 VDD1.2 VDD1.2 VDD1.2 VDD1.2 VDD1.2 VDD1.2 C134 0.01uF Place SOC_V3.3 bypass caps next to BGA power pins D L6 USB1VDDA3.3 USB2VDDA3.3 USBCVDDA3.3 V1.2 0.01uF 0.1uF J15 H15 C139 0.1uF SOC_V3.3 SOC_V3.3 C129 0.01uF C135 C144 0.01uF 0.01uF C142 C141 0.1uF 0.1uF C127 0.01uF C130 0.1uF C128 0.1uF C143 0.01uF C126 0.1uF V2.5 Place V2.5 bypass caps next to BGA power pins C C162 C164 C168 C170 C166 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF C169 0.1uF C167 0.1uF C165 0.1uF C163 0.1uF B R6 R7 R8 R9 R10 R11 R12 R13 R14 T8 T9 T10 T11 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 J12 H12 USBVSS1 USBVSS2 H13 J13 K13 USBVSSA3.3 USBVSSA3.3 USBVSSA3.3 N7 N8 PLLVSS1.2 PLLVSS1.2 M8 PLLVSSA3.3 L8 PLLVSSISO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H7 H8 H9 H10 H11 J7 J8 J9 J10 J11 K7 K8 K9 K10 K11 K12 L7 L9 L10 L11 L12 L13 L14 M9 M10 M11 M12 M13 N9 N10 N11 N12 N13 P7 P8 P9 P10 C B KSZ9692PB Place caps close to the group of respective voltage pins V2.5 C70 C188 C67 C69 10uF/10V 10uF/10V 10uF/10V 10uF/10V SOC_V3.3 V1.2 A C178 C117 C181 C161 C146 10uF/10V 10uF/10V 10uF/10V 10uF/10V 10uF/10V C171 0.1uF C155 0.1uF C154 0.1uF C115 C114 C116 C122 10uF/10V 10uF/10V 10uF/10V 10uF/10V A C120 0.1uF MICREL SEMICONDUCTOR Title SoC Tset Board 5 4 3 2 Size Custom Document Number KSZ9692PB Power Date: Tuesday, February 01, 2011 Rev 1.0 Sheet 1 5 of 20 5 4 3 2 1 V3.3 V3.3 V3.3 Not Support NAND Boot DNP R34 DNP DNP R79 R33 4.7K 4.7K 4.7K SADDR6 SADDR0 D SADDR3 Internal Pull-Down: NAND boot device small page size 512 byte (default) Internal Pull-Down: NAND boot device small block size (default) External Pull-Up: NAND boot device small page size 528 byte External Pull-Up: NAND boot device large block size Internal Pull-Down: NAND FLASH device does not support automatic page crossing (default) D External Pull-Up: NAND FLASH device supports automatic page crossing Not Support NAND Boot V3.3 V3.3 V3.3 V3.3 DNP R35 R38 4.7K 4.7K DNP R39 4.7K R37 Port 1 Set to MII Port 0 RGMII 4.7K Set to SADDR11 SADDR7 SADDR8 3,7 ERWEN0 C C External Pull-Up: 16-bit boot device Internal Pull-Down: boot from NOR device (default) Internal Pull-Down: MII mode (Default) Internal Pull-Down: MII mode (default) External Pull-Up: boot from NAND device External Pull-Up: External Pull-Up: RGMII mode RGMII mode V3.3 R80 NAND 4.7K 3,7 For Globe Rest at page 7 (NOR), page 12 (WAN LAN), at Page 11 (Generate RESET signal) EROEN B B External Pull-Up: WRSTO is active low Pull-Down: WRSTO is active High (Default) NAND boot device size:128Mbit (default) 3,7 SADDR[23:0] SADDR0 SADDR1 SADDR2 SADDR3 SADDR4 SADDR5 SADDR6 SADDR7 SADDR8 SADDR9 SADDR10 SADDR11 SADDR12 SADDR13 SADDR14 SADDR15 A A MICREL SEMICONDUCTOR Title SoC Tset Board 5 4 3 2 Size Custom Document Number Strap In Options Date: Monday, January 31, 2011 Rev 1.1 Sheet 1 6 of 20 5 4 3 2 1 D D SDATA[15:0] 3 +5V Boot NOR Flash FB14 1 SADDR0 SADDR1 SADDR2 SADDR3 SADDR4 SADDR5 SADDR6 SADDR7 SADDR8 SADDR9 SADDR10 SADDR11 SADDR12 SADDR13 SADDR14 SADDR15 SADDR16 SADDR17 SADDR18 SADDR19 SADDR20 SADDR21 V3.3 C R36 10K 4,16 G_RESETN 3,6 3,6 3 EROEN ERWEN0 RCSN0 Am29LV640T 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10 13 14 12 28 11 26 2 FBEAD U4 3,6 SADDR[23:0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 BYTE# 47 VCC 37 RY/BY 15 ACC RESET OE WE VSS CE VSS 48PIN_TSOP_Standand 46 27 SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 SDATA[15:0] 3 JP2 Ext. I/O Bank 1 Interrupt3 3,6 33 GPIO3 4,11 V3.3 R217 ECSN0 4,11 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 SDATA15 SDATA13 SDATA11 SDATA9 SDATA7 SDATA5 SDATA3 SDATA1 GPIO2 ERWEN0 R224 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SDATA14 SDATA12 SDATA10 SDATA8 SDATA6 SDATA4 SDATA2 SDATA0 G_RESETN R214 R215 R216 R213 33 33 33 33 4,16 C SADDR2 SADDR3 SADDR4 EROEN 3,6 0.1 pitch throu Hole Write WORD Enable??? AM29LV640T V3.3 Static memory data bus pullup C136 C137 10uF/10V B SDATA[15:0] 3 B 0.1uF RN12 1 V3.3 10K SDATA4 2 SDATA123 SDATA5 4 SDATA135 6 V3.3 1 RN11 10K 2 3 4 5 10 9 8 7 SDATA2 SDATA10 SDATA3 SDATA11 V3.3 6 SDATA0 SDATA8 SDATA1 SDATA9 SDATA6 SDATA14 SDATA7 SDATA15 10 9 8 7 A A MICREL SEMICONDUCTOR Title SoC Tset Board 5 4 3 2 Size Custom Document Number NOR Flash Date: Tuesday, February 01, 2011 Rev 1.0 Sheet 1 7 of 20 5 4 3 2 1 Note: Support DDR 32-bit data width D D RDATA[31:0] 3 3 RADDR[13:0] U14 RADDR0 RADDR1 RADDR2 RADDR3 RADDR4 RADDR5 RADDR6 RADDR7 RADDR8 RADDR9 RADDR10 RADDR11 RADDR12 C 3 RBA0 RBA1 26 27 BA0 BA1 3 3 3 3 RWEN RCASN RRASN RCSN 21 22 23 24 WE# CAS# RAS# CS# 3 RCKE 44 CKE 45 46 CK CK# R249 3 RDM0 RDM1 3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 3 3 RCLK0 100 1% 29 30 31 32 35 36 37 38 39 40 28 41 42 20 47 RDM[3:0] 34 48 66 6 12 52 58 64 RCLKN0 Recommend DNP terminator R250 and R249 to get a better DDR clock signal and more stable system U15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 RDATA0 RDATA1 RDATA2 RDATA3 RDATA4 RDATA5 RDATA6 RDATA7 RDATA8 RDATA9 RDATA10 RDATA11 RDATA12 RDATA13 RDATA14 RDATA15 LDQS UDQS 16 51 RDQS0 RDQS1 NC1 NC2 NC3 NC4 NC5 NC6 NC7 14 17 19 25 43 50 53 VREF VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ 49 33 1 18 55 61 3 9 15 LDM UDM VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ RADDR0 RADDR1 RADDR2 RADDR3 RADDR4 RADDR5 RADDR6 RADDR7 RADDR8 RADDR9 RADDR10 RADDR11 RADDR12 RDQS[3:0] 3 RADDR13 3 RBA0 RBA1 26 27 BA0 BA1 3 3 3 3 RWEN RCASN RRASN RCSN 21 22 23 24 WE# CAS# RAS# CS# 3 RCKE 44 CKE 45 46 CK CK# 20 47 LDM UDM R250 3 V2.5 V2.5 RDM2 RDM3 3 RDM[3:0] 34 48 66 6 12 52 58 64 RCLKN1 Recommend DNP terminator R250 and R249 to get a better DDR clock signal and more stable system MT46V32M16P A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 3 3 RCLK1 100 1% 29 30 31 32 35 36 37 38 39 40 28 41 42 VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 RDATA16 RDATA17 RDATA18 RDATA19 RDATA20 RDATA21 RDATA22 RDATA23 RDATA24 RDATA25 RDATA26 RDATA27 RDATA28 RDATA29 RDATA30 RDATA31 LDQS UDQS 16 51 RDQS2 RDQS3 NC1 NC2 NC3 NC4 NC5 NC6 NC7 14 17 19 25 43 50 53 VREF VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ 49 33 1 18 55 61 3 9 15 RDQS[3:0] 3 C RADDR13 Note: RADDR13 is for 1Gb device V2.5 R140 100 1% V2.5 MT46V32M16P R145 R144 100 1% C90 0.1uF C94 0.1uF 100 1% C91 0.1uF R146 C89 0.1uF 100 1% B B V2.5 V2.5 C87 C83 C245 C236 C225 C216 C209 C201 C211 C220 10uF/10V 10uF/10V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C86 C84 C246 C237 C226 C217 C202 C210 C212 C221 10uF/10V 10uF/10V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF A A MICREL SEMICONDUCTOR Title SoC Tset Board 5 4 3 2 Size Custom Document Number DDR Memory Date: Tuesday, February 01, 2011 Rev 1.0 Sheet 1 8 of 20 5 4 3 2 1 V3.3 R264 10K D D J44 4 U2_RXD 4 U1_RXD 4 U1_TXD 2 1 V3.3 HEADER 2 R137 10K UART Male DB9 Connector GPIO12 R243 0 GPIO14 R252 0 U1_DSRN 4 U1_CTSN RTSN V3.3 C T1IN T2IN T3IN 28 24 C1+ C1- 1 2 R268 10K C228 C238 0.1uF 4 14 13 12 0.1uF U2_TXD C85 0.1uF C239 0.1uF R136 VCC 4 R1OUT R2OUT R3OUT R4OUT R5OUT R1IN R2IN R3IN R4IN R5IN T1OUT T2OUT T3OUT 4 5 6 7 8 nU1DSRN nU1RXD nU1RTSN nU1TXD nU1CTSN 9 10 11 R2OUTB 20 INVALID 21 nU1RIN 1 6 2 7 3 8 4 9 5 DB9 MC C2+ C2- C UART port 1 22 23 FORCEOFF FORCEON 27 3 V+ V- GND RIN 19 18 17 16 15 25 4,7,11 GPIO[19:0] P1 26 U16 MAX3243CAI/SSOP28 1K B B A A MICREL SEMICONDUCTOR Title SoC Tset Board 5 4 3 2 Size Custom Document Number UART Date: Tuesday, February 01, 2011 Rev 1.0 Sheet 1 10 of 20 5 4 3 Programmable GPIO LED Indicators 2 1 3.3V POWER LED V3.3 D9 4,7,10 GPIO[19:0] GPIO8 GPIO9 1 D V3.3 D4 2 R181 620 LED 0805 R180 620 1 2 R6 620 LED 0805 D D8 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 1 2 LED 0805 JP44 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 2 4 6 8 10 12 14 16 18 20 22 1 3 5 7 9 11 13 15 17 19 21 HEADER 11x2 C C User Programmable GPIO B B A A MICREL SEMICONDUCTOR Title SoC Tset Board 5 4 3 2 Size Custom Document Number GPIO-LED Date: Tuesday, February 01, 2011 Rev 1.0 Sheet 1 11 of 20 4 3 2 Push Button Reset 2 14 R32 U6C 2 4 D7 1N4148 V3.3 U8A V3.3 1 Power On Reset 6 S1 PORSTN 5 2 1 4 3 SW PUSHBUTTON 1 TRSTN 3 C39 D 7 74LVX02 1 100K 5 74LVX14 D 10uF/10V V3.3 U9 4.7K 4.7K R64 4 R60 Y V3.3 4.7K GND 5 R56 3 VCC 4.7K A R52 NC 2 4.7K From Power On Reset 1 R82 PORST NC7SP05 JTAG Connector U6F JP8 ICE_TRST 12 ICE_nTRST 13 4 4 4 TDI TMS TCK 4 TDO 74LVX14 U6D C 4 RESETN RESETN 8 TDI TMS TCK TDO U6E RESETP 9 10 74LVX14 33 Ohm 33 Ohm 33 Ohm 33 Ohm R76 R83 33 Ohm 33 Ohm 1 3 5 7 9 11 13 15 17 19 DBGRQ Not Supported DBGACK Not Supported ICE_nSRST 11 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20 C HEADER 10X2 74LVX14 V3.3 U8D 4,7 G_RESETN 14 Spare Gates J42 9 J43 RESETP JUMPER 2 1 WRSTO WRSTO 4 7 74LVX14 J40 V3.3 U6A JUMPER 8 10 74LVX02 U6G R53 R57 R61 R65 JUMPER J41 JUMPER V3.3 GND VCC 14 B C118 74LVX14 C138 0.1uF 4.7K 7 4.7K B New for globe reset 14 U8C R74 U8B R87 0.1uF 14 5 11 4 13 6 12 7 74LVX02 74LVX02 7 4.7K V3.3 U6B A R55 A 4 3 MICREL SEMICONDUCTOR 74LVX14 Title SoC Test Board Rev 5 4 3 2 Size Custom Document Number JTAG - RESET Date: Tuesday, February 01, 2011 Rev 1.1 Sheet 1 16 of 20 5 4 3 2 1 V2.5 TP7 V3.3 U12 VIN VBIAS VOUT 5 +5V D C77 C79 2 10uF/10V 0.1uF 6 3 C74 C73 TAB GND ADJ MIC49300 0.1uF 1 D C71 C82 C81 10uF/10V 0.1uF C93 + TBD uF 330uF/10V DNP R118 511 1% 1uF/10V R109 976 1% 4 Note: V2.5 must be adjusted to 2.6V for Micron DDR device MT46V32M16-5B. See Micron Electrical Specification. For DDR devices that require 2.5V, install 1K in R109, 562 ohm in R118 C C Ground Test Points TP10 TP9 TP4 TP12 TP3 TP11 B B A A MICREL SEMICONDUCTOR Title SoC Tset Board 5 4 3 2 Size Custom Document Number DDR Power Date: Monday, January 31, 2011 Rev 1.0 Sheet 1 17 of 20 5 4 3 2 1 D D +5V L1 V1.2 TP2 U2 C12 0.1uF 1 10 C10 R11 10uF/10V 10 4 BIAS 2 1 uH C17 D1 SSA33L R3 0.1uF 1 82pF R12 6.65K 1% C11 10uF/10V SW SW 1 C9 VIN VIN 2.7 1% 2 9 C4 4.7uF/6.3V C28 + C3 330uF/10V 0.1uF 10K 7 PGOOD 6 EN C5 33K 1% R14 2 C14 0.1uF 680pF 47K 11 3 8 EP AGND PGND R13 V3.3 C FB C 5 R15 MIC4724 C18 0.1uF Note: RC added to EN control to enforce power sequencing B B A A MICREL SEMICONDUCTOR Title SoC Tset Board 5 4 3 2 Size Custom Document Number 1.2V Power Date: Tuesday, February 01, 2011 Rev 1.0 Sheet 1 18 of 20 5 4 3 2 1 +5V R1 0.012 Ohms + C2 + 68UF/10V C1 68UF/10V D D R10 10 0.1uF 5V DC Jack Q1 1 2 3 C15 U1 J12 1 VIN CS 4 2 COMP OUTP 8 5 VDD OUTN 7 6 GND FB 3 4 V3.3 2 3 1 C30 + 47uF/10V C6 R5 18.2K 1uF/10V C16 5 6 7 8 L2 Si4825DY 1 TP1 2 2.5 uH MIC2193YM 1uF/10V 1 Q2 5 6 7 8 C7 0.0027uF D6 1N5819HW 4 + C13 + 220UF/10V C8 220UF/10V R9 10K 1% C 2 1 2 3 C Si4858DY R7 6.04K SOC_V3.3 TP5 V3.3 B B FB4 FBEAD C54 + C57 330uF/10V C56 0.1uF 0.01uF USB_V3.3 TP6 V3.3 FB5 FBEAD C55 + 10uF/10V A C58 0.1uF C59 0.01uF A MICREL SEMICONDUCTOR Title SoC Test Board 5 4 3 2 Size Custom Document Number 3.3V Power Date: Tuesday, February 01, 2011 Rev 1.0 Sheet 1 19 of 20