ICs for TV
AN5491K
Synchronous signal and deflection distortion correction processing IC
supporting I2C bus for HD, wide television
• Supports the multiple-point horizontal frequency
(15.7 kHz to 62.7 kHz)
• Horizontal duty is controllable by external voltage.
• Built-in full functions for correction
(Horizontal and vertical: 16 items)
• Over-current detection, shut-down and hold-down
0.5±0.1
1.778
■ Features
36.8±0.3
The AN5491K is a deflection processor IC for synchronous signal processing and screen distortion correction. It synchronizes with the input signal of High-vision,
wide television, NTSC, PAL and VGA by the external
binary input signal of them so that a multimedia television
can be realized easily.
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
0.9±0.25
Unit: mm
■ Overview
0.96±0.25
3.3±0.25
13.7±0.3
4.76±0.25
3° to 15°
15.3±0.25
+0.1
0.3 –0.05
SDIP042-P-0600A
■ Applications
• High-vision televisions, Wide screen televisions and
Projection televisions
1
2
H-AFC2
FBP in 41
H-OSC 42
H-duty adj. 39
40
Gain-SW
Shut down
det.
X-ray
det.
36
HP
slice
H-out 38
H
AFC1
Lock det. 37
6
5
V-BLK
gen.
Counter
input
34
Counter
2
27
7
H-GND
19
25
26
31
35
2
GND
33
7
I2L
Sync. DEF DAC
BOW
I2C
decode
Data
latch
Trapezoid
crrection
V-latch
pulse
V/I
converter
VP
slice
V
OSC
V-AGC
timing
H-parabola
Trape
V-SAW
correction
V-S
Ramp
/AGC
V EHT-AC
EHT
out
correction
Latch-SW
V-amp.
Phase
crrection
V-LIN
EW H-WID Phase V-POS
out Parallel out
POL
32
4
VGA
30
Counter PG Counter decode
× 32
×8
×4
×2
×1
29
Counter BF
Corner level
Corner
correction
EW out
28
Upper
Lower
Phase out
24
2 2 2
DEF GND
fH switch
input
V-out
Lock
det.
EHT-AC
H
out
V- EHT
H- EHT
23
H
duty
EHT-DC
H
AFC2
22
H-POS
AGC
H
VCO
AN5491K
ICs for TV
■ Block Diagram
21
20
18
17
16
15
14
13
10
9
8
7
6
5
4
3
2
1
Trapezoid
Ramp
V-OSC
VS2
VP in
DEF VCC
SCL
SDA
12
I2L VCC
11
V-SAW in
V-SAW lower
V-SAW upper
BLK out
Comparator out
Comparator in
Comparator ref.
Shut down
H-VCC
H-pulse in
H-AFC1
ICs for TV
AN5491K
■ Pin Descriptions
Pin No.
Description
Pin No.
Description
1
H-AFC1
22
V-AGC
2
H-pulse input
23
EHT-DC input
3
H-VCC (6.2 V)
24
EHT-AC input
4
Shut down SW
25
×8
5
Comparator ref. (6.5 V)
26
×4
6
Comparator
27
VGA
7
Comparator output
28
V-output
8
BLK output
29
DEF GND
9
V-SAW slice voltage (High)
30
Phase output
10
V-SAW slice voltage (Low)
31
×2
11
V-SAW input
32
EW output
12
I2L
VCC (5 V)
33
Corner slice voltage
13
I2C
SDA input
34
I2L GND
14
I2C SCL input
35
×1
15
DEF VCC (9 V)
36
H-GND
16
V-pulse input
37
Lock det.
17
V-pulse output
38
H-output
18
V-OSC
39
H-duty
19
× 32
40
H-AFC2
20
V-ramp
41
FBP input
21
Trapezoid correction voltage
42
H-OSC
■ Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
VCC
Supply current
Power dissipation
ICC
*2
Operating ambient temperature
Storage temperature
*1
*1
Rating
Unit
VCC1
5.6
VCC2
10
ICC1
24
ICC2
29
I3
14
V
mA
PD
600
mW
Topr
−20 to +70
°C
Tstg
−55 to +150
°C
Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C.
*2: The power dissipation shown is for the independent IC without a heat sink in free air at Ta = 70°C.
3
AN5491K
ICs for TV
■ Recommended Operating Range
Parameter
Supply voltage
Symbol
Range
Unit
VCC1
4.5 to 5.0 to 5.5
V
VCC2
8.1 to 9.0 to 9.9
■ Electrical Characteristics at Ta = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC characteristics
Circuit current ICC1
I12
VCC1 = 5 V, VCC2 = 9 V
13.6
17.0
20.4
mA
Circuit current ICC2
I15
VCC1 = 5 V, VCC2 = 9 V
16.8
21.0
25.2
mA
Circuit current ICC3
I3
VCC1 = 5 V, VCC2 = 9 V,
VCC3 = 6.5 V
6.0
7.5
9.0
mA
Synchronizing signal processing
4
Horizontal free-running oscillation
frequency 1 [Divide-by-8]
fHO8
Pin 2: Without input, Pin 25: High
Pins 19, 26, 31, 35: Low
61.5
62.7
63.9
kHz
Horizontal free-running oscillation
frequency 2 [Divide-by-16]
fHO16
Pin 2: Without input
Pins 19, 25, 26, 31, 35: Low
30.8
31.4
32.0
kHz
Horizontal free-running oscillation
frequency 3 [Divide-by-32]
fHO32
Pin 2: Without input
Pin 19: High
15.4
15.7
16.0
kHz
Horizontal output pulse duty cycle 1
[Divide-by-32]
τHO1
Pin 2: Without input, Pin 39: 2 V
Pin 19: High
11.7
14.0
16.6
µs
Horizontal output pulse duty cycle 2
[Divide-by-32]
τHO2
Pin 2: Without input, Pin 39: 5 V
Pin 19: High
23.9
28.5
33.7
µs
Horizontal high-level output voltage
VFHH
DC voltage for pin 38 high-level
2.8
3.5
4.2
V
Horizontal low-level output voltage
VFHL
DC voltage for pin 38 low-level
0
0.3
V
Horizontal output start voltage
VFHS
Minimum voltage of pin 3 to become f > 10 kHz when horizontal
oscillation output is 1 V[p-p] or
more in divide-by-32 mode.
4.2
5.0
V
Screen center variable range 1
[Divide-by-16]
tDH16
Pin 25: Low,
Pins 19, 26, 31, 35: High
Change amount of phase difference
between HP and H-out of Data 08:
[00] to [1F]
2.16
2.70
3.24
µs
Screen center variable range 2
[Divide-by-32]
tDH32
Pin 19: Low,
Change amount of phase difference
between HP and H out of Data 08:
[00] to [1F]
3.8
4.8
5.8
µs
Horizontal input pulse threshold voltage
VT2
Slice level of pin 2
0.9
1.5
2.1
V
Over-voltage protective operation
voltage
V4
Pin 4 voltage at I4 = 50 µA
0.60
0.75
0.90
V
ICs for TV
AN5491K
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Deflection correction processing
VP pulse for OSD low-level
VLOSD
VCC1 = 5 V, VCC2 = 9 V
0
0.4
V
VP pulse for OSD high-level
VHOSD
VCC1 = 5 V, VCC2 = 9 V
2.2
2.75
3.3
V
EHT-AC input pin voltage
V24
Pin 24: Open
2.00
2.45
2.90
V
Vertical input signal threshold voltage
VTFV
Pin 16: Input
0.9
1.5
2.1
V
35
44
53
Hz
Vertical free-running oscillation
frequency
fVO
Pin 16: Without input
external R = 10 kΩ, C = 3.3 µF
Typical vertical output amplitude
VV
V amplitude DAC: Typ.
0.88
1.10
1.32
V[p-p]
Typical EW output amplitude
VEW
EW output amplitude for typical vertical output amplitude = 1.25 V[p-p]
0.8
1.0
1.2
V[p-p]
Phase out amplitude
VPHASE
Side pin parallel, DAC: Typ.
− 0.1
0
0.1
V[p-p]
Ramp waveform amplitude
VRAMP
fV = 50 Hz to 120 Hz
2.15
2.45
2.75
V[p-p]
IAGC
1.6
2.0
2.4
mA
Service SW: ON time
Vertical output DC
V28SW
3.1
3.5
3.9
V
BLK pulse high-level
VHBLK
4.5
5.0
5.5
V
BLK pulse low-level
VLBLK
0
0.4
V
AGC input and output current
Vertical output amplitude
variable ratio (max.)
∆VAMPmax V amplitude ratio between
typ. → max.
+40
+50
+60
%
Vertical output amplitude
variable ratio (min.)
∆VAMPmin V amplitude ratio between
typ. → max.
−40
−50
−60
%
Vertical output DC variable amount (min.) ∆VSHIFTmin Vertical DC: Typ. → min.
− 0.28 − 0.38 − 0.48
V
Vertical output DC variable amount (max.) ∆VSHIFTmax Vertical DC: Typ. → max.
+0.28 +0.38 +0.48
V
Vertical output trapezoidal waveform ∆VTRAPmin Trapezoidal waveform correction: − 0.28 − 0.38 − 0.48
correction variable amount (min.)
Typ. → min.
V
Vertical output trapezoidal waveform ∆VTRAPmin Trapezoidal waveform correction: +0.28 +0.38 +0.48
correction variable amount (max.)
Typ. → max.
V
External trapezoidal waveform
center voltage
V21
2.4
3.0
3.6
V
Vertical output center DC level
V28
2.8
3.5
4.2
V
EW output (min.) to parabolic
amplitude change
VEWmin
Parabolic amplitude: Min.
− 0.1
0
0.1
V[p-p]
EW output (max.) to parabolic
amplitude change
VEWmax
Parabolic amplitude: Max.
1.4
1.8
2.2
V[p-p]
EW output (min.) (DC)
to horizontal amplitude change
∆VEWmin Horizontal amplitude: Min.
− 0.95 −1.15 −1.35
V
EW output (max.) (DC)
to horizontal amplitude change
∆VEWmax Horizontal amplitude: Max.
+0.95 +1.15 +1.35
V
EW output (bottom voltage) 1
to EHT-DC change
∆VEDC1 EHT-DC: 5.0 V → 3.8 V
Horizontal EHT: Max.
EHT-AC gain: Min.
+1.04 +1.30 +1.56
V
5
AN5491K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Deflection correction processing (continued)
EW output (bottom voltage) 2
to EHT-DC change
∆VEDC2 EHT-DC: 5.0 V → 6.2 V
Horizontal EHT: Max.
EHT-AC gain: Min.
−1.04 −1.30 −1.56
V
EW output (bottom voltage) 1
to EHT-AC change
∆VEAC1 EHT-AC: 2.35 V → 1.35 V
Horizontal EHT: Max.
EHT-AC gain: Max.
+0.25 +0.35 +0.45
V
EW output (bottom voltage) 2
to EHT-AC change
∆VEAC2 EHT-AC: 2.35 V → 3.35 V
Horizontal EHT: Max.
EHT-AC gain: Max.
− 0.25 − 0.35 − 0.45
V
EW output parabolic DC level
V32
Typ.
2.2
2.7
3.4
V
Parallelogram correction fluctuation 1 ∆VUPH1 Parallelogram correction:
(upper side)
Typ. → min.
+0.16 +0.26 +0.36
V
Parallelogram correction fluctuation 2 ∆VUPH2 Parallelogram correction:
(upper side)
Typ. → max.
− 0.16 − 0.26 − 0.36
V
Parallelogram correction fluctuation 3 ∆VBPH1 Parallelogram correction:
(lower side)
Typ. → min.
− 0.25 − 0.35 − 0.45
V
Parallelogram correction fluctuation 4 ∆VBPH2 Parallelogram correction:
(lower side)
Typ. → max.
+0.16 +0.26 +0.36
V
Bow shape correction fluctuation 1
(upper side)
∆VUSD1 Bow shape correction:
Typ. → min.
− 0.24 − 0.34 − 0.44
V
Bow shape correction fluctuation 2
(upper side)
∆VUSD2 Bow shape correction:
Typ. → max.
+0.12 +0.22 +0.32
V
Bow shape correction fluctuation 3
(lower side)
∆VBSD1
Bow shape correction:
Typ. → min.
− 0.17 − 0.27 − 0.37
V
Bow shape correction fluctuation 4
(lower side)
∆VBSD2
Bow shape correction:
Typ. → max.
+0.12 +0.22 +0.32
V
I2C interface
SCL, SDA input threshold voltage
VTH
VCC1 = 5 V
1.5
3.0
dB
Sink capacity at ACK
VACK
I = 3 mA in case of pull-up resistor
1.6 Ω
0.4
V
Maximum clock frequency
fSCL
100
kHz
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
τAGC
95
µs
Ramp discharge current
IRAMP1
3.6
mA
Ramp charge current 1
IRAMP2
f = 120 Hz, Pin 4: 5.7 V
138
µA
Ramp charge current 2
IRAMP3
f = 30 Hz, Pin 4: 7.5 V
32.9
µA
DC characteristics
AGC pulse width
6
ICs for TV
AN5491K
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VBLK
4
5
6
V
I28
−2
mA
DC characteristics (continued)
BLK output amplitude
Vertical output drive current
Vertical output amplitude fluctuation
with supply voltage
VV
∆VCC
Difference of VCCmax − VCCmin
0.1
V
Vertical output DC fluctuation
with supply voltage
V28
∆VCC
Difference of VCCmax − VCCmin
1.0
V
EW output amplitude fluctuation
with supply voltage
VEW
∆VCC
Difference of VCCmax − VCCmin
0.1
V
EW output DC fluctuation
with supply voltage
V32
∆VCC
Difference of VCCmax − VCCmin
1.0
V
Horizontal free-running oscillation
frequency [Divide-by-15]
fHO15
Pin 2: Without input, Pin 19: Low
Pins 25, 26, 31, 35: High
32.9
33.5
34.1
kHz
Horizontal output pull-in range
[Divide-by-8]
fHP8
Pin 2: Without input, Pin 25: High ±2 000 ±2 600
Pins 19, 26, 31, 35: Low
Hz
Comparator detection operation voltage
V6
Pin 6: Minimum voltage to become
high, Pin 5: 6.2 V
5.7
6.3
6.9
V
Lock detection output voltage
V37
V37 in horizontal AFC lock mode
5.7
6.3
6.9
V
Lock detection charge and discharge
current
ILOCK
DC measurement in divide-by-32
±0.8
mA
FBP (AFC2) slice level
VTFBP
Minimum voltage of pin 41 at
which AFC operates.
1.5
1.9
2.3
V
Synchronizing signal processing
Horizontal AFC µ
µ
DC measurement in divide-by-32
37
µA/µs
Horizontal VCO β
β
Slant of β curve near f = 15.7 kHz
1.9
Hz/mV
FBP allowable range 1
[Divide-by-8]
tFBP8
Time from H-out rise to FBP
center
3
9
µs
FBP allowable range 2
[Divide-by-16]
tFBP16
Time from H-out rise to FBP
center
4
13
µs
FBP allowable range 3
[Divide-by-32]
tFBP32
Time from H-out rise to FBP
center
6
20
µs
AFC1 reference current 1
IAFC1
Data 0C = "11" (D1, D0)
0.82
mA
AFC1 reference current 2
IAFC2
Data 0C = "01" (D1, D0)
1.1
mA
AFC1 reference current 3
IAFC3
Data 0C = "10" (D1, D0)
1.5
mA
AFC1 reference current 4
IAFC4
Data 0C = "00" (D1, D0)
2.0
mA
Horizontal output pull-in range 1
[Divide-by-16]
fHP16
Pin 2: Without input
Pins 19, 25, 26, 31, 35: Low
Hz
Horizontal output pull-in range 2
[Divide-by-32]
fHP32
Pin 2: Without input
Pin 19: High
Hz
±1 000 ±1 300
±500
±650
7
AN5491K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Deflection correction processing
8
Vertical output S-shape variable
ratio 1
∆VSC1
Vertical S-shape:
Ratio of min.→max.
−28
%
Vertical output S-shape variable
ratio 2
∆VSC2
Vertical S-shape: Ratio of min.→
max. (Change of V-out 40% to
60% point)
1.5
%
Vertical output (upper side)
linearity variable ratio 1
∆VULIN1 Vertical linearity (upper side):
Typ.→max.
+12
%
Vertical output (upper side)
linearity variable ratio 2
∆VULIN2 Vertical linearity (upper side):
Typ.→min.
−10
%
Vertical output (lower side)
linearity variable ratio 1
∆VBLIN1 Vertical linearity (lower side):
Typ.→max.
+9
%
Vertical output (lower side)
linearity variable ratio 2
∆VBLIN2 Vertical linearity (lower side):
Typ.→min.
−11
%
Vertical output
EHT-DC change 1
∆VEDC1 EHT-DC = 5.0 V → 3.8 V
Vertical EHT: Max., EHT gain: Max.
−30
%
Vertical output
EHT-DC change 2
∆VEDC2 EHT-DC = 5.0 V → 6.2 V
Vertical EHT: Max., EHT gain: Max.
+25
%
Vertical output
EHT-AC change 1
∆VEAC1 EHT-AC = 2.35 V → 1.35 V
EHT: Max., EHT gain: Max.
−12
%
Vertical output
EHT-AC change 2
∆VEAC2 EHT-AC = 2.35 V → 3.35 V
EHT: Max., EHT gain: Max.
+12
%
EW output (min.)
to trapezoidal waveform change
∆VTRAPmin Trapezoidal SW: On,
Trapezoidal: Typ. → min.
−40
%
EW output (max.)
to trapezoidal waveform change
∆VTRAPmax Trapezoidal SW: On,
Trapezoidal: Typ. → max.
+40
%
EW output (min.) to upper corner
trapezoidal waveform change
∆VUCmin Upper corner: Typ. → min.
Corner slice voltage: 1 V
−45
%
EW output (max.) to upper corner
trapezoidal waveform change
∆VUCmax Upper corner: Typ. → max.
Corner slice voltage: 1 V
+45
%
EW output (min.) to lower corner
trapezoidal waveform change
∆VBCmin Lower corner: Typ. → min.
Corner slice voltage: 1 V
−45
%
EW output (max.) to lower corner
trapezoidal waveform change
∆VBCmax Lower corner: Typ. → max.
Corner slice voltage: 1 V
+45
%
External trapezoidal waveform correction ∆VETR1
fluctuation 1 (Parabolic amplitude)
External trapezoidal correction:
3V→2V
−40
%
External trapezoidal waveform correction ∆VETR2
fluctuation 2 (Parabolic amplitude)
External trapezoidal correction:
3V→4V
+40
%
ICs for TV
AN5491K
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
3, 4, 5, 6-bit DAC DNLE
L1
1LSB =
{Data(max.) − Data(00)}/7,15,31,63
0.1
1.0
1.9
LSB/step
7-bit DAC DNLE (Except for 40)
L2
1LSB = {Data(max.) − Data(00)}/127
0.1
1.0
1.9
LSB/step
7-bit DAC DNLE (40 only)
L3
1LSB = {Data(max.) − Data(00)}/127
−1.0
1.0
2.0
LSB/step
I2C
interface
■ Terminal Equivalent Circuits
Pin No.
Equivalent circuit
1
Description
6.5 V
3.15 V
4.3 V
27 kΩ
1
AFC1:
Horizontal frequency detection pin
• Pin for adjusting the frequency of horizontal input pulse and the internal reference pulse.
• Connect a lag lead filter.
Voltage
DC
approx. 4.3 V
5.3 V
2
9V
3V
100 kΩ
2
1 kΩ
1.5 V
3
VCC:
Horizontal system power supply (6.5 V) pin
• Connect an external zener
12 V
330 Ω
3
4
28 kΩ 28 kΩ
4
H-pulse in:
Horizontal synchronizing signal input pin
• Polarity is as shown in the right figure
(Negative).
• Slice level is 1.5 V.
• Input polarity is one polarity only
(not corresponding to both polarities).
6.5 V
AC
1.5 V
H rate
DC
6.5 V
Shut down:
DC
Control pin for shut-down
Normal: GND
• Horizontal output stops (GND) if a voltage
1 VBE and over (more than approx. 0.75 V)
is applied to the pin.
9
AN5491K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
5
6.5 V
Description
Voltage
Comparator ref.:
Reference voltage input pin for comparator
• Attach zener diode externally (approx. 6.2 V)
(Usable as reference voltage for hold-down)
DC
Comparator:
Input pin for comparator detection
• (Usable as pin for hold-down detection)
DC
Comparator out:
Comparator detection output pin
• Connect pull-up resistors outside the IC.
(usable as hold-down control pin)
Note) Use under 400 µA or less.
DC
Normally:
High
5
1 kΩ
6
6.5 V
5
6
1 kΩ
1 kΩ
7
9V
25 kΩ
48.3 kΩ
7
20 kΩ
20 kΩ
8
9V
BLK out:
Blanking pulse output pin
• Normally: Low
At BLK: High (5 V)
DC
At BLK: High
8
99.8 kΩ
9
Upper side slice:
Upper side slice voltage input pin for BLK
pulse generation
9V
Upper side
9
20 kΩ
145 Ω
145 Ω
BLK
10
DC
ICs for TV
AN5491K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
10
Voltage
Lower side slice:
Lower side slice voltage input pin for BLK
Pulse generation
9V
10
DC
Lower side
20 kΩ
145 Ω
BLK
11
9V
V-SAW in:
V-SAW input pin for BLK pulse generation
AC
VCC:
Power supply (5 V) pin for DAC/I2L
• Connect a pass capacitor (0.01 µF) between
pin 12 and GND (pin 19).
DC
5V
25 µA
11
20 kΩ
145 Ω
12
13
5V
SDA:
I2C data input pin
20 µA
13
1 kΩ
14
5V
GND
5V
SCL:
I2C clock input pin
20 µA
5V
14
1 kΩ
15
GND
VCC:
Pin for deflection system power supply (9 V)
• Connect a pass capacitor between the pin
and GND.
DC
9V
11
AN5491K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
16
9V
290 Ω
25 µA
16
30 kΩ
1.5 V
290 Ω
17
9V
17
55 kΩ
18
5V
9V
36 kΩ
18
1 kΩ
V-pulse in:
Vertical sync. signal input pin
• Polarity is as shown in the right figure
(Negative)
• Slice level is 1.5 V.
• Input polarity is only one polarity
(Not correspond to both polarities)
6.5V
150 kΩ
19
AC
(Pulse)
1.5 V
0V
V rate
V-pulse out:
AC
Vertical sync. signal output pin
(Pulse)
• If vertical sync. signal input is present:
2.5 V
Outputs the pulse synchronized with input V.
Not present: Outputs free-running V pulse.
0V
(Usable for microcomputer OSD control)
V rate
V-OSC:
Vertical oscillation pin
• Connect CR.
• Free-running oscillation when there is no
input.
AC
5.8 V
3.1 V
V rate
50 µA
19
Voltage
× 32:
Horizontal free-running oscillation frequency
control pin
• To be used by high/low control.
• Input is controlled by open collector output.
DC
V-ramp pin:
• The pin for generating reference V sawtooth
waveform for IC inside.
• Connect an 0.22 µF mylar capacitor.
AC
30 kΩ
30 kΩ
30 kΩ
20
9V
1kΩ
2.5 V
20
V rate
2.5V
12
0V
ICs for TV
AN5491K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
21
9V
25 µA
21
Description
Voltage
External trapezoidal waveform:
The pin for controlling trapezoidal waveform compensation from outside.
• Used by linking to V-position shift (at AC coupling). typ. 3.0 V
DC
2 V to 4 V
V-AGC:
Vertical AGC pin
• AGC pin to make a vertical output amplitude constant.
• Connect 3.3 µF tantalum capacitor.
DC
145 Ω
22
9V
500 Ω
22
145 Ω
500 Ω
23
9V
3.8 V
23
20 kΩ
EHT-DC:
DC
Pin for extremely high-tension compensation
(EHT)
• DC-coupled to pin.
Operating range:
3.8 V to 6.2 V
5.45 V
24
EHT-AC
Pin for extremely high-tension compensation
• AC-coupled to pin.
9V
25 µA
20 kΩ
25 µA
AC
2.35 V in an
open mode
20 kΩ
24
145 Ω
Operating range:
1.35 V to 3.35 V
145 Ω
25
6.5 V
150 kΩ
25
20 kΩ
× 8:
Horizontal free-running oscillation frequency
control pin
• To be used by high/low control.
• Input is controlled by open collector output.
DC
20 kΩ
13
AN5491K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
26
6.5 V
150 kΩ
26
20 kΩ
Description
Voltage
× 4:
Horizontal free-running oscillation frequency
control pin
• To be used by high/low control.
• Input is controlled by open collector output.
DC
V-FB:
Forced progressive mode pin
• To be used by high/low control.
• At high: Multi-point mode
At low: Progressive mode
DC
V-out:
V sawtooth waveform output pin
• Typ. 1.25 V[p-p]
AC
20 kΩ
27
6.5 V
27
60 kΩ
28
300 Ω
9V
×5
9V
100 Ω
28
×5
0V
290 Ω
29
30
GND:
GND pin for deflection-system circuit (9 V)
9V
290 Ω
30
290 Ω
14
DC
GND
Phase out:
AC
Pin for side pin (Bow shape) correction, parallelogram correction and control pulse output.
DC
• Connect to H-AFC2 pin via 1 µF (non- approx. 3.7 V
polarity) capacitor.
Max.
300 mV[p-p]
ICs for TV
AN5491K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
31
6.5 V
150 kΩ
31
20 kΩ
Description
Voltage
× 2:
Horizontal free-running oscillation frequency
control pin
• To be used by high/low control.
• Input is controlled by open collector output.
DC
EW out:
Parabolic waveform output pin
AC
20 kΩ
32
9V
500 Ω
9V
40 kΩ
32
10 kΩ
300 Ω
1.5 V
33
9V
50 µA
50 µA
33
Corner slice:
DC
The voltage to set a slice point of upper and
lower corner correction.
• The correction gain can be controlled inde- Externally set
pendently by I2C bus for upper and lower, at 0 VDC to
respectively.
1.25 VDC
GND: GND pin for 5 V system (I2C/I2L)
34
35
× 1:
Horizontal free-running oscillation frequency
control pin
• To be used by high/low control.
6.5 V
150 kΩ
35
DC
GND
DC
10 kΩ
36
37
200 Ω
820 µA
37
880 µA
GND: GND pin for 6.5 V system
(Horizontal system)
6.5 V
DC
GND
Lock det.:
DC
Horizontal lock detection pin
• Connect 0.022 µF and 1 MΩ between the At lock mode:
pin and GND.
6V
At unlocked
mode: GND
15
AN5491K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
38
6.5 V
3.2 mA
15 kΩ
Description
Voltage
H-out:
Horizontal output pin
• The length of high-period can be adjusted
by a separate pin.
AC
2.9 V
GND
38
H rate
40 kΩ
39
H-duty:
Pin for controlling the length of high-period
of horizontal output pulse.
• Apply DC voltage from the outside.
6.5 V
124 kΩ
39
DC
1 V to 5 V
10 kΩ
124 kΩ
40
6.5 V
1.9 V
40
3.9 V
41
6.5 V
50 µA
2.7 kΩ
41
42
6.5 V
270 Ω
270 Ω
100 µA
16
DC
1.5 V to 4.5 V
FBP input pin:
AC
• Slices at 1.9 V (in the IC) and then uses
1.9 V
as AFC2 control pulse.
• Do not input any signal under GND insiGND
de the IC.
1.9 V
100 kΩ
42
AFC2:
Horizontal phase detection pin
• Pin for controlling phase difference between horizontal output pulse and FBP.
• Phase out waveform is also connected to
this pin via capacitor.
• Connect 0.015 µF between this pin and
GND.
300 Ω
200 µA
10 kΩ
3.0 V
H-OSC:
AC
Reference oscillation pin (500 kHz)
2.25 V
• Connect CERALOCK (CSB500F48), and
temperature guaranteed (N750) 220 pF
capacitor in series between this pin and
0.5 V[p-p]
GND.
ICs for TV
AN5491K
■ Application Circuit Example
9V
3.3 µF
AGC
EHT DC
22
21
23
20
Trapezoid
Ramp
0.22 µF
24
EHT AC
18
3.3 µF
V-OSC
9 V 10 kΩ
V-out
DEF GND
Phase out
28
17
29
16
30
15
VS2
VP in
9V
14
32
EW out
33
Corner level
13
SCL
4.7 kΩ
SDA
12
V
5V
× 32
×8
×4
×2
×1
27
VGA
I2L
H-GND
1 MΩ
Lock det.
0.22 µF
H-out
V-SAW lower
9
V-SAW upper
8
36
7
37
6
38
5
39
1 µF
6.5 V
40
41
220 pF *1
H-OSC
10
BLK out
Comparator out
Comparator in
4
42
3 6.5 V
H-VCC
330 Ω 12 V
2
1
Comparator ref.
Shut down
10 kΩ
H-AFC2
FBP in
V-SAW in
6.5 V
6.5V
I2L VCC
11
34
GND
H-duty adj.
19
25
26
31
35
DEF VCC
4.7 kΩ
H-pulse in
22 µF 620 Ω
H-AFC1
0.033 µF
*1: Horizontal oscillator
TAFCSB500F48
[Murata Manufacturing Co. Ltd.]
17