INTERSIL HP4936DY

HP4936DY
Data Sheet
August 1999
5.8A, 30V, 0.037 Ohm, Dual N-Channel,
Logic Level Power MOSFET
• Logic Level Gate Drive
• 5.8A, 30V
• rDS(ON) = 0.037Ω at ID = 5.8A, VGS = 10V
• rDS(ON) = 0.055Ω at ID = 4.7A, VGS = 4.5V
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D1(8)
D1(7)
Ordering Information
HP4936DY
PACKAGE
SO-8
4469.3
Features
This power MOSFET is manufactured using an innovative
process. This advanced process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable
and battery-operated products.
PART NUMBER
File Number
BRAND
S1(1)
G1(2)
P4936DY
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HP4936DYT.
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
SO-8
8-8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HP4936DY
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
HP4936DY
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
30
V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
30
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±16
V
Drain Current
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (10µs Pulse Width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
5.8
30
A
A
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
0.02
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 150
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TA = 25oC to 125oC.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V
30
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 9)
1
-
-
V
VDS = 30V, VGS = 0V
-
-
1
µA
VDS = 30V, VGS = 0V, TA = 55oC
-
-
25
µA
VGS = ±16V
-
-
100
nA
ID = 4.7A, VGS = 4.5V (Figures 6, 8)
-
0.042
0.055
Ω
ID = 5.8A, VGS = 10V (Figures 6, 8)
-
0.030
0.037
Ω
VDD = 15V, ID ≅ 1A,
RL = 15Ω, VGEN = 10V,
RGS = 6Ω (Figures 12, 13)
-
10
16
ns
-
10
16
ns
td(OFF)
-
27
40
ns
tf
-
24
35
ns
-
18
25
nC
-
4.5
-
nC
-
2.5
-
nC
-
625
-
pF
-
270
-
pF
-
50
-
pF
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
rDS(ON)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Total Gate Charge
Qg
Gate to Source Charge
Qgs
Gate to Drain Charge
Qgd
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Ambient
RθJA
VDS = 15V, VGS = 10V, ID ≅ 5.8A
(Figures 14, 15)
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 4)
-
-
62.5
oC/W
MIN
TYP
MAX
UNITS
ISD = 1.7A (Figure 7)
-
0.8
1.2
V
ISD = 1.7A, dISD/dt = 100A/µs
-
45
80
ns
Pulse Width <10s (Figure 11)
Device Mounted on FR-4 Material
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
Reverse Recovery Time
VSD
trr
8-9
TEST CONDITIONS
HP4936DY
Typical Performance Curves
30
VGS = 10, 9, 8, 7, 6, 5V
4V
24
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
30
Unless Otherwise Specified
18
PULSE DURATION = 80µs
DUTY CYCLE = 0.8% MAX
12
3V
6
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.8% MAX
TA = -55oC
24
125oC
18
12
6
2, 1V
0
0
0
0.5
1.5
1.0
2.0
2.5
3.5
3.0
0
4.0
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
2
3
4
FIGURE 1. OUTPUT CHARACTERISTICS
FIGURE 2. TRANSFER CHARACTERISTICS
1250
0.10
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
0.08
1000
C, CAPACITANCE (pF)
rDS(ON), DRAIN TO SOURCE
ON STATE RESISTANCE (W)
PULSE DURATION = 80µs
DUTY CYCLE = 0.8% MAX
0.06
VGS = 4.5V
0.04
VGS = 10V
0.02
750
0
6
12
18
24
30
CISS
COSS
500
250
0
CRSS
0
36
0
6
12
18
24
VDS , DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
FIGURE 3. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
10
FIGURE 4.
30
CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
2.00
1.75
VDS = 15V
ID = 5.8A
8
PULSE DURATION = 80µs
DUTY CYCLE = 0.8% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
VGS , GATE TO SOURCE VOLTAGE (V)
6
5
VGS, GATE TO SOURCE VOLTAGE (V)
VGS = 10V
ID = 5.8A
1.50
6
1.25
4
1.00
2
0.75
0
0
4
8
12
16
20
Qg, GATE CHARGE (nC)
FIGURE 5.
GATE TO SOURCE VOLTAGE vs GATE CHARGE
8-10
0.5
-50
-25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 6. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
150
HP4936DY
Typical Performance Curves
0.09
PULSE DURATION = 80µs
DUTY CYCLE = 0.8% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.8% MAX
0.08
rDS(ON), DRAIN TO SOURCE
ON STATE RESISTANCE (W)
ISD, SOURCE TO DRAIN CURRENT (A)
100
Unless Otherwise Specified (Continued)
10
TJ = 150oC
1
TJ = 25oC
0.1
0.01
0.07
0.06
0.05
ID = 5.8A
0.04
0.03
0.02
0.01
0.001
0.2
0
0.4
0.6
0.8
1.0
1.2
0
FIGURE 7. SOURCE TO DRAIN DIODE VOLTAGE
4
6
8
10
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
TO SOURCE VOLTAGE
50
0.4
0.2
40
0
POWER (W)
VGS(TH) VARIANCE (V)
2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, SOURCE TO DRAIN VOLTAGE (V)
ID = 250µA
-0.2
30
20
-0.4
10
-0.6
-0.8
-50
0
0
-25
25
50
75
100
125
150
0.01
TJ, JUNCTION TEMPERATURE (oC)
0.10
1.00
10.00
t, PULSE WIDTH (s)
FIGURE 9. GATE THRESHOLD VOLTAGE VARIANCE vs
JUNCTION TEMPERATURE
FIGURE 10. SINGLE PULSE POWER CAPABILITY vs PULSE
WIDTH
2
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE = 0.5
PDM
0.2
0.1
t1
0.1
0.05
t2
NOTES:
DUTY CYCLE, D = t1/t2
TJ = PD x ZθJA x RθJA + TA
SURFACE MOUNTED
0.02
SINGLE PULSE
0.01
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
1
FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
8-11
10
30
HP4936DY
Test Circuits and Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
50%
10%
FIGURE 12. SWITCHING TIME TEST CIRCUIT
50%
PULSE WIDTH
FIGURE 13. SWITCHING TIME WAVEFORM
VDD
VDS
RL
Qg
Qgd
VGS
Qgs
VGS
+
VDD
VDS
DUT
0
Ig(REF)
Ig(REF)
0
FIGURE 14. GATE CHARGE TEST CIRCUIT
FIGURE 15. GATE CHARGE WAVEFORMS
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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