ISL43210 ® Data Sheet October 30, 2007 Low-Voltage, Single Supply, Single SPDT Analog Switch The Intersil ISL43210 device is a precision, bidirectional, single SPDT analog switch designed to operate from a single +2.7V to +12V supply. Targeted applications include battery powered equipment that benefit from the devices’ low power consumption (5µW), low leakage currents (3nA max), and fast switching speeds (tON = 28ns, tOFF = 20ns). Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This device may be used to “mux-in” additional functionality while reducing ASIC design risk. It’s small package alleviates board space limitations, making it an ideal solution. The ISL43210 is a single committed SPDT, which is perfect for use in 2-to-1 multiplexer applications. FN6563.2 Features • Fully specified at 12V, 5V, and 3.3V supplies for 10% tolerances • ON-resistance (rON) . . . . . . . . . . . . . . . . . . . . . . . . . . 19Ω • rON matching between channels . . . . . . . . . . . . . . . . . . . <1Ω • Low charge injection . . . . . . . . . . . . . . . . . . . . . . . 5pC (Max) • Single supply operation . . . . . . . . . . . . . . . . . +2.7V to +12V • Low power consumption (PD) . . . . . . . . . . . . . . . . . . . .<5µW • Low leakage current. . . . . . . . . . . . . . . . . . . . . . . . . 10nA • Fast switching action - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns • Guaranteed break-before-make switching • Minimum 2000V ESD protection per method 3015.7 • TTL, CMOS compatible TABLE 1. FEATURES AT A GLANCE ISL43210 • Available in 6 Ld SOT-23 package SPDT or 2x1 MUX • Pb-free available (RoHS compliant) SW 1/SW 2 3.3V rON 32Ω 3.3V tON/tOFF 40ns/20ns 5V rON 19Ω 5V tON/tOFF 28ns/20ns 12V rON 11Ω 12V tON/tOFF 25ns/17ns Package 6 Ld SOT-23 Applications • Battery-powered, handheld, and portable equipment - Cellular/mobile phones - Pagers - Laptops, notebooks, palmtops • Communications systems - Radios, ADSL Modems - PBX, PABX Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” • Test and measurement equipment - Ultrasound - Computerized Tomography (CT) Scanner - Magnetic Resonance Image (MRI) - Position Emission Tomography (PET) Scanner - Electrocardiograph • Heads-up displays • Audio and video switching • Various circuits - +3V/+5V DACs and ADCs - Sample and hold circuits - Digital filters - Operational amplifier gain switching networks - High frequency analog switching - High speed multiplexing - Integrator reset circuits 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL43210 Pinout (Note 1) ISL43210 (6 LD SOT-23) TOP VIEW IN 1 6 NO V+ 2 5 COM GND 3 4 NC NOTE: 1. Switch Shown for Logic “0” Input. Truth Table Ordering Information ISL43210 LOGIC PIN NC PIN NO 0 ON OFF 1 OFF ON NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V. Pin Descriptions PART NUMBER ISL43210IH-T* PART MARKING 123I ISL43210IHZ-T* 123Z (Note) TEMP. RANGE (°C) PACKAGE PKG. DWG. # -40 to +85 6 Ld SOT-23 P6.064 Tape and Reel -40 to +85 P6.064 6 Ld SOT-23 (Pb-free) Tape and Reel *Please refer to TB347 for details on reel specifications. PIN NAME PIN NUMBER FUNCTION V+ 2 System Power Supply Input (+2.7V to +12V) GND 3 Ground Connection IN 1 Digital Control Input COM 5 Analog Switch Common Pin NO 6 Analog Switch Normally Open Pin NC 4 Analog Switch Normally Closed Pin 2 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6563.2 October 30, 2007 ISL43210 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 15V Input Voltages IN (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) NO, NC (Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 40mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015) . . . . .2kV Thermal Resistance (Typical, Note 3) θJA (°C/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 2. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) Full 0 - V+ V 25 - 19 30 Ω TYP MAX (Notes 5, 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V (See Figure 5) ON-Resistance, rON rON Matching Between Channels, ΔrON V+ = 5V, ICOM = 1.0mA, VNO or VNC = 3.5V Full - 23 40 Ω 25 - 0.8 2 Ω Full - 1 4 Ω rON Flatness, RFLAT(ON) V+ = 5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V (Note 7) Full - 7 8 Ω NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V 25 -3 0.01 3 nA Full -5 - 5 nA 25 -3 - 3 nA COM OFF Leakage Current, ICOM(OFF) V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V, 4.5V or Floating VNO or VNC = 3V, RL = 1kΩ, CL = 35pF, VIN = 0V to 3V (See Figure 1) VNO or VNC = 3V, RL = 1kΩ, CL = 35pF, VIN = 0V to 3V (See Figure 1) RL = 300Ω, CL = 35pF, VNO = VNC = 3V, VIN = 0V to 3V (See Figure 3) Full -5 - 5 nA 25 -5 - 5 nA Full -10 - 10 nA 25 - 28 - ns Full - 40 - ns 25 - 20 - ns Full - 30 - ns Full - 10 - ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2) 25 - 3 - pC OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz (See Figure 4) 25 - 76 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 60 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) 25 - 8 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) 25 - 8 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) 25 - 28 - pF 3 FN6563.2 October 30, 2007 ISL43210 Electrical Specifications - 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. (Continued) TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS Full 2.7 - 12 V Full -1 0.0001 1 µA POWER SUPPLY CHARACTERISTICS Power Supply Range V+ = 5.5V, VIN = 0V or V+, all channels on or off Positive Supply Current, I+ DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Full - - 0.8 V Input Voltage High, VINH Full 2.4 - - V Full -1 - 1 µA Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Electrical Specifications - 3.3V Supply PARAMETER Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP Full 0 - MAX (Notes 5, 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V rON Matching Between Channels, ΔrON V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 1.5V rON Flatness, RFLAT(ON) V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1V, 1.5V NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V COM OFF Leakage Current, ICOM(OFF) V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V or floating V+ V 25 - 32 50 Ω Full - 40 60 Ω 25 - 0.8 2 Ω Full - 1 4 Ω 25 - 6 10 Ω Full - 7 12 Ω 25 -3 0.01 3 nA Full -5 - 5 nA 25 -3 0.01 3 nA Full -5 - 5 nA 25 -5 - 5 nA Full -10 - 10 nA DYNAMIC CHARACTERISTICS Turn-ON Time, tON VNO or VNC = 1.5V, RL = 1kΩ, CL = 35pF, VIN = 0V to 3V 25 - 40 - ns Full - 60 - ns 25 - 20 - ns Turn-OFF Time, tOFF VNO or VNC = 1.5V, RL = 1kΩ, CL = 35pF, VIN = 0V to 3V Full - 30 - ns Break-Before-Make Time Delay, tD RL = 300Ω, CL = 35pF, VNO or VNC = 1.5V, VIN = 0V to 3V Full - 20 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω 25 - 1 - pC OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz 25 - 76 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 56 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V 25 - 8 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V 25 - 8 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) 25 - 28 - pF V+ = 3.6V, VIN = 0V or V+, all channels on or off Full -1 - 1 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ 4 FN6563.2 October 30, 2007 ISL43210 Electrical Specifications - 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. (Continued) TEMP (°C) MIN (Notes 5, 6) TYP Input Voltage Low, VINL Full - - 0.8 V Input Voltage High, VINH Full 2.4 - - V Full -1 - 1 μA PARAMETER TEST CONDITIONS MAX (Notes 5, 6) UNITS DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Electrical Specifications - 12V Supply PARAMETER Test Conditions: V+ = +10.8V to +13V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) Full 0 - V+ V 25 - 11 20 Ω TYP MAX (Notes 5, 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 10V rON Matching Between Channels, ΔrON V+ = 12V, ICOM = 1.0mA, VNO or VNC = 10V rON Flatness, RFLAT(ON) V+ = 12V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V (Note 7) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 13V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V COM OFF Leakage Current, ICOM(OFF) V+ = 13V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V COM ON Leakage Current, ICOM(ON) V+ = 13V, VCOM = 1V, 12V, or VNO or VNC = 1V, 12V or floating Full - 15 25 Ω 25 - 0.8 2 Ω Full - 1 4 Ω 25 - 1 4 Ω Full - - 6 Ω 25 -3 0.01 3 nA Full -5 - 5 nA 25 -3 0.01 3 nA Full -5 - 5 nA 25 -5 - 5 nA Full -10 - 10 nA DYNAMIC CHARACTERISTICS VNO or VNC = 10V, RL = 1kΩ, CL = 35pF, VIN = 0V to 4V Turn-ON Time, tON VNO or VNC = 10V, RL = 1kΩ, CL = 35pF, VIN = 0V to 4V Turn-OFF Time, tOFF RL = 300Ω, CL = 35pF, VNO or VNC = 10V, VIN = 0V to 4V Break-Before-Make Time Delay, tD 25 - 25 - ns Full - 35 - ns 25 - 17 - ns Full - 26 - ns Full - 2 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω 25 - 5 - pC OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz 25 - 76 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz 25 - -105 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 63 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V 25 - 8 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V 25 - 8 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) 25 - 28 - pF Full -1 - 1 µA POWER SUPPLY CHARACTERISTICS V+ = 13V, VIN = 0V or V+, all channels on or off Positive Supply Current, I+ 5 FN6563.2 October 30, 2007 ISL43210 Electrical Specifications - 12V Supply Test Conditions: V+ = +10.8V to +13V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. (Continued) PARAMETER TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS Full - - Full 4 - - V Full -1 - 1 μA DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 13V, VIN = 0V or V+ 0.8 V NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. 7. Limits established by characterization and are not production tested. Test Circuits and Waveforms V+ tr < 20ns tf < 20ns 3V OR 4V LOGIC INPUT 50% 0V tOFF SWITCH INPUT VNO SWITCH INPUT VOUT VOUT NO OR NC COM IN 90% SWITCH OUTPUT C 90% 0V LOGIC INPUT CL 35pF RL 1kΩ GND tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------R L + r ON FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ SWITCH OUTPUT VOUT RG ΔVOUT V+ LOGIC INPUT ON ON OFF VG NO OR NC GND C VOUT COM IN CL 0V LOGIC INPUT Q = ΔVOUT x CL FIGURE 2B. TEST CIRCUIT FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION 6 FN6563.2 October 30, 2007 ISL43210 Test Circuits and Waveforms (Continued) V+ 3V OR 4V LOGIC INPUT 0V C NO VNX VOUT COM NC 90% SWITCH OUTPUT VOUT 0V tD CL 35pF RL 300Ω IN GND LOGIC INPUT CL includes fixture and stray capacitance. FIGURE 3B. TEST CIRCUIT FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME V+ V+ C C rON = V1/1mA SIGNAL GENERATOR NO OR NC NO OR NC VNX INX 0V OR VINH 1mA 0.8V OR VINH COM COM ANALYZER IN V1 GND GND RL FIGURE 5. rON TEST CIRCUIT FIGURE 4. OFF ISOLATION TEST CIRCUIT V+ C V+ C SIGNAL GENERATOR NO1 OR NC1 COM1 50Ω NO OR NC IN1 COM2 ANALYZER INX IN2 0V OR VINH 0V OR 2.4V NO2 OR NC2 GND RL FIGURE 6. CROSSTALK TEST CIRCUIT 7 0V OR VINH IMPEDANCE ANALYZER COM NC GND FIGURE 7. CAPACITANCE TEST CIRCUIT FN6563.2 October 30, 2007 ISL43210 Detailed Description Power-Supply Considerations The ISL43210 bidirectional, single SPDT analog switch offers precise switching capability from a single 2.7V to 12V supply with low ON-resistance (19Ω) and high speed operation (tON = 28ns, tOFF = 20ns). The device is especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2.7V), low power consumption (5µW), low leakage currents (3nA max), and the tiny SOT-23 packaging. High frequency applications also benefit from the wide bandwidth, and the very high off isolation rejection. The ISL43210 construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 13V maximum supply voltage, the ISL43210 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies, as well as room for overshoot and noise spikes. Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low rON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION DIODE The minimum recommended supply voltage is 2.7V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the “Electrical Specification” tables beginning on page 5 and “Typical Performance Curves” beginning on page 9 for details. V+ and GND also power the internal logic and level shifter. The level shifter convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This device cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds This switch is TTL compatible (0.8V and 2.4V) over a supply range of 3V to 11V (see Figure 15). At 12V the VIH level is about 2.5V. This is still below the TTL guaranteed high output minimum level of 2.8V, but noise margin is reduced. For best results with a 12V supply, use a logic family the provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 300MHz (see Figure 16). Figure 16 also illustrates that the frequency response is very consistent over a wide V+ range, and for varying analog signal levels. V+ OPTIONAL PROTECTION RESISTOR INX VNO OR NC VCOM GND OPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch’s input to its output. Off isolation is the resistance to this feedthrough. Figure 17 details the high off isolation rejection provided by this part. At 10MHz, off isolation is about 50dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off isolation rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of 8 FN6563.2 October 30, 2007 ISL43210 these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. Typical Performance Curves TA = +25°C, Unless Otherwise Specified. 40 45 40 35 35 V+ = 3.3V 30 30 20 25 rON (Ω) rON (Ω) +85°C +25°C 25 +85°C 20 +25°C 15 -40°C 10 15 30 25 20 15 10 20 15 -40°C V+ = 5V +85°C +25°C -40°C +85°C V+ = 12V +25°C 10 5 -40°C 0 5 3 4 5 6 7 8 V+ (V) 9 10 11 12 13 4 6 VCOM (V) 8 10 12 FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE 0.50 0.40 0.30 2 60 V+ = 3.3V +25°C 50 +85°C 0.10 0 0.25 0.20 0.15 40 -40°C 30 V+ = 5V +25°C 0.10 +85°C +85°C 0.05 0 0.15 20 V+ = 5V V+ = 12V 10 V+ = 3.3V -40°C 0 V+ = 12V +25°C 0.10 -40°C 0.05 0 Q (pC) ΔrON (Ω) 0.20 -10 +85°C +25°C -40°C 0 2 4 6 VCOM (V) 8 -20 10 FIGURE 11. rON MATCH vs SWITCH VOLTAGE 9 12 0 2 4 6 8 10 12 VCOM (V) FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE FN6563.2 October 30, 2007 ISL43210 Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued) 100 35 90 80 30 +85°C tOFF (ns) tON (ns) 70 60 +85°C 50 25 -40°C -40°C 40 20 -40°C +25°C 30 20 +25°C 2 3 4 5 6 7 V+ (V) 8 9 10 11 15 12 FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE 2.5 VINH AND VINL (V) VINH -40°C 2.0 +85°C +25°C 1.5 +85°C V+ = 3.3V TO 12V 0 GAIN -3 -6 20 40 -40°C 60 +25°C 1.0 RL = 50Ω VIN = 0.2VP-P TO 2.5VP-P (V+ = 3.3V) VIN = 0.2VP-P TO 4VP-P (V+ = 5V) VIN = 0.2VP-P TO 5VP-P (V+ = 12V) VINL +85°C 0.5 3 2 4 5 6 7 8 V+ (V) 9 10 11 12 1 13 10 100 10 100 FREQUENCY (MHz) 600 RL = 50Ω V+ = 3V TO 13V 20 0 30 10 40 20 50 30 ±PSRR (dB) V+ = 3.3V, SWITCH OFF 60 ISOLATION 70 90 70 100 80 100k 1M 10M FREQUENCY (Hz) FIGURE 17. OFF ISOLATION 10 100M 500M V+ = 12V, SWITCH ON 50 60 10k V+ = 12V, SWITCH OFF 40 80 110 1k 80 FIGURE 16. FREQUENCY RESPONSE FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE OFF ISOLATION (dB) 0 PHASE PHASE (°) NORMALIZED GAIN (dB) 3.0 0.3 V+ = 3.3V, SWITCH ON 1 10 100 1000 FREQUENCY (MHz) FIGURE 18. ±PSRR vs FREQUENCY FN6563.2 October 30, 2007 ISL43210 Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: ISL43210: 58 PROCESS: Si Gate CMOS 11 FN6563.2 October 30, 2007 ISL43210 Small Outline Transistor Plastic Packages (SOT23-6) 0.20 (0.008) M P6.064 VIEW C C 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE CL INCHES e b SYMBOL 6 5 4 CL CL E1 E 1 2 3 e1 C D CL A A2 SEATING PLANE A1 -C- WITH b PLATING b1 c c1 MILLIMETERS MAX MIN MAX NOTES A 0.036 0.057 0.90 1.45 - A1 0.000 0.0059 0.00 0.15 - A2 0.036 0.051 0.90 1.30 - b 0.012 0.020 0.30 0.50 - b1 0.012 0.018 0.30 0.45 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.008 0.08 0.20 6 D 0.111 0.118 2.80 3.00 3 E 0.103 0.118 2.60 E1 0.060 0.068 1.50 3.00 - 1.75 3 e 0.0374 Ref 0.95 Ref - e1 0.0748 Ref 1.90 Ref - L 0.10 (0.004) C MIN 0.014 0.022 0.35 0.55 L1 0.024 Ref. 0.60 Ref. L2 0.010 Ref. 0.25 Ref. N 6 6 4 5 R 0.004 - 0.10 - R1 0.004 0.010 0.10 0.25 α 0o 8o 0o 8o Rev. 3 9/03 BASE METAL NOTES: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 4X θ1 2. Package conforms to EIAJ SC-74 and JEDEC MO178AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. R 5. “N” is the number of terminal positions. GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 4X θ1 VIEW C All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN6563.2 October 30, 2007