Application Note, Rev 1 .0, February 2009 TLE4998C User Programming Guide Sensors N e v e r s t o p t h i n k i n g . Edition 2009-02 Published by Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany © Infineon Technologies AG 2009. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TLE4998C-Programming Guide 1 1.1 1.2 1.3 1.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.2 2.3 2.4 Interface Access Details - Part I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Command Frame Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Frame Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interface Parity Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 3.1 3.2 3.3 Interface Access Details - Part II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Electrical Parameters for Interface Access . . . . . . . . . . . . . . . Timing and Electrical Parameters for Programming . . . . . . . . . . . . . . . . . 12 12 12 13 4 4.1 4.2 4.3 4.4 4.5 Interface Access Details - Part III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complete Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic EEPROM Access and Programming Procedure . . . . . . . . . . . . . . . DATA Access Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temporary Overwrite of EEPROM Data . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 17 21 25 26 5 Application Circuit for Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Application Note 1 3 3 3 4 6 Rev 1.0, 2009-02 TLE4998C-Programming Guide Revision history Date/Version: 2009-02 Rev 1.0 Previous Version: Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Application Note 2 Rev 1.0, 2009-02 User Programming Guide TLE4998C TLE4998C-Programming Guide 1 Overview 1.1 General Information • • • • • • This document is valid for the TLE4998C products and derivatives It is intended as add-on to the currently available TLE4998 datasheets It gives an overview of the internal signal processing capabilities It contains basic information about accessing the device using the digital interface It describes how to access internal registers and parameters stored in the EEPROM Furthermore it shows how to apply the programming voltage for the EEPROM and how to verify the programming • The herein given electrical specification has to be understood directly on the sensor interface. Additional effects concerning the external circuitry, the attached programming equipment or any degradation e.g. in combination with EMC is not considerd 1.2 Block Diagram Figure 1 shows a simplified block diagram of the TLE4998. VDD Bias spinning HALL Supply EEPROM TST* A D OUT DSP Temp. Sense Interface Protocol Generation A D GND ROM * TST pin only for TLE4998x4 types Figure 1 Block Diagram Application Note 3 Rev 1.0, 2009-02 TLE4998C-Programming Guide Overview The device can be accessed using a two-wire synchronous interface. The device supply pin (Vdd pin) acts as clock line and the output pin (OUT pin) is used as a bidirectional serial data line and to apply the required programming voltage. This method allows the connection of several devices to a single power supply line while accessing the devices either separately or in parallel. Using a parallel access, multiple devices can be accessed simultaneously, consuming less time than for a serial programming. This is especially important for time-consuming operations like programming the EEPROMs in multi-device setups. 1.3 Pin Configuration Figure 2 shows the location of the four pins of the PG-SSO-4-1 package and Table 1 gives the corresponding pin definition and function. The same information can be found for the PG-SSO-3-10 package in Figure 3 and Table 2, respectively. B 2.67 d 0.2 B Center of sensitive area 1.53 A 2 3 Hall-Probe 4 0.2 A 1 Branded Side d : Distance chip to branded side of IC PG-SSO-4-1: 0.3 ±0.08 mm AEP03654 Figure 2 Pin Configuration for the PG-SSO-4-1 package Table 1 Pin Definitions and Functions for the PG-SSO-4-1 package Pin No. Symbol Function 1 TST Test pin (connection to GND is recommended) 2 VDD Supply voltage / programming interface (clock) 3 GND Ground 4 OUT Output/ programming interface (I/O data, Vprog) Application Note 4 Rev 1.0, 2009-02 TLE4998C-Programming Guide Overview 0.38 ±0.05 2.03 ±0.1 1.625 ±0.1 Center of Hall Probe Branded Side Hall-Probe 1 2 3 AEP03717 Figure 3 Pin configuration for the PG-SSO-3-10 package Table 2 Pin Definitions and Functions for the PG-SSO-3-10 package Pin No. Symbol Function 1 VDD Supply voltage / programming interface (clock) 2 GND Ground 3 OUT Output/ programming interface (I/O data, Vprog) More information regarding location of branding, Hall probe etc. can be found in the corresponding datasheet. Application Note 5 Rev 1.0, 2009-02 TLE4998C-Programming Guide Overview 1.4 Signal Flow Figure 4 shows the signal flow diagram including important internal data values. Range H_ADC LP D_OUT Limiter Gain (Clamp) Hall Sensor A D TC2 T_ADC X D X + Protocol Generation out Offset Temperature Sensor A X H_CAL X 1 + + X TC1 -T0 Stored in EEPROM Memory T_CAL Temperature Compensation Figure 4 Block Diagram Table 3 Internal data values Address. Symbol Function 0x00 D_OUT Data out value (16 bit unsigned, with clamping)1) 0x05 H_CAL Calibrated Hall value1)2) 0x06 T_CAL Calibrated temperature value, incl. reference-temp. T01)2) 0x0A H_ADC Uncalibrated Hall ADC value 1)3) 0x0B T_ADC Uncalibrated temperature ADC value 1)3) 1) requires activated interface - access possible only with unlocked devices 2) requires special debug mode 3) please note that this value does not include any compensation - these are just the internal “raw” ADC values Application Note 6 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part I 2 Interface Access Details - Part I 2.1 Functional Interface Description All internal data is organized in a memory-like setup. Each data value or EEPROM parameter is located at a specific address. The data width is always 16 bit. The interface uses specific frames for information exchange, which can have one of the two following functions: • Command frames contain a specific task (e.g. read/write data, select EEPROM programming etc.) and a corresponding address • Data frames contain a 16 bit data value sent to or received from the device - these frames can only follow a proper command frame for reading or writing data A valid frame has these properties: • • • • • • A frame consists always of 21 bits A bit is shifted in or out via the output line with a rising clock edge on the supply line. A frame always starts and ends with a '1' (frame bits) The LSB of a transmitted frame is shifted in first The LSB of a resulting frame is shifted out first The whole frame sent to the device, including frame bits, is protected with an even positional and an odd positional parity bit The first frame sent must always be a valid command to activate the interface mode and has to be sent within 19ms after power up. As an additional protection, the device does not deactivate its output stage during this transmission (using 21 clock pulses) as shown in Figure 5. This means that the external interface driver needs to overrule the open drain output stage of the sensor during this initial transmission. VDD Vout power up LSB interface activated MSB during first transmission, the output stage is still switched on Figure 5 First frame transmission to the device Note: Overruling Vout requires a strong driver, since the line must be driven to both low levels close to GND for any “0”-bit and close to VDD for any “1”-bit in order to assure a proper detected by the sensor. Application Note 7 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part I Later, to avoid additional power consumption in the output stage of the device, the internal driver is deactivated as soon as the first clock pulse of a frame is detected, and put on again after completion of the transmission. This is illustrated in Figure 6. VDD leading driver off pulse interface active interface active Vout protocol output Z protocol output MSB during transmission the buffer is switched off internal buffer on Figure 6 LSB internal buffer on Further frame transmission to the device (write access) In case of a wrong command or data frame, the interface is immediately locked and the device falls back to its normal application mode. As long as the device is in the interface mode, selected test modes stay activated, too. Special transmission modes based on these frames, used for programming of the EEPROM, will be explained in the EEPROM programming section. The read access to the device is triggered by clock pulses on the supply line as shown in figure Figure 7. The exact timing of both read and write accesses are outlined in Section 3.2. VDD tailing driver on pulse Vout MSB LSB digital data readout, buffer in I /O mode internal buffer on Figure 7 2.2 internal buffer on Frame reception from the device (read access) Command Frame Description As already described, the data transmission is performed by command frames. These command frames are supported by following data frames, if required. A general command frame is shown in Figure 8. Available commands are given in Table 4. Available addresses are summarized in Section 4.1 based on address maps. The parity Application Note 8 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part I bits PE (bit 17) and PO (bit 18) need to be set in a way that the following conditions are met (bit 0 is the LSB, bit 20 is the MSB): • bit0 XOR bit2 XOR bit4 XOR …. XOR bit20 = 0 • bit1 XOR bit3 XOR bit5 XOR …. XOR bit19 = 0 Please refer to Chapter 2.4 for a source code example of a parity generator. MSB 1 LSB 1 P O P E 0 0 ADDR (6bit) 1 Figure 8 Command Frame Table 4 List of available device commands 0 CMD (6bit) 1 CMD No. Bits1) Function 0x0 Leave interface mode 2) 0x1 “000000” “000001” 0x2 “000010” Continuous data readout from given address without increment (power-on cycle needed to leave this state) 0x3 “000011” Continuous readout from given address with increment (readout finished when address “xxx111” is reached – block read, can not be canceled before!) 4) 0x9 “001001” Single write data to given address without increment 3) 0xA “001010” Continuous write data to given address without increment (finished by sending an arbitrary sync. command frame to cancel) 0xB “001011” Continuous write data to given address with increment (block write, finished at address “xxx111” or by sending an arbitrary sync. command frame to cancel) 4) 0xC “001100” Enable EEPROM write mode (programs “1”-bits) 2) 5) 0xD Enable EEPROM erase mode (programs “0”-bits) 2) 5) 0xE “001101” “001110” 0xF “001111” Enable EEPROM refresh (update EEPROM registers) 2) Single data readout from given address without increment 3) Enable EEPROM margin mode (program level check) 2) 6) 1) Left is MSB, right is LSB 2) No data frame must follow 3) Exactly one data frame must follow. 4) One or more data frames must follow until address reaches block boundary (“xxx111”). Application Note 9 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part I 5) A program pulse must follow after the frame (output stage is kept disabled). 6) A margin voltage level must follow before the last Vdd clock pulse falling edge (this edge is used for refreshing the EEPROM registers using the margin voltage). 2.3 Data Frame Description A general data frame sent to the device is shown in Figure 9. The parity bits PE (bit 17) and PO (bit 18) need to be set (in the same way as for the command frame) that the following conditions are met (bit 0 is the LSB, bit 20 is the MSB): • bit0 XOR bit2 XOR bit4 XOR …. XOR bit20 = 0 • bit1 XOR bit3 XOR bit5 XOR …. XOR bit19 = 0 Please refer to Chapter 2.4 for a source code example of a parity generator. Figure 10 shows a general data frame received from the sensor. Instead of a zero bit followed by two parity bits, the least significant 3 bits of the address used for the readout are transmitted together with the data. This allows to check the plausibility of the received data. MSB 1 LSB 0 Figure 9 P O P E DATA (16bit) 1 Data frame (write to device) MSB 1 LSB ADR (3 LSBs) Figure 10 2.4 DATA (16bit) 1 Data frame (read from device) Interface Parity Calculation An example parity generator is shown using a pseudo code. The array “framedatabits” contains the data bits to transmit including the framebits, its index corresponds to 0 ... LSB and 20 ... MSB. This parity calculation is valid for command and data frame transmissions: // count framedatabits from 0 (LSB) to 20 (MSB) - this are 21 bits // bit 0 and 20 are always '1' (framebits) pe = framedatabit(19); Application Note 10 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part I po = 0; for (i=1; i<17; i++) // go through all data bits { // handle even/odd separately if ((i&1)==1) { if (framedatabit(i)==1) { if (pe) pe=0; else pe=1; }//toggle pe } else { if (framedatabit(i)==1) { if (po) po=0; else po=1; }//toggle po } } framedatabit(17) = pe; framedatabit(18) = po; For example, a command 0x03 using address 0x02 should be transmitted (this command triggers a block readout for addresses 0x02 to 0x07): Table 5 Valid Frame Example Bitcount 20 19 18 17 16 15 14 13 12 11 10 9 Descr. of CMD-frame 1 Descr. of DATA-frame 1 Bits for PO 2 1 0 0 C 5 C 4 C 3 C 2 C 1 C 0 LSB D 5 D 4 D 3 D 2 D 1 D 0 LSB 1 MSB P O P E D D D D D D D 15 14 13 12 11 10 9 D 8 D 7 X X 1 Application Note 1 X 1 0 X 0 0 X X 0 A 2 3 A 0 X A 3 4 A 1 X A 4 5 0 X A 5 6 P E 0 0 7 P O MSB Bits for PE CMD-frame 1 8 0 X X 0 0 11 X X 1 D 6 0 X X 1 0 X X 0 0 X X 0 0 1 1 X X 1 1 1 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part II 3 Interface Access Details - Part II 3.1 General Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TLE4998 during programming and debugging. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Operating Range1) Table 6 Parameter Symbol Limit Values Unit Notes min. max. 4.5 5.5 V 47 1000 nF from Vdd to GND 2) 3) Load capacitance VDD CS CL - 8 nF from OUT to GND 3) Ambient temperature Ta 10 30 °C at programming 4) Supply voltage Supply buffer cap. 1) Keeping signal levels within the limits specified in this table ensures correct setup and programming. 2) Prevents severe supply drops causing a device reset during interface access. For high reliability use, the capacitance must be soldered to the device to avoid contact failures. 3) Please be aware that the driving circuits of Vdd and Vout need also additionally proper driving strength for these capacitors. 4) Interface readouts are also possible at higher and lower temperatures (altough not explicitly tested and guaranteed), but applying the programming- or margin- voltage outside this room temperature range is strictly forbidden. 3.2 Timing and Electrical Parameters for Interface Access For accessing the interface, the supply pin and output pin must be properly accessed; the timing parameters correspond to Figure 11. tC H tC L t H LD t M IN VDD tSET t SU tH LD t SET Vout LSB MSB command frame Figure 11 LSB data read frame Frame timing Application Note 12 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part II 3.3 Table 7 Timing and Electrical Parameters for Programming Electrical levels and interface timing Parameter Vdd clock high level Vdd clock low level OUT data out high level OUT data out low level OUT data in high level OUT data in low level OUT data input current Vdd clock high time Vdd clock low time Data in setup time Data in hold time Data out settling time Time between frames Symbol Vdd,CLKHI Vdd,CLKLOW VO,OHIGH VO,OLOW VO,IHIGH VO,ILOW IO tCH tCL tSU tHLD tSET tMIN Limit Values Unit Notes min. typ. max. 9 10 11 V 1) 4.8 5.0 5.2 V this is Vdd1) - - - V 2) - - - V 50% Vdd - Vdd V -0.2 0.0 0.1 V -5 - 5 mA 3) 2.5 50 - µs 2.5 50 - µs exact bitrate tbd4) 1.5 2.0 - µs to rising Vdd 2.3 3.0 - µs after rising Vdd - 1.0 1.7 µs after rising Vdd 10.0 - - µs 5) 1) Prevent over-/ underswing during Vdd switching to avoid unexpected sensor behavior (e.g. undervoltage sensor reset). 2) Corresponds to the open drain specification in the data sheet. 3) Capability of external driver, especially during initial interface access (to overwrite device output). 4) Excact bitrates depend also on several further conditions, like length of cables (inductors) and the electrical behavior of the used programming device/setup. Furthermore the desired customer margins for the timing and voltage levels may limit the bitrate even more. In case of problems try the typical recommended bitrate first and optimize the timing based on measurements using the given system. Also temperatures outside the allowed temperature range for the EEPROM programming are not considered in the above recommendation. 5) In interface mode, EMC influences or Vdd drops during and between frames may cause internally to stop the interface mode due to safety reasons; a power cycle is needed to allow interface access again. Application Note 13 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part II Additionally, for programming, Figure 12 shows a general Vprog pulse timing: tM IN VDD tM IN tH LD t H LD Vout MSB erase or write command frame Figure 12 LSB tPR OG,W R or t PR OG,ER VO ,PR OG /t (rise) V O,PR OG/t (fall) V prog pulse (buffer stays off) next command frame Program pulse timing A margin readout needs a special behavior (Figure 13) at the end of a command frame: VDD Vdd /t (fall) t MIN tMARG tMIN t HLD Vout tHLD MSB margin command frame (buffer stays off) Figure 13 LSB apply VO,MARG and capture EEPROM data next command frame Margin setup timing Application Note 14 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part II Table 8 Electrical levels and interface timing Parameter Symbol Limit Values min. typ. Unit Notes max. IO OUT margin level VO,MARG Threshold margin level VTH 0 5 mA 1) -0.1 7 V 2) 2.23 4.5 0.4 V V check ’1’3) check ’0’4) tMARG Vdd slope for margin Vdd/t OUT program level VO,PROG OUT prog. slope (rise) VO,PROG/t OUT prog. slope (fall) VO,PROG/t OUT write time tPROG,WR OUT erase time tPROG,ER 200 OUT input current Margin setup time µs 1.25 - 10 V/µs falling edge 19.2 19.3 19.4 V low tolerance!2) 5) 2 V/µs 6) -10 6) V/µs 7) 9.9 10.0 10.1 ms 79.2 80.0 80.8 ms 1) When Vo,prog or Vo,marg is applied. 2) Proper command must be applied first to switch off internal output stage of device. 3) Level range within which programmed EEPROM bits start to flip from ones to zeros - to be checked after programming: - a too low value could be given by too short programming pulse or a too low programming voltage - a too high value could be given by a too long programming pulse or a too high programming voltage To check the programmed ‘1’ threshold levels, the “Margin zero on” bit needs to be set to ‘0’ in the test register 4) To check the programmed ‘0’ threshold levels, the “Margin zero on” bit needs to be set to ‘1’ in the test register 5) Time to reach VO,PROG min. must not exceed 50µs 6) Time to reach 1V max. must not exceed 50µs 7) Ramp up/down needs to be assured by the programming hardware - especially faster slopes, when applying the programming voltage, may damage the EEPROM cell. Application Note 15 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part II Due to this specification for the programming pulse, either a linear programming ramp or an exponential ramp (using an R/C circuit) may be applied as shown in Figure 14. Figure 14 Example slopes for VO,PROG Application Note 16 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part III 4 Interface Access Details - Part III 4.1 Complete Memory Map Table 9 Memory map Address. Symbol Function 0x00 D_OUT Data out value (16 bit unsigned, with clamping) 0x05 H_CAL Calibrated Hall value 0x06 T_CAL Calibrated temperature value, incl. reference-temp. T0 0x0A H_ADC Uncalibrated Hall ADC value 0x0B T_ADC Uncalibrated temperature ADC value 0x0F STATUS Chip status register 0x10...0x1A EEPROM EEPROM map 1) 0x1B TEST Test mode register 1) 1) these addresses allow write access, too • D_OUT, H_CAL, T_CAL, H_ADC, T_ADC: These registers correspond to the signal flow diagram shown in Chapter 1.4 • STATUS: This register contains internal status information as well as the chip version • EEPROM: These registers contains the EEPROM based parameter-set of the device • TEST: This register activates several test modes necessary for accessing internals of the device Note: To access the registers (except STATUS, H_ADC, T_ADC, D_OUT and TEST) the internal digital signal processor must be deactivated as it has priority over interface read and write commands. Please check out the TEST register content how to disable the DSP. 4.2 Register Details 4.2.1 H_ADC This register contains a 16bit signed value. When read as unsigned value and this value is larger than 32767, it is necessary to subtract 65536 to get a signed value again: 0111111111111111 0100111000100000 0000000000000001 0000000000000000 1111111111111111 1011000111100000 1000000000000000 Application Note (unsigned (unsigned (unsigned (unsigned (unsigned (unsigned (unsigned dec. dec. dec. dec. dec. dec. dec. 32767) 20000) 1) 0) 65535) 45536) 32768) the (theoretical) max. pos. field the max. allowed positive field is a growing positive field is the zero field (without offset error) is a growing negative field (-1) the max. allowed negative field (-20000) the (theoretical) max. neg. field (-32768) 17 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part III For valid usage of the device, the H_ADC value must be always in a range of +/- 20000 decimal, which corresponds to approximately 2/3 of the theoretical integer range. Otherwise the used magnetic flux density is too high and the ADC might be saturated. 4.2.2 T_ADC This register contains a 15bit unsigned value. This value is not important for the usage of the IC. Just for information this value is roughly in a range of 22000 to 29000 decimal for temperatures between -50°C and 150°C. 4.2.3 H_CAL This register contains a 16bit signed value similar to the H_ADC value and is required to calculate the output D_OUT value for a specific magnetic value. This value is at a given magnetic range (for a calibrated device) in the range of +/- 30000 (approx. 1.5 times of H_ADC) when the max. positive or negative field is applied. 4.2.4 T_CAL This register contains a 16 bit signed value and delivers the current junction temperature of the device. To retreive the actual temperature in °C, the register value needs to be calculated with TJ=T_CAL/16+48. 4.2.5 D_OUT This value is the 16 bit unsigned decimal result applied to the internal protocol generation for the open drain output stage. It includes the clamping limits if programmed. The value range is from decimal 0 to 65535. 4.2.6 STATUS The content of the status register is shown in Figure 15. LSB ROMSIG2 ROMSIG1 ROMSIG0 HWver2 HWver1 HWver0 6 5 4 3 2 1 0 CRC ok ROMSIG3 7 LOCKED 8 perr_adr0 9 perr_adr1 10 perr_adr2 11 perr_adr3 12 perr_more 13 perr_col 14 ROMSIG4 Figure 15 15 Status register • CRC ok must be ’1’, otherwise the DSP BIST failed and the device is defective. Application Note 18 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part III • LOCKED must be ’0’ as long as the lockbits are not programmed. Newly programmed lock bits effect the LOCKED bit after the next power cycle. A locked interface indicates that the chip has been locked successfully. • perr_adr must be on address 0xF (=”1111”) otherwise it shows the first EEPROM address (=line) where the internal parity check failed. • perr_more must be ’0’, otherwise more than one EEPROM address (=lines) has a parity error. • perr_col must be ’0’, otherwise one or more EEPROM columns have a parity error. • HWver contains the actual silicon revision (for the TLE4998C B11, this number is set to “001”). • ROMSIG must be 0x15 (=”10101”) otherwise the DSP ROM is not valid and the device itself is defective. To summarize, for a sensor without defects and appropriate parity programming, the status register should have the setting 0xA93D for the TLE4998C. 4.2.7 TEST The content of the test register is shown in Figure 16. MSB LSB 0 0 0 0 DSP stop DSP off REF off 0 Figure 16 7 6 5 4 3 2 1 0 0 8 0 9 0 10 0 11 0 12 Margin zero on 13 FEC off 14 PROTOCOL off 15 Test register All bits are ’0’ after reset. All bits not described or used must kept at ’0’. • “Margin zero on” needs to be set to ‘1’ for testing the EEPROM threshold voltages of cells programmed to ‘0’. The bit has to be set to ‘0’ if the EEPROM threshold voltages of cells programmed to ‘1’ are tested • “FEC off” switches off the error correction of the EEPROM. This bit should be set when reading the EEPROM content to ensure to retreive the real data stored in the EEPROM (address range 0x10 to 0x1A) • “REF off” switches off the automatic (cyclic) refresh performed by the DSP to actualize the EEPROM registers from the EEPROM cells. When writing new values to the EEPROM registers this bit must be set, otherwise these values will be always overwritten by the EEPROM content • “DSP off” switches off the signal processor immediately. This bit must be set prior to access the internal register values via the interface (H_CAL, T_CAL and EEPROM). Application Note 19 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part III • “DSP stop” should be set prior (as a separate step before switching the DSP off) when reading out the calculated data H_CAL and T_CAL. This allows the DSP to finish the calculation of the current sample and all values in the RAM are consistent. Normally the cycle time of the protocol should be waited before the DSP is switched off completely (“DSP off” =1). • “PROTOCOL off” should only be set together with “DSP off ”. It can be set if it is desired to get correct protocol output after “DSP off” and “PROTOCOL off” are cleared again. Otherwise, correct protocol output is guaranteed only after reset. 4.2.8 EEPROM The content of the EEPROM setup registers is shown in Table 10. The red marked parameters set the sensor hardware, the yellow marked parameters are used by the DSP algorithms and the magenta/cyan values correspond to the parity setup for the internal forward error correction (FEC). All parameters are unsigned integer values. The white areas must not be changed. Table 10 EEPROM registers ADR Description 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0x10 Parity of each column 0x11 IC lock (high locks), clamp Pl high/low, frame type 0x12 gain setting Pl G - register (bit 14...0) 0x13 offset setting Pl OS - register (bit 14...0) 0x14 ID, PC...temp. cal. status bit, Predivider, TQ value Pl ID 0x15 Bandwidth, Range, TL value, IC lock (low locks) Pl BW 0x16 Protocol, precal, TT value (precal) Pl Prot 0x17 precal Pl precal area - do not modify 0x18 precal Pl precal area - do not modify 0x19 precal Pl precal area - do not modify 0x1A precal Pl precal area - do not modify 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Pc Pc Pc Pc Pc Pc Pc Pc Pc Pc Pc Pc Pc P c Pc Pc L H CH - register (bit 5...0) P C Prediv (bit 3...0) R (1...0) (2...0) CL - register (bit 5...0) TQ - register (bit 7...0) TL - register (bit 8...0) precal area - do not modify (1...0) F (1...0) L L precal area - do not modify, TT - regis. (bit 4...0) • The parity Pc of each column (including the precalibration ranges) must be even for even bit positions (bit0=LSB, bit2, bit4, ... bit14) and the parity Pc for all odd columns (bit1, bit3, ... bit13) must be odd. The parity Pc for the column at bit15 (MSB) must be Application Note 20 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part III • • • • even. The parity Pl of every EEPROM line (adress 0x11 ... 0x1A) needs to be calculated in a way that the sum of bits is always odd The two ID bits are used to define a sensor’s ID in the SPC ID mode. For the dynamic range and synchronous modes, the ID bits are free and can be used by the customer. PC stands for precal bit. Infineon’s eval software toggles this bit after the first programming. This way it is possible to see whether a device has still the precalibrated settings. LH and LL are lock bits (LH locked if '1', LL locked if '0'). As soon as either LH, LL or both are set to locked state, the interface mode cannot be accessed anymore. Therefore, LH and LL can be used to lock the interface and avoid that the interface is accessed and registers changed by mistake after final programming All other parameters (G, OS, etc.) are are defined and explained in the datasheet Note: Don’t forget to switch off the FEC during access of the EEPROM to read the data actually stored in the EEPROM cells to detect possible faults. 4.3 Basic EEPROM Access and Programming Procedure Following steps are required to setup the EEPROM and to program new values, assuming additional external memory called EEP_NEW (new EEP values), EEP_PROG (for intermediate values) and EEP_OLD (current EEP values). Application Note 21 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part III EEPROM programming Vdd = 5V EEP_OLD EEP_NEW INIT-CMD: cmd=0x01 adr=0x0F READ DATA Is 0xA93D? NO ILLEGAL STATUS: analyse problem CMD (write): cmd=0x09 adr=0x1B DAT: 0x06C0 (DSP, FEC, REF off) CMD (b read) cmd=0x03 adr=0x10 RD. B-DATA CMD (read) cmd=0x01 adr=0x18 READ DATA CMD (read) cmd=0x01 adr=0x19 READ DATA CMD (read) cmd=0x01 adr=0x1A READ DATA Create erase pattern * 11x 16bit > EEP_OLD < Store this initial dataset (allows later restore) 2x 11x 16bit CMD(marg.): cmd=0x0E adr=0x00 Readout could be looped for several margin voltages (starting from a very high voltage e.g. 5V) to find the margin level of the EEPROM Vm arg+V dd-ramp CMD (b read) cmd=0x03 adr=0x10 RD. B-DATA CMD (read) cmd=0x01 adr=0x18 READ DATA CMD (read) cmd=0x01 adr=0x19 READ DATA CMD (read) cmd=0x01 adr=0x1A READ DATA > EEP_NEW < Given by TC setup and/or 2P algorithms etc. CMD (bwrite) cmd=0x0b adr=0x10 WR. B-DATA CMD (write) cmd=0x09 adr=0x18 WR. DATA CMD (write) cmd=0x09 adr=0x19 WR. DATA CMD (write) cmd=0x09 adr=0x1A WR. DATA content = EEP_NEW ? Vdd = 0V (off) FINISHED CMD (EEP erase): cmd=0x0D adr=0x00 Vprog PULSE Figure 17 CMD (bwrite) cmd=0x0b adr=0x10 WR. B-DATA CMD (write) cmd=0x09 adr=0x18 WR. DATA CMD (write) cmd=0x09 adr=0x19 WR. DATA CMD (write) cmd=0x09 adr=0x1A WR. DATA CMD (EEP write): cmd=0x0C adr=0x00 Vprog PULSE User input, TC setup algorithm or 2P calibration algorithm setup EEP_OLD 2x 11x 16bit EEP_NEW Create write pattern ° NO margin higher required limit ? Optionally do a last status readout (adr. 0x0F) to check the IF mode is still active and the device is ok. NO ILLEGAL MARGIN READ: analyse problem * Erase pattern: For each line I from 0x10 to 0x1A: EEP_PROG[i] = INVERT ((EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_OLD[i]) (as precal areas must not be changed, the bits in this areas must remain ‚1') ° Write pattern: For each line I from 0x10 to 0x1A: EEP_PROG[i] = (EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_NEW[i] (as precal areas must not be changed, the bits in this areas must remain ‚0') Basic EEPROM programming flow Description of the flowchart shown in Figure 17: 1. Switch on the device 2. Send an inital command (status line readout) - read the status,check that the device is valid and the EEPROM content is valid - if it is not correct, do not continue and check for the failure 3. Set the test register bits FECoff=1, DSPoff=1, REFoff=1 (allows EEPROM access) Application Note 22 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part III 4. Read out the EEPROM content to the array EEP_OLD (store also for reference purposes and for traceability of programming) - Parallel task: prepare the data necessary to program as array EEP_NEW (see application notes for calculation of TC parameters and how to do a 2-point calibration) 5. Calculate the bits to be cleared from EEP_OLD to EEP_NEW as EEP_PROG array 6. Write the EEPROM content from the EEP_PROG array to the EEPROM registers 7. Send the EEPROM erase command - Apply an erase programming pulse on the output pin (see electrical specification) 8. Calculate the bits to be set from EEP_OLD to EEP_NEW as EEP_PROG array 9. Write the EEPROM content from the EEP_PROG array to the EEPROM registers 10.Send the EEPROM write command - Apply a porgramming pulse on the output pin (see electrical specification) 11.Send a margin command - During the falling edge of the margin pulse on VDD, apply VO,MARG on the output (see electrical specification) 12.Read out the EEPROM content to the array EEP_PROG 13.Verify the EEP_PROG data against EEP_NEW to check the programming (no/all bits flipped) - Optionally, item 11 to 13 might be looped to find the exact VTH EEPROM level. - If the acquired VTH level is too low, do not continue and check for the failure. 14.Finally it is recommended to send a read command to check the status register again to see if the sensor is still running in the interface mode before switching off the device Note: The EEPROM parity status bits are not meaningful at that time. Also the LOCK bit does not correspond to the settings in the EEPROM. Detail one: How to set the TEST register: 1. Send a write command (TEST register set: CMD=0x09, ADR=0x1B) 2. Send the new data word for the TEST register Detail two: How to read out the EEPROM content: 1. Send a block command (EEPROM data readout: CMD=0x03, ADR=0x10) 2. Read the first 8 data words of the EEPROM and store it in an array 3. Send a read command (EEPROM data readout: CMD=0x01, ADR=0x18) 4. Read the 9th data word of the EEPROM and store it in an array 5. Send a read command (EEPROM data readout: CMD=0x01, ADR=0x19) 6. Read the 10th data word of the EEPROM and store it in an array 7. Send a read command (EEPROM data readout: CMD=0x01, ADR=0x1A) 8. Read the 11th data word of the EEPROM and store it in an array Detail three: How to set the EEPROM content: 1. Send a block command (EEPROM data writeout: CMD=0x0B, ADR=0x10) 2. Send the first 8 data words from the array to the EEPROM Application Note 23 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part III 3. Send a write command (EEPROM data write: CMD=0x09, ADR=0x18) 4. Send the 9th data word from the array to the EEPROM 5. Send a write command (EEPROM data write: CMD=0x09, ADR=0x19) 6. Send the 10th data word from the array to the EEPROM 7. Send a write command (EEPROM data write: CMD=0x09, ADR=0x1A) 8. Send the 11th data word from the array to the EEPROM Detail four: How to calculate the bits to be cleared from EEP_OLD to EEP_NEW: 1. For each data word i in the arrays calculate: 2. EEP_PROG[i] = INVERT ((EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_OLD[i]) Example of a calculated erase mask: EEP_OLD: 0101010101010101 EEP_NEW: 0101110001010101 EEP_PROG: 1111111011111111 Detail five: How to calculate the bits to be set from EEP_OLD to EEP_NEW: 1. For each data word i in the arrays calculate: 2. EEP_PROG[i] = (EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_NEW[i] Example of a calculated program mask: EEP_OLD: 0101010101010101 EEP_NEW: 0101110001010101 EEP_PROG: 0000100000000000 Detail six: How to determine the EEPROM margin voltages The threshold voltage of EEPROM cells is dependent on the programming voltage and programming pulse length. For reliable programming the programming pulse has to be kept within the specification (Table 8) at the sensor interface. The margin command can be used to check the threshold voltages of the programmed cells: A voltage VO,MARG is applied after the margin mode command (CMD No. 0xE, see timing diagram in Figure 13). For EEPROM cells with a threshold voltage smaller than the applied VO,MARG, a '0' will be stored to the EEPROM registers, for those with a higher threshold voltage, a '1' will be written. By sweeping the applied VO,MARG, the effective threshold voltages of each EEPROM cell can be identified. The threshold voltages of cells programmed to ‘1’ can be found in this way. In order to check the threshold voltages of EEPROM cells programmed to ‘0’, it is necessary to activate the “Margin zero on” bit in the test register (Figure 16). The smallest possible VO,MARG is 0V, and it is therefore not possible to determine the threshold voltages below 0V. Note: This routine can be merged with other (exemplary shown) routines. In that case only one initial frame (the very first interface access) is required after power-on. Application Note 24 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part III 4.4 DATA Access Example The following steps are required to read out other internal data like the calibrated temperature and Hall value (as shown below). Of course these routines can be used for an EEPROM access as well (in that case also FEC off should be set to ’1’). EEPROM programming V dd = 5V CMD (write): cmd=0x09 adr=0x21 DAT: 0x0C80 (DSP stop, DSP off, PROT. off) INIT-CMD: cmd=0x01 adr=0x0F READ DATA Is 0xA93D ? NO ILLEGAL STATUS: analyse problem CMD (write): cmd=0x09 adr=0x21 DAT: 0x0800 (DSP stop) Optionally do a last status readout (adr. 0x0F) to check if the IF mode is still active and the device is ok . CMD (read) cmd=0x01 adr=0x05 READ DATA Like reading out H_CAL, also all other RAM and EEPROM registers can be read out here in a loop. Vdd = 0V (off) FINISHED Wait for min. cycle time of the protocol Figure 18 Basic data access flow Description of the above flowchart: 1. Switch on the device 2. Send an inital command (status register readout) 3. Read the status data, check that the device is valid and the EEPROM content is valid 4. Set the test register: DSP stop=1 (see previous chapter) 5. Set the test register: DSP stop=1, DSP off=1, PROTOCOL off=1 (see previous chap.) 6. Send a read command (H_CAL) - Read the data word - This readout might be looped for reading out also other parameters (like T_CAL) 7. Finally it is recommended to send a read command to check the status register again to see, if the sensor is still running in the interface mode before switching off the device Note: This routine can be merged with other (exemplary shown) routines. In that case only one initial frame (the very first interface access) is required after power-on. It is recommended to do a power cycle to get back to normal operating mode, even if it is possible by switching off “DSP stop”, “DSP off” and “PROTOCOL off”. Application Note 25 Rev 1.0, 2009-02 TLE4998C-Programming Guide Interface Access Details - Part III 4.5 Temporary Overwrite of EEPROM Data Following steps are required to readout other internal data like the calibrated temperature and Hall value (as shown below). As the error correction stays disabled, it is not necessary to use correct parity values for this temporary setup. In case the parity is always corrected (and it is desired to check the complete behavior and correct EEPROM array calculation), the “FEC off” bit could be switched off again after the temprary EEPROM write, too. Wait cycle time of protocol (min. time). EEPROM programming Vdd = 5V INIT-CMD: cmd=0x01 adr=0x0F READ DATA Is 0xA93D ? NO ILLEGAL STATUS: analyse problem Figure 19 CMD (write) cmd=0x09 adr=0x10..1A WR. DATA CMD (write): cmd=0x09 adr=0x21 DAT: 0x06C0 (DSP, FEC, REF, PROT. off) Optionally , do a last status readout (adr. 0x0F) to check if the IF mode is still active and the device is ok . CMD (write): cmd=0x09 adr=0x21 DAT: 0x0240 (FEC, REF off) Vdd = 0V (off) All other EEPROM registers can be written here in a loop (as required). Here the output should show (temporarily) the desired result (before switching off the supply, of course). FINISHED Basic (temporary) EEPROM register overwrite flow Description of the above flowchart: 1. Switch on the device. 2. Send an inital command (status register readout). 3. Read the status data, check that the device is valid and the EEPROM content is valid. 4. Set the test register: DSP off=1 FEC off=1 REF off=1 PROTOCOL off=1 (see previous chapter). 5. Send a write command (for any EEPROM register). The parity bits in the 16 bit data word may be kept zero, if FEC off =1. 6. Set the test register: FEC off=1 REF off=1 (see previous chapter). The device is now temporarily working with the new EEPROM setting. 7. Finally it is recommended to send a read command to check the status register again to see, if the sensor is still running in the interface mode before switching off the device. Application Note 26 Rev 1.0, 2009-02 TLE4998C-Programming Guide Application Circuit for Programming Note: This routine can be merged with other (exemplary shown) routines. In that case only one initial frame (the very first interface access) is required after power-on. 5 Application Circuit for Programming Figure 20 shows the connection of multiple sensors to a programmer. 5V application module 2k2 VDD VDD TLE OUT 4998x 47n GND I/O 1 4n7 GND VDD 47n 2k2 TLE OUT 4998x GND Figure 20 optional PROGRAMMER I/O 2 4n7 Application Circuit Note: For calibration and programming, the interface has to be connected directly to the output pin. Application Note 27 Rev 1.0, 2009-02 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG