MD1822DB1 User Guide

Supertex inc.
MD1822DB1
MD1822 + TC7920: Three Level
High Speed ±100V 2.0A Pulser Demoboard
Demoboard Features
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General Description
Ultrasound high voltage & high current RTZ pulser
MD1822 driving TC7920 with two pairs of MOSFETs
3-level voltage pulse waveform outputs
±2.0A source and sink current capability
40 MHz frequency clock on board
Programmable logic waveform generation
JTAG connection for CPLD programming
Connectors for external clock and signals
3.3V CMOS logic interface
Applications
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Medical ultrasound imaging
Piezoelectric transducer drivers
Material flaw detection
ATE and waveform generator
Transducer power driver
Capacitive and MEMS sensor driver
Ultrasonic NDT detection and sonar ranger
Block Diagram
The MD1822DB1 is a demoboard for the three level ±100V
2.5A pulser chip-set of the MD1822 MOSFET driver and the
TC7920 MOSFET. The demoboard consists of one MD1822
in the 3x3mm 16-lead QFN package driving the TC7920
which has two pairs of high speed and high voltage complimentary P- and N-MOSFETs in in one 4x4mm, 8-lead DFN
package. This circuit is an ideal, cost-optimized, high voltage
and high current RTZ ultrasound transmit pulser.
The CPLD-programmable logic circuit (40 MHz crystal oscillator) generates accurately timed high-speed waveforms
on a separate CPL board. Multiple frequency and waveform
combinations can be selected as bipolar pulse waveforms.
An external clock input can be used if the on-board oscillator is disabled. The external trigger input can be used to
synchronize the output waveforms. There are five push
buttons for selecting demonstration waveform, frequency,
phase, and mode functions. Color LEDs indicate the demo
selection states. Jumpers on the board can select either the
330pF/2.5k on-board load, or user test loads.
JTAG
+12V
+3.3V
6
PE
EXTRG
+100V
VPP
VDD/VH
INC
EXCLK
40MHz
OSC
EN
CLKIN
Waveform
Generator
CPLD
IND
X1
INA
EXT
CL
330pF
INB
5
WAVE
FREQ
SEL
CLMP
ENAB
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XDCR
-100V
VNN
LED1
LED2
PWR
ENA
MOD
RL
2.5k
VSS/VL
TC7920
MD1822
Supertex inc.
www.supertex.com
MD1822DB1
MD1822DB1 Board and PCB Layout
Actual size = 100mm x 70mm
Operating Supply Voltages and Current (on J10)
Symbol
VCC
GND
Parameter
Min
Typ
Max
Units
Logic supply
1.8
3.3
3.3
V
150mA
-
0
-
V
---
5.0
10
11.5
V
10mA
Circuit ground or 0V
Suggested Current Limit *
VDD
MD1822 positive supply
VPP
TC7920 HV positive supply
0
-
100
V
5.0mA
VNN
TC7920 HV negative supply
-100
-
0
V
5.0mA
Note:
* Current limits should be changed according the testing waveform, frequency and duty cycles.
Push Button Operation Functions
Button Symbol
Description
WAVE
Demo waveforms selection
FREQ
Demo waveform frequency selection
SEL
Not Used
ENA
MD1822 PE pin control
PHASE
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Not Used
2
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3
2
1
3
2
1
J7
EXTRG
J5
CH1
2
3
2
3
J3
2
EXCLK
J2
EX=Low
C21
0
R19
50
1
1
R32
50
1
GND
2 1
R13
1k
3
4
R5
1k
R4
1k
EXTRG
CH1
C28
0.1
SW1
C27
0.1
R27
200
SW3
R26
200
SW2
TP21
R22
33k
R21
33k
TP12
39
40
R20
33k
VCC
2 1
YLW
R6
1k
GRN
31
YLW
TP6
TP9 36
TESTA
TP8
37
TESTB
38
TESTC
43
CLK
1 2
TP7
TP10
R15
50 TP16
OUT
VCC
40MHzX1
EN
YLW
30
R7
1k
RED
R3
1k
D5
U2
XC9572XZ - VQ44
LED2
C6
0.1
D4
29
LED3
D3
ENA
D2
28
PWR
D1
32
LED1
4
GND
17
GND
25
GND
PE
INA
IND
C30
0.1
R29
200
SW5
R28
200
SW4
C29
0.1
R24
33k
R23
33k
C31
0.1
R30
200
D6A
1
6
TP24
C16
0.1
VCC
VCC
1
2
11
OUTB
OUTA
OUTD
OUTC
VNN
3
D7
B1100-13
VSS
6
14
1
2
7
D8
B1100-13
TP22
17
13
12
9
C12A
10nF
3
1
7 2
6
5 5
1 8
C12B
10nF
2
3
C12C
10nF
10
8
4
C12D
10nF
VH1
VDD
GND VSS VSS VL2 VL1
INB
INA
IND
INC
PE
2
C11
1.0
VDD VH2
C10
0.1
U1
MD1822
TP20
1 2
TP15
1
16
5
4
15
R17
200
VDD VPP
R10
200
1 2 3 4 5
J10
Header 5
4
3
TP21
1 2
R16
200
TP13
D6B
20 R42 50
19 R41 50
R9
200
1 2
1 2
1 2
R8
200
TP4
TP3
C5
0.1
VCC
TP2
C9
0.1
18 R39 50
1 2 3 4 5 6
J8
JTAG
TP14
TP17
INB
C8
0.1
22 R38 50
21
C7
0.1
INC
C4
0.1
35
VCC
26
VCC
VCC 15
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2 WAV
3
FRE
5
SEL
6
ENABLE
7
PHASE
12
13 N.C.
N.C.
TMS
TDI
TDO
TCK
P
P
VNN
N
TC7920
U4
C3
1µF
100V
N
4
8
7
6
12
11
10
9
R34
0
VPP
TC7920
U3
C2
1µF
100V
R18
0
R25
0
R31
0
2
3
6
Optional
5
1
D9
MMBD3004BRM
4
R11
2.49k
1W
R33
0
C18
330p
250V
2
TXOUT
TP1
1 2
R14
3
5.0
1
J9
Schematic Diagram
10
9
24
11
VCC
MD1822DB1
Supertex inc.
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MD1822DB1
Demo Waveforms
Demo Waveform A` (8-Cycle)
Demo Waveform A (8-Cycle)
PIN
NIN
DMP
VPP
TX
0V
VNN
Demo Waveform B` (2-Cycle)
Demo Waveform B (2-Cycle)
PIN
NIN
DMP
TX1
VPP
0V
VNN
Demo Waveform C (4.5-Cycle)
Demo Waveform C` (4.5-Cycle)
PIN
NIN
DMP
TX
VPP
0V
VNN
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MD1822DB1
Demo Waveforms (cont.)
Demo Waveform D (8-Cycle w/o Damping)
PIN
NIN
DMP
VPP
TX
0V
VNN
Demo Waveform E (16-Cycle w/o Damping)
PIN
NIN
DMP
VPP
TX
0V
VNN
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MD1822DB1
Test Waveforms
Fig 1: Input and output waveforms at VDD= 10V, VPP/VNN = ±70V, Load = 330pF//2.5k.
Fig 2: Input and output waveforms at VDD= 10V, VPP/VNN = ±70V, Load = 330pF//2.5k.
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MD1822DB1
Test Waveforms (cont.)
Fig 3: Input and output waveforms at VDD=10V, VPP/VNN= ±70V, Load = 330pF//2.5k.
Fig 4: Input to output delay and rise time of output at VDD = 10V, VPP/VNN = ±70V, Load = 330pF//2.5k,
IOUT= 330pF(103V/13.6ns) = 2.5A.
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MD1822DB1
Test Waveforms (cont.)
Fig 5: Input to output delay and fall time of output at VDD = 10V, VPP/VNN = ±70V, Load = 330pF//2.5k,
IOUT = 330pF(104V/13.2ns) = 2.5A.
JTAG or Boundary Scan Mode
JTAG or Boundary Scan mode is an industry standard (IEEE
1149.1, or 1532) serial programming mode. External logic
from a cable, microprocessor, or other device is used to
drive the JTAG specific pins, Test Data Out (TDO), Test Data
JTAG Connector
Pin Number
In (TDI), Test Mode Select (TMS), and Test Clock (TCK).
This mode has gained popularity due to its standardization
and ability to program CPLD through the same four JTAG
pins. The data in this mode is loaded at one bit per TCK.
Description
J8-1
TMS
Test Mode Select of CPLD.
J8-2
TDI
Test Data In of CPLD.
J8-3
TDO
Test Data Out of CPLD.
J8-4
TCK
Test Clock of CPLD.
J8-5
GND
Logic Power Supply Ground 0V for programming and testing only.
J8-6
VCC
Logic Power Supply +3.3V for CPLD programming or testing only.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
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8
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com