LTC2644 Dual 12-/10-/8-Bit PWM to VOUT DACs with 10ppm/°C Reference FEATURES DESCRIPTION No Latency PWM-to-Voltage Conversion n Voltage Output Updates and Settles within 8µs n100kHz to 30Hz PWM Input Frequency n±2.5LSB Max INL; ±1LSB Max DNL (LTC2644-12) n Guaranteed Monotonic n Pin-Selectable Internal or External Reference n2.7V to 5.5V Supply Range n1.71V to 5.5V Input Voltage Range n Low Power: 2.7mA at 3V, <1µA Power-Down n Guaranteed Operation from –40°C to 125°C n12-Lead MSOP Package The LTC®2644 is a family of dual 12-, 10-, and 8-bit PWMto-voltage output DACs with an integrated high accuracy, low drift, 10ppm/°C reference in a 12-lead MSOP package. It has rail-to-rail output buffers and is guaranteed monotonic. APPLICATIONS The LTC2644 has a full-scale output of 2.5V using the 10ppm/°C internal reference. It can operate with an external reference, which sets the full-scale output equal to the external reference voltage. Each DAC enters a pin-selectable idle state when the PWM input is held unchanged for more than 60ms. The part operates from a single 2.7V to 5.5V supply and supports PWM input voltages from 1.71V to 5.5V. n n n n n n n The LTC2644 measures the period and pulse width of the PWM input signals and updates the voltage output DACs after each corresponding PWM input rising edge. The DAC outputs update and settle to 12-bit accuracy within 8µs typically and are capable of sourcing and sinking up to 5mA (3V) or 10mA (5V), eliminating voltage ripple and replacing slow analog filters and buffer amplifiers. Digital Calibration Trimming and Adjustment Level Setting Process Control and Industrial Automation Instrumentation Automotive L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245, 5859606, 6891433, 6937178, 7414561. TYPICAL APPLICATION 2-Channel PWM to Voltage Output DAC PWM Input to DAC Output PWM INPUTS INA BUFFERED VOLTAGE OUTPUTS VOUTA INB VOUTB LTC2644 1.7V TO 5.5V 0.1µF IOVCC REF PD VCC GND IDLSEL REFSEL GND INA 2V/DIV INPUT: 1V TO 5.5V OUTPUT: 1.25V 2.7V TO 5.5V 0.1µF VOUTA 500mV/DIV 0.1µF 2644 TA01a 20µs/DIV 2644TA01b 2644f For more information www.linear.com/LTC2644 1 LTC2644 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltages (VCC, IOVCC)....................... –0.3V to 6V INA, INB......................................................... –0.3V to 6V IDLSEL, PD, REFSEL..................................... –0.3V to 6V VOUTA, VOUTB....................–0.3V to Min (VCC + 0.3V, 6V) REF...................................–0.3V to Min (VCC + 0.3V, 6V) Operating Temperature Range LTC2644C................................................. 0°C to 70°C LTC2644I..............................................–40°C to 85°C LTC2644H........................................... –40°C to 125°C Maximum Junction Temperature........................... 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec).................... 300°C TOP VIEW VCC VOUTA VOUTB IDLSEL IOVCC GND 1 2 3 4 5 6 12 11 10 9 8 7 GND REFSEL REF INA INB PD MS PACKAGE 12-LEAD PLASTIC MSOP (4mm × 4.9mm) TJMAX = 150°C, θJA = 135°C/W 2644f 2 For more information www.linear.com/LTC2644 LTC2644 ORDER INFORMATION LTC2644 C MS –L 12 #TR PBF LEAD FREE DESIGNATOR TAPE AND REEL TR = 2,500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V PACKAGE TYPE MS = 12-Lead MSOP TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) H = Automotive Temperature Range (–40°C to 125°C) PRODUCT PART NUMBER Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ PRODUCT SELECTION GUIDE PART NUMBER LTC2644-L12 LTC2644-L10 LTC2644-L8 PART MARKING* RESOLUTION CHANNELS VFS WITH INTERNAL REFERENCE MAXIMUM INL PACKAGE DESCRIPTION 644L12 644L10 2644L8 12-Bit 10-Bit 8-Bit 2 2 2 2.5V 2.5V 2.5V ±2.5LSB ±1LSB ±0.5LSB 12-Lead Plastic MSOP 12-Lead Plastic MSOP 12-Lead Plastic MSOP *Temperature grades are identified by a label on the shipping container. 2644f For more information www.linear.com/LTC2644 3 LTC2644 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2644-L12/-L10/-L8 (VFS = 2.5V) LTC2644-L8 SYMBOL PARAMETER CONDITIONS MIN TYP LTC2644-L10 MAX MIN TYP LTC2644-L12 MAX MIN TYP MAX UNITS DC Performance Resolution DNL l 8 10 12 Bits 8 10 12 Bits Monotonicity VCC = 3V, Internal Ref. (Note 3) l Differential Nonlinearity VCC = 3V, Internal Ref. (Note 3) l ±0.5 ±0.5 ±1 LSB INL Integral Nonlinearity VCC = 3V, Internal Ref. (Note 3) l ±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 LSB ZSE Zero-Scale Error VCC = 3V, Internal Ref., Code = 0 l 0.5 5 0.5 5 0.5 5 mV VOS Offset Error VCC = 3V, Internal Ref. (Note 4) l ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV VOSTC VOS Temperature Coefficient VCC = 3V, Internal Ref. (Note 9) GE Gain Error VCC = 3V, Internal Ref. GETC Gain Temperature Coefficient VCC = 3V, Internal Ref. (Note 9) C-grade I-grade H-grade Load Regulation Internal Ref., Mid-Scale, VCC = 3V ±10%, –5mA ≤ IOUT ≤ 5mA l 0.009 0.016 0.035 0.064 0.14 0.256 LSB/mA VCC = 5V ±10%, –10mA ≤ IOUT ≤ 10mA l 0.009 0.016 0.035 0.064 0.14 0.256 LSB/mA Internal Ref., Mid-Scale, VCC = 3V ±10%, –5mA ≤ IOUT ≤ 5mA l 0.09 0.156 0.09 0.156 0.09 0.156 Ω VCC = 5V ±10%, –10mA ≤ IOUT ≤ 10mA l 0.09 0.156 0.09 0.156 0.09 0.156 Ω ROUT DC Output Impedance ±10 ±0.2 l SYMBOL PARAMETER ±10 ±0.8 10 10 10 ±0.2 ±10 ±0.8 ±0.2 10 10 10 µV/°C ±0.8 10 10 10 CONDITIONS MIN VOUT DAC Output Span External Reference Internal Reference PSR Power Supply Rejection VCC = 3V ±10% or 5V ±10% ISC Short Circuit Output Current (Note 5) Sinking Sourcing VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND l l TYP %FSR ppm/°C ppm/°C ppm/°C MAX UNITS 0 to VREF 0 to 2.5 V V –80 dB 27 –28 48 –48 mA mA V Power Supply VCC Positive Supply Voltage For Specified Performance l 2.7 5.5 IOVCC Digital Input Supply Voltage For Specified Performance l 1.71 5.5 ICC Supply Current (Note 6) VCC = 3V, Internal Reference VCC = 5V, Internal Reference l l 2.7 4.6 4 6 mA mA IOVCC = 5V l 25 50 µA VCC = 5V, PD = 0V l 0.5 5 µA IOVCC = 5V, PD = 0V l 0.5 5 µA ICC(IOVCC) Supply Current, IOVCC (Note 6) ISD Supply Current in Power-Down Mode (Note 6) ISD(IOVCC) Supply Current in Power-Down Mode, IOVCC (Note 6) 2644f 4 For more information www.linear.com/LTC2644 LTC2644 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2644-L12/-L10/-L8 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC V 200 kΩ Reference Input VREF Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power-Down Mode 160 7.5 DAC Powered Down l pF 0.005 1.5 µA 1.25 1.26 V Reference Output Output Voltage Reference Temperature Coefficient l 1.24 ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving 10 µF 2.5 mA Short Circuit Current (Note 9) VCC = 5.5V, REF Shorted to GND Digital Inputs (INA, INB, PD) VIH Digital Input High Voltage l VIL Digital Input Low Voltage l 0.8•IOVCC 0.5 V V ILK Digital Input Leakage INA/INB = GND to IOVCC l ±1 µA CIN Digital Input Capacitance (Note 7) l 5 pF AC Performance ts en Settling Time From INA/INB Rising Edge (Note 8) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) 7.0 7.4 7.8 µs µs µs Voltage Output Slew Rate 1.0 V/µs Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 2.1 nV • s DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switched 0 to FS 0.9 nV • s Multiplying Bandwidth External Reference 320 kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 200 180 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1µF 35 40 680 730 nVP-P nVP-P nVP-P nVP-P 2644f For more information www.linear.com/LTC2644 5 LTC2644 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2644-L12/-L10/-L8 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tPWH INA/INB High Time l 25 ns tPWL INA/INB Low Time l 25 ns tPER INA/INB Rising Edge to Rising Edge Period LTC2644-L12 l 0.160 33 ms LTC2644-L10 l 0.040 33 ms LTC2644-L8 l 0.010 33 ms l 50 70 ms t3 INA/INB Idle Mode Timeout t4 INA/INB Rising Edge to DAC Update Delay fMAX INA/INB Frequency 3.2 LTC2644-L12 l 0.03 LTC2644-L10 l LTC2644-L8 l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages with respect to GND. Note 3: Linearity and monotonicity are defined from code 16 to code 4095 (LTC2644-12), code 4 to code 1023 (LTC2644-10) or code 1 to code 255 (LTC2644-8). Note 4: Inferred from measurement at code 16 (LTC2644-12), code 4 (LTC2644-10) or code 1 (LTC2644-8), and at full-scale. µs 6.25 kHz 0.03 25 kHz 0.03 100 kHz Note 5: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 6: INx at 0V or IOVCC. Note 7: Guaranteed by design and not production tested. Note 8: Internal Reference mode. DAC is stepped ¼ scale to ¾ scale and ¾ scale to ¼ scale. Load is 2kΩ in parallel with 100pF to GND. Note 9: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 2644f 6 For more information www.linear.com/LTC2644 LTC2644 TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, unless otherwise noted.) LTC2644-12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 3V tPER = 200µs INTERNAL REFERENCE 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 VCC = 3V tPER = 200µs INTERNAL REFERENCE 0 –0.5 0 25 –1.0 100 50 75 DUTY CYCLE (%) 0 50 75 DUTY CYCLE (%) 25 2644 G01 INL vs Temperature 1.0 INL = (POS) DNL (LSB) INL (LSB) –1.0 –50 INL = (NEG) –25 1.260 VCC = 3V 0.5 0 –0.5 Reference Output Voltage vs Temperature DNL vs Temperature VCC = 3V 0.5 2644 G02 DNL = (POS) 0 100 125 –1.0 –50 1.245 –25 0 25 50 75 TEMPERATURE (°C) 100 2644 G03 125 1.240 –50 –25 0 25 50 75 TEMPERATURE (°C) 2644 G04 Settling to ±1LSB Rising INX 5V/DIV 1.250 DNL = (NEG) –0.5 0 25 50 75 TEMPERATURE (°C) VCC = 3V 1.255 VREF (V) 1.0 100 100 125 2644 G05 Settling to ±1LSB Falling 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS VOUTX 1LSB/DIV 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 7µs 7.8µs VOUTX 1LSB/DIV INX 5V/DIV 2µs/DIV 2644 G06 2µs/DIV 2644 G07 2644f For more information www.linear.com/LTC2644 7 LTC2644 TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, unless otherwise noted.) LTC2644-10 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 3V tPER = 50µs INTERNAL REFERENCE 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 VCC = 3V tPER = 50µs INTERNAL REFERENCE 0 –0.5 0 25 –1.0 100 50 75 DUTY CYCLE (%) 0 25 100 50 75 DUTY CYCLE (%) 2644 G08 2644 G09 LTC2644-8 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 3V tPER = 10µs INTERNAL REFERENCE 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 VCC = 3V tPER = 10µs INTERNAL REFERENCE 0 –0.5 0 25 –1.0 100 50 75 DUTY CYCLE (%) 0 25 100 50 75 DUTY CYCLE (%) 2644 G10 2644 G11 LTC2644 Load Regulation 8 Current Limiting 0.20 VCC = 5V VCC = 3V 0.15 6 2 ∆VOUT (mV) ∆VOUT (mV) VCC = 5V VCC = 3V 2 0.10 4 0 –2 –4 0.05 0 –0.05 –0.10 –6 INTERNAL REF. CODE = MID-SCALE –8 –10 –30 Offset Error vs Temperature 3 OFFSET ERROR (mV) 10 –20 –10 0 10 20 30 IOUT (mA) –0.15 –0.20 –30 INTERNAL REF. CODE = MID-SCALE –20 –10 0 10 20 30 IOUT (mA) 2644 G12 1 0 –1 –2 –3 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 2644 G13 2644 G14 2644f 8 For more information www.linear.com/LTC2644 LTC2644 TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, unless otherwise noted.) (Internal Reference, VFS = 2.5V) INX to VOUTX Delay Full-Scale Transition Large-Signal Response Entering Idle Mode Zero-Scale from Mid-Scale (IDLSEL = GND) INA 2/DIV INA 2V/DIV VOUTA 500mV/DIV VOUTA 500mV/DIV VOUTX 0.5V/DIV VFS = VREF = VCC = 5V 1/4 SCALE TO 3/4 SCALE 2µs/DIV 2µs/DIV 2644 G15 Entering Idle Mode Full-Scale from Mid-Scale (IDLSEL = GND) INA 2V/DIV 10ms/DIV 2644 G16 Exiting Idle Mode Zero-Scale to Mid-Scale (IDLSEL=GND) 2644 G17 Exiting Idle Mode Full-Scale to Mid-Scale (IDLSEL = GND) INA 2V/DIV INA 2V/DIV VOUTA 500mV/DIV VOUTA 500mV/DIV VOUTA 500mV/DIV 10ms/DIV 1ms/DIV 2644 G18 1ms/DIV 2644 G19 Exiting Idle Mode Power-Down (1 Channel) to Mid-Scale (IDLSEL = VCC) 2644 G20 Power-On-Reset to Idle Mode Full-Scale (IDLSEL = GND) INA 2V/DIV VCC 2V/DIV VREF 1V/DIV INA 2V/DIV VREF 1V/DIV VOUTA 500mV/DIV VOUTA 2V/DIV 500µs/DIV 2644 G21 10ms/DIV 2644 G22 2644f For more information www.linear.com/LTC2644 9 LTC2644 TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, unless otherwise noted.) (Internal Reference, VFS = 2.5V) Supply Current vs Duty Cycle (tPW/tPER) Supply Current vs Input Period (tPER) 8 3.00 LTC2644-12 DUTY CYCLE = 50% 2-CHANNELS ACTIVE 7 2.75 6 ICC (mA) 4 VCC = 3V 3 LTC2644-12 VCC = 5V 2.1nV-s TYPICAL tPER = 200µs INX 5V/DIV tPER = 20ms VCC = 5V 5 ICC (mA) LTC2644-12 VCC = 3V, IDLSEL = 0V 2-CHANNELS ACTIVE Mid-Scale Glitch Impulse 2.50 VOUTX 5mV/DIV 2.25 2 1 0 1 1000 100 PERIOD (µs) 10 10,000 100,000 2.00 0 25 50 75 Gain Error vs Reference Input 0 0.8 –2 0.6 –4 0.4 GAIN ERROR (%FSR) 1.0 dB –6 –8 –10 –12 VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL SCALE 1k VCC = 5.5V GAIN ERROR OF 2 CHANNELS 0.2 0 –0.2 –0.4 –0.6 –1.0 1M 1 1.5 2 2.5 3 3.5 4 4.5 REFERENCE VOLTAGE (V) 2644 G26 500 5V SOURCING VOUT (V) NOISE VOLTAGE (nV/√Hz) 4.0 3V SOURCING 2.5 2.0 1.5 5V SINKING 1.0 5 5.5 –1.0 –50 –25 0 25 50 75 TEMPERATURE (°C) 400 100 125 2644 G28 DAC-to-DAC Crosstalk (Dynamic) VCC = 5V CODE = MID-SCALE INTERNAL REF INA 5V/DIV DACA SWITCH 0-FS 2V/DIV 300 LTC2644-12, VCC = 5V VREF = 2.5V 0.9nV-s TYP 200 VOUTB 1mV/DIV 100 3V SINKING 0.5 0 –0.5 Noise Voltage vs Frequency 5.0 3.0 0 2644 G27 Headroom at Rails vs Output Current 3.5 0.5 –0.8 10k 100k FREQUENCY (Hz) 4.5 Gain Error vs Temperature 1.0 GAIN ERROR (%FSR) Multiplying Bandwidth –18 2644 G25 2645 G24 2 –16 2µs/DIV DUTY CYCLE (%) 2644 G23 –14 100 0 1 2 3 4 5 6 IOUT (mA) 7 8 9 10 2644 G29 0 100 1k 10k 100k FREQUENCY (Hz) 1M 2µs/DIV 2644 G31 2644 G30 2644f 10 For more information www.linear.com/LTC2644 LTC2644 PIN FUNCTIONS VCC (Pin 1): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V. Bypass to GND with a 0.1µF capacitor. VOUTA, VOUTB (Pins 2, 3): DAC Analog Voltage Outputs. The DAC output voltage can be calculated by the following equation: VOUTX = VREF • tPWHX/tPERX where VREF is 2.5V in internal reference mode or the REF pin voltage in external reference mode, tPWHX is the pulse width of the preceding INX period and tPERX is the time between the two most recent INX rising edges. IDLSEL (Pin 4): Idle Mode Select Input. Connect IDLSEL to GND or VCC to select the behavior of the DAC output when there has been no rising edge on the PWM input for more than the idle mode timeout delay t3 (nominal delay is 60ms). Available idle mode states are power-down with high impedance output, hold previous state, zero-scale or full-scale. This pin also selects the initial state of the DAC outputs following a power-on reset. IOVCC (Pin 5): I/O Supply Voltage Input. 1.71V ≤ IOVCC ≤ 5.5V. Bypass to GND with a 0.1µF capacitor. GND (Pins 6, 12): Ground. PD (Pin 7): Active-Low Power-Down Input. Connect PD to GND to place the part in power-down with a typical supply current of <1µA. Connect PD to IOVCC for normal operation. INA, INB (Pins 9, 8): PWM Inputs. Apply a pulse-width modulated input frequency between 30Hz and 6.25kHz (12-bit), 25kHz (10-bit) or 100kHz (8-bit). After each INX rising edge, the part calculates the duty cycle based upon the pulse width and period and updates DAC channel VOUTX. Logic levels are referenced to IOVCC. REFSEL (Pin 11): Reference Select Input. Connect REFSEL to GND to select internal reference mode. Connect REFSEL to VCC to select external reference mode. REF (Pin 10): Reference Voltage Input or Output. When REFSEL is connected to VCC, REF is an input (1V ≤ VREF ≤ VCC) where the voltage supplied sets the full-scale DAC output voltage. When REFSEL is connected to GND, the 10ppm/°C, 1.25V internal reference (half full-scale) is available at the pin. This output may be bypassed to GND with up to 10µF and must be buffered when driving external DC load current. 2644f For more information www.linear.com/LTC2644 11 LTC2644 BLOCK DIAGRAM REFSEL 5 IOVCC 4 IDLSEL INTERNAL REFERENCE SWITCH 7 PD 9 8 VREF INA PWM TO BINARY CONVERSION DAC A INB PWM TO BINARY CONVERSION DAC B 12 GND REF 11 10 VCC 1 VOUTA VOUTB 2 3 GND 6 2644 BD 2644f 12 For more information www.linear.com/LTC2644 LTC2644 TIMING DIAGRAMS tPWH tPWL INX tPER t3 tS VOUT = (tPWH/tPER) • VREF VOUTX IDLE STATE 2644 TD01a t4 Figure 1a. SAMPLE #1 tPWH1 HOLD #1 tPER1 tHOLD1 > t3 SAMPLE #2 tPWH2 HOLD #2 INX tPER2 tPWL < t3 VOUT2 = (tPWH2/tPER2)*VREF 2644 TD01b VOUT1 = (tPWH1/tPER1)*VREF t4 VOUTX t4 Figure 1b. Sample/Hold Operation (IDLSEL = VCC) SAMPLE #1 tPWH1 SAMPLE #2 tPWH2 INX tPER1 tIDLE(LOW) ≥ t3 tPER2 tIDLE(HIGH) ≥ t3 VOUT = VREF VOUT1 = (tPWH1/tPER1) • VREF VOUTX t4 IDLE STATE TIMEOUT LOW VOUT = GND VOUT2 = (tPWH2/tPER2) • VREF t4 IDLE STATE TIMEOUT HIGH 2644 TD01c Figure 1c. Transparent Operation (IDLSEL = GND) 2644f For more information www.linear.com/LTC2644 13 LTC2644 OPERATION The LTC2644 is a family of dual PWM input, voltage output DACs in a 12-lead MSOP package. The part measures the pulse width and period of the PWM inputs and updates each DAC output after the corresponding PWM input rising edge. Each DAC can operate rail-to-rail using an external reference, or with a 2.5V full-scale voltage using an integrated reference. Three resolutions (12-, 10-, and 8-bit) are available. PWM-to-Voltage Conversion The LTC2644 converts a PWM input to an accurate, stable, buffered voltage without the latency, slow settling, and highvalue passive components required for discrete solutions. The PWM input pins (INX) accept frequencies from 30Hz up to 6.25kHz (12-bit), 25kHz (10-bit), or 100kHz (8-bit). The duty cycle is calculated after each PWM input rising edge based upon the previous high and low pulse width. The resulting digital DAC code k is calculated as: k = 2N • tPWHX / tPERX where tPWHX is the pulse width of the preceding INX period and tPERX is the time between the two most recent INX rising edges. The digital-to-analog transfer function is: k VOUT(IDEAL) = N VREF, for k = 0 to 2N – 1 2 where N is the resolution, VREF is 2.5V for internal reference mode or the REF pin voltage for external reference mode. DAC Update Timing The update for DAC output VOUTX occurs following each rising edge input on INX (Figure 1a). Delay tS is the delay from an INX rising edge to the VOUTX settled output voltage corresponding to the previous period’s duty cycle. Delay tS is composed of the computational cycle delay (t4) and the actual settling of the output DAC. The PWM-to-binary, internal computational cycle begins immediately following the INX rising edge. The computational cycle is completed after delay t4 and the DAC output VOUTX is updated. The DAC output typically settles to 12-bit accuracy within 8µs from the INX rising edge. PWM Input Idle Mode Selection When no PWM input rising edge is received for more than the idle mode timeout delay t3 (nominal delay is 60ms), the DAC output enters an idle mode state which can be configured by connecting IDLSEL to GND or VCC according to Table 1 below. Note that these pins also control the initial state of the DACs after power-on reset. Table 1. Power-On Reset and Idle Mode States IDLSEL Power-On Reset INX Idle Low INX Idle Hi GND Zero-Scale Zero-Scale Full-Scale VCC Power-Down Hi-Z Power-Down Hi-Z Hold Transparent Operation For applications in which the PWM input duty cycle may be 0% or 100%, connect IDLSEL to GND to select transparent operation, in which case an idle low input sets the DAC to zero-scale or an idle high input sets the DAC to full-scale. Figure 1c illustrates the timing for transparent operation. Any pair of PWM input rising edges separated by less than the idle mode timeout delay t3 (50ms minimum) will cause the DAC code to be updated following the second rising edge. Note that an idle high input state may be followed by an idle low input state. Sample/Hold Operation The LTC2644 has the capability to sample the pulsewidth/period and hold the corresponding voltage level indefinitely. Unlike analog filter implementations which require the PWM input to run continuously, the LTC2644 may operate with a discontinuous PWM input. Connect IDLSEL to VCC to select sample/hold operation, in which a single pair of rising edges is sufficient to update the DAC, and the DAC code retains its previous value when the PWM input idles high. Figure 1b illustrates correct timing for 2644f 14 For more information www.linear.com/LTC2644 LTC2644 OPERATION sample/hold operations. Any pair of rising edges separated by less than the idle timeout delay t3 (50ms minimum) will cause the DAC code to be updated. Any pair of rising edges separated by more than t3 (70ms maximum) will be ignored and the DAC code will retain its previous value. Note that after power-on-reset or when INX idles low, the DAC will power down with a high impedance output. Short INX Period Operation The accuracy of the PWM to voltage conversion is guaranteed for INX input frequencies up to 6.25 kHz (12-bit), 25kHz (10-bit) or 100kHz (8-bit). Faster INX input frequencies will proportionally decrease the resolution and accuracy of the analog output. For INX input periods of less than the computational delay t4 (nominally 3.2µs), the DAC update will be skipped and the DAC code will retain its previous value. Short INX Pulse-Width Operation Provide INX input high and low pulse widths greater than tPWH and tPWL to ensure that the DAC output is updated after every INX rising edge. High going pulses narrower than tPWH will cause the DAC code to be calculated as zero-scale, and low going pulses narrower than tPWL will cause the DAC code to be calculated as full-scale. For much narrower pulse widths of only a few nanoseconds, the input edge may not be recognized, in which case the DAC update will be skipped entirely and the DAC code will retain its previous value. Power-On Reset The LTC2644 resets the output to a known state when power is first applied, making system initialization consistent and repeatable. Connect the IDLSEL pin to GND or VCC according to Table 1 to cause the DACs to initialize to zero-scale or with the device powered down and the DAC outputs high impedance. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2644 contains circuitry to reduce the power-on glitch when zero-scale reset is selected: the analog output typically rises less than 5mV above zero-scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. Reference Modes For applications where an accurate external reference is not available, nor desirable due to limited space, the LTC2644 has a user-selectable, integrated reference. Internal Reference mode can be selected by connecting the REFSEL pin to GND. The 10ppm/°C, 1.25V internal reference is available at the REF pin. This voltage is internally amplified by 2x to provide a 2.5V full-scale DAC output voltage range. Adding bypass capacitance to the REF pin will improve noise performance; 0.1µF is recommended, and up to 10µF can be driven without oscillation. The REF output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in External Reference mode by connecting the REFSEL pin to VCC. In this mode, an input voltage supplied externally to the REF pin provides the reference (1V ≤ VREF ≤ VCC) and the supply current is reduced. In this mode the full-scale DAC output voltage is equal to the voltage at the REF pin. Power-Down Mode For power constrained applications, power-down mode can be used to reduce the supply current whenever less than two DAC outputs are needed. When in power-down mode, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. 2644f For more information www.linear.com/LTC2644 15 LTC2644 OPERATION If IDLSEL is connected to VCC, either or both channels can be powered down by keeping the PWM input(s) (INA/INB) low for the idle mode timeout delay t3. The integrated reference is automatically powered down when external reference mode is selected or when both DAC channels are powered down. In addition, both DAC channels and the integrated reference can be powered down by pulling the PD pin low. When the integrated reference is powered down, the REF pin becomes high impedance (typically > 1GΩ). 50Ω • 1mA, or 50mV). See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. Normal operating current resumes when PD returns high for transparent operation (IDLSEL = GND). For sample/ hold operation (IDLSEL = VCC), the LTC2644 remains in full power-down until the first rising edge is received on any PWM input. Any pair of PWM input rising edges separated by less than the idle mode timeout delay t3 (50ms minimum) will cause the DAC code to be updated. The DAC output(s) will remain in Hi-Z until the channel is updated following the second rising PWM input edge. Since the analog output of the DAC cannot go below ground, it may limit the lowest codes reachable as shown in Figure 2b. Similarly, limiting can occur near full-scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 2c. No full-scale limiting will occur if VREF is less than VCC–FSE. Voltage Output The LTC2644’s integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ω. The amplifier’s DC output impedance is 0.1Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is The amplifier is stable driving capacitive loads of up to 500pF. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. The resistance from the LTC2644 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1Ω). Note that the LTC2644 is no more susceptible to this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. 2644f 16 For more information www.linear.com/LTC2644 LTC2644 OPERATION Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2644 is sinking large currents, this current flows out of the ground pin and directly into the power ground trace without affecting the analog ground plane voltage. It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0V NEGATIVE OFFSET 0V 0 2048 INPUT CODE (a) 2645 F02 4095 INPUT CODE (b) Figure 2. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12 Bits). (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale 2644f For more information www.linear.com/LTC2644 17 LTC2644 TYPICAL APPLICATIONS VLOOP 5.4V TO 80V IN LT3010-5 OUT SHDN 1µF + SENSE GND 1µF PD OPTO-ISOLATORS PWMINA PWMINB 500Ω 0.1µF PS9851-2 INA 500Ω INB IOVCC REF VCC VOUTA RGAIN1 76.8k 0.1% VOUTB RGAIN2 76.8k 0.1% LTC2644 -12 PWM TO BINARY DAC A PWM TO BINARY DAC B ROFFSET2 374k 0.1% ROFFSET1 374k 0.1% 3.01k IOUTA V + + 1k – 1000pF + 1k – REFSEL GND 10Ω LTC2055 IDLSEL 2N3440 2N3440 – V 1000pF 10Ω 10k 10k IOUTB 3.01k 2644 F03 Figure 3. An Opto-Isolated, PWM Regulated 4mA to 20mA Process Controller 2.7V TO 5.5V C3 0.1µF EXT INPUT: 1V TO VCC C4 0.1µF 5V C2 0.1µF IOVCC ISOLATION BARRIER ANALOG PWM DUTY CYCLE CONTROL (0V TO 1V) PS9851-1 LTC6992 MOD OUT GND V+ SET DIV RSET 50k PD REF LTC2644 -12 INA PWM TO BINARY DAC A INB PWM TO BINARY DAC B 2.25V TO 5.5V C1 0.1µF VCC IDLSEL REFSEL VOUTA VOUTB DAC CONTROL VOLTAGE OUTPUT (0V TO VREF) VOUTB = Hi-Z GND 2644 F04 Figure 4. Analog Control Voltage with PWM Transmission to DAC Control Voltage Output 2644f 18 For more information www.linear.com/LTC2644 LTC2644 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 12-Lead Plastic MSOP (Reference LTC DWG # 05-08-1668 Rev A) 0.889 ±0.127 (.035 ±.005) 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.65 (.0256) BSC 0.42 ±0.038 (.0165 ±.0015) TYP 12 11 10 9 8 7 RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) 0° – 6° TYP 0.406 ±0.076 (.016 ±.003) REF GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 1 2 3 4 5 6 0.650 (.0256) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 0.1016 ±0.0508 (.004 ±.002) MSOP (MS12) 0213 REV A 2644f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more information www.linear.com/LTC2644 tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2644 TYPICAL APPLICATION 5V C3 0.1µF C4 0.1µF 0.1µF 4.7µF 2.2k IOVCC PD INA INB VCC IDLSEL REFSEL REF 0.1µF LTC2644 -12 PWM TO BINARY DAC A 10k VOUTA PWM TO BINARY DAC B VIN ILM 143k PGOOD INTVCC LTC3850EUF RJK0305DPB TG1 BOOST1 FREQ 0.1µF 2.2µH 0.008k SW1 VOUTB = Hi-Z 1nF CMDSH-3 100k 10k 0.1µF VOUTB VIN 6.5V TO 14V RJK0301DPB BG1 3.32k VOUT 3.3V ±10% PGND GND FOR NO MARGINING, KEEP INA LOW. (VOUTA = Hi-Z) TO MARGIN 10% HIGH, SET INA DUTY CYCLE TO 1/4096 (VOUTA = 0V) TO MARGIN 10% LOW, SET INA DUTY CYCLE TO 2621/4096 (VOUTA = 1.6V) 1nF 500kHz 100pF 10k 10k SENSE1+ ITH1 MODE/PLLIN RUN1 1nF SENSE1– TKSS1 10nF 10k VFB1 SGND 63.4k 15pF 2645 F05 20k Figure 5. Voltage Margining Application with LTC3850 (3.3V ±10%) RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2645 Quad 12-/10-/8-Bit PWM to VOUT DACs with 10ppm/°C Reference Zero Latency Bus Update, 100kHz to 30Hz Input Frequency, ±2.5LSB INL, 2.7V to 5.5V Supply Range, 16-Lead MSOP Package LT®1991 Precision, 100µA Gain Selectable Amplifier Gain Accuracy of 0.04%, Gains from –13 to 14, 100µA Precision Op Amp LT1469-2 Dual 200MHz, 30V/µs 16-Bit Accurate Op Amp 200MHz Gain Bandwidth, 125µV Offset, 30V/µs Slew Rate Precision Op Amp LTC2055 Dual Micropower Zero-Drift Op Amp 2.7V Minimum Supply Voltage, 150µA Supply Current per Amplifier, Zero-Drift Op Amp LTC6992 Timer Blox: Voltage-Controlled Pulse Width Modulator (PWM) 3.8Hz to 1MHz Output Frequency Range, 0V to 1V Analog Input, < 1.7% Maximum Frequency Error LTC2632/LTC2633 Dual 12-/10-/8-Bit SPI/I2C VOUT DACs with 10ppm/°C Reference ±2.5LSB INL, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, 8-Lead ThinSOT™ Package 2644f 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2644 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2644 LT 0814 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014