ISL6273 ® Data Sheet March 7, 2006 1.2A Low Quiescent Current 1.5MHz High Efficiency Synchronous Buck Regulator ISL6273 is a 1.2A, 1.5MHz step-down regulator, which is ideal for powering low-voltage microprocessors in compact devices such as PDAs and cellular phones. It is optimized for generating low output voltages down to 0.8V. The supply voltage range is from 2.7V to 5.5V allowing the use of a single Li+ cell, three NiMH cells or a regulated 5V input. It has guaranteed minimum output current of 1.2A. 1.5MHz pulse-width modulation (PWM) switching frequency allows using small external components. It has flexible operation mode selection of forced PWM mode and low IQ mode with as low as 25µA quiescent current for highest light load efficiency to maximize battery life. The ISL6273 includes a pair of low on-resistance P-channel and N-channel internal MOSFETs to maximize efficiency and minimize external component count. 100% duty-cycle operation allows less than 200mV dropout voltage at 1.2A. The ISL6273 offers a 200ms Power-On-Reset (POR) timer at power up. The timer output can be reset by RSI. When shutdown, ISL6273 discharges the output capacitor. Other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. The ISL6273 is offered in a 10 Ld 3x3mm DFN package with 1mm maximum height. The complete converter occupies less than 1 cm2 area. ISL6273IRZ TEMP. RANGE PART (°C) MARKING Features • High efficiency Synchronous Buck Regulator with up to 95% Efficiency • 200ms Reset Timer • Discharge Output Cap when Shutdown • 2.7V to 5.5V Supply Voltage • 3% Output Accuracy Over Temperature/Load/Line • 1.2A Guaranteed Output Current • 25µA Quiescent Supply Current in IQ Mode • Selectable Forced PWM Mode and IQ Mode • Less than 1µA Logic Controlled Shutdown Current • 100% Maximum Duty Cycle for Lowest Dropout • Internal Loop Compensation • Internal Digital Soft-Start • Peak Current Limiting, Short Circuit Protection • Over-Temperature Protection • Enable • Small 10 Ld 3x3mm DFN • Pb-Free Plus Anneal Available (RoHS Compliant) Applications Ordering Information PART NUMBER (NOTE) • Single Li-Ion Battery-Powered Equipment PACKAGE (Pb-free) PKG. DWG. # 273Z -40 to 85 10 Ld 3x3 DFN L10.3x3C ISL6273IRZ-T 273Z -40 to 85 10 Ld 3x3 DFN L10.3x3C NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • DSP Core Power • PDAs and Palmtops Pinout ISL6273 (10 LD 3X3 DFN) TOP VIEW PVIN 1 10 PHASE VCC 2 9 PGND EN 3 8 SGND POR 4 MODE 1 FN9256.0 5 7 FB 6 RSI CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6273 Absolute Maximum Ratings (Reference to SGND) Thermal Information Supply Voltage (PVIN, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V EN, RSI, MODE, PHASE, POR . . . . . . . . . . . . . -0.3V to VCC+0.3V FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Thermal Resistance (Notes 1, 2) θJA (°C/W) θJC (°C/W) 3x3 DFN Package . . . . . . . . . . . . . . 44 5.5 Junction Temperature Range. . . . . . . . . . . . . . . . . . . -40°C to 125°C Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Recommended Operating Conditions PVIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.2A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specification are measured at the following conditions: TA = 25°C, VPVIN = VVCC = 3.6V, EN = VCC, RSI = 0V, MODE = VCC, L = 1.8µH, C1 = 10µF, C2 = 10µF, IOUT = 0A (see the Typical Application Circuit). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Rising - 2.5 2.7 V Falling 2.2 2.4 - V MODE = VCC, no load at the output - 25 50 µA MODE = SGND, no load at the output - 5 8 mA ISD VCC = PVIN = 5.5V, EN = low - 0.1 2 µA VFB TA = 0°C to 85°C 0.784 0.8 0.816 V TA = -40°C to 85°C 0.78 0.8 0.82 V FB = 0.75V - 0.1 - µA Output Voltage Accuracy PVIN = VO + 0.5V to 5.5V, Io = 0 to 1.2A , TA = -40°C to 85°C -3 - 3 % Line Regulation PVIN = VO + 0.5V to 5.5V (minimal 2.7V) - 0.2 - %/V 1.2 - - A Adjustable version, design info only - 20 - µA/V PVIN = 3.6V, Io = 200mA - 0.12 0.22 Ω PVIN = 2.7V, Io = 200mA - 0.16 0.27 Ω PVIN = 3.6V, Io = 200mA - 0.11 0.22 Ω PVIN = 2.7V, Io = 200mA - 0.15 0.27 Ω 1.5 2.1 2.6 A - 100 - % 1.35 1.5 1.75 MHz - - 140 ns - 1.1 - ms SUPPLY VCC Undervoltage Lockout Threshold Quiescent Supply Current VUVLO IPVIN Shut Down Supply Current OUTPUT REGULATION FB Regulation Voltage FB Bias Current IFB Maximum Output Current COMPENSATION Error Amplifier Trans-conductance PHASE P-Channel MOSFET On Resistance N-Channel MOSFET On Resistance P-Channel MOSFET Peak Current Limit IPK PHASE Maximum Duty Cycle PWM Switching Frequency fS PHASE Minimum On Time TA = -40°C to 85°C MODE = low (forced PWM mode) Soft Start-Up Time 2 FN9256.0 March 7, 2006 ISL6273 Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specification are measured at the following conditions: TA = 25°C, VPVIN = VVCC = 3.6V, EN = VCC, RSI = 0V, MODE = VCC, L = 1.8µH, C1 = 10µF, C2 = 10µF, IOUT = 0A (see the Typical Application Circuit). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - - 0.3 V 150 200 275 ms - 0.01 0.1 µA 1.2 - - V POR Output Low Voltage Sinking 1mA, FB = 0.7V Delay Time POR Pin Leakage Current POR = VCC = 3.6V Minimum Supply Voltage for Valid POR Signal Internal PGOOD Low Rising Threshold Percentage of Nominal Regulation Voltage 89.5 92 94.5 % Internal PGOOD Low Falling Threshold Percentage of Nominal Regulation Voltage 85 88 91 % Internal PGOOD High Rising Threshold Percentage of Nominal Regulation Voltage 105.5 108 110.5 % Internal PGOOD High Falling Threshold Percentage of Nominal Regulation Voltage 102 105 108 % - 50 - µs Logic Input Low - - 0.4 V Logic Input High 1.4 - - V - 0.1 1 µA Thermal Shutdown - 150 - °C Thermal Shutdown Hysteresis - 25 - °C Internal PGOOD Delay Time EN, MODE, RSI Logic Input Leakage Current Pulled up to 5.5V 3 FN9256.0 March 7, 2006 ISL6273 Typical Operating Performance 3.37 100 VO = 2.8V 3.36 VO = 2.5V VO = 1.2V 80 3.35 VOUT (V) EFFICIENCY (%) 90 70 3.34 60 3.32 50 3.31 40 0.1 1 10 3.3 0.1 1000 100 VIN = 3.6V 3.33 1 FIGURE 1. EFFICIENY vs LOAD CURRENT (VIN = 3.6V) 100 1000 FIGURE 2. VOUT vs LOAD CURRENT (VIN = 3.6V) 1.84 100 1.82 90 80 VOUT (V) EFFICIENCY (%) 10 LOAD CURRENT (mA) LOAD CURRENT (mA) VIN = 2.7V 70 1.8 VIN = 2.7V 1.78 60 1.76 50 40 0.1 1 10 100 1000 1.74 0.1 1 LOAD CURRENT (mA) FIGURE 3. EFFICIENCY vs LOAD CURRENT (VO = 1.8V) 1000 7 INPUT CURRENT IN PWM MODE OF 2.8V INPUT CURRENT IN PFM MODE OF 2.8V 0.06 6 INPUT CURRENT (mA) INPUT CURRENT (mA) 100 FIGURE 4. VOUT vs LOAD CURRENT (VIN = 2.7V) 0.07 0.05 0.04 0.03 0.02 0.01 0 2.9 10 LOAD CURRENT (mA) 5 4 3 2 1 3.4 3.9 4.4 4.9 VIN VOLTAGE RANGE (2.9V-5.5V) FIGURE 5. IQ vs VIN (PFM) 4 5.4 0 2.9 3.4 3.9 4.4 4.9 5.4 VIN VOLTAGE RANGE (2.9V-5.5V) FIGURE 6. IQ vs VIN (PWM) FN9256.0 March 7, 2006 ISL6273 Typical Operating Performance (Continued) 1.61 1.6 1.608 1.595 1.606 1.59 VO (V) SWITCHING FREQUENCY (MHz) 1.605 1.585 1.604 1.58 1.602 1.575 1.57 2.7 1.6 3.2 3.7 4.2 4.7 5.2 2.7 3.7 4.7 VIN (V) VIN (V) FIGURE 7. SWITCHING FREQUENCY vs VIN FIGURE 8. LINE REGULATION (IO = 1A) 1.61 VO (V) 1.605 1.6 1.595 1.59 0 200 400 600 800 1000 IO (mA) FIGURE 9. LOAD REGULATION (VIN = 3.6V IN PWM MODE) FIGURE 11. PFM MODE (VIN = 3V; VO = 1.6V; IO = 50mA) 5 FIGURE 10. SOFT-START FIGURE 12. STEADY-STATE IN PWM MODE (VIN = 3.6V; VO = 1.6V; IO = 1A) FN9256.0 March 7, 2006 ISL6273 Typical Operating Performance (Continued) FIGURE 13. TRANSIENT LOAD TEST (PFM & PWM VIN = 3.6V; VO = 1.6V; IO = 0A~1A) Pin Descriptions FIGURE 14. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V; VO = 1.6V; IO = 0A~1A) FB Input supply voltage. Connect a 10µF ceramic capacitor to power ground. Buck regulator output feedback. Connect to the output through a resistor divider for adjustable output voltage (ISL6273-ADJ). For preset output voltage, connect this pin to the output. VCC RSI Supply voltage for internal analog and digital control circuits, delivered from PVIN. Bypass with 0.1µF ceramic capacitor to signal ground. This input resets the 200ms timer. When the output voltage is within the PGOOD window, an internal timer is started and generates a POR signal 200ms later when RSI is low. A low RSI resets POR and RSI high to low transition restarts the internal counter if the output voltage is within the window, otherwise the counter is reset by the output voltage condition. PVIN EN Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output capacitor when driven to low. Do not leave this pin floating. Exposed Pad POR 200ms timer output. At power up or EN HI, this output is a 200ms delayed Power-Good signal for the output voltage. This output can be reset by a low RSI signal. 200ms starts when RSI goes to high. The exposed pad must be connected to the PGND pin for proper electrical performance. The exposed pad must also be connected to as much as possible for optimal thermal performance. MODE Mode Selection pin. Connect to logic high or input voltage VCC for low IQ mode; connect to logic low or ground for forced PWM mode. Do not leave this pin floating. PHASE Switching node connection. Connect to one terminal of inductor. PGND Power ground. Connect all power grounds to this pin SGND Analog ground. SGND and PGND should only have one point connection. 6 FN9256.0 March 7, 2006 ISL6273 Typical Applications ISL6273 - 25 INPUT 2.7V-5.5V C1 10 µF OUTPUT 2.5V/1.2A L PVIN PHASE VCC PGND EN SGND 1.8uH C2 10µF C3: 0.1µF R1 100k POR MODE VCC PARTS L DESCRIPTION Output inductor FB MANUFACTURERS RSI PART NUMBER SPECIFICATIONS SIZE Sumida CDRH4D18 2R2 2.2µH/1.32A/58mΩ 5.0×5.0×2.0mm Coilcraft 1008PS-182M 1.8µH/1.9A/90mΩ 3.8x3.8x2.8mm C1 Input capacitor Murata GRM21BR60J106KE19L 10µF/6.3V/3mΩ 2.0x1.25x1.25mm (0805) C3 Bypass capacitor Taiyo Yuden EMK107BJ104MA 0.1µF/16V 1.6x0.8x0.8mm (0603) C2 Output capacitor Murata GRM21BR60J106KE19L 10µF/6.3V/3mΩ 2.0x1.25x1.25mm (0805) R1 Pull-up resistor Various 100kΩ 1.6x0.8x0.45mm (0603) FIGURE 15. TYPICAL APPLICATION FOR FIXED OUTPUT VERSION INPUT 2.7V-5.5V C1 10uF ISL6273 - ADJ L PVIN PHASE VCC PGND EN SGND C3: 0.1µF OUTPUT 1.3V/1.2A 1.8uH C2 10uF R2 100K R3 160K R1 100k POR VCC MODE FB RSI FIGURE 16. TYPICAL APPLICATION FOR ADJUSTABLE VERSION 7 FN9256.0 March 7, 2006 ISL6273 Block Diagram VCC MODE Soft Start Shutdown 0.8pF 400k Bandgap 0.8V + EN Shutdown 25pF 5Ω 5Ω + COMP EAMP PVIN Oscillator PWM/PFM LOGIC CONTROLLER PROTECTION DRIVER + FB PHASE PGND Note 1 Slope Comp + CSA1 0.864V + + OCP 1V + SGND 0.736V + SKIP POR 200ms Delay RSI 0.2V 0.2V Zero -Cross Sensing SCP + Note 1: For adjustable output version, the internal feedback resistor divider is disabled and the FB pin is directly connected to the error amplifier. FIGURE 17. FUNCTIONAL BLOCK DIAGRAM 8 FN9256.0 March 7, 2006 ISL6273 Theory of Operation The ISL6273 is a step-down switching regulator optimized for battery-powered handheld applications. The regulator operates at 1.5MHz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The quiescent current when the output is not loaded is typically only 25µA. The supply current is typically only 0.1µA when the regulator is shut down. The ISL6273 has four fixed output voltage versions and one adjustable version. compensation ramp and the current-sense amplifier CSA output. VEAMP VCSA1 Duty Cycle IL VOUT PWM Control Scheme The ISL6273 employs the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 17 shows the block diagram. The current loop consists of the oscillator, the PWM comparator COMP, current sensing circuit, and the slope compensation for the current loop stability. The current sensing circuit consists of the resistance of the P-channel MOSFET when it is turned on and the current sense amplifier CSA. The gain for the current sensing circuit is typically 0.4V/A. The control reference for the current loops comes from the error amplifier EAMP of the voltage loop. The PWM operation is initialized by the clock from the oscillator. The P-channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA and the compensation slope (0.675V/µs) reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the PMOSFET and to turn on the N-channel MOSFET. The N-MOSFET stays on until the end of the PWM cycle. Figure 18 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the FIGURE 18. PWM OPERATION WAVEFORMS The output voltage is regulated by controlling the reference voltage to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage control loop. The feedback signal comes from the FB pin. The soft-start block only affects the operation during the start-up and will be discussed separately shortly. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated with the 30pF and 300kΩ RC network. The maximum EAMP voltage output is precisely clamped to the bandgap voltage (1.172V). SKIP Mode The ISL6273 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the effective switching frequency. Figure 19 illustrates the skip-mode operation. A zero-cross sensing circuit shown in Figure 17 monitors the N-MOSFET current for zero crossing. When 8 consecutive cycles of the N-MOSFET crossing zero are detected, the regulator enters the skip mode. During the 8 detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. Clock 8 Cycles Current Limit IL Load Current 0 Nominal + 1.5% VOUT Nominal FIGURE 19. SKIP MODE OPERATION WAVEFORMS 9 FN9256.0 March 7, 2006 ISL6273 Once the skip mode is entered, the pulse modulation starts being controlled by the SKIP comparator shown in Figure 17. Each pulse cycle is still synchronized by the PWM clock. The N-MOSFET is turned on at the clock and turned off when its current reaches 20% of the current limit value (0.2V at the CSA output). As the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. When the output voltage reaches 1.5% above the nominal voltage, the P-MOSFET is turned off immediately. Then the inductor current is fully discharged to zero and stays at zero. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-MOSFET will be turned on again at the clock, repeating the previous operations. The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage. Mode Control The ISL6273 has a MODE pin that controls the operation mode. When the MODE pin is driven to low or shorted to ground, the regulator operates in a forced PWM mode. The forced PWM mode remains the fixed PWM frequency at light load instead of entering the skip mode. Overcurrent Protection The overcurrent protection is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 17. The current sensing circuit has a gain of 0.4V/A, from the N-MOSFET current to the CSA output. When the CSA output reaches 1V, which is equivalent to 2.5A for the switch current, the OCP comparator is tripped to turn off the P-MOSFET immediately. Short-Circuit Protection A short-circuit protection SCP comparator monitors the FB pin voltage for output short-circuit protection. When the FB is lower than 0.2V, the SCP comparator forces the PWM oscillator frequency to drop to 1/3 of the normal operation value. This comparator is effective during start-up or an output short-circuit event. POR Signal The ISL6273 offers a power-on reset (POR) signal for resetting the microprocessor at the power up. When the output voltage is not within a power-good window, the POR pin outputs an open-drain low signal to reset the microprocessor. The output voltage is monitored through the FB pin. For the fixed output voltage versions, the monitoring node is the center of the resistive voltage divider. For the adjustable version, the FB pin voltage is monitored directly. When the voltage of the monitored node is within the window of 0.736V and 0.864V, a power-good signal is issued to turn off the open-drain POR pin. The rising edge of the POR output is delayed by 200ms. 10 RSI Signal The RSI signal is a reset input control for the POR signal. The power-good signal is gated by the RSI signal, as shown in Figure 17. When the RSI is high, the POR signal will remain low, independent on the power good signal. UVLO When the input voltage is below the undervoltage lock out (UVLO) threshold, the regulator is disabled. Soft Start-Up The soft start-up eliminates the inrush current during the start-up. The soft start block outputs a ramp reference to both the voltage loop and the current loop. The two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. At the very beginning of the start-up, the output voltage is less than 0.2V; hence the PWM operating frequency is 1/3 of the normal frequency. Figure 10 shows the start-up waveforms. Power MOSFETs The power MOSFETs are optimized for best efficiency. The on resistance for the P-MOSFET is typically150mΩ and the on resistance for the N-MOSFET is typically 150mΩ. 100% Duty Cycle The ISL6273 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the ISL6273 can no longer maintain the regulation at the output, the regulator completely turns on the P-MOSFET. The maximum drop out voltage under the 100% duty-cycle operation is the product of the load current and the on resistance of the P-MOSFET. Enable The enable (EN) input allows user to control the turning on or off the regulator for purposes such as power-up sequencing. The the regulator is enabled, there is typically a 300µs delay for waking up the bandgap reference. Then the soft start-up begins. When the regulator is disabled, the P-MOSFET is turned off immediately and the N-MOSFET is turned on. Thermal Shut Down The ISL6273 has built-in thermal protection. When the internal temperature reaches 150°C, the regulator is completely shut down. As the temperature drops to 130°C, the ISL6273 resumes operation by stepping through a soft start-up. VCC By-Passing The VCC is voltage is the supply to the internal control circuit and is derived from the PVIN pin. An internal 10Ω resistor connects the two pins and also serves as an filtering resistor. An external 0.1µF ceramic capacitor is recommended to bypass the VCC supply. FN9256.0 March 7, 2006 ISL6273 Applications Information Output Inductor and Capacitor Selection To consider state steady and transient operation, ISL6273 typically uses a 1.8µH output inductor. Higher or lower inductor value can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased as shown in Table 1. The inductor ripple current can be expressed as follows: VO V O • 1 – -------- V IN ∆I = --------------------------------------L • fS OUTPUT CAPACITOR VALUE (µF) 600 505 410 315 220 125 30 0.8 The inductor’s saturation current rating needs be at least larger than the peak current. The ISL6273 protects the peak current 2.1A. The saturation current needs be over 2.1A for maximum output current application. ISL6273 uses internal compensation network and the output capacitor value is dependant on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. The recommended minimum output capacitor values are shown in Table 1. TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT VOUT COUT L 0.8V 10µF 1.0µH~2.2µH 1.2V 10µF 1.2µH~2.2µH 1.6V 10µF 1.8µH~2.2µH 1.8V 10µF 1.8µH~3.3µH 2.5V 10µF 1.8µH~3.3µH 3.3V 6.8µF 1.8µH~4.7µH 3.6V 4.7µF 1.8µH~4.7µH In Table 1, the minimum output capacitor value is given for different output voltage to make sure the whole converter system stable. Due to the limitation on power dissipation when the regulator disable and discharge output capacitor, there is the maximum output capacitor value. The maximum output capacitor value is variable with the output voltage. The plot curve is shown in Figure 20. Input Capacitor Selection The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. A 10µF X5R or X7R ceramic capacitor is a good starting point for the input capacitor selection. 11 1.27 1.73 2.2 2.67 OUTPUT VOLTAGE (V) 3.13 3.6 FIGURE 20. THE MAXIMUM CAP vs THE OUTPUT VOLTAGE Output Voltage Setting Resistor Selection The resistors R2 and R3 shown in Figure 16 set the output voltage for the adjustable version. The output voltage can be calculated by: R V O = 0.8 • 1 + ------2- R 3 where the 0.8V is the reference voltage. The voltage divider consists of R2 and R3 increases the quiescent current by Vo/(R2+R3) so larger resistance is desirable. On the other hand, the FB pin has leakage current that will cause error in the output voltage setting. The leakage current has a typical value of 0.1µA. To minimize the accuracy impact on the output voltage, select the R3 no larger than 200kΩ. Layout Recommendation The layout is a very important converter design step to make sure the designed converter works well. For ISL6273 buck converter, the power loop is composed of the output inductor L, the output capacitor COUT, Phase pin and PGND pin. It is necessary to make the power loop as small as possible. In order to make the output voltage regulate well and avoid the noise couple from the power loop specially for PFM mode operation, SGND pin should be connected with PGND pin at the terminals of the load. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for EMI performance. FN9256.0 March 7, 2006 ISL6273 Dual Flat No-Lead Plastic Package (DFN) L10.3x3C 2X 10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE 0.15 C A A D MILLIMETERS 2X 0.15 C B E SYMBOL MIN 0.80 0.90 1.00 - - - 0.05 - 0.20 REF 0.18 D D2 B A C SEATING PLANE D2 6 INDEX AREA 0.08 C A3 SIDE VIEW (DATUM B) 0.10 C 7 8 2.48 7, 8 - 3.00 BSC 1.49 e 1.64 1.74 7, 8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 10 2 Nd 5 3 2. N is the number of terminals. NX k 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. E2 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. E2/2 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW 5 0.10 M C A B 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2. CL NX (b) 2.38 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. (DATUM A) 8 5, 8 NOTES: 2 N 0.30 Rev. 0 3/05 D2/2 1 E2 0.25 - 3.00 BSC 2.23 E // NOTES A b TOP VIEW MAX A1 A3 6 INDEX AREA NOMINAL (A1) 9 L 5 e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN9256.0 March 7, 2006