Data Sheet

Freescale Semiconductor
Advance Information
Document Number: MC33800
Rev. 5.0, 10/2007
Engine Control Integrated
Circuit
33800
The 33800 is a combination output switch and driver Integrated
Circuit (IC) which can be used in numerous powertrain applications.
The IC contains two programmable constant current drivers (CCD),
an octal, low side, serial switch (OSS), and six, external MOSFET
gate pre-drivers (GD). The IC has over-voltage, under-voltage, and
thermal protection. All drivers and switches, including the external
MOSFETs, have over-current protection, off-state open load
detection, on-state shorted load detection, and fault annunciation via
the serial peripheral interface (SPI).
Additional features include: Low power Sleep Mode, Heated
Exhaust Gas Oxygen (HEGO) sensor diagnostics, output control via
serial and/or parallel inputs, PWM capability, and programmable
current output with dithering. These features, along with cost effective
packaging, make the 33800 ideal for Powertrain Engine Control
applications.
ENGINE CONTROL
EK SUFFIX (Pb-FREE)
98ASA99334D
54-PIN SOICW-EP
ORDERING INFORMATION
Features
•
•
•
•
•
•
•
•
•
•
•
Wide operating voltage range, 5 < VPWR < 36V
Interfaces to 3.3V and 5V microprocessors via SPI protocol
Low, Sleep Mode, standby current, typically 10uA.
Internal or external voltage reference
Internal oscillator with calibrate capability
Measures resistance to monitor HEGO sensors
CCDs have programmable current, dither frequency and amplitude
OSSs can be paralleled to increase current capability
GDs have programmable frequency and duty cycle PWM
All outputs controllable via serial and/or parallel inputs
Pb-free packaging designated by suffix code EK
Device
Temperature
Range (TA)
Package
MCZ33800EK/R2
-40°C to 125°C
54 SOICW EP
33800
VBAT
VPWR
VDD
MCU
2.5V
VPWR
CCD1_REC
CCD1_OUT
VDD
VCAL
RI_REF
REXT
VPWR
CCD2_REC
CCD2_OUT
MOSI
SI
SCLK
SCLK
OUT1
CS
CS
OUT8
MISO
SO
AN0
VBAT
EN
{
LRFDBK
VSSNS123
DEFAULT
P1,P3,P5,P7
PWM1
PWM6
GND
VDSNS1
{
GD1
VDSNS6
GD6
VSSNS456
Figure 1. MC33800 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
VBAT
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR, VDD
POR
Sleep PWR
Oscillator
Bandgap
VPWR
VDD
GND
VCAL
VDD
15µA
15µA
80µA
CCD2_OUT
CCD1_OUT
CCD2 Outputs
CCD1 Outputs
CCD2_REC
CCD1_REC
DEFAULT
53V
EN
100K
Gate Control
Open/Short
40µA
P1
+
–
15µA
RS
CCGND
CCGND
lLimit
P3
15µA
Outputs 1 to 8
P5
OUT 1
to
Gate Control
Open/Short
P7
Logic Control &
SPI Interface
15µA
SI
75µA
53V
15µA
OUT 8
+
–
VDD
RS
PGND
PGND
PGND
lLimit
15µA
15µA
Predriver1,2,3
CS
SCLK
SO
PWM1
VDSNS1
VPWR
Gate Drive
Control &
Diagnostics
15µA
GD1
PWM2
VSSNS123
15µA
Predriver4,5,6
PWM3
15µA
Gate Drive
Control &
Diagnostics
PWM4
15µA
GD4
VSSNS456
PWM5
15µA
+
PWM6
VCAL
Differential
Amplifier
−
15µA
VCAL
+
+
−
+
LRFDBK
−
−
RI_REF
VDSNS4
VPWR
REXT
Exposed
Pad
Figure 2. 33800 Simplified Internal Block Diagram
33800
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
VDSNS4
GD4
VDSNS5
GD5
VDSNS6
GD6
VSSNS456
LRFDBK
SI
SCLK
CS
P1
P3
P5
P7
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
CCD2_GND
CCD2_OUT
CCD2_REC
EN
RI_REF
CCD1_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDSNS3
GD3
VDSNS2
GD2
VDSNS1
GD1
VSSNS123
REXT
PGND1
OUT1
PGND2
OUT2
OUT3
OUT4
OUT5
PGND
OUT6
OUT7
OUT8
DEFAULT
SO
VDD
VCAL
GND
VPWR
CCD1_GND
CCD1_REC
Figure 3. 33800 Pin Connections
Table 1. 33800 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.
Pin Number
Pin Name
Pin Function
Formal Name
1, 3, 5, 50,
52, 54
VDSNS1-
Input
Drain Voltage Sense
2, 4, 6, 49,
51, 53
GD1-GD6
Output
Gate Driver Output
Input
VDSNS6
Definition
The VDSNS pin is used to monitor the drain voltage of the external
MOSFET.
The GD pin provides gate drive for an external MOSFET
Source Voltage Sense The VSSNS pins are used to monitor the source voltage of the external
MOSFETS.
7
VSSNS456
48
VSSNS123
8
LRFDBK
Output
Load Resistance
Feedback
The LRFDBK pin is an operational amplifier output.
9
SI
Input
Serial Input Data
The SI input pin is used to receive serial data from the MCU. The serial
input data is latched on the rising edge of SCLK, and the input data
transitions on the falling edge of SCLK.
10
SCLK
Input
Serial Clock Input
The SCLK input pin is used to clock in and out the serial data on the SI
and SO Pins while being addressed by the CS.
11
CS
Input
Chip Select
The Chip Select input pin is an active low signal sent by the MCU to
indicate that the device is being addressed. This input requires CMOS
logic levels and has an internal active pull up current source.
12
P1
Input
Input One
Input control of OSS output 1. When configured via the SPI, P1 input may
be used to control OSS output 1 and output 2 in parallel.
13
P3
Input
Input Three
Input control of OSS output 3. When configured via the SPI, P3 input may
be used to control OSS output 3 and output 4 in parallel.
14
P5
Input
Input Five
Input control of OSS output 5. When configured via the SPI, P5 input may
be used to control OSS output 5 and output 6 in parallel.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33800 Pin Definitions(continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.
Pin Number
Pin Name
Pin Function
Formal Name
Definition
15
P7
Input
Input Seven
Input control of OSS output 7. When configured via the SPI, P7 input may
be used to control OSS output 7 and output 8 in parallel.
16,17, 18, 19,
20, 21
PWMX
Input
Pulse Width
Modulated Input
The PWMX input pin is used for direct parallel control of the GDX (Gate
Drive Output X) predriver or as on/off control of the internal PWM
controller. Control strategy is programmed via the SPI.
22
CCD2_GND
Ground
CCD2 Ground
The CCD2_GND pin provides a dedicated ground for the CCD2 constant
current controller
23
CCD2_OUT
Output
Current Controlled
Driver 2 Output
The CCD2_OUT pin is connected to a series internal sense resistor and
power MOSFET driver. The CCD2_OUT has a pull up and pull down
current source and is used for fault threshold monitoring.
24
CCD2_REC
Input
Current Controlled
Driver 2 Recirculation
Input
The CCD2_REC pin provides a recirculation path for the load current.
The CCD2_REC pin is connected to the node between the internal sense
resistor and power MOSFET driver. The device uses the differential
voltage between CCD2_REC and CCD2_OUT to determine the load
solenoid current.
25
EN
Input
ENABLE
26
RI_REF
Output
Resistor for Current
Reference
The RI_REF pin is used to generate a reference current. The reference
is used in the regulation of the constant current controller. The constant
current controller regulation current is inversely proportional to the
reference current through the external resistor. A 39.2kΩ 1% resistor to
ground will set the 1FF programmed current value of the CCD1 to
1075mA and the CCD2 to be 232mA.
27
CCD1_OUT
Output
Current Controlled
Driver 1 Output
The CCD1_OUT pin is connected to a series internal sense resistor and
power MOSFET driver. The CCD1_OUT has a pull up and pull down
current source and is used for fault threshold monitoring.
28
CCD1_REC
Input
Current Controlled
Driver 1 Recirculation
Input
The CCD1_REC pin provides a recirculation path for the load current.
The CCD1_REC pin is connected to the node between the internal sense
resistor and power MOSFET driver. The device uses the differential
voltage between CCD1_REC and CCD1_OUT to determine the load
solenoid current.
29
CCD1_GND
Ground
CCD1 Ground
The CCD1_GND pin provides a dedicated ground for the CCD1 constant
current controller
30
VPWR
31
GND
Ground
Ground
Analog ground for the internal control circuits of the IC. This ground
should be used for decoupling of VDD and VPWR supply.
32
VCAL
Input
Voltage Calibrated
Input
VCAL input is a precision (2.5V, +8.0mV, -20mV over temperature)
reference input, used in several internal circuits. A 1.0nF to 10nF
decoupling capacitor is required on the VCAL input pin to ground.
33
VDD
34
SO
Output
Serial Output Data
35
DEFAULT
Input
Default Mode Enable
36-38, 40,
41-43, 45
OUT1-OUT8
Output
OSS Output 1-8
The EN pin is an active high input.
Power Input Analog Voltage Supply The VPWR pin provides power to all pre-driver, driver and output circuits
and other internal functions such as the oscillator and SPI circuits.
Power Input Digital Voltage Supply
The VDD pin supplies power to the Serial Output (SO) buffer along with
the pull up current sources for the chip select (CS) and DEFAULT inputs.
The SO output pin is used to transmit serial data from the device to the
MCU. The SO pin remains tri-stated until selected by the active low CS.
The serial output data is available to be latched by the MCU on the rising
edge of SCLK. The SO data transitions on falling edge of the SCLK.
The DEFAULT pin is an active high input.
Octal Serial Switch (OSS) low side driver output 1-8.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 1. 33800 Pin Definitions(continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.
Pin Number
Pin Name
Pin Function
Formal Name
Definition
39
PGND3
Ground
OSS 3-8 Ground
This PGND pins provide a dedicated ground for the Octal Serial Switch
(OSS) low side driver outputs 3 - 8.
44
PGND2
Ground
OSS 2 Ground
This PGND pin provides a dedicated ground for the Octal Serial Switch
(OSS) low side driver output 2.
46
PGND1
Ground
OSS 1 Ground
This PGND pin provides a dedicated ground for the Octal Serial Switch
(OSS) low side driver output 1.
47
REXT
Output
Resistor External
Reference
_
_
Ground
Exposed Pad Ground
The REXT pin is used to generate a reference current.
The package exposed pad provides thermal conductivity for the die and
should be grounded to system ground.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
VPWR
-1.5 to 45
VDD
-0.3 to 7.0
–
-0.3 to VDD
VDC
VDSNS
-0.3 to 60
VDC
ECLAMP
30
mJ
ECLAMP
45
mJ
ECLAMP
75
mJ
ECLAMP
25
mJ
IOSS_SS
350
mA
ECLAMP
75
mJ
–
4.0
MHz
VESD1
VESD2
±2000
±200
TSTG
-55 to 150
°C
TC
-40 to 125
°C
Operating Junction Temperature
TJ
-40 to 150
°C
Power Dissipation (TA = 25°C)
PD
1.7
W
°C/W
ELECTRICAL RATINGS
Supply Voltage
VDC
VPWR
VDD
CS, SI, SO, SCLK, EN, DEFAULT, PWMx, P1, P3, P5, P7
Predriver Drain Voltage (VDSNS1 to VDSNS6)
OSS Output Clamp Energy (OUT3 to OUT8)(Single Pulse)
TJunction = 150°C, IOUT = 0.45A
OSS Output Clamp Energy (OUT1 & OUT2)(Single Pulse)
TJunction = 150°C, IOUT = 0.45A
CCD1 Output Clamp Energy (Single Pulse)
TJunction = 150°C, IOUT = 0.45A
CCD2 Output Clamp Energy (Single Pulse)
TJunction = 150°C, IOUT = 0.45A
OSS Output Continuous Current (OUT1 to OUT8 Steady State)
TJunction = 150°C
CCD1 Output Clamp Energy (CCD1_REC OUTPUT)
TJunction = 150°C, IOUT = 1.0 A
Frequency of SPI Operation (VDD = 5.0V)(3)
ESD Voltage(1)
V
Human Body Model
Machine Model
THERMAL RATINGS
Storage Temperature
Operating Case Temperature
(2)
THERMAL RESISTANCE
Thermal Resistance
Junction to Ambient
RθJA
71
Between the Die and the Exposed Die Pad
RθJC
1.2
Notes
1. ESD data available upon request. All pins tested individually. ESD1 testing is performed in accordance with the Human Body Model
(AEC-Q100-002). and the Machine Model (AEC-Q100-003).
2. Maximum power dissipation at TJ =150°C junction temperature with no heat sink used.
3.
This parameter is guaranteed by design but is not production tested.
33800
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT (VPWR, VDD)
Supply Voltage
V
Fully Operational
VPWR (FO)
Supply Current
5.0
–
36
–
10.0
14.0
IPWR (ON)
mA
All Outputs Disabled (Normal & Default Mode)
µA
Sleep State Supply Current
VDD ≤ 0.8 V, VPWR = 18V
IPWR (SS)
–
10
30
EN ≤ 0.8 V, VDD = 5.5V
IVDD (SS)
–
2.0
5.0
VPWR(OV)
36.5
39
44
V
VPWR(OVHYS)
0.5
1.5
3.0
V
VPWR(UV)
3.0
4.0
4.4
V
VPWR(UVHYS)
100
200
650
mV
Logic Supply Voltage
VDD
3.0
–
5.5
V
Logic Supply Current
IDD
180
300
525
VDD(UV)
0.8
2.5
2.8
V
VDD(UVHYS)
100
–
650
mV
VBIAS
2.2
2.5
2.8
V
VPWR Over-voltage Shutdown Threshold Voltage(4)
VPWR Over-voltage Shutdown Hysteresis Voltage
VPWR Under-voltage Shutdown Threshold
Voltage(5)
VPWR Under-voltage Shutdown Hysteresis Voltage
Static Condition
Logic Supply Under-voltage Shutdown Threshold Voltage (5)
Logic Supply Under-voltage Hysteresis
Internally Generated VCAL
(6)
µA
CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD1_OUT)
Drain-to-Source ON Resistance
TJ = 125°C, VPWR = 13V
TJ = 25°C, VPWR = 13V
TJ = -40°C, VPWR = 13V
Internal Current Sense Resistor
Ω
RDS(ON)
–
–
–
Programmable from 50Hz to 500Hz in 50Hz Increments after
Calibration
0.7
1.2
Ω
ICCD1
DAC Value = 17C HEX +/- (3%)
DAC Value = 05F HEX +/- (15%)
Load Resistance = 5Ω, Load Inductance = 10mH, Dither Off
Programmable Dither Frequency
0.60
–
–
RSENSE
DAC Value = 000, VCCD1REC = 0.0V, ICCD1OUT = 100mA
RSENSE = VCCD1OUT / ICCD1OUT
Current Regulation
–
0.25
–
mA
775
157
800
200
823
235
fDITHER
%
-10
10
Notes
4. Over-voltage thresholds minimum and maximum include hysteresis.
5. Under-voltage thresholds minimum and maximum include hysteresis.
6. Using the internally generated VCAL increases all applicable parametric tables by +- 10%
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CDD1_OUT) (CONTINUED)
Programmable Dither Amplitude Peak to Peak
IDITHER
Programmable from 0.0mA to 350mA in 50mA increments
CCD1 Fault Detection Voltage Threshold
CCD1 Output Leakage Current
2.5
3.0
VOC
V
50
55
60
1.5
–
2.8
–
–
–
8000
20
ICCD1(PULLUP)
-60
-40
-20
µA
ICCD1(PULLDOWN)
20
40
60
µA
–
–
–
–
1.0
–
2.0
–
–
IOUT (LIM)
ICCD1 (LKG)
Pull-up enabled, Dither Off, CCD1OUT = VOC - 1.0V
Pull-up enabled, Dither Off, CCD1OUT = VPWR = 24V
CCD1 Pull Up Current
V
2.0
Outputs Programmed OFF
CCD1 Output Self Limiting Current
10
VOUT(FLTTH)
Outputs Programmed OFF
CCD1 Output Clamp Voltage
%
-10
A
µA
Pull-up enabled, DAC = 000, CCD1OUT = CCD1REC = 2.0V
CCD1 Pull Down Current
Pull-up disabled, DAC = 000, CCD1OUT = CCD1REC = 2.0V
CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD2_OUT)
Drain-to-Source ON Resistance
TJ = 125°C, VPWR = 13V
TJ = 25°C, VPWR = 13V
TJ = -40°C, VPWR = 13V
Internal Current Sense Resistor
Ω
RDSON
Ω
RSENSE
DAC Value = 000, VCCD2REC = 0V, ICCD2OUT = 100mA
RSENSE = VCCD2OUT / ICCD2OUT
Current Regulation
10
-10
10
%
V
2.0
2.5
3.0
VOC
V
50
55
60
–
–
–
8000
20
0.5
–
1.0
ICCD2 (LKG)
Pull-up enabled, Dither Off, CCD2OUT = VOC - 1.0V
Pull-up enabled, Dither Off, CCD2OUT = VPWR = 24V
CCD2 Output Self Limiting Current
-10
VOUT(FLTTH)
Outputs Programmed OFF
CCD2 Output Leakage Current
%
IDITHER
Outputs Programmed OFF
CCD2 Output Clamp Voltage
180
47.5
fDITHER
Programmable from 0.0mA to 90mA in 10.9mA increments
CCD2 Fault Detection Voltage Threshold
173
43.2
mA
166
38.9
Programmable from 50Hz to 500Hz in 50Hz Increments after
Calibration
Programmable Dither Amplitude Peak to Peak
5.0
ICCD2
DAC Value = 17C HEX +/- (4%)
DAC Value = 05F HEX +/- (10%)
Load Resistance = 32Ω, Load Inductance = 130mH, Dither Off
Programmable Dither Frequency
3.5
IOUT (LIM)
µA
A
33800
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
ICCD2(PULLUP)
-60
-40
-20
µA
ICCD2(PULLDOWN)
20
40
60
µA
–
–
1.4
–
0.7
–
–
–
–
–
–
1.7
–
1.0
–
–
–
–
1.0
–
2.0
4.0
–
6.0
CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD2_OUT) (CONTINUED)
CCD2 Pull Up Current
Pull-up enabled, DAC = 000, CCD1OUT = CCD1REC = 2.0V
CCD2 Pull Down Current
Pull-up disabled, DAC = 000, CCD2OUT = CCD2REC = 2.0V
OCTAL SERIAL DRIVERS (OUT1 - 8)
Drain-to-Source ON Resistance (OUT1 - 2)
IOUT = 0.350A, TJ = 125°C, VPWR = 13V
IOUT = 0.350A, TJ = 25°C, VPWR = 13V
IOUT = 0.350A, TJ = -40°C, VPWR = 13V
Drain-to-Source ON Resistance (OUT3 - 8)
Ω
RDS (ON)
IOUT = 0.350A, TJ = 125°C, VPWR = 13V
IOUT = 0.350A, TJ = 25°C, VPWR = 13V
IOUT = 0.350A, TJ = -40°C, VPWR = 13V
Output Self Limiting Current
Ω
RDS (ON)
IOUT (LIM)
Output 3 to Output 8
Output 1, Output 2
Output Fault Detection Voltage Threshold.
(7)
VOUT(FLTTH)
Outputs Programmed OFF
Output OFF Open Load Detection Current
V
2.0
2.5
3.0
40
75
100
µA
IOCO
VDrain = 18V, Outputs Programmed OFF
Output Clamp Voltage Low Side Drive
A
VOC
ID = 20mA
V
50
55
60
–
–
–
–
–
–
20
3000
10
TLim
155
–
185
°C
TLim (HYS)
5.0
10
15
°C
Input Logic High-voltage Thresholds(8)
VIH
0.7 x VDD
–
VDD + 0.3
V
Input Logic Low-voltage Thresholds(8)
VIL
GND - 0.3
–
0.2 x VDD
V
VHYS
100
–
300
mV
CIN
–
–
20
pF
-10
–
10
Output Leakage Current
µA
IOUT (LKG)
VDD = 5.0V, VDrain = 24V, Open Load Detection Current Disabled
VDD = 5.0V, VDrain = VOC - 1.0V, Open Load Detection Current
Disabled
VDD = 0V, VDrain = 24V, Device Disabled
Over-temperature Shutdown(8)
(8)
Over-temperature Shutdown Hysteresis
SPI DIGITAL INTERFACE (SO, SI, CS, SCLK)
Input Logic Voltage Hysteresis(8)
Input Logic Capacitance(8)
Sleep Mode Input Logic Current(8)
VDD = 0.0V
µA
I LOGICSS
Notes
7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts.
8. This parameter is guaranteed by design, however is not production tested.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
-10
–
10
5.0
15
25
-5.0
–
-25
-10
–
10
-10
–
10
-5.0
–
-30
–
–
10
VDD - 0.4
–
–
–
–
0.4
ENPD
10
50
100
µA
V GS (ON)
V GS (OFF)
5.0
–
7.0
0.2
9.0
0.5
V
Gate Drive Sink and Source Current
I GATEDRIVE
–
2.0
5.0
mA
Sleep Mode Gate to Source Resistor
R GS (PULLDOWN)
65
200
300
KΩ
SPI DIGITAL INTERFACE (SO, SI, CS, SCLK) (CONTINUED)
Sleep Mode EN and DEFAULT Input Current
Normal Mode Input Logic Pull-down Current(9)
SCLK, Tri-state SO Output
IDEFAULTPU
CS Input Current
CS Pull-up Current
VSOHIGH
ISOHIGH = -1.0mA
V
VSOLOW
ISOLOW = 1.0mA
EN Input Pull-down Current
µA
ICS(LKG)
CS = 5.0V, VDD = 0.0V
SO Low-state Output Voltage
µA
ICSPU
CS = 0.0V
SO High-state Output Voltage
µA
ICS
CS = VDD
I
µA
µA
I SCLK, I TRISO
0.0V to 5.0V
CS Leakage Current to VDD
µA
ILOGICPD
0.8V to 5.0V
Normal Mode DEFAULT Pull-up Current
µA
I LOGICSS
VD D = 0.0V, VEN = 5.0V, VD E FA U LT = 5.0V
V
EN = VDD
PREDRIVER OUTPUT FUNCTION (GD1 - GD6)
Gate Drive Output Voltage
IGATEDRIVE = 100µA
IGATEDRIVE = - 100µA
Short Fault Detection Voltage Threshold
VDS(FLTTH)
VDD = High, Outputs Programmed ON
Programmable from 0.5V to 3.0V in 0.5V increments.
Open Fault Detection Voltage Threshold
VDD = High, Outputs Programmed OFF
V
-20%
+20%
VDS(FLTTH)
V
2.0
2.5
3.0
Notes
9. Parameter applies to P1, P3, P5, P7, PWM1 to PWM6, SI and VCAL, and are guaranteed by design.
33800
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
40
180
400
50
55
60
–
–
25
-10%
2.6
+10%
V
6.0
V
PREDRIVER OUTPUT FUNCTION (GD1 - GD6) (CONTINUED)
Drain Sense Fault Detection Current
Output Clamp Voltage
VOC
Driver Command Off, VGATE = 2.0V
Sleep Mode Drain Sense Leakage Current
V
µA
IDSNS (LKG)
VDD = 0.0V, VDSNS = 24V,
Load Resistance Feedback Accuracy Sample and Hold After 150ms
µA
IDSNS(flt-sns)
Gate Drive Off, VDS = 18V
LRFBCKACC
REXT = 24ohm, RLOAD = 10ohm, LRFDBK = VCAL*2.5*(RLOAD/REXT)
Load Resistance Feedback Output Voltage
LRFBCKMax
(VDSNS1 - VDSNS2) ≥ 10V, PWM Diagnostics Select = 0001
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD1_OUT)
On State Open Load Detect Timer(10)
ms
Fault is detected with driver on, timer expired
tONOPENTIMER
6.0
12
24
tOFFOPENTIMER
30
60
90
30
60
90
10
14
24
ms
V/µs
Off State Open Load Detect Timer(10)
µs
Fault detected with driver off & voltage threshold not achieved
(Driver off timer)
On State Shorted Load Detect Timer(10)
tONSHORTTIMER
Fault is detected with driver switching and drain voltage remains greater
than threshold for specified time.
Short Retry Time(10)
tRETRY
µs
Output Slew Rate
VBAT = 14V, Measured from 4.0V to 10.0V
t SR(RISE)
2.0
3.0
4.0
VBAT = 14V, Measured from 10.0V to 4.0V
t SR(FALL)
-2.0
-3.0
-4.0
Driver On Time Blanking Period(10)
tBP(OFF)
7.0
10
µs
Driver Off Time Blanking Period(10)
tBP(ON)
7.0
10
µs
6.0
12
24
30
60
90
30
60
90
10
14
24
CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD2_OUT)
On State Open Load Detect Timer(10)
ms
Fault is detected with driver on, timer expires (Driver on timer)
Off State Open Load Detect Timer(10)
tONOPENTIMER
tOFFOPENTIMER
Fault is detected with driver off and voltage threshold is not achieved.
(Driver off timer)
On State Shorted Load Detect Timer(10)
µs
tONSHORTTIMER
Fault is detected with driver switching and drain voltage remains greater
than threshold for specified time.
Short Retry Time(10)
tRETRY
µs
Output Slew Rate
ms
V/µs
VBAT = 14V, Measured from 4.0V to 10.0V
t SR(RISE)
1.5
–
4.0
VBAT = 14V, Measured from 10.0V to 4.0V
t SR(FALL)
-1.5
–
-4.0
CCD2 DAC Update Rate(10)
ms
Response time from present current level to new programmed level
tRESPONSE
1.0
Driver On Time Blanking Period(10)
tBP(ON)
3.0
4.3
µs
Driver Off Time Blanking Period(10)
tBP(OFF)
12
17.2
µs
OCTAL SERIAL DRIVERS (OUT1 - OUT8)
Output On Current Limit Fault Filter Timer(10)
Output Refresh
Timer(10)
(10)
Output On Short Circuit Fault Filter Timer
tCL
30
50
90
µs
tREF
5.0
10
15
ms
tSC
400
500
650
µs
Notes
10. Assumes oscillator has been calibrated using SPI Calibrate Command.
33800
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
tOC
400
500
650
µs
RLOAD = 51Ω
t SR(RISE)
1.0
5.0
10
RLOAD = 51Ω
t SR(FALL)
1.0
5.0
10
OCTAL SERIAL DRIVERS (OUT1 - OUT8) (CONTINUED)
Output Off Open Circuit Fault Filter Timer(11)
Output Slew Rate
V/µs
P1 Input Propagation Delay
µs
Input @ 50% VDD to Output voltage 10% of final value
t(RISEDELAY)
6.0
Input @ 50% VDD to Output voltage 90% of initial value
t(FALLDELAY)
6.0
Input @ 50% VDD to Output voltage 10% of final value
t(RISEDELAY)
5.0
Input @ 50% VDD to Output voltage 90% of initial value
t(FALLDELAY)
5.0
P3, P5, P7 Input Propagation Delay
µs
OSCILLATOR AND TIMER ACCURACY
Calibrated Timer Accuracy(11)
Un-calibrated Timer Accuracy
SPI DIGITAL INTERFACE TIMING (SO, SI, CS, SCLK)
t TIMER
–
–
±10
%
t TIMER
–
–
±80
%
1.0
–
–
100
–
–
(12)
Required Low State Duration on VPWR for Reset(13)
Falling Edge of CS to Rising Edge of SCLK
t LEAD
Required Setup Time
Falling Edge of SCLK to Rising Edge of CS
ns
t LAG
Required Setup Time
SI to Rising Edge of SCLK
ns
50
–
–
16
–
–
20
–
–
t R (SI)
–
5.0
–
ns
t SI (SU)
Required Setup Time
Rising Edge of SCLK to SI
ns
t SI (HOLD)
Required Hold Time
SI, CS, SCLK Signal Rise Time(14)
SI, CS, SCLK Signal Fall Time
µs
t RESET
VPWR ≤ 0.2V
(14)
Time from Falling Edge of CS to SO
ns
t F (SI)
–
5.0
–
ns
Low-impedance(15)
t SO (EN)
–
–
150
ns
(16)
t SO (DIS)
–
–
150
ns
t VALID
–
25
150
ns
1.0
µs
Time from Rising Edge of CS to SO High-impedance
Time from Falling Edge of SCLK to SO Data Valid
Sequential Transfer Rate
(17)
tSTR
Time required between data transfers
Notes
11.
12.
13.
14.
15.
16.
17.
Assumes oscillator has been calibrated using SPI Calibrate Command
These parameters are guaranteed by design. Production test equipment uses 1MHz, 5.0V SPI interface.
This parameter is guaranteed by design, however it is not production tested.
Rise and Fall time of incoming SI, CS, and SCLK signals for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the fall of SCLK with 200pF load.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
100
128
400
Unit
PREDRIVER OUTPUT FUNCTION (GD1 - GD6)
Open Fault Detection Filter Timer(18)
VDS(FLTTH)
VDD = High, Outputs Programmed OFF
Short Fault Detection Filter Timer(18)
tDS(FLTTMR)
VDD = High, Outputs Programmed ON
Programmable from 30µs to 960µs in replicating increments.
Gate Drive Rise Slew Rate
µs
µs
-10%
+10%
t GDSR(RISE)
Cload = 1.0nF, VGS from 0.5 to 5.0V
Gate Drive Fall Slew Rate
V/µs
–
1.7
–
–
1.7
–
t GDSR(FALL)
Cload = 1.0nF, VGS from 5.0 to 0.5V
PWM1 to PWM6 Input Propagation Delay
V/µs
tPWMDELAY
20
300
ns
t LRSR(RISE)
0.5
–
2.0
V/µs
t LRSR(FALL)
0.5
–
2.0
V/µs
tLOADSAMPLE
200
µs
tFDBKVALID
400
us
Measured from PWM input at 4.5V and GDx output at 0.5V.
Load Resistance Feedback Output Rise Slew Rate
CLOAD = 40pF
Load Resistance Feedback Output Fall Slew Rate
CLOAD = 40pF
Load Resistance Sample Duration(18)
Load Resistance Feedback Valid
(18)
Time from rising edge of CS to Load Resistance measurement valid
Notes
18. Assumes oscillator has been calibrated using SPI Calibrate Command.
33800
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
0.2 VDD
tLAG
tLEAD
0.7 VDD
0.2 VDD
SCLK
tSI(SU)
SI
0.7 VDD
0.2 VDD
tSI(HOLD)
MSB IN
tSO(EN)
SO
tVALID
0.7 VDD
0.2 VDD
tSO(DIS)
LSB OUT
MSB OUT
Figure 4. SPI Timing Characteristics
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
ANALOG VOLTAGE SUPPLY (VPWR)
SERIAL CLOCK INPUT (SCLK)
The VPWR pin is battery input to the 33800 IC. The VPWR
pin requires external reverse battery and transient protection.
Maximum input voltage on VPWR is 45V. All IC analog
current and internal logic current is provided from the VPWR
pin. With VDD and EN applied to the IC, the application of
VPWR will perform a Power-ON Reset (POR).
The system clock (SCLK) pin clocks the internal shift
register of the 33800. The SI data is latched into the input
shift register on the rising edge of SCLK signal. The SO pin
shifts status bits out on the falling edge of SCLK. The SO data
is available for the MCU to read on the rising edge of SCLK.
With CS in a logic high state, signals on the SCLK and SI pins
will be ignored and the SO pin is tri-state.
DIGITAL VOLTAGE SUPPLY (VDD)
CHIP SELECT (CS)
The VDD input pin is used to determine communication
logic levels between the microprocessor and the 33800
device. Current from VDD is used to drive SO output and pullup current for CS. VDD must be applied for Normal Mode
operation. Removing VDD from the IC will place the device in
Sleep Mode. Power-ON Reset will be performed with the
application of VDD supply.
The system MCU selects the 33800 to receive
communication using the chip select (CS) pin. With the CS in
a logic low state, command words may be sent to the 33800
via the serial input (SI) pin, and status information is received
by the MCU via the serial output (SO) pin. The falling edge of
CS enables the SO output and transfers status information
into the SO buffer.
Rising edge of the CS initiates the following operation:
GROUND (GND)
The GND pin provides a low current analog ground for the
IC. The VPWR and VDD supplies are both referenced to the
GND pin. GND pin should be used for decoupling both
supplies.
CONSTANT CURRENT DRIVER GROUND
(CCDX_GND)
The Constant Current Driver Ground (CCDX_GND) pins
provide dedicated grounds for the Constant Current output
drivers. Both CCDX_GND1 and CCDX_GND2 grounds are
isolated from the other grounds of the IC.
GROUND (PGND1 - 3, CCD1_GND, CCD2_GND)
There are three PGND pins associated with the OSS
drivers. OUT1 driver and OUT2 driver have dedicated
PGND1 & PGND2 pins. Drivers OUT3 through Driver OUT8
share one PGND3 pin. In general all ground pins must be
connected together and terminated to ground on the circuit
board.
SOURCE VOLTAGE SENSE (VSSNS123,
VSSNS456)
The Source Sense Ground pins (VSSNS123, VSSNS456)
provide dedicated grounds for the hex MOSFET pre-drivers.
The pins are used by the IC to monitor the drain to source
voltage of the external MOSFET. This pin must be connected
to the source of the external MOSFET and system ground.
VSSNS123 and VSSNS456 ground pins are isolated from
other internal IC grounds.
1. Disables the SO driver (high-impedance)
2. Activates the received command word, allowing the
33800 to activate/deactivate output drivers.
To avoid any spurious data, it is essential the high-to-low
and low-to-high transitions of the CS signal occur only when
SCLK is in a logic low state. Internal to the 33800 device is an
active pull-up to VDD on CS. In cases were voltage exists on
CS without the application of VDD, no current will flow from
CS to the VDD pin.
SERIAL INPUT DATA (SI)
The SI pin is used for serial instruction data input. SI
information is latched into the input register on the rising edge
of SCLK. A logic high state present on SI will program a one
in the command word on the rising edge of the CS signal. To
program a complete word, 16-bits of information must be
entered into the device.
SERIAL OUTPUT DATA (SO)
The SO pin is the output from the shift register. The SO pin
remains tri-stated until the CS pin transitions to a logic low
state. All normal operating drivers are reported as zero, all
faulted drivers are reported as one. The negative transition of
CS enables the SO driver.
The SI / SO shifting of the data follows a first-in-first-out
protocol, with both input and output words transferring the
most significant bit (MSB) first.
ENABLE (EN)
The ENABLE pin is an active high digital input pin used to
enable the device. With the EN pin low the device is in Sleep
Mode. With the EN pin high, the device is in Normal Mode
(VDD and VPWR applied). Exit from Sleep Mode initiates a
33800
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
Power On Reset (POR). All internal registers will be placed in
the reset state. The device has an Internal 100 kΩ resistor
pull down on the ENABLE pin.
PULSE WIDTH MODULATION (PWM)
The PWM pins are control input pins for the MOSFET predrivers. The PWM pins provide parallel control and can be
programmed for an OR function with the SPI bit or an AND
function with the SPI bit (See Table 12, on page 25 for SPI
message detail). Each PWM input pin has an internal 15µA
pull down current source. The current sources are active
when the device is in Normal Mode.
DRAIN VOLTAGE SENSE (VDSNSX)
The VDSNSx pin has multiple functions for control and
diagnostics of the external MOSFET:
1. By monitoring the drain voltage of the external device,
short circuits and open circuits are detected. The filter
timer and threshold voltage are easily programmed
through SPI (see Table 10, on page 23 and Table 11,
on page 24 for SPI messages).
2. The VDSNSx pins are use to determine the external
load resistance. Further information is provided in the
Device Operation section of this specification.
3. The VDSNSx pins provide a drain to gate clamp for
fast turn off of inductive loads and MOSFET protection.
GATE DRIVER OUTPUTS (GDX)
The GDX pins are the gate drive outputs for an external
MOSFETS. Internal to the device is a Gate to Source resistor
designed to hold the external MOSFET in the OFF state while
the device is in POR.
operate. For applications where measurements are not
critical, the VCAL pin may grounded and an internally
generated reference will be used. Using the internally
generated reference will add ±10% to all tolerances in the
parametric table.
LOAD RESISTANCE FEEDBACK (LRFDBK)
The LRFDBK pin is an operational amplifier output. The
amplifier output voltage is proportional to the load resistance
for the selected channel. The channel is selected via the SPI.
DEFAULT
The DEFAULT input controls the operation of each driver
to a Default Mode. The DEFAULT input must be logic 0 for full
function of all output drivers. For more information on the
DEFAULT operation (See Functional Device Operation on
page 19).
With the DEFAULT pin HIGH, the device is placed in
Default Mode. The DEFAULT pin is pulled up to the VDD
supply through an active pull up current source. In Default
Mode the device operates in the following manner:
1. OSS outputs are disabled.
2. CCD1 and CCD2 outputs are disabled.
3. SPI ON/OFF control of GATE DRIVE (GD1 to GD6)
outputs and on board PWM controllers are disabled. PWMx
input control is enabled.
In the Default Mode the device retains all register
information and output status information. Normal operation
will resume when the DEFAULT pin transitions low again and
the device will operate as programmed prior to Default Mode.
RESISTOR EXTERNAL REFERENCE (REXT)
The input pins for octal serial switch outputs 1,3,5,7. Each
input control pin has an internal pull down current source.
Two outputs may be controlled in parallel using the PX pins
(See Functional Device Operation on page 25).
The reference current is used in the equation to calculate
the load resistance of the PWM outputs. The load resistance
measurement current is inversely proportional to REXT
current. The resistor value may be changed to adjust the load
measurement current. A 24Ω resistor to ground sets the
LRFDBK output to 260mV/Ω.
VOLTAGE CALIBRATED INPUT (VCAL)
EXPOSED PAD
The Voltage calibrated input (VCAL) provides the IC with
a reference voltage for analog circuits. VCAL (EXT or INT)
must be applied for the CCD1 and CCD2 constant current
controllers and Load Resistance measurement function to
The silicon die is epoxy attached to the top side of the pad.
Although the device does not use the pad for electrical
conduction, the bottom side exposed pad of the package
should be grounded.
INPUTS (P1, P3, P5, P7)
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Figure 5. Functional Block Diagram
ANALOG CONTROL CIRCUITRY
The 33800 is designed to operate from 5.0 to 36V on the
VPWR pin. The VPWR pin supplies power to all internal
regulators, analog and logic circuit blocks. The VDD supply is
used for setting communication threshold levels and
supplying power to the SO driver. This IC architecture
provides low quiescent current Sleep Modes. Applying
VPWR to the device will cause a Power On Reset (POR). The
on-chip oscillator supports the selectable PWM frequency
and duty cycle. The on-chip voltage regulator and bandgap
supply the required voltages to the internal circuitry.
current limits to accommodate lamp inrush current. The
device allows for parallel control of the outputs or SPI control
through the use of several input command words.
CONSTANT CURRENT LOW SIDE DRIVERS: CCD1
AND CCD2
The CCD1/CCD2 constant current controllers are
switching hysteretic current controllers with a superimposed
dither. The controllers are designed to provide a
programmable constant current through a solenoid valve.
Fluid flow is controlled by the amount of current run through
the driven solenoid valve.
MCU INTERFACE AND OUTPUT CONTROL
The device is designed with six flexible PWM gate driver
outputs. Each driver may be controlled directly from the MCU
and may be programmed through the SPI for a specific
frequency and duty cycle.
LOW–SIDE DRIVERS: OUT1 – OUT8
GATE PRE-DRIVERS: GD1 – GD6
The GD1 – GD6 pins are the gate drive outputs for external
MOSFETS. They can be PWM’ed with speed and duty cycle
choices per the SPI command registers. Internal to the device
is a Gate to Source resistor designed to hold the external
MOSFET in the OFF state while the device is in POR.
The 33800 provides flexible control of 8 low side driver
outputs. Outputs 1 and 2 are specifically designed with higher
33800
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
POWER SUPPLY
NORMAL MODE
The 33800 is designed to operate from 5.0 to 36V on the
VPWR pin. The VPWR pin supplies power to all internal
regulators, analog and logic circuit blocks. The VDD supply is
used for setting communication threshold levels and
supplying power to the SO driver. This IC architecture
provides flexible microprocessor interfacing with low
quiescent current Sleep Modes.
Normal Mode allows full functional control of the device.
Transferring from Sleep Mode to Normal Mode performs a
POR and resets all internal registers to the POR state. When
entering Normal Mode from Default Mode, no POR is
performed and register states are maintained.
Features programmed in Normal Mode are listed below.
Further explanation of each feature is provided in subsequent
paragraphs.
• Programmable PWM Frequency & Duty Cycle
• Programmable PWM Drain Fault Threshold
• CCD2 Constant Current Dither Frequency and Amplitude
• CCD2 DAC Programming
• CCD1 Constant Current Dither Frequency and Amplitude
• CCD1 DAC Programming
• On/Off OSS Open Load Detect Current
• Calibration of Timers (Calibration Command )
• Reset (Reset Command )
• No Operation (NO_OP Command)
POWER-ON RESET (POR)
Applying VPWR, VDD and EN to the device will cause a
Power On Reset (POR) and place the device in Normal or
Default Mode.
Table 5. Modes of Operation
VPWR
VDD
ENable
DEFAULT
MODE
L
X
X
X
Power
Off
H
L
X
X
SLEEP
H
H
L
X
SLEEP
H
H
H
L
NORMAL
H
H
H
H
DEFAULT
Command register settings from Power-ON Reset (POR)
via VPWR or VDD are as follows:
• All Outputs Off
• Inputs Enabled and OR’d with SPI Bit.
• PWM Frequency and Duty Cycle Control Disabled.
• OSS Open Load Detect Current Enabled.
• OSS Outputs with Individual Control.
• Control Inputs P1,P3,P5,P7 Enabled and OR’d with the
SPI Bit.
• CCD1 Output Off, Diagnostic Pull-up Enabled, DAC = 0.
• CCD2 Output Off, Diagnostic Pull-up Enabled, DAC = 0.
Power On Reset circuit incorporates a 0.5µs timer to
prevent high frequency transients from causing a POR.
During the low-voltage condition, internal logic states are
maintained. To guarantee a POR from VPWR, the VPWR pin
must be less than 0.2V for greater than 1.0µs.
DEFAULT MODE
The Default Mode allows the user to disable all outputs
except the PWM pre-driver. In Default Mode the PWM predriver outputs may only be controlled via the PWM input pins.
All register control bits and fault bits are maintained in Default
Mode, however control for the pre-driver is accomplished
through the PWM pins only.
With the DEFAULT pin HIGH, the device is placed in
Default Mode. When exiting Default Mode, output control
reverts to the internal register settings.
In Default Mode the device operates with the following
parameters.
1. OSS outputs are disabled.
2. CCD1 and CCD2 outputs are disabled.
3. SPI ON/OFF control of GATE DRIVE (GD1 to GD6)
outputs is disabled. PWMx input control is enabled. The
device will operate as programmed prior to Default Mode.
In Default Mode the device retains all register information
and output status information. Normal operation will resume
when the DEFAULT pin transitions low again.
SLEEP MODE
MODES OF OPERATION
The 33800 has three operating modes, Normal, Sleep and
Default Mode. A discussion on Normal Mode follows.
Sleep Mode is entered by placing a logic [0] on the
ENABLE or VDD pins. All outputs are commanded off and the
device enters a low quiescent current state.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI AND MCU INTERFACE DESCRIPTION
The 33800 device directly interfaces to a 3.3 or 5.0V
microcontroller unit (MCU) using 16 bit Serial Peripheral
Interface (SPI) protocol. SPI serial clock frequencies up to
4.0MHz may be used when programming and reading output
status information (production tested at 1MHz). Figure 6
illustrates the serial peripheral interface (SPI) configuration
between an MCU and one 33800.
Command data is sent to the 33800 device through the SI
input pin. As data is being clocked into the SI pin, status
information is being clocked out of the device by the SO
output pin. The response data received by the MCU during
SPI communication depends on the previous SPI message
sent to the device. The next SO response data is listed at the
bottom of each command table ( Table 7, on page 22, Table
12, on page 25, Table 22, on page 30 Table 23, on page 31,
Table 26, on page 34.
the serial configuration, 32-clock cycles are required to
transfer data in / out of the ICs.
Microcontroller
33800
MOSI
SI
Shift Register
MISO
SCLK
Parallel
Ports
SO
SCLK
CS
33800
SI
SO
SPI Integrity Check
SCLK
Checking the integrity of the SPI communication with the
initial power-up of the VDD and EN pins is recommended.
After initial system start-up or reset, the MCU will write one
32-bit pattern to the 33800. The first 16-bits read by the MCU
will be the fault status (SO message 1) of the outputs. The
second 16-bits will be the same bit pattern sent by the MCU.
By the MCU receiving the same bit pattern it sent, bus
integrity is confirmed. The second 16-bit pattern the MCU
sends to the device is the a command word and will be
operated on by the device accordingly on rising edge of CS.
Important A SCLK pulse count strategy has been
implemented to ensure integrity of SPI communications. SPI
messages consisting of 16 SCLK pulses and multiples of 8
clock pulses thereafter will be acknowledged. SPI messages
consisting of other than 16 + multiples of 8 SCLK pulses will
be ignored by the device.
CS
Figure 7. SPI Parallel Interface with Microprocessor
Microcontroller
33800
MOSI
SI
Shift Register
MISO
SCLK
Parallel
Ports
SO
SCLK
CS
33800
Microcontroller
MOSI
SI
Shift Register
SI
16-Bit Shift Register
MISO
33800
SO
SO
SCLK
CS
SCLK
Receive
Buffer
To Logic
CS
Parallel
Ports
Figure 8. SPI Serial Interface with Microprocessor
PROGRAMMABLE PWM GATE DRIVER OUTPUTS
Figure 6. SPI Interface with Microprocessor
Two or more 33800 devices may be used in a module
system. Multiple ICs may be SPI-configured in parallel or
serial. Figures 7 and 8 show the configurations. When using
The 33800 device is designed with six flexible PWM gate
driver outputs. Each driver may be controlled directly from the
MCU or may be programmed through the SPI for a specific
frequency and duty cycle.
The pre-drivers are designed with four diagnostic features:
33800
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
• Off State Open Load Detect
• On State Short Circuit Detect
• Programmable Drain Threshold and Timer for Short Fault
Detection
• Load Resistance Measurement
Each pre-driver is capable of detecting an open load in the
off state and shorted load in the on state. All faults are
reported through SPI communication. For open load
detection, a resistor is placed between the drain sense pin
and source sense pin of the IC. An open load fault is reported
when the drain voltage is less than the 2.5V threshold. A
shorted load fault is reported when the drain voltage is
greater than the programmed threshold voltage.
Programming of the drain short fault threshold voltage is
done through SPI commands provided in Table 7.
Bits 6 through 9 are used to perform the load resistance
measurement function as described in the Gate Drive On/Off
Command section below.
GATE DRIVE ON/OFF COMMAND
The GD ON/OFF Command provides control bits for two
functions:
• On/Off control of the GDx outputs.
• Load Resistance measurement function.
On/Off control bit 0 through bit 5 control gate drive outputs
GD1 through GD6 respectively. Setting the bit to logic1 will
enable the gate drive to the external MOSFET. Setting the bit
to logic 0 will actively pull the gate to ground.
GD ON/OFF Command bits 6 through 9 control the load
measurement feature. The gate drive pre-drivers are
selected in matched pairs. Selecting a load resistance
measurement disables a specified output pair and performs
the resistance measurement using the defined pair. All other
outputs will operate as programmed. Resistance is measured
by passing a known current through the load and by
measuring the voltage across it. The resistor placed on the
REXT pin determines the current through the load during
measurement. The voltage output on the LRFDBK pin is the
differential load voltage with the defined current through it.
From the two parameters, the load resistance may be
calculated. Table 6 illustrates the load diagnostic multiplex
function.
Table 6. Load Resistance Measurement Select
Bits 9876
MUX Select
0000
Normal Operation
0001
VDSNS1 to REXT, VDSNS2 to Diff-Amp +
0010
VDSNS2 to REXT, VDSNS1 to Diff-Amp +
0011
VDSNS3 to REXT, VDSNS4 to Diff-Amp +
0100
VDSNS4 to REXT, VDSNS3 to Diff-Amp +
0101
VDSNS5 to REXT, VDSNS6 to Diff-Amp +
0110
VDSNS6 to REXT, VDSNS5 to Diff-Amp +
0111
Normal Operation
1000
Normal Operation
1001
Normal Operation
1010
VDSNS2 to REXT, VDSNS1 to Diff-Amp +
1011
VDSNS3 to REXT, VDSNS1 to Diff-Amp +
1100
VDSNS4 to REXT, VDSNS1 to Diff-Amp +
1101
VDSNS5 to REXT, VDSNS1 to Diff-Amp +
1110
VDSNS6 to REXT, VDSNS1 to Diff-Amp +
1111
Normal Operation
PWM PIN ENABLE COMMAND
The PWM Pin Enable Command provides control bits for
two functions:
• Enable or Disable of PWM input pins.
• Enable or Disable of the internal PWM controller for GD1
through GD6.
PWM pin Enable bit 0 through bit 5 enable or disable the
PWM1 through PWM6 input pins respectively. A logic 0 in the
SPI word will enable the PWM input pin, while logic 1 in the
SPI word will disable the PWM input pin. Default state is with
the PWM input pin enabled. With the PWM input pin disabled,
the AND/OR function is also disabled and control is achieved
through the Gate Drive ON/OFF command or the internal
PWM controller.
AND /OR COMMAND
The AND/OR Command provides control bits for two
functions:
• Determines AND/OR relation between ON/OFF SPI bit
and PWM input pin.
• Enable or Disable of the internal PWM controller for G1
through GD6.
The AND /OR command describes the condition by which
the PWM input pin controls the output driver. A logic[0] in the
AND / OR register will OR the PWM input pin with the
respective bit in the ON/OFF register. Likewise, a logic[1] in
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
the AND / OR register will AND the PWM input pin with the
respective bit in the ON/OFF register. The AND/OR function
is disabled when the PWM input pin is disabled.
Table 7. PWM Command
PWM Commands
Control Address
15
14
13
12
Command Bits
11
10
9
8
7
6
5
Rld Load Resistance
Measurement Select
GDX ON/OFF Command
0 = Off, 1 = On
0
1
0
0
1
X
0
0
0
0
AND/OR Command
0 = PWMX Pin OR with SPI
1 = PWMX Pin AND with SPI
0
1
0
1
0
X
X
0
0
3
2
1
0
Gate Drive ON/OFF Bit
0
0
PWM Controller
Enable Bit
PWM Pin Enable Command
0 = PWMX Pin Enabled
1 = PWMX Pin Disabled
4
0
0
0
0
0
0
PWM Pin Enable Bit
0
0
0
0
0
0
0
0
0
0
0
0
PWM3 PWM2 PWM1
1
0
1
1
X
X
0
0
0
PWM6 PWM5 PWM4
Command
Control Address
Frequency Select
Duty Cycle Select
PWM1 Freq & DC
0
1
1
0
0
X
0
0
0
0
0
0
0
0
0
0
PWM2 Freq & DC
0
1
1
0
1
X
0
0
0
0
0
0
0
0
0
0
PWM3 Freq & DC
0
1
1
1
0
X
0
0
0
0
0
0
0
0
0
0
PWM4 Freq & DC
0
1
1
1
1
X
0
0
0
0
0
0
0
0
0
0
PWM5 Freq & DC
1
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
PWM6 Freq & DC
1
0
0
0
1
X
0
0
0
0
0
0
0
0
0
0
Control Address
V DSNS3
VDSNS2
VDSNS1
VDSNS123 Short Threshold
1
0
0
1
0
X
X
0
1
1
0
1
1
0
1
1
VDSNS123 Short Timer
1
0
0
1
1
X
X
0
1
1
0
1
1
0
1
1
Control Address
VDSNS6
VDSNS5
VDSNS4
VDSNS456 Short Threshold
1
0
1
0
0
X
X
0
1
1
0
1
1
0
1
1
VDSNS456 Short Timer
1
0
1
0
1
X
X
0
1
1
0
1
1
0
1
1
Next SO Response (Message 1) OvrVlt Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault
0 = No Fault, 1 = Fault
,TLim
Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu
or
sPW sPW sPW sPW sPW sPW sOUT sOUT sOUT sOUT sOUT sOUT sOUT sOUT
CAL
M6
M5
M4
M3
M2
M1
8
7
6
5
4
3
2
1
Flt
33800
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 8. And/Or/SPI/Parallel Control
PWM Pin AND/OR
ON/
Rload
EN
Bit
OFF
Measure 0 = en 0 = OR
Bit
1 = dis 1 = AND
PWM
Freq/
DC EN
Bit
PWM
Pin
Output
≠0
X
X
X
X
X
Rload
Measure
0
1
X
0
0
X
OFF
0
1
X
0
1
X
Freq/DC
0
1
X
1
X
X
ON
0
0
0
0
0
0
OFF
0
0
0
0
1
0
Freq/DC
0
0
0
X
X
1
ON
0
0
0
1
X
X
ON
0
0
1
0
0
X
OFF
0
0
1
X
0
0
OFF
0
0
1
0
1
X
Freq/DC
0
0
1
X
1
0
Freq/DC
0
0
1
1
X
1
ON
Table 9 defines the output frequency with the selected
input bits.
Table 9. Frequency Select
Frequency Select
Bits
987
Frequency Hz
000
10 Hz
001
20 Hz
010
40 Hz
011
80 Hz
100
160 Hz
101
320 Hz
110
640 Hz
111
1.28 kHz
Notes: Tolerance on selected frequency is +-10% with part
calibrated. On state short faults may not be detected if t_on_short >
1/f_pwm * duty_cycle * 0.98.Off state open faults may not be
detected if t_off_open > 1/fpwm * (1-duty_cycle) * 0.75.
VDSNSX SHORT THRESHOLD COMMAND
The short fault threshold voltage of the external MOSFET
may be programmed via SPI. Table 10 illustrates the bit
pattern required for a particular short fault threshold. Open
load fault detect threshold is set internally to 2.5V and may
not be programmed.
PWM FREQUENCY/DUTY CYCLE COMMAND
The PWM Frequency/Duty Cycle Command allows the
user to individually program a PWM output with a frequency
and duty cycle. Once the PWM Freq/DC registers are
programmed, the PWM output GD1, GD2, GD3 are
controlled via the AND/OR command and GD4, GD5, GD6
are controlled via the PWM pin Enable Command. Pre-driver
output control bits supersede the internal PWM controller.
GDx outputs must be commanded OFF for the controller to
function. (SeeTable 8)
The duty cycle of the PWM outputs is controlled by bits 0
through 6, inclusive. The duty cycle value is 1% per binary
count from 1 to 100 with counts of 101 through 127 defaulting
to 100%. For example:
Sending SPI WORD; 01100x1110001100
This would set PWM1 output to 1.28Khz frequency with a
12% duty cycle.
Table 10. VDSNSx Fault Threshold Select
PWM VDS FLT
Bits
210
543
876
VDSNSx Fault Threshold Select
000
0.5V
001
1.0V
010
1.5V
011
2.0
100
2.5V
101
3.0V
110
No Change
111
No Change
VDSNSX SHORT FAULT TIMER COMMAND
The Short Fault Timer can be programmed via the SPI to
the values listed in Table 11, on page 24. When the 33800
detects an over-current condition, as defined by VDS
exceeding the programmed short fault voltage threshold, the
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
33800 will wait for the Short Fault Time period and then shut
down the output drive, setting the fault status bit to a 1 in the
Serial Output Response Register.
Table 11. PWM Short Fault Timer
Predriver 1
VDSNS1
PWM FLT Timer
Bits
210
543
876
Fault Timer Select
000
30µs
001
60µs
010
120µs
011
240µs
100
480µs
101
960µs
110
No Change
111
No Change
VPWR
Gate Drive
Control &
Diagnostics
GD1
VSSNS123
Predriver 2
VDSNS2
VPWR
Gate Drive
Control &
Diagnostics
GD2
VSSNS123
Differential
+ Amplifier
Notes: Tolerance on fault timer setting is ±10% with calibrated part.
−
+
−
LRFDBK
Example: Load Measurement Operation
To perform an accurate load resistance measurement the
33800 device uses an alternate channel to determine a
differential load voltage and forces a known load current.
With the differential load voltage and the forced current the
load resistance is calculated. As shown in Table 6, channel 2
is used as the battery reference for the load measurement of
channel 1. The current through the channel 1 load is set by
the external resistor. Setting the resistance to 25Ω forces a
current of 100mA. The measurement is sampled within
200µs and is held for 150ms on the Load Resistance
Feedback (LRFDBK) output. The differential amplifier has a
fixed gain of 2.5V. Hence for this example, a 10Ω load will
produce a 2.5V output. When a second pair is selected for
measurement, the sample and hold is reset and the
measurement is immediately directed to the new load
measurement. The previous pair immediately revert back to
normal operation.
VCAL
+
−
REXT
Figure 9. Example of Channel 1 Measurement
OCTAL OUTPUT DRIVER (OCTAL SERIAL
SWITCH; OSS)
The 33800 provides flexible control of 8 low side driver
outputs. Outputs 1 and 2 are specifically designed with higher
current limit to accommodate lamp inrush current. The device
allows for parallel control and/or SPI control through the use
of several input command words. This section describes the
logic operation and commands for the octal driver.
The 33800 Octal Output Driver message set consists of
eight commands, and one response as shown in Table 12.
Bits 11 through 15 determine the specific command and bits
0 through 10 determine how a specific output will operate.
The 33800 operates on the command word on the rising edge
of CS. The Most Significant Bit (MSB) is sent and received
first.
Note Upon Power-ON Reset all OSS bits are defined as
shown in Table 12.
33800
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 12. OSS SPI Control Commands and Response
Command
Control Address
Command Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OSS ON/OFF Command
0 = off, 1 = on
0
0
0
0
1
X
X
X
0
0
0
0
0
0
0
0
Open Load Current Enable
0 = disable, 1 = enable
0
0
0
1
0
X
X
X
0
0
0
0
0
0
0
0
Shutdown / Retry from VPWR Over
Voltage
0 = shutdown, 1 = retry
0
0
0
1
1
X
X
X
1
1
1
1
1
1
1
1
Shutdown / Retry from Short
Circuit
0 = shutdown, 1 = retry
0
0
1
0
0
X
X
X
1
1
1
1
1
1
1
1
TLim Command
0 = disable, 1 = enable
0
0
1
0
1
X
X
X
1
1
1
1
1
1
1
1
Fault Timer Command
0 = Fault Timer Disabled
1 = Fault Timer Enabled
0
0
1
1
0
X
X
X
1
1
1
1
1
1
1
1
Parallel
Outputs(7&8,5&6,3&4,1&2)
Parallel Input Pin Enable
0 = Individual Control, PX enabled
1 = Parallel Control, PX disabled
0
0
1
1
1
X
X
X
0
0
0
0
0
0
0
0
AND/OR Control
0 = PX Pin OR with SPI
1 = PX Pin AND with SPI
0
Output Output Output Output P7 en P5 en P3 en P1 en
7&8
5&6
3&4
1&2
1
0
0
0
X
X
X
0
0
0
0
0
0
0
0
Next SO Response (Message 1) OvrVlt Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault
0 = No Fault, 1 = Fault
,TLim
Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu
or
sPW sPW sPW sPW sPW sPW sOUT sOUT sOUT sOUT sOUT sOUT sOUT sOUT
CAL
M6
M5
M4
M3
M2
M1
8
7
6
5
4
3
2
1
Flt
ON /OFF CONTROL COMMAND
To program the 8 outputs of the 33800 ON or OFF, a 16bit serial stream of data is entered into the SI pin. The first 8bits of the control word are used to identify the on / off
command and the remaining 8-bits are used to turn ON or
OFF the specific output driver. When commanding an output
ON or OFF, the Most Significant Bit (MSB) is sent and
received first. Bit 7 corresponds to output 8 down to bit 0
which corresponds to output 1.
OPEN LOAD CURRENT ENABLE COMMAND
The Open Load Enable Command is provided to enable or
disable the open load detect pull-down current. This feature
allows the device to be used in LED applications. On power
up reset (POR) or the RESET command the pull-down
current sources are disabled. To enable the open load
current source, the user must program the Open Load
Current Disable Control register with logic[1]. Open load
faults may not be reported with the pull-down current source
disabled.
OVER-VOLTAGE SHUTDOWN/RETRY COMMAND
The Over Voltage Shutdown/Retry Command allows the
user to select the fault strategy for the outputs. The overvoltage control bit sets the operation of the outputs when
returning from over-voltage. Setting the over-voltage bit to
logic[0] will force all outputs to remain OFF when VPWR
returns to normal level. Setting the over-voltage bit to logic[1]
will command outputs to resume their previous state when
VPWR returns to normal level.
TLIM COMMAND, TIMER COMMAND
The TLim and Timer commands are used to enhance the
short circuit protection strategy of the Octal Serial Switch
output drivers.
The Timer protection scheme uses a low duty cycle in the
event of a short circuit. The TLim protection circuit uses the
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
temperature of the output driver to determine the fault. Both
methods may be selected or used individually. The following
table provides an explanation of operation during fault
condition.
The low duty cycle used for the timer protection scheme is
set by the fault timer used to detect the short circuit. For short
circuits detected based on the output voltage exceeding the
fault detection voltage threshold, the outputs will be turned off
for the duration of the refresh timer (typically 10ms) and
turned on for the duration of the on-state short circuit fault
timer (typically 500µs). For short circuits detected based on
the output current exceeding the output current limit, the
outputs will be turned off for the duration of the refresh timer
(typically 10 ms) and turned on for the duration of the current
limit fault timer (typically 50µs).
For off-state open load faults with retry timer enabled, the
off-open fault is released and re-detected every 1-2 retry
timer periods. Retry timer for 1-2, 3-4, 5-6, and 7-8 are out of
phase and may report a load present, if the OSS read
command CS is issued after the release, and before the redetection (~500µs) of the off-state open load fault.
Table 13. TLim/Timer Control
Shutdn
Retry Bit
TLIM
Bit
Fault
Timer
Bit
1
0
X
Operation During Short Fault
Timer only, Outputs will retry on
period
OUT1-8 = ~500us for short
circuit faults, and 50us for current
limit faults ON, ~10ms OFF.
1
1
0
TLim only, Outputs will retry on
TLim hysteresis.
1
1
1
Timer and TLim, Outputs will
retry on period and driver
temperature below threshold.
OUT1-8 = ~500us ON, ~10ms
OFF
0
0
X
Timer only, Outputs will not retry
on period
PARALLEL OUTPUT, PX PIN ENABLE COMMAND
The Parallel Output command allows the user to parallel
output for increased current capability and enables control of
the PX input pin.
A logic 0 in the Parallel Output Command provides
individual control. Logic 1 commands outputs to operate in
parallel. For example, with bit 4 in the Parallel Output
command a logic 1, outputs 1 & 2 are controlled together
With the outputs paralleled, and the P1 pin enabled, a logic
1 on SPI bit 0 or SPI bit 1 will command both outputs on.
Similarly a logic 1 on the P1 pin will command both outputs
on.
PX pin Enable bit 0 through bit 3 enables or disables the
P1, P3, P5, P7 pins respectively. A logic 0 in the SPI word will
enable the PX input pin, while logic 1 in the SPI word will
disable the PX input pin. Default state is with the PX input
pins enabled.
When paralleling output 1 & 2 the current limit is
maintained at 4.0 to 6.0A. Parallel current limit for drivers
3&4, 5&6, 7&8 is increased to a range of 2.0 to 4.0A.
Using a MOSFET as output switches allows the
connection of paired outputs. The RDS(ON) of MOSFET
devices have inherent positive temperature coefficient
providing balanced current sharing between outputs without
destructive operation. This mode of operation may be
desirable in the event the application requires lower power
dissipation or the added capability of switching higher
currents. Performance of parallel operation results in a
corresponding decrease in RDS(ON), while the Output Current
Limit increases correspondingly. Output OFF Open Load
Detect current may increase based on how the Output OFF
Open Load Detect is programmed.
Table 14. And/Or/SPI/Parallel Control
Parallel
En Bit
PX Pin
En Bit
PX Pin
AND/
OR Bit
SPI
Bit 1
SPI
Bit 0
Output
1&2
1
0
X
X
0
0
OFF
1
0
X
X
0
1
ON
1
0
X
X
1
0
ON
1
0
X
X
1
1
ON
1
1
0
1(or)
0
0
OFF
1
1
0
1(or)
0
1
ON
1
1
0
1(or)
1
0
ON
1
1
0
1(or)
1
1
ON
1
1
0
0(and)
X
X
OFF
1
1
X
0(and)
0
0
OFF
1
1
1
0(and)
0
1
ON
1
1
1
0(and)
1
0
ON
1
1
1
0(and)
1
1
ON
OUT1-8 = ~500us ON, OFF
0
0
1
1
0
1
TLim only, Outputs will not retry
on TLim hysteresis.
Timer and TLim, Outputs will not
retry on period or TLim.
OUT1-8 = ~500us ON, OFF
All OSS outputs have a current limit control loop. Current
limit is always active in Normal Mode. Current limit for OUT1
and OUT2 is 4.0 to 6.0A. Current limit for OUT3 through
OUT8 is 1.0 to 2.0A.
33800
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
AND /OR COMMAND
The AND/OR Command provides control bits for the
following function:
• Determines AND/OR relation between ON/OFF SPI bit
and PX input pin.
The AND /OR command describes the condition by which
the PX input pin controls the output driver. A logic[0] in the
AND / OR register will OR the PX input pin with the respective
bit in the ON/OFF register. Likewise, a logic[1] in the AND /
OR register will AND the PX input pin with the respective bit
in the ON/OFF register. The AND/OR function is disabled
when the PX input pin is disabled.
SERIAL OUTPUT (SO) RESPONSE REGISTER
Fault reporting is accomplished through the SPI interface.
All logic[1]s received by the MCU via the SO pin indicate fault.
All logic[0]s received by the MCU via the SO pin indicate no
fault. All fault bits are cleared on the positive edge of CS. SO
bits 15 to 0 represent the fault status of outputs 15 to 0. The
timing between two write words must be greater than 450µs
to allow adequate time to sense and report the proper fault
status.
CCD1 CONSTANT CURRENT CONTROLLER
The CCD1 constant current controller is a switching
hysteretic current controller with a superimposed dither. The
controller is designed to provide a programmable constant
current through a solenoid valve. Fluid flow is controlled by
the amount of current run through the solenoid valve.
The master SPI device sends 16 bit command words to
the 33800 device (see Table 15). The master device sets up
the output current based on the CCD1 Control command.
The IC is capable of sinking an average output current from
0mA to 1075mA (without dither). If operating the device with
dither, the DAC + Dither value must be less than 1075mA or
greater than 0.0mA. Commands outside of this command
range will automatically lock out dither.
Programming the solenoid current begins by sending the
CCD1 Control command. The command consists of an
control address, Diagnostic Pull Up Enable bit
(Diag_pu_EN), Dither Disable bit (DTHR_DIS), and a 9-bits
of data for digital to analog conversion (DAC). The data is
received and the DAC provides bias for a comparator to
produce a threshold level. The comparator drives a switch
control circuit which generates a frequency modulated signal
for the output drive. The differential voltage across the sense
resistor provides the feedback necessary to maintain the
desired output current. The output current is continuously
monitored as a differential voltage across the internal sense
resistor. When the current is in recirculation and the driver is
in the off state, the current will decay to the lower limit switch
point. When the current reaches the lower limit, the driver will
turn on to increase the current until the upper limit switch
point is reached. The output current will continue to switch
between the switch points, resulting in the desired average
current. The switch points are set to a fixed ±5% of the
commanded current. The switching frequency and accuracy
are dependent upon the load inductance and resistance,
battery voltage, dither amplitude and frequency, switch points
and the commanded current.
Current dither is a method by which the average current is
increased and decreased through the solenoid valve. The
33800 allows the user to program the frequency and
amplitude of the dither control. Dither amplitude is
implemented by increasing and decreasing the DAC by the
programmed dither value. The rate at which the value
changes is set by the programmed dither frequency. When
reprogramming the dither amplitude or dither frequency, the
update will occur on the start of a positive cycle.
The maximum value of the output (DAC + Dither) must be
less than 1075mA. When a greater value is programmed the
device will disable the dither on the output. Similarly, the
minimum value of the output (DAC - Dither) must be greater
than 0.0mA. Requesting a lower value will disable the dither
on the output.
ON/OFF CONTROL BIT
The CCD1 output may be used as a standard 1.0A low
side driver. For on/off control, the CCD1_DIS bit int the
CCD1Frequency & Amplitude command must be set to logic
1. This disables the constant current driver and enables the
on/off control. To turn the driver ON a logic 1 is placed in the
ON/OFF control bit. A logic 0 placed in the ON/OFF control
bit will turn the driver OFF.
The protection scheme in low side driver mode operates
the same as constant current mode.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 15. CCD1 Constant Current Controller Commands
Command
Control Address
15
14
13
12
Command Bits
11
CCD1 Command Address
CCD1 Control
0 = Pull Down
Current Source
1 = Pull Up Current
Source
1
0
1
1
0
CCD1 Command Address
CCD1 Frequency
& Amplitude
1
0
1
Next SO Response OvrVlt Reset Trim
(Message 2)
TLim or
Set(19)
0 = No Fault, 1 = CAL Flt
Fault
Notes
19.
20.
21.
22.
1
10
9
8
7
6
Diag DTHR
Pull Up DIS
1
0
0
CCD1
Retry
ON/
OFF
1
0
5
4
3
2
1
0
0
0
0
9 BIT DAC Command Data
0
0
0
CCD1 TLim
DIS
EN
0
1
0
0
0
Dither Amplitude
0
1
1
Dither Frequency
0
1
0
0
VCAL Open Short Open Short Fault Fault Fault Fault Fault Fault Fault Fault
Status Fault Fault Fault Fault Status Status Status Status Status Status Status Status
int=0 CCD2 CCD2 CCD1 CCD1 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
ext=1
Trim Set bit indicates (0=untrimmed, 1= trimmed)
VCAL Status bit indicates when internal or external supply is used. VCAL Bit = 0 indicates external, VCAL Bit = 1indicates internal.
Reset Bit indicates the device has performed a POR.
CCD1 DISable bit allows the CCD1 driver to operate as a standard 1.0A low side driver. With CCD1_DIS bit = 1 the CCD1 function is
disabled.
Table 16. CCD1 Dither Frequency Select
Table 17. CCD1 Dither Amplitude Select
Bits 3210
Dither Frequency
Bits 654
Dither Amplitude
0000
Dither Off
000
Dither Off
0001
50Hz
001
50.4mA
0010
100Hz
010
100.8mA
0011
150Hz
011
151.2mA
0100
200Hz
100
201.6mA
0101
250Hz
101
252.0mA
0110
300Hz
110
302.4mA
0111
350Hz
111
352.8mA
1000
400Hz
1001
450Hz
1010
500 Hz
1011
133Hz
1100
166Hz
1101
233Hz
1110
266Hz
1111
No change
CCD2 CONSTANT CURRENT CONTROLLER
Notes: Frequencies above 250Hz are +- 20%
The CCD2 constant current controller is a switching
hysteretic current controller with a superimposed dither. The
controller is designed to provide a programmable constant
current through a solenoid valve. By controlling current
through the solenoid valve, fluid flow control is achieved.
The master SPI device sends 16-bit command words to
the 33800 device (see Table 18). The master device sets up
the output current based on the CCD2 Control command.
The IC is capable of sinking an average output current from
0.0mA to 232mA (without dither). If operating the device with
dither, the DAC + Dither value must be less than 232mA or
33800
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
greater than 0.0mA. Commands outside of this command
range will automatically lock out dither.
Programming the solenoid current begins by sending the
CCD2 Control command. The command consists of an
control address, Diagnostic Pull-up Enable bit (Diag_pu_EN),
Dither Disable bit (DTHR_DIS), and a 9-bits of data for digital
to analog conversion (DAC). The data is received and the
DAC provides bias for a comparator to produce a threshold
level. The comparator drives a switch control circuit which
generates a frequency modulated signal for the output drive.
The differential voltage across the sense resistor provides
the feedback necessary to maintain the desired output
current. The output current is continuously monitored as a
differential voltage across the internal sense resistor. When
the current is recirculation and the driver is in the off state, the
current will decay to the lower limit switch point. When the
current reaches the lower limit, the driver will turn on to
increase the current until the upper limit switch point is
reached. The output current will continue to switch between
the switch points, resulting in the desired average current.
The switch points are set to a fixed +/-5% of the commanded
current. The switching frequency and accuracy are
dependent upon the load inductance and resistance, battery
voltage, dither amplitude and frequency, switch points, and
the commanded current.
Current dither is a method by which the average current is
increased and decreased through the solenoid valve. The
33800 allows the user to program the frequency and
amplitude of the dither control. Dither amplitude is
implemented by increasing and decreasing the DAC by the
programmed dither value. The rate at which the value is
changed is set by the programmed dither frequency. When
reprogramming the dither amplitude or dither frequency, the
update will occur on the start of a positive cycle.
The maximum value of the output (DAC + Dither) must be
less than 232mA. When a greater value is programmed, the
device will disable dither on the output. Similarly, the
minimum value of the output (DAC - Dither) must be greater
than 0.0mA. Requesting a lower value will disable dither on
the output.
Table 18. CCD2 Constant Current Controller Commands
Command
Control Address
15
14
13
12
Command Bits
11
CCD2 Command Address
CCD2 Control
0 = Pull-down Current Source
1 = Pull-up Current Source
1
1
0
0
0
CCD2 Command Address
CCD2 Frequency & Amplitude
1
1
0
0
1
10
9
8
7
Diag DTHR
Pull- DIS
up
0
0
5
4
3
0
0
0
0
0
0
Dither Amplitude
X
2
1
0
0
0
9 BIT DAC Command Data
CCD2
Retry
1
6
X
X
0
1
1
0
Dither Frequency
0
1
0
0
Next SO Response (Message 2) OvrVlt Reset Trim VCAL Open Short Open Short Fault Fault Fault Fault Fault Fault Fault Fault
0 = No Fault, 1 = Fault
,TLim
Set (23) Status Fault Fault Fault Fault Status Status Status Status Status Status Status Status
int=0 CCD2 CCD2 CCD1 CCD1 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
or
ext=1
CAL
Flt
Notes
23. Trim Set bit indicates (0 = untrimmed, 1 = trimmed)
24. VCAL Status bit indicates when internal or external supply is used. VCAL Bit = 0 indicates external, VCAL Bit = 1indicates internal.
25. Reset Bit indicates the device has performed a POR.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 19. CCD2 Dither Frequency Select
Table 20. CCD2 Dither Amplitude Select
Bits 3210
Dither Frequency
Bits 456
Dither Amplitude
0000
Dither Off
000
Dither Off
0001
50Hz
001
21.8mA
0010
100Hz
010
32.7mA
0011
150Hz
011
43.6mA
0100
200Hz
100
54.5mA
0101
250Hz
101
65.4mA
0110
300Hz
110
75.3mA
0111
350Hz
111
87.2mA
1000
400Hz
1001
450Hz
1010
500Hz
1011
133Hz
1100
166Hz
1101
233Hz
1110
266Hz
1111
No change
Calibration Command
In cases where an accurate time base is required, the user
may calibrate the internal timers using the calibration
command (refer to Table 5). After the 33800 device receives
the calibration command, the device expects a 32µs logic[0]
calibration pulse on the CS pin. The pulse is used to calibrate
the internal clock. SPI communication is allowed during
calibration. Because the oscillator frequency changes with
temperature, calibration is required for an accurate time
base. The calibration command may be used to update the
device on a periodic basis.
Notes: Frequencies above 250Hz are +- 20% assumes part is calibrated
Table 21. Calibration Command
Command
Control Address
Calibration Command
Command Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
Reset Command
states or the paragraph entitled Power-ON Reset (POR) on
page 19 of this datasheet.
The reset command resets all registers to Power-ON
Reset (POR) state. Refer to Table 22, on page 30, for POR
.
Table 22. Reset Command
Command
Reset
Control Address
Command Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
Next SO Response OvrVlt Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault
(Message 1)
,TLim
Status Status Status Status Status Status Status Status Status Status Status Status Status Status
0 = No Fault, 1 =
or
PWM PWM PWM PWM PWM PWM OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
Fault
CAL
6
5
4
3
2
1
Flt
33800
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
No Operation Command
Sending these two commands perform no operation. The device outputs will remain in previous state.
.
Table 23. No Operation Command
Command
Control Address
Command Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NO Operation
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
NO Operation
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
Next SO Response
(Message 1)
0 = No Fault, 1 = Fault
OvrVl Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault
t,TLi
Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu
m or
sPW sPW sPW sPW sPW sPW sOUT sOUT sOUT sOUT sOUT sOUT sOUT sOUT
CAL
M6
M5
M4
M3
M2
M1
8
7
6
5
4
3
2
1
Flt
FAULT OPERATION
Command Register Definition:
0 = Output Command Off
1 = Output Command On
SO Definition:
0 = No fault
1 = Fault
On each SPI communication, a 16-bit command word is
sent to the 33800 and a 16-bit status word is received from
the 33800.
The Most Significant Bit (MSB) is sent and received first.
Table 24. Fault Operation
Serial Output (SO) Pin Reports
Over-current
SO Pin reports short-to-battery/supply or over-current condition.
Output ON Open Load Fault
Not reported on GDX and OUTX outputs. Reported on CCD1 and CCD2 outputs
Output OFF Open Load Fault
SO Pin reports output “OFF” open load condition.
Device Shutdowns
Over-voltage
Total device shutdown at VPWR = 36.5 to 44V. Resumes normal operation with proper voltage. Upon
recovery all outputs assume previous state or OFF based on the over-voltage bit in the Shutdown / Retry
Control register.
Over-current
OUTX & CCDX outputs will remain in current limit until tSC limit is reached. With TLim enabled, OUTX &
CCDX outputs will remain in current limit until TLim is reached.
SPI Command Summary
Table 25 below provides a comprehensive list of SPI
commands recognized by device 33800 and the reset state
of each register.
Table 25. SPI Commands
Command Name
Control Address
Command Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
MISCELLANEOUS
Common Commands
Calibration Command
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 25. SPI Commands
Command Name
Control Address
Command Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
NO Operation
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
NO Operation
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
OUT
3
OUT
2
OUT
1
OSS COMMANDS
OSSX Commands
OSS ON/OFF
1 = on, 0 = off
0
0
0
0
1
X
X
X
0
0
0
0
0
0
0
0
Open Load Current Enable
0 = enable, 1 = disable
0
0
0
1
0
X
X
X
0
0
0
0
0
0
0
0
Shutdown / Retry from VPWR
Over-voltage
0 = shutdown, 1 = retry
0
0
0
1
1
X
X
X
1
1
1
1
1
1
1
1
Shutdown / Retry from Short
Circuit
0 = shutdown, 1 = retry
0
0
1
0
0
X
X
X
1
1
1
1
1
1
1
1
TLim Enable
1 = enable, 0 = disable
0
0
1
0
1
X
X
X
1
1
1
1
1
1
1
1
Fault Timer Enable
1 = enable, 0 = disable
0
0
1
1
0
X
X
X
1
1
1
1
1
1
1
1
Parallel Outputs Enable
(7&8,5&6,3&4,1&2)
0 = Individual Control
1 = Parallel Control
PX Pin Enable
0 = enable PX
1 = disable PX (SPI only)
0
0
1
1
1
X
X
X
1
Out
7&8
1
OUT
5&6
1
OUT
4&3
1
OUT
2&1
0
P7
EN
0
P5
EN
0
P3
EN
0
P1
EN
AND/OR Control
1 = PX Pin AND with SPI
0 = PX Pin OR with SPI
0
0
0
0
0
1
0
0
0
X
X
X
0
0
0
0
33800
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 25. SPI Commands
Command Name
Control Address
15
14
13
12
Command Bits
11
10
9
8
7
6
5
4
3
2
1
0
GDX COMMANDS
RLD Load Resistance
Measurement Select
GDX ON/OFF Command
0 = Off, 1 = On
0
1
0
0
1
X
0
0
0
Gate Drive ON/OFF Bit
0
0
0
PWM Controller
Enable Bit
0
0
0
0
PWM Pin Enable Bit
PWM Pin Enable Command
0 = PWMX Pin Enabled
1 = PWMX Pin Disabled
0
1
0
1
0
X
X
0
0
0
PWM3 PWM2 PWM1
0
0
0
0
0
0
AND/OR Command
0 = PWMX Pin OR with SPI
1 = PWMX Pin AND with SPI
0
1
0
1
1
X
X
0
0
0
PWM6 PWM5 PWM4
0
0
0
0
0
0
Frequency Select
Duty Cycle Select
PWM1 Freq & Duty Cycle
0
1
1
0
0
X
0
0
0
0
0
0
0
0
0
0
PWM2 Freq & Duty Cycle
0
1
1
0
1
X
0
0
0
0
0
0
0
0
0
0
PWM3 Freq & Duty Cycle
0
1
1
1
0
X
0
0
0
0
0
0
0
0
0
0
PWM4 Freq & Duty Cycle
0
1
1
1
1
X
0
0
0
0
0
0
0
0
0
0
PWM5 Freq & Duty Cycle
1
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
PWM6 Freq & Duty Cycle
1
0
0
0
1
X
0
0
0
0
0
0
0
0
0
0
VDSNS3
VDSNS2
VDSNS1
VDSNS123 Short Threshold
1
0
0
1
0
X
X
0
1
1
0
1
1
0
1
1
VDSNS123 Short Timer
1
0
0
1
1
X
X
0
1
1
0
1
1
0
1
1
VDSNS6
VDSNS5
VDSNS4
VDSNS456 Short Threshold
1
0
1
0
0
X
X
0
1
1
0
1
1
0
1
1
VDSNS456 Short Timer
1
0
1
0
1
X
X
0
1
1
0
1
1
0
1
1
Diag
EN
DTHR
DIS
1
0
0
0
0
0
0
CCD1
Retry
LSD
ON/
OFF
CCD1
DIS
TLim
EN
1
0
0
1
Diag
EN
DTHR
DIS
CCD COMMANDS
CCD1 Control
CCD1 Frequency & Amplitude
1
1
0
0
1
1
1
1
0
1
9 BIT DAC Command Data
0
0
0
0
Dither Amplitude
0
0
0
Dither Frequency
0
0
0
0
9 BIT DAC Command Data
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 25. SPI Commands
Command Name
CCD2 Control
Control Address
Command Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
CCD2
Retry
X
X
X
Dither Amplitude
Dither Frequency
CCD2 Frequency & Amplitude
1
1
0
0
1
1
X
X
X
0
0
0
0
0
0
0
TLIM Query Command
1
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
TLim Query Response(27)
0
0
0
0
0
0
0
OSS0
0
1=TLIM Fault on:
Calibration Error, Freq. high:
Calibration Error, Freq. low:
VPWR Over-voltage
0
0
0
0
0
0
0
0
CCD1 OSS7 OSS6 OSS5 OSS4 OSS3 OSS2 OSS1
1
1
1
UNUSED COMMANDS
Invalid Command
1
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
Invalid Command
1
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
Notes
26. 1 = VPWR Over-Voltage and 0 = Ok
27. 1 = 0 = Ok
Table 26. Serial Output (SO) Response Register
Next SO Response (Message 1)
0 = No Fault, 1 = Fault
OvrVlt, Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault
or
Status Status Status Status Status Status Status Status Status Status Status Status Status Status
TLim
PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
Fault
Next SO Response (Message 2)
0 = No Fault, 1 = Fault
OvrVlt, Reset Trim VCAL Open Short Open Short Fault Fault Fault Fault Fault Fault Fault Fault
or
Set(28) Status Fault Fault Fault Fault Status Status Status Status Status Status Status Status
TLim
int=0 CCD2 CCD2 CCD1 CCD1 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
Fault
ext=1
Notes
28. Trim Set bit indicates (0 = untrimmed, 1 = trimmed)
33800
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
Output OFF Open Load Fault
Output Voltage Shutdown
An Output OFF Open Load Fault is the detection and
reporting of an open load when the corresponding output is
disabled (input bit programmed to a logic low state). The
Output OFF Open Load Fault is detected by comparing the
drain-to-source voltage of the specific MOSFET output to an
internally generated reference. Each output has one
dedicated comparator for this purpose.
Each output has an internal pull-down current source or
resistor. The pull-down current sources are enabled on
power-up and must be enabled for Open Load Detect to
function. In cases were the Open Load Detect current is
disabled, the status bit will always respond with logic 0. The
device will only shut down the pull-down current in Sleep
Mode or when disabled via the SPI.
During output switching, especially with capacitive loads,
a false Output OFF Open Load Fault may be triggered. To
prevent this false fault from being reported, an internal fault
filter of 100µs to 450µs is incorporated. The duration for
which a false fault may be reported is a function of the load
impedance, RDS(ON), COUT of the MOSFET, as well as the
supply voltage, VPWR. The rising edge of CS triggers the builtin fault delay timer. The timer must time out before the fault
comparator is enabled to detect a faulted threshold. Once the
condition causing the Open Load Fault is removed, the
device resumes normal operation. The Open Load Fault,
however, will be latched in the output SO Response register
for the MCU to read.
An over voltage condition on VDD (> 7.0) may result in
permanent damage to the 33800. Over-voltage on the VPWR
pin will cause the 33800 to shut down until the voltage returns
to a normal value. Over voltage exceeding the maximum
recommended voltage (45V) may cause permanent damage
to the 33800.
Under-voltage Shutdown
An under-voltage condition on VDD results in the global
shutdown of all outputs and reset of all control registers. The
under-voltage threshold is between 0.8 and 2.8V.
An under-voltage condition on VPWR also results in the
global shutdown of all outputs and reset of all control
registers. The under-voltage threshold is between 3.0 and
4.4V
Low-voltage condition (4.4V< VPWR <9.0V) will operate
per the command word, however status reported on SO pin
is not guaranteed and performance may be out of
specification limits.
Output Voltage Clamp
Each output of the 33800 incorporates an internal voltage
clamp to provide fast turn-OFF and transient protection of
each output. Each clamp independently limits the drain-tosource voltage to 50V. The total energy clamped (EJ) can be
calculated by multiplying the current area under the current
curve (IA) times the clamp voltage (VCL) (see Figure 10).
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.3A, indicates the maximum
energy to be 50mJ at 150°C junction temperature per output.
.
Drain-to-Source C lamp
Drain-to-Source
Voltage (V CL =Clamp
45
V)
50V)
Voltage (VCL = 50V)
Drain
DrainVoltage
Voltage
Clamp
Energy
Clamp
Energy
(E(E
J = I=
A Ix V
x CL
V) )
DrainCurrent
Current
Drain
0.3 A)
(I(IDD==0.3A)
Drain-to-Source ON
Drain-to-Source
ON
Voltage (V
(O N) )
Voltage
(VDS
DS(ON))
GND
GND
J
A
Curren t
Area (IA )
CL
Time
Time
Figure 10. Output Voltage Clamping
Reverse Battery Protection
The 33800 device requires external reverse battery
protection on the VPWR pin.
All outputs consist of a power MOSFET with an integral
substrate diode. During reverse battery condition, current will
flow through the load via the substrate diode. Under this
circumstance relays may energize and lamps will turn on. If
load reverse battery protection is desired, a diode must be
placed in series with the load.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
EK (Pb-FREE) SUFFIX
54-PIN SOICW EXPOSED PAD
98ASA99334D
ISSUE C
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
EK (Pb-FREE) SUFFIX
54-PIN SOIC EXPOSED PAD
98ASA99334D
ISSUE C
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Analog Integrated Circuit Device Data
Freescale Semiconductor
37
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
1.0
7/2006
• Initial Release
2.0
8/2006
• Updated format and style
3.0
7/2007
4.0
8/2007
5.0
10/2007
• Changed Part Number PC33800EK/R2 to MCZ33800EK/R2 in Ordering Information.
• Changed Category from Product Preview to Advance Information.
• Changed Octal Serial Driver, Output Refresh Timer, minimum value from “-” to 2.0ms on
page 12
• Added paragraph for PWM Frequency/Duty Cycle Command on page 23
• Revised Table 12, OSS SPI Commands and Response on page 25
• Revised Table 26, SPI Commands on page 31
33800
38
Analog Integrated Circuit Device Data
Freescale Semiconductor
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MC33800
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