DG406/883, DG407/883 TM Single 16-Channel/Differential 8-Channel CMOS Analog Multiplexers April 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • ON-Resistance 100Ω (Max) • Low Power Consumption (PD <1.2mW) • Fast Transition Time (300ns Max) • Low Charge Injection • TTL, CMOS Compatible • Single or Split Supply Operation The DG406/883 and DG407/883 monolithic CMOS analog multiplexers are drop-in replacements for the popular DG506A/883 and DG507A/883 series devices. They each include an array of sixteen analog switches, a TTL and CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplexers are present. Applications • • • • • • These multiplexers feature lower signal ON resistance (<100Ω) and faster transition time (tTRANS <250ns) compared to the DG506A/883 and DG507A/883. Charge injection has been reduced, simplifying sample and hold applications. Battery Operated Systems Data Acquisition Medical Instrumentation Hi-Rel Systems Communication Systems Automatic Test Equipment The improvements in the DG406 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 30VP-P signals when operating with ±15V power supplies. Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. DG406AK/883 -55 to 125 28 Ld CERDIP F28.6 DG407AK/883 -55 to 125 28 Ld CERDIP F28.6 The sixteen switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. Pinouts DG406/883 (CERDIP) TOP VIEW DG407/883 (CERDIP) TOP VIEW V+ 1 28 D V+ 1 28 DA NC 2 27 V- DB 2 27 V- NC 3 26 S8 NC 3 26 S8A S16 4 25 S7 S8B 4 25 S7A S15 5 24 S6 S7B 5 24 S6A S14 6 23 S5 S6B 6 23 S5A S13 7 22 S4 S5B 7 22 S4A S12 8 21 S3 S4B 8 21 S3A S11 9 20 S2 S3B 9 20 S2A S10 10 19 S1 S2B 10 19 S1A S9 11 18 EN S1B 11 18 EN GND 12 17 A0 GND 12 17 A0 NC 13 16 A1 NC 13 16 A1 A3 14 15 A2 NC 14 15 A2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 Spec Number 512041-883 FN3720.1 DG406/883, DG407/883 Functional Block Diagrams DG406 DG407 S1A S1 S2A S2 S3A S3 S4A S4 S5A S5 S6A S6 S7A S7 S8A S8 D S9 S1B S10 S2B S11 S3B S12 S4B S13 S5B S14 S6B S15 S7B S16 S8B TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING ADDRESS DECODER 1 OF 16 A0 A1 A2 DA DB TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING ADDRESS DECODER 1 OF 8 ENABLE A3 EN A0 DG406 TRUTH TABLE A1 ENABLE A2 EN DG407 TRUTH TABLE A3 A2 A1 A0 EN ON SWITCH A2 A1 A0 EN ON SWITCH PAIR X X X X 0 None X X X 0 None 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 2 0 0 1 1 2 0 0 1 0 1 3 0 1 0 1 3 0 0 1 1 1 4 0 1 1 1 4 0 1 0 0 1 5 1 0 0 1 5 0 1 0 1 1 6 1 0 1 1 6 0 1 1 0 1 7 1 1 0 1 7 0 1 1 1 1 8 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 Logic “0” = V AL < 0.8V Logic “1” = V AH > 2.4V X = Don’t Care Spec Number 2 512041-883 DG406/883, DG407/883 Absolute Maximum Ratings Thermal Information Voltages Referenced to VV+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44.0V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Digital Inputs, VS , VD (Note 1) . . . . . . (V-) -2V to (V+) +2V or 20mA, Whichever Occurs First Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA (Pulsed 1ms, 10% Duty Cycle Max) Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 55 12 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on SX , D X or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +VSUPPLY = +15V, -VSUPPLY = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified PARAMETER Drain-Source ON Resistance Matching Between Channels Source OFF Leakage Current Drain OFF Leakage Current SYMBOL rDS(ON) CONDITIONS VD = 10V, IS = -10mA VD = -10V, IS = 10mA (Note 4) ∆rDS(ON) rDS(ON) Max - rDS(ON) Min (Note 3) IS(OFF) ID(OFF) DG406 VEN = 0V, VS = ±10V, VD = +10V VEN = 0V, VS = ±10V, VD = +10V GROUP A SUBGROUP DEVICE TYPE (NOTE 3) MIN (NOTE 3) MAX UNITS 1, 3 All - 90 Ω 2 All - 120 Ω 1 All - 15 Ω 1 All -0.5 0.5 nA 2, 3 All -50 50 nA 1 DG406 -1 1 nA -200 200 nA -1 1 nA -100 100 nA -1 1 nA -200 200 nA -1 1 nA -100 100 nA 2, 3 DG407 1 DG407 2, 3 Drain ON Leakage Current ID(ON) DG406 VS = VD = ±10V Sequence Each Switch ON (Note 4) 1 DG406 2, 3 DG407 1 DG407 2, 3 Logic High Input Current IAH VA = 2.4V, 15V 1, 2, 3 All -1 1 µA Logic Low Input Current IAL VEN = 0V, 2.4V, VA = 0V 1, 2, 3 All -1 1 µA Positive Supply Current ICC VEN = 2.4V, VA = 0V 1 All - 100 µA 2, 3 All - 500 µA 1 All -1 - µA 2, 3 All -10 - µA Negative Supply Current IEE Spec Number 3 512041-883 DG406/883, DG407/883 TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +VSUPPLY = +15V, -VSUPPLY = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified (Continued) PARAMETER Positive Standby Current Negative Standby Current SYMBOL ICC Standby CONDITIONS VEN = VA = 0V or 5V IEE Standby GROUP A SUBGROUP DEVICE TYPE (NOTE 3) MIN (NOTE 3) MAX UNITS 1 All - 30 µA 2, 3 All - 75 µA 1 All -1 - µA 2, 3 All -10 - µA NOTES: 3. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 4. Room = 25oC, Cold and Hot = as determined by the operating temperature suffix. TABLE 1A. ELECTRICAL PERFORMANCE SPECIFICATIONS (SINGLE SUPPLY) Devices tested at +VSUPPLY = +12V, -VSUPPLY = 0V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified PARAMETER Drain-Source ON Resistance Positive Current Negative Current SYMBOL rDS(ON) ICC GROUP A SUBGROUP DEVICE TYPE MIN MAX UNITS VD = 3V, 10V IS = -1mA 1 All - 120 Ω VEN = 0V or 5V, VA = 0V or 5V 1 All - 30 µA 2, 3 All - 75 µA 1 All -1 - µA 2, 3 All -5 - µA CONDITIONS IEE Switching Time of Multiplexer tTRANS VS1 = 8V, VSS - 0V, VIN = 2.4V 1 All - 450 ns Enable Turn-ON Time tON(EN) 1 All - 600 ns Enable Turn-OFF Time tOFF(EN) VINH = 2.4V, VINL = 0V, VS1 = 5V 1 All - 300 ns TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +VSUPPLY = +15V, -VSUPPLY = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified PARAMETER Transition Time Enable Turn-ON Time Enable Turn-OFF Time Break Before Leakage Current SYMBOL tTRANS tON(EN) CONDITIONS CL = 35pF, RL = 300Ω, See Figure 1 CL = 35pF, RL = 300Ω, See Figure 2 tOFF(EN) tOPEN CL = 35pF, RL = 300Ω, See Figure 3 GROUP A SUBGROUP DEVICE TYPE MIN MAX UNITS 9 All - 300 ns 10, 11 All - 400 ns 9 All - 200 ns 10, 11 All - 400 ns 9 All - 150 ns 10, 11 All - 300 ns 9 All 25 - ns 10, 11 All 10 - ns Spec Number 4 512041-883 DG406/883, DG407/883 TABLE 3. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +VSUPPLY = +15V, -VSUPPLY = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified PARAMETER SYMBOL CONDITIONS NOTE TEMP (oC) MIN TYP MAX UNITS Off Isolation Time VISO VEN = 0V, RL = 1K, f = 100kHz, GEN = 1VP-P Sine Wave, See Figure 5 5 25 50 - - dB Charge Transfer Error V CTE CL = 10nF, VS = 0V, RS = 0Ω, See Figure 4 5 25 - - 10 mV V CT RL = 1K, f = 100kHz, GEN = 1VP-P Sine Wave, See Figure 5 5 25 50 - - dB Source OFF Capacitance CS(OFF) VEN = 0V, VS = 0V, f = 1MHz 65 25 - - 10 pF Drain OFF Capacitance CD(OFF) VEN = 0V, VD = 0V, f = 1MHz DG406 5 25 - - 200 pF DG407 5 25 - - 100 pF DG406 5 25 - - 400 pF DG407 5 25 - - 200 pF Crosstalk Drain ON Capacitance CD(ON) VEN = 0V, VD = 0V, f = 1MHz NOTE: 5. Parameters listed via process parameters and are not directly tested at final production. These parameters are lab characterized upon design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production rich reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 AND 2) Interim Electrical Parameters (Pre Burn0In) 1 Final Electrical Test Parameters 1 (Note 6), 2, 3, 9, 10, 11 Group A Test Requirements 1, 2, 3, 9, 10, 11 Group C and D Endpoints 1 NOTE: 6. PDA applied to Subgroup 1 only. Spec Number 5 512041-883 DG406/883, DG407/883 Test Circuits and Waveforms +15V EN A3 A2 A1 V+ ±10V S1 +2.4V S2 - S15 A0 GND V- 10V A1 50Ω 300Ω DG407 10V S8B DB V- 50Ω 35pF ±10V S1B † A0 GND VO D V+ EN A2 DG406 S 16 ± +2.4V ± +15V VO 300Ω 35pF -15V -15V † = S1A - S8A , S2B - S7B , DA FIGURE 1A. FIGURE 1B. tr < 20ns tf < 20ns 3V LOGIC INPUT 50% 0V SWITCH OUTPUT VO 50% VS1B 80% 0V 80% VS8B tTRANS S1 ON tTRANS S8 ON FIGURE 1C. FIGURE 1. TRANSITION TIME +15V +15V A3 A2 A1 V+ A1 S2 - S16 A0 DG406 A0 EN GND V- 50Ω V+ A2 -5V S1 D DG407 50Ω 35pF GND -5V † EN VO 300Ω S1B V- DB VO 300Ω 35pF -15V -15V † = S1A - S8A , S2B - S8B , DA FIGURE 2A. LOGIC INPUT FIGURE 2B. tr < 20ns tf < 20ns 3V 50% 50% 0V tON(EN) tOFF(EN) 0V SWITCH OUTPUT VO 90% VO FIGURE 2C. Spec Number 6 512041-883 DG406/883, DG407/883 Test Circuits and Waveforms (Continued) FIGURE 2. ENABLE SWITCHING TIME +15V +2.4V EN A3 tr < 20ns tf < 20ns 3V LOGIC INPUT V+ ALL S AND DA +5V DG406 DG407 A1 D, A0 GND V- DB A2 50Ω SWITCH OUTPUT VO VO 300Ω 50% 0V 35pF VD 80% 0V tOPEN -15V FIGURE 3A. FIGURE 3B. FIGURE 3. BREAK-BEFORE-MAKE INTERVAL +15V SX V+ LOGIC INPUT EN VGEN = 0-3V A0 A1 DG406 DG407 D A3 GND OFF OFF ON 0V VO CL 10nF A2 3V SWITCH OUTPUT V- ∆VO -15V 5V FIGURE 4. CHARGE INJECTION +15V +15V SX1 VS RG = 50Ω VGEN = 1VP-P V+ SX16 A0 DG406 DG407 A1 S1 SX2 VS 1kΩ D A2 A3 GND EN V- -15V OFF ISOLATION = 20LOG 1VP-P VO RG = 50Ω RL 1kΩ V+ SX16 A0 DG406 DG407 A1 D VO RL 1kΩ A2 A3 GND EN V- -15V VOUT CROSSTALK = 20LOG VIN FIGURE 5. OFF ISOLATION VOUT VIN FIGURE 6. CROSSTALK Spec Number 7 512041-883 DG406/883, DG407/883 Burn-In Circuit CERDIP BURN-IN SCHEMATIC DG406/407AK/883 1 +V +15V C1 D1 R1 +5V OUT/OUTA 28 2 NC/OUT B -15V -V 27 3 NC IN 8/8A 26 4 IN 16/8B IN 7/7A 25 5 IN 15/7B IN 6/6A 24 6 IN 14/6B IN 5/5A 23 7 IN 13/5B IN 4/4A 22 8 IN 12/4B IN 3/3A 21 9 IN 11/3B IN 2/2A 20 10 IN 10/2B IN 1/1A 19 11 IN 9/1B EN 18 12 GND A0 17 13 VREF A1 16 14 A3/NC A2 15 R2 D2 C2 NOTE: R1, R2 = 10kΩ ±5%, 1/2W or 1/4W (Per Socket) C1, C2 = 0.01µF (Min, Per Socket) or 0.1µF (Min, Per Row) D1, D2 = IN402 (or Equivalent, Per Board) Schematic Diagram (Typical Channel) V+ GND VREF D A0 V+ LEVEL SHIFT AX DECODE/ DRIVE V- S1 V+ EN SN V- Spec Number 8 512041-883 DG406/883, DG407/883 Typical Design Information The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design information only. No guarantee is implied. 160 80 140 70 rDS(ON), ON-RESISTANCE (Ω) rDS(ON) , ON RESISTANCE (Ω) Typical Performance Curves 120 ±5V 100 80 60 40 20 0 -20 ±8V ±10V ±12V ±15V ±20V -16 -12 -8 -4 0 4 8 VD , DRAIN VOLTAGE (V) 12 16 60 30 -40 oC 20 -55oC ID , I S , CURRENT (pA) rDS(ON) , ON-RESISTANCE (Ω) 80 160 10V 120 12V 15V 20V 22V -10 -5 0 5 VD , DRAIN VOLTAGE (V) 10 15 V+ = 15V, V- = -15V VS = -VD FOR ID(OFF) VD = VS(OPEN) FOR ID(ON) 40 IS(OFF) 0 DG406 I D(ON), I D(OFF) -40 DG407 ID(ON), ID(OFF) -80 40 0 V+ = 15V V- = -15V 10 120 V+ = 7.5V 80 0oC FIGURE 8. rDS(ON) vs VD AND TEMPERATURE V- = 0V 200 25oC 40 FIGURE 7. rDS(ON) vs VD AND SUPPLY 240 85oC 50 0 -15 20 125oC 0 4 8 12 VD , DRAIN VOLTAGE (V) 16 -120 -15 20 FIGURE 9. rDS(ON) vs VD AND SUPPLY -10 -5 0 5 10 VS , VD , SOURCE DRAIN VOLTAGE (V) 15 FIGURE 10. ID , IS LEAKAGE CURRENTS vs ANALOG VOLTAGE Spec Number 9 512041-883 DG406/883, DG407/883 Typical Performance Curves 100nA 350 V+ = 15V, V- = -15V VS OR VD = ±10V 300 250 1nA TIME (ns) ID , IS , CURRENT (A) 10nA (Continued) I D(ON), ID(OFF) 100pA 10pA IS(OFF) 200 tON(EN) 150 100 1pA 0.1pA -55 tTRANS tOFF(EN) 50 -35 -15 5 25 45 65 85 105 0 125 5 10 15 VSUPPLY , SUPPLY VOLTAGE (±V) TEMPERATURE (oC) FIGURE 11. ID , IS LEAKAGE vs TEMPERATURE 20 FIGURE 12. SWITCHING TIMES vs BIPOLAR SUPPLIES 700 -140 600 -120 500 -100 ISOL (dB) TIME (ns) V- = 0V tTRANS 400 300 tON(EN) -60 -40 200 tOFF(EN) -20 100 0 -80 5 10 15 V+, SUPPLY VOLTAGE (V) 0 100 20 FIGURE 13. SWITCHING TIMES vs SINGLE SUPPLY 10 8 300 280 1M 10M V+ = 15V, V- = -15V 260 240 I+ 4 220 2 TIME (ns) I , CURRENT (mA) 10K 100K f, FREQUENCY (Hz) FIGURE 14. OFF-ISOLATION vs FREQUENCY EN = 5V, A X = 0V OR 5V 6 0 IGND -2 tTRANS 200 180 tON(EN) 160 140 -4 I- 120 -6 100 -8 -10 10 1K tOFF(EN) 80 100 1K 10K 100K 1M 60 -55 10M -35 -15 5 25 45 65 85 105 125 TEMPERATURE (oC) f, FREQUENCY (Hz) FIGURE 15. SUPPLY CURRENTS vs SWITCHING FREQUENCY FIGURE 16. tON /tOFF vs TEMPERATURE Spec Number 10 512041-883 DG406/883, DG407/883 Typical Performance Curves (Continued) 3 VA (V) 2 1 0 0 5 10 15 20 VSUPPLY , SUPPLY VOLTAGE (±V) FIGURE 17. SWITCHING THRESHOLD vs SUPPLY VOLTAGE Spec Number 11 512041-883 DG406/883, DG407/883 Die Characteristics DIE DIMENSIONS: PASSIVATION: 2490µm x 4560µm x 485µm ±25µm Type: Nitride Thickness: 8kÅ ±1kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: SiAl Thickness: 12kÅ ±1kÅ 9.1 x 104 A/cm2 Metallization Mask Layout DG406/883 NC V+ D V- S16 S8 S15 S7 S14 S6 S13 S5 S12 S4 S11 S3 S10 S2 S9 S1 GND A3 A2 A1 A0 EN Die Characteristics DIE DIMENSIONS: 2490µm x 4560µm x 485µm ±25µm Spec Number 12 512041-883 DG406/883, DG407/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) -D- -A- M (b) -B- SECTION A-A D S D BASE PLANE -C- SEATING PLANE Q A L S1 α eA A A b2 e b ccc M (c) b1 M C A-B S INCHES BASE METAL E bbb S F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 C A-B S eA/2 c aaa M C A - B S D S D S SYMBOL MIN MAX MIN MAX NOTES A - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.490 E 0.500 0.610 37.85 5 15.49 5 e 0.100 BSC 2.54 BSC - 0.600 BSC 15.24 BSC - 7.62 BSC - L 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 12.70 eA eA/2 NOTES: MILLIMETERS 0.300 BSC 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. α 90o aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. N 28 28 8 Rev. 0 4/94 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite 100 Irvine, CA 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7946 EUROPE Intersil Europe Sarl Ave. William Graisse, 3 1006 Lausanne Switzerland TEL: +41 21 6140560 FAX: +41 21 6140579 ASIA Intersil Corporation Unit 1804 18/F Guangdong Water Building 83 Austin Road TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433 Spec Number 13 512041-883