Data Sheet

PCA8565A
Real-time clock/calendar
Rev. 3 — 1 September 2014
Product data sheet
1. General description
The PCA8565A is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low
power consumption. A programmable clock output, interrupt output, and voltage-low
detector are also provided. All addresses and data are transferred serially via a two-line
bidirectional I2C-bus. Maximum bus speed is 400 kbit/s. The built-in word address register
is incremented automatically after each written or read data byte.
For a selection of NXP Real-Time Clocks, see Table 37 on page 39
2. Features and benefits
 AEC-Q100 compliant for automotive applications
 Provides year, month, day, weekday, hours, minutes, and seconds based on
32.768 kHz quartz crystal
 Clock operating voltage: 1.8 V to 5.5 V
 Extended operating temperature range: 40 C to +125 C
 Low backup current: typical 0.65 A at VDD = 3.0 V and Tamb = 25 C
 400 kHz two-line I2C-bus interface (at VDD = 1.8 V to 5.5 V)
 Programmable clock output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz, and
1 Hz)
 Alarm and timer functions
 Two integrated oscillator capacitors
 Internal Power-On Reset (POR)
 I2C-bus slave address: read A3h; write A2h
 Open-drain interrupt pin
3. Applications
 Automotive
 Industrial
 Applications that require a wide operating temperature range
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.
PCA8565A
NXP Semiconductors
Real-time clock/calendar
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
PCA8565AU
Description
Version
wire bond die 9 bonding pads
PCA8565AU
4.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCA8565AU/5BB/1
PCA8565AU/5BB/1,01
unsawn wafer; thickness 280 m
1
935289264015
5. Marking
Table 3.
PCA8565A
Product data sheet
Marking codes
Type number
Marking code
PCA8565AU/5BB/1
PC8565A-1
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Rev. 3 — 1 September 2014
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
6. Block diagram
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Block diagram of PCA8565A
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
7. Pinning information
7.1 Pinning
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Viewed from active side. For mechanical details, see Figure 24.
Fig 2.
Pin configuration for PCA8565A
7.2 Pin description
Table 4.
Pin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol
Product data sheet
Description
OSCI
1
oscillator input
OSCO
2
oscillator output
INT
3
interrupt output (open-drain; active LOW)
VSS
4
ground supply voltage[1]
SDA
5
serial data input and output
SCL
6
serial clock input
CLKOUT
7
clock output (open-drain)
VDD
8
supply voltage
CLKOE
9
CLKOUT output enable input
[1]
PCA8565A
Pin
The substrate (rear side of the die) is wired to VSS but should not be electrically contacted.
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Rev. 3 — 1 September 2014
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
8. Functional description
The PCA8565A contains 16 8-bit registers with an auto-incrementing address register, an
on-chip 32.768 kHz oscillator with two integrated capacitors, a frequency divider which
provides the source clock for the RTC, a programmable clock output, a timer, an alarm, a
voltage low detector, and a 400 kHz I2C-bus interface.
All 16 registers (see Table 5) are designed as addressable 8-bit parallel registers although
not all bits are implemented. The first two registers (memory address 00h and 01h) are
used as control and/or status registers. The memory addresses 02h through 08h are used
as counters for the clock function (seconds up to years counters). Address locations 09h
through 0Ch contain alarm registers which define the conditions for an alarm.
Address 0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the timer control
and timer registers, respectively.
The seconds, minutes, hours, days, weekdays, months, years, as well as the minute
alarm, hour alarm, day alarm, and weekday alarm registers are all in Binary Coded
Decimal (BCD) format.
When one of the RTC registers is written or read, the contents of all time counters are
frozen. Therefore, faulty writing or reading of the clock and calendar during a carry
condition is prevented.
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
8.1 Register organization
Table 5.
Register overview
Bit positions labelled as - are not implemented. Bit positions labelled as N should always be written with logic 0. After reset, all
registers are set according to Table 8.
Address
Register name
Bit
7
6
5
4
3
2
1
0
Control registers
00h
Control_status_1
TEST1
N
STOP
N
TESTC
N
N
N
01h
Control_status_2
N
N
N
TI_TP
AF
TF
AIE
TIE
-
WEEKDAYS (0 to 6)
Time and date registers
02h
VL_seconds
VL
SECONDS (0 to 59)
03h
Minutes
-
MINUTES (0 to 59)
04h
Hours
-
-
HOURS (0 to 23)
05h
Days
-
-
DAYS (1 to 31)
06h
Weekdays
-
-
-
-
07h
Century_months
C
-
-
MONTH (1 to 12)
08h
Years
YEARS (0 to 99)
Alarm registers
09h
Minute_alarm
AE_M
MINUTE_ALARM (0 to 59)
0Ah
Hour_alarm
AE_H
-
HOUR_ALARM (0 to 23)
0Bh
Day_alarm
AE_D
-
DAY_ALARM (1 to 31)
0Ch
Weekday_alarm
AE_W
-
-
-
-
WEEKDAY_ALARM (0 to 6)
-
-
-
-
-
-
FD
-
-
-
-
-
TD
CLKOUT control register
0Dh
CLKOUT_control
Timer registers
0Eh
Timer_control
TE
0Fh
Timer
TIMER
PCA8565A
Product data sheet
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
8.2 Control registers
8.2.1 Register Control_status_1
Table 6.
Bit
7
Control_status_1 - control and status register 1 (address 00h) bit description
Symbol
Value
Description
Reference
TEST1
0[1]
normal mode;
Section 8.10
1
EXT_CLK test mode
N
0[2]
default value
-
STOP
0[1]
RTC clock runs
Section 8.11
1
RTC clock is stopped;
must be set logic 0 during normal operations
6
5
all RTC divider chain flip-flops are asynchronously set logic 0;
the RTC clock is stopped (CLKOUT at 32.768 kHz is still available);
I2C-bus watchdog doesn’t work
4
N
0[2]
default value
3
TESTC
0
Power-On Reset (POR) override facility is disabled;
Section 8.3.1
set logic 0 for normal operation
2 to 0
N
1[1]
Power-On Reset (POR) override is enabled
000[2]
default value
-
[1]
Default value.
[2]
Bits labeled as N should always be written with logic 0.
8.2.2 Register Control_status_2
Table 7.
Bit
Control_status_2 - control and status register 2 (address 01h) bit description
Symbol
Value
Description
7 to 5
N
000[1]
default value
4
TI_TP
0[2]
1
INT active when TF or AF is active (subject to the status of TIE and AIE) Section 8.9
and
INT pulses active according to Table 29 (subject to the status of TIE);
Section 8.7
Remark: if AF and AIE are active then INT will be permanently active
0[2]
read: alarm flag inactive
3
AF
Reference
Section 8.9
write: alarm flag is cleared
1
read: alarm flag active
write: alarm flag remains unchanged
2
TF
0[2]
read: timer flag inactive
Section 8.9
write: timer flag is cleared
1
read: timer flag active
write: timer flag remains unchanged
1
AIE
0
TIE
0[2]
alarm interrupt disabled
1
alarm interrupt enabled
0[2]
timer interrupt disabled
1
timer interrupt enabled
[1]
Bits labeled as N should always be written with logic 0.
[2]
Default value.
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
Section 8.9
Section 8.9
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
8.3 Reset
The PCA8565A includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I2C-bus logic is initialized including the address pointer and
all registers are set according to Table 8. I2C-bus communication is not possible during
reset.
Table 8.
Register reset values[1]
Address
Register name
Bit
7
6
5
4
3
2
1
0
00h
Control_status_1
0
0
0
0
1
0
0
0
01h
Control_status_2
0
0
0
0
0
0
0
0
02h
VL_seconds
1
x
x
x
x
x
x
x
03h
Minutes
x
x
x
x
x
x
x
x
04h
Hours
x
x
x
x
x
x
x
x
05h
Days
x
x
x
x
x
x
x
x
06h
Weekdays
x
x
x
x
x
x
x
x
07h
Century_months
x
x
x
x
x
x
x
x
08h
Years
x
x
x
x
x
x
x
x
09h
Minute_alarm
1
x
x
x
x
x
x
x
0Ah
Hour_alarm
1
x
x
x
x
x
x
x
0Bh
Day_alarm
1
x
x
x
x
x
x
x
0Ch
Weekday_alarm
1
x
x
x
x
x
x
x
0Dh
CLKOUT_control
x
x
x
x
x
x
0
0
0Eh
Timer_control
0
x
x
x
x
x
1
1
0Fh
Timer
x
x
x
x
x
x
x
x
[1]
Registers marked ‘x’ are undefined at power-up and unchanged by subsequent resets.
8.3.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this
mode requires that the I2C-bus pins, SDA and SCL, be toggled in a specific order as
shown in Figure 3. All timings are required minimums.
Once the override mode has been entered, the device immediately stops, being reset,
and normal operation may commence, i.e., entry into the EXT_CLK test mode via I2C-bus
access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be
set logic 1 before re-entry into the override mode is possible. Setting TESTC logic 0
during normal operation has no effect, except to prevent entry into the POR override
mode.
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
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POR override sequence
8.4 Time and date registers
The majority of the registers are coded in the BCD format to simplify application use.
8.4.1 Register VL_seconds
Table 9.
Bit
Symbol
Value
Place value Description
7
VL
0
-
clock integrity is guaranteed
1[1]
-
integrity of the clock information is not guaranteed
6 to 4 SECONDS 0 to 5
ten’s place
actual seconds coded in BCD format, see Table 10
3 to 0
unit place
[1]
0 to 9
Start-up value.
Table 10.
8.4.1.1
VL_seconds - seconds and clock integrity status register (address 02h) bit
description
Seconds coded in BCD format
Seconds value in
decimal
Upper-digit (ten’s place)
Digit (unit place)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
0
0
0
0
0
0
0
01
0
0
0
0
0
0
1
02
0
0
0
0
0
1
0
:
:
:
:
:
:
:
:
09
0
0
0
1
0
0
1
10
0
0
1
0
0
0
0
:
:
:
:
:
:
:
:
58
1
0
1
1
0
0
0
59
1
0
1
1
0
0
1
Voltage-low detector and clock monitor
The PCA8565A has an on-chip voltage-low detector (see Figure 4). When VDD drops
below Vlow, bit VL in the VL_seconds register is set to indicate that the integrity of the
clock information is no longer guaranteed. The VL flag can only be cleared by command.
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
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Voltage-low detection
The VL flag is intended to detect the situation when VDD is decreasing slowly, for example
under battery operation. Should the oscillator stop or VDD reach Vlow before power is
re-asserted, then the VL flag is set. This will indicate that the time may be corrupted.
8.4.2 Register Minutes
Table 11.
Minutes - minutes register (address 03h) bit description
Bit
Symbol
Value
Place value Description
7
-
-
-
unused
6 to 4 MINUTES
0 to 5
ten’s place
actual minutes coded in BCD format
3 to 0
0 to 9
unit place
8.4.3 Register Hours
Table 12.
Bit
Hours - hours register (address 04h) bit description
Symbol
Value
Place value Description
7 to 6 -
-
-
unused
5 to 4 HOURS
0 to 2
ten’s place
actual hours coded in BCD format
3 to 0
0 to 9
unit place
8.4.4 Register Days
Table 13.
Bit
Value
Place value Description
7 to 6 -
-
-
unused
5 to 4 DAYS[1]
0 to 3
ten’s place
actual day coded in BCD format
3 to 0
0 to 9
unit place
[1]
PCA8565A
Product data sheet
Days - days register (address 05h) bit description
Symbol
The PCA8565A compensates for leap years by adding a 29th day to February if the year counter contains a
value which is exactly divisible by 4, including the year 00.
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
8.4.5 Register Weekdays
Table 14.
Bit
Weekdays - weekdays register (address 06h) bit description
Symbol
Value
Description
7 to 3 -
-
unused
2 to 0 WEEKDAYS
0 to 6
actual weekday values, see Table 15.
Table 15.
Weekday assignments
Day[1]
Bit
2
1
0
Sunday
0
0
0
Monday
0
0
1
Tuesday
0
1
0
Wednesday
0
1
1
Thursday
1
0
0
Friday
1
0
1
Saturday
1
1
0
[1]
Definition may be re-assigned by the user.
8.4.6 Register Century_months
Table 16.
Symbol
Value
Place value Description
7
C[1]
0[2]
-
indicates the century is x
1
-
indicates the century is x + 1
6 to 5 -
-
-
unused
4
0 to 1
ten’s place
actual month coded in BCD format, see Table 17
0 to 9
unit place
MONTHS
3 to 0
PCA8565A
Product data sheet
Century_months - century flag and months register (address 07h) bit description
Bit
[1]
This bit may be re-assigned by the user.
[2]
This bit is toggled when the register Years overflows from 99 to 00.
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
Table 17.
Month assignments in BCD format
Month
Upper-digit
(ten’s place)
Digit (unit place)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
January
0
0
0
0
1
February
0
0
0
1
0
March
0
0
0
1
1
April
0
0
1
0
0
May
0
0
1
0
1
June
0
0
1
1
0
July
0
0
1
1
1
August
0
1
0
0
0
September
0
1
0
0
1
October
1
0
0
0
0
November
1
0
0
0
1
December
1
0
0
1
0
8.4.7 Register Years
Table 18.
Bit
PCA8565A
Product data sheet
Years - years register (08h) bit description
Symbol
Value
Place value Description
7 to 4 YEARS
0 to 9
ten’s place
3 to 0
0 to 9
unit place
actual year coded in BCD format
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Rev. 3 — 1 September 2014
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
8.5 Setting and reading the time
Figure 5 shows the data flow and data dependencies starting from the 1 Hz clock tick.
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Data flow for the time function
During read/write operations, the time counting circuits (memory locations 02h through
08h) are blocked.
This prevents
• Faulty reading of the clock and calendar during a carry condition
• Incrementing the time registers, during the read cycle
After this read/write access is completed, the time circuit is released again and any
pending request to increment the time counters that occurred during the read access is
serviced. A maximum of 1 request can be stored; therefore, all accesses must be
completed within 1 second (see Figure 6).
As a consequence of this method, it is very important to make a read or write access in
one go, that is, setting or reading seconds through to years should be made in one single
access. Failing to comply with this method could result in the time becoming corrupted.
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Fig 6.
PCA8565A
Product data sheet
Access time for read/write operations
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PCA8565A
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Real-time clock/calendar
As an example, if the time (seconds through to hours) is set in one access and then in a
second access the date is set, it is possible that the time may increment between the two
accesses. A similar problem exists when reading. A roll over may occur between reads
thus giving the minutes from one moment and the hours from the next.
Recommended method for reading the time:
1. Send a START condition and the slave address for write (A2h).
2. Set the address pointer to 2 (VL_seconds) by sending 02h.
3. Send a RESTART condition or STOP followed by START.
4. Send the slave address for read (A3h).
5. Read VL_seconds.
6. Read Minutes.
7. Read Hours.
8. Read Days.
9. Read Weekdays.
10. Read Century_months.
11. Read Years.
12. Send a STOP condition.
8.6 Alarm registers
When one or more of the alarm registers are loaded with a valid minute, hour, day or
weekday and its corresponding bit alarm enable (AE_x) is logic 0, then that information is
compared with the actual minute, hour, day and weekday.
When all enabled comparisons first match, the Alarm Flag (AF) is set. AF will remain set
until cleared by command. Once AF has been cleared it is only set again when the
time increments to match the alarm condition once more. (For clearing the AF, see
Section 8.9.1.1 on page 19.)
Alarm registers which have their bit AE_x at logic 1 are ignored.
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
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PCA8565A
NXP Semiconductors
Real-time clock/calendar
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(1) Only when all enabled alarm settings are matching.
It’s only on increment to a matched case that the alarm is set, see Section 8.9.1.1.
Fig 7.
Alarm function block diagram
8.6.1 Register Minute_alarm
Table 19.
Minute_alarm - minute alarm register (address 09h) bit description
Bit
Symbol
Value
Place value Description
7
AE_M
0
-
minute alarm is enabled
1[1]
-
minute alarm is disabled
6 to 4 MINUTE_ALARM
0 to 5
ten’s place
3 to 0
0 to 9
unit place
minute alarm information coded in BCD
format
[1]
Default value.
8.6.2 Register Hour_alarm
Table 20.
Bit
Symbol
Value
Place value Description
7
AE_H
0
-
hour alarm is enabled
1[1]
-
hour alarm is disabled
-
-
unused
5 to 4 HOUR_ALARM
0 to 2
ten’s place
3 to 0
0 to 9
unit place
hour alarm information coded in BCD
format
6
[1]
PCA8565A
Product data sheet
Hour_alarm - hour alarm register (address 0Ah) bit description
-
Default value.
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Real-time clock/calendar
8.6.3 Register Day_alarm
Table 21.
Day_alarm - day alarm register (address 0Bh) bit description
Bit
Symbol
Value
Place value Description
7
AE_D
0
-
day alarm is enabled
1[1]
-
day alarm is disabled
-
-
unused
5 to 4 DAY_ALARM
0 to 3
ten’s place
3 to 0
0 to 9
unit place
day alarm information coded in BCD
format
6
[1]
-
Default value.
8.6.4 Register Weekday_alarm
Table 22.
Weekday_alarm - weekday alarm register (address 0Ch) bit description
Bit
Symbol
Value
Description
7
AE_W
0
weekday alarm is enabled
1[1]
weekday alarm is disabled
-
unused
6 to 3 -
2 to 0 WEEKDAY_ALARM 0 to 6
[1]
weekday alarm information coded in BCD format
Default value.
8.7 Timer function
The 8-bit countdown timer at address 0Fh is controlled by the timer control register at
address 0Eh. The timer control register determines one of 4 source clock frequencies for
the timer (4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz) and enables or disables the timer. The timer
counts down from a software-loaded 8-bit binary value. At the end of every countdown,
the timer sets the Timer Flag (TF) in the register Control_status_2. The TF may only be
cleared by command. The asserted TF can be used to generate an interrupt (on pin INT).
The interrupt may be generated as a pulsed signal every countdown period or as a
permanently active signal which follows the state of TF. Bit TI_TP is used to control this
mode selection. When reading the timer, the current countdown value is returned.
8.7.1 Register Timer_control
The timer register is an 8-bit binary countdown timer. It is enabled and disabled via the
bit TE in register Timer_control. The source clock for the timer is also selected by the
TD[1:0] in register Timer_control. Other timer properties such as interrupt generation are
controlled via register Control_2.
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Table 23.
Bit
7
Timer_control - timer control register (address 0Eh) bit description
Symbol
Value
Description
TE
0[1]
timer is disabled
1
timer is enabled
-
unused
6 to 2 -
timer source clock frequency select[2]
1 to 0 TD[1:0]
00
4.096 kHz
01
64 Hz
10
1 Hz
11[2]
1⁄
60
Hz
[1]
Default value.
[2]
These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to
1⁄ Hz for power saving.
60
8.7.2 Register Timer
Table 24.
Bit
Timer - timer register (address 0Fh) bit description
Symbol
Value
7 to 0 TIMER[7:0]
Description
00h to FFh countdown period in seconds:
n
CountdownPeriod = -------------------------------------------------------------SourceClockFrequency
where n is the countdown value
Table 25.
Timer register bits value range
Bit
7
6
5
4
3
2
1
0
128
64
32
16
8
4
2
1
The timer register is an 8-bit binary countdown timer. It is enabled or disabled via the
Timer_control register. The source clock for the timer is also selected by the Timer_control
register. Other timer properties such as single or periodic interrupt generation are
controlled via the register Control_status_2 (address 01h).
For accurate read back of the count down value, it is recommended to read the register
twice and check for consistent results, since it is not possible to freeze the countdown
timer counter during read back.
8.8 Register CLKOUT_control and clock output
A programmable square wave is available at the CLKOUT pin. Frequencies of
32.768 kHz, 1.024 kHz, 32 Hz and 1 Hz can be generated for use as a system clock,
microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT
is an open-drain output, and if disabled it becomes high-impedance.
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Table 26.
Bit
CLKOUT_control - CLKOUT control register (address 0Dh) bit description
Symbol
7 to 2 -
Value
Description
-
unused
1 to 0 FD[1:0]
[1]
frequency output at pin CLKOUT
00[1]
32.768 kHz
01
1.024 kHz
10
32 Hz
11
1 Hz
Default value.
8.9 Interrupt output
8.9.1 Bits TF and AF
When an alarm occurs, AF is set to 1. Similarly, at the end of a timer countdown, TF is
set to 1. These bits maintain their value until overwritten by command. If both timer and
alarm interrupts are required in the application, the source of the interrupt is determined
by reading these bits.
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Example where only the minute alarm is used and no other interrupts are enabled.
Fig 8.
PCA8565A
Product data sheet
AF timing
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When bits TIE and AIE are disabled, pin INT will remain high-impedance.
Fig 9.
Interrupt scheme
8.9.1.1
Clearing the alarm flag (AF)
Table 28 shows an example for clearing bit AF but leaving bit TF unaffected. Clearing the
flags is made by a write command; therefore bits 7, 6, 4, 1 and 0 must be written with their
previous values. Repeatedly re-writing these bits has no influence on the functional
behavior.
To prevent the timer flags being overwritten while clearing AF, a logical AND is performed
during a write access. Writing a logic 1 will cause the flag to maintain its value, whereas
writing a logic 0 will cause the flag to be reset.
Table 27.
Register
Control_2
Flag location in register Control_2
Bit
7
6
5
4
3
2
1
0
-
-
-
-
AF
TF
-
-
The following table shows what instruction must be sent to clear bit AF. In this example bit
TF is unaffected.
Table 28.
Register
Control_2
Example to clear only AF (bit 3) in register Control_2
Bit
7
6
5
4
3
2
1
0
-
-
-
-
0
1
-
-
8.9.2 Bits TIE and AIE
These bits activate or deactivate the generation of an interrupt when TF or AF is
asserted, respectively. The interrupt is the logical OR of these two conditions when both
AIE and TIE are set.
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8.9.3 Countdown timer interrupts
The pulse generator for the countdown timer interrupt uses an internal clock and is
dependent on the selected source clock for the countdown timer and on the countdown
value n. As a consequence, the width of the interrupt pulse varies (see Table 29).
Table 29.
INT operation (bit TI_TP = 1)[1]
Source clock (Hz)
INT period (s)
n = 1[2]
n > 1[2]
4096
1⁄
8192
1⁄
4096
64
1⁄
128
1⁄
64
1
1⁄
64
1⁄
64
1⁄
60
1⁄
64
1⁄
64
[1]
TF and INT become active simultaneously.
[2]
n = loaded countdown value. Timer stops when n = 0.
8.10 External clock (EXT_CLK) test mode
A test mode is available which allows for on-board testing. In such a mode it is possible to
set up test conditions and control the operation of the RTC.
The test mode is entered by setting bit TEST1 in register Control_status_1. Then
pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal with the
signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then
generate an increment of one second.
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a
maximum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is
divided down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into
a known state by using the bit STOP. When the STOP bit is set, the prescaler is reset to
logic 0 (STOP must be cleared before the prescaler can operate again).
From a STOP condition, the first 1 second increment will take place after 32 positive
edges on pin CLKOUT. Thereafter, every 64 positive edges will cause a one-second
increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.
When entering the test mode, no assumption as to the state of the prescaler can be made.
Operation example:
1. Set EXT_CLK test mode (Control_status_1, bit TEST1 = 1).
2. Set bit STOP (Control_status_1, bit STOP = 1).
3. Clear bit STOP (Control_status_1, bit STOP = 0).
4. Set time registers to desired value.
5. Apply 32 clock pulses to pin CLKOUT.
6. Read time registers to see the first change.
7. Apply 64 clock pulses to pin CLKOUT.
8. Read time registers to see the second change.
Repeat steps 7 and 8 for additional increments.
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8.11 STOP bit function
The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP
bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and
thus no 1 Hz ticks will be generated (see Figure 10). The time circuits can then be set and
will not increment until the STOP bit is released (see Figure 11 and Table 30).
)
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Fig 10. STOP bit functional diagram
The STOP bit function will not affect the output of 32.768 kHz on CLKOUT, but will stop
the generation of 1.024 kHz, 32 Hz, and 1 Hz.
The lower two stages of the prescaler (F0 and F1) are not reset; and because the I2C-bus
is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be
between zero and one 8.192 kHz cycle (see Figure 11).
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Fig 11. STOP bit release timing
PCA8565A
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Table 30.
First increment of time circuits after STOP bit release
Bit
Prescaler bits
STOP
F0F1-F2 to F14
[1]
1 Hz tick
Time
Comment
hh:mm:ss
Clock is running normally
0
12:45:12
01-0 0001 1101 0100
prescaler counting normally
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally
1
XX-0 0000 0000 0000
12:45:12
prescaler is reset; time circuits are frozen
08:00:00
prescaler is reset; time circuits are frozen
08:00:00
prescaler is now running
08:00:00
-
08:00:00
-
08:00:00
-
:
:
New time is set by user
1
XX-0 0000 0000 0000
STOP bit is released by user
0
XX-1 0000 0000 0000
XX-0 1000 0000 0000
XX-1 1000 0000 0000
:
WRV
XX-0 0000 0000 0000
-
08:00:01
0 to 1 transition of F14 increments the time circuits
10-0 0000 0000 0001
08:00:01
-
:
:
:
08:00:01
-
08:00:01
-
10-0 0000 0000 0000
08:00:01
-
:
:
-
11-1 1111 1111 1110
08:00:01
-
00-0 0000 0000 0001
08:00:02
0 to 1 transition of F14 increments the time circuits
11-1 1111 1111 1111
00-0 0000 0000 0000
V
08:00:00
00-0 0000 0000 0001
11-1 1111 1111 1110
DDD
[1]
F0 is clocked at 32.768 kHz.
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP
bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset
(see Table 30) and the unknown state of the 32 kHz clock.
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9. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial Data Line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse, as changes in the data line at this time
will be interpreted as a control signal (see Figure 12).
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Fig 12. Bit transfer
9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the
STOP condition (P); see Figure 13.
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Fig 13. Definition of START and STOP conditions
9.3 System configuration
A device generating a message is a transmitter; a device receiving a message is a
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see Figure 14).
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Real-time clock/calendar
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Fig 14. System configuration
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 15.
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Fig 15. Acknowledgement on the I2C-bus
PCA8565A
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9.5 I2C-bus protocol
9.5.1 Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the start procedure.
The PCA8565A acts as a slave receiver or slave transmitter. Therefore, the clock signal
SCL is only an input signal, but the data signal SDA is a bidirectional line.
Two slave addresses are reserved for the PCA8565A:
Read: A3h (10100011)
Write: A2h (10100010)
The PCA8565A slave address is shown in Figure 16.
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Fig 16. Slave address
9.5.2 Clock and calendar READ or WRITE cycles
The I2C-bus configuration for the different PCA8565A READ and WRITE cycles is shown
in Figure 17, Figure 18, and Figure 19. The word address is a 4-bit value that defines
which register is to be accessed next. The upper four bits of the word address are not
used.
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Fig 17. Master transmits to slave receiver (WRITE mode)
PCA8565A
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Real-time clock/calendar
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(1) At this moment master transmitter becomes master receiver and PCA8565A slave receiver becomes slave transmitter.
Fig 18. Master reads after setting word address (write word address; READ data)
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Fig 19. Master reads slave immediately after first byte (READ mode)
9.5.3 Interface watchdog timer
During read/write operations, the time counting circuits are frozen. To prevent a situation
where the accessing device becomes locked and does not clear the interface, the
PCA8565A has a built in watchdog timer. Should the interface be active for more than 1 s
from the time a valid slave address is transmitted, then the PCA8565A will automatically
clear the interface and allow the time counting circuits to continue counting.
The watchdog is implemented to prevent the excessive loss of time due to interface
access failure e.g. if main power is removed from a battery backed-up system during an
interface access.
Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The
watchdog will trigger between 1 s and 2 s after receiving a valid slave address.
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Real-time clock/calendar
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b. Incorrect data transfer: read or write
Fig 20. Interface watchdog timer
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
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Real-time clock/calendar
10. Internal circuitry
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Fig 21. Device diode protection
11. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
PCA8565A
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12. Limiting values
Table 31. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Max
Unit
supply voltage
0.5
+6.5
V
IDD
supply current
50
+50
mA
ISS
ground supply current
50
+50
mA
VI
input voltage
0.5
+6.5
V
VO
output voltage
0.5
+6.5
V
II
input current
10
+10
mA
IO
output current
10
+10
mA
Ptot
total power dissipation
Ilu
Tstg
Product data sheet
Min
VDD
VESD
PCA8565A
Conditions
-
300
mW
electrostatic discharge
voltage
HBM
[1]
-
3000
V
MM
[2]
-
250
V
latch-up current
all pins but OSCI
[3]
-
100
mA
[4]
65
+150
C
storage temperature
[1]
Pass level; Human Body Model (HBM) according to Ref. 4 “JESD22-A114”.
[2]
Pass level; Machine Model (MM), according to Ref. 5 “JESD22-A115”.
[3]
Pass level; latch-up testing, according to Ref. 7 “JESD78” at maximum ambient temperature
(Tamb(max) = +125 C).
[4]
According to the store and transport requirements (see Ref. 11 “UM10569”) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.
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13. Static characteristics
Table 32. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +125 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise
specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
I2C-bus active; fSCL = 400 kHz
1.8
-
5.5
V
for clock data integrity
Vlow
-
5.5
V
-
100
250
A
-
25
100
A
VDD = 5.0 V
-
1100
1800
nA
VDD = 3.0 V
-
1000
1600
nA
VDD = 2.0 V
-
950
1500
nA
VDD = 5.0 V
-
850
1500
nA
VDD = 3.0 V
-
775
1300
nA
VDD = 2.0 V
-
750
1200
nA
VDD = 5.0 V
-
600
1200
nA
VDD = 3.0 V
-
550
1000
nA
VDD = 2.0 V
-
550
900
nA
VDD = 5.0 V
-
600
1200
nA
VDD = 3.0 V
-
550
1000
nA
VDD = 2.0 V
-
550
900
nA
VDD = 5.0 V
-
850
1500
nA
VDD = 3.0 V
-
775
1300
nA
VDD = 2.0 V
-
750
1200
nA
-
550
-
nA
Supplies
VDD
IDD
supply voltage
supply current
interface active;
Tamb = 40 C to +125 C
fSCL = 400 kHz
fSCL = 100 kHz
interface inactive (fSCL = 0 Hz);
CLKOUT = VDD
[1][2]
Tamb = 125 C
Tamb = 105 C
Tamb = 85 C
Tamb = 25 C
Tamb = 40 C
Tamb = 40 C to +85 C
VDD = 1.8 V
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Table 32. Static characteristics …continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +125 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise
specified.
Symbol Parameter
IDD
supply current
Conditions
Min
Typ
Max
Unit
VDD = 5.0 V
-
1300
2500
nA
VDD = 3.0 V
-
1100
1900
nA
VDD = 2.0 V
-
1000
1700
nA
VDD = 5.0 V
-
1100
2200
nA
VDD = 3.0 V
-
900
1600
nA
VDD = 2.0 V
-
800
1400
nA
VDD = 5.0 V
-
900
1900
nA
VDD = 3.0 V
-
700
1300
nA
VDD = 2.0 V
-
600
1100
nA
VDD = 5.0 V
-
900
1900
nA
VDD = 3.0 V
-
700
1300
nA
VDD = 2.0 V
-
600
1100
nA
VDD = 5.0 V
-
1100
2200
nA
VDD = 3.0 V
-
900
1600
nA
VDD = 2.0 V
-
800
1400
nA
VSS  0.3
-
0.3VDD
V
0.7VDD
-
-
V
1
0
+1
A
-
-
7
pF
pin SDA
3
-
-
mA
pin INT
1
-
-
mA
1
-
-
mA
1
0
+1
A
interface inactive (fSCL = 0 Hz);
CLKOUT enabled at 32 kHz
[1][2]
Tamb = 125 C
Tamb = 105 C
Tamb = 85 C
Tamb = 25 C
Tamb = 40 C
Inputs
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
pins SCL, SDA, CLKOE, OSCI
ILI
input leakage current
pins SCL, SDA; VI = VDD or VSS
Ci
input capacitance
[3]
Outputs
LOW-level output current
IOL
output sink current;
VOL = 0.4 V; VDD = 5 V
pin CLKOUT; VO = VDD or VSS
output leakage current
ILO
Voltage detector and temperature
Vlow
low voltage
-
0.9
1.7
V
Tamb
ambient temperature
40
-
+125
C
[1]
Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.
[2]
Worst case is at high temperature and high supply voltage.
[3]
Tested on sample basis.
PCA8565A
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14. Dynamic characteristics
Table 33. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to + 125 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless
otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
6
8
10
pF
-
0.2
-
ppm
[2]
-
50
-
%
[5]
-
-
400
kHz
0.6
-
-
s
Oscillator
CL(itg)
[1]
integrated load capacitance
VDD = 200 mV; Tamb = 25 C
fosc/fosc relative oscillator frequency variation
CLKOUT output
CLKOUT
duty cycle on pin CLKOUT
Timing characteristics: I2C-bus[3][4]
fSCL
SCL clock frequency
tHD;STA
hold time (repeated) START condition
tSU;STA
set-up time for a repeated START condition
0.6
-
-
s
tLOW
LOW period of the SCL clock
1.3
-
-
s
tHIGH
HIGH period of the SCL clock
0.6
-
-
s
tr
rise time
of SCL and SDA signals
-
-
0.3
s
of SCL and SDA signals
tf
fall time
-
-
0.3
s
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP condition
0.6
-
-
s
tw(spike)
spike pulse width
Cb
capacitive load for each bus line
[1]
[2]
tolerable
-
-
50
ns
-
-
400
pF
 C OSCI  C OSCO 
Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: C L  itg  = -------------------------------------------- .
 C OSCI + C OSCO 
Unspecified for fCLKOUT = 32.768 kHz.
[3]
All timing values are valid within the operating supply voltage range at ambient temperature and referenced to VIL and VIH with an input
voltage swing of VSS to VDD.
[4]
A detailed description of the I2C-bus specification is given in Ref. 9 “UM10204”.
[5]
I2C-bus access time between two starts or between a start and a stop condition to this device must be less than one second.
PCA8565A
Product data sheet
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6'$
W%8)
W/2:
WI
6&/
W+'67$
WU
W+''$7
W68'$7
W+,*+
6'$
W6867$
W68672
PJD
Fig 22. I2C-bus timing waveforms
15. Application information
9''
6'$
)
Q)
6&/
9''
0$67(5
75$160,77(5
5(&(,9(5
6&/
&/2&.&$/(1'$5
26&,
3&$$
26&2
966
9''
6'$
5
6'$ 6&/
,&EXV
5
DDE
Connect CLKOE to an appropriate level.
Fig 23. Application diagram
PCA8565A
Product data sheet
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16. Test information
16.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
PCA8565A
Product data sheet
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17. Bare die outline
:LUHERQGGLHERQGLQJSDGV
3&$$8
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H
$
H
\
H
(
[
;
3
3
3
3
GHWDLO;
PP
VFDOH
1RWH
0DUNLQJFRGH3&$
SFDDXBGR
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YHUVLRQ
5HIHUHQFHV
,(&
-('(&
-(,7$
(XURSHDQ
SURMHFWLRQ
,VVXHGDWH
3&$$8
Fig 24. Bare die outline
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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Table 34. Dimensions of PCA8565AU
Original dimensions are in mm.Chip dimensions including sawline.
Unit (mm)
A
D
E
e
e1
e2
P1
P2
P3
P4
max
-
-
-
-
-
-
-
-
-
-
nom
0.28
1.26
1.89
1.05
0.22
0.9
0.1
0.09
0.1
0.09
min
-
-
-
-
-
-
-
-
-
-
Table 35. Pin description
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip; see Figure 24.
Symbol
Pad
X
Y
OSCI
1
523.0 m
689.4 m
OSCO
2
523.0 m
469.4 m
INT
3
523.0 m
429.8 m
VSS
4
523.0 m
684.4 m
SDA
5
524.9 m
523.8 m
SCL
6
524.9 m
138.6 m
CLKOUT
7
524.9 m
162.5 m
VDD
8
524.9 m
443.3 m
CLKOE
9
524.9 m
716.3 m
5()
5()
&
&
5()
DDD
)
Fig 25. Alignment marks
Table 36. Alignment mark description
All x/y coordinates represent the position of the REF point (see Figure 25) with respect to the center
(x/y = 0) of the chip; see Figure 24.
PCA8565A
Product data sheet
Symbol
Size (m)
X
Y
C1
100  100
465.2 m
826.3 m
C2
100  100
523.5 m
890.0 m
F
90  117
569.9 m
885.5 m
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18. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
19. Packing information
19.1 Wafer information
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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—P
—P
—P
6DZODQH
6HDOULQJSOXVJDSWR
DFWLYHFLUFXLWa—P
—P
GHWDLO;
0DUNLQJFRGH
3LQ
6WUDLJKWHGJH
RIWKHZDIHU
;
DDD
Bad die are inked out.
Fig 26. Wafer layout
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
38 of 47
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCA8565A
Product data sheet
20. Appendix
20.1 Real-Time Clock selection
Table 37.
Selection of Real-Time Clocks
Type name
Alarm, Timer, Interrupt Interface IDD,
Battery Timestamp,
Watchdog
output
typical (nA) backup tamper input
AEC-Q100
compliant
Special features
Packages
PCF8563
X
1
I2C
250
-
-
-
-
SO8, TSSOP8,
HVSON10
PCF8564A
X
1
I2C
250
-
-
-
integrated oscillator caps
WLCSP
600
-
-
grade 1
high robustness,
Tamb40 C to 125 C
TSSOP8, HVSON10
Rev. 3 — 1 September 2014
All information provided in this document is subject to legal disclaimers.
PCA8565
X
1
I2C
PCA8565A
X
1
I2C
600
-
-
-
integrated oscillator caps,
Tamb40 C to 125 C
WLCSP
PCF85063
-
1
I2C
220
-
-
-
basic functions only, no
alarm
HXSON8
PCF85063A
X
1
I2C
220
-
-
-
tiny package
SO8, DFN2626-10
PCF85063B
X
1
SPI
220
-
-
-
tiny package
DFN2626-10
230
X
X
-
time stamp, battery
backup, stopwatch 1⁄100 s
SO8, TSSOP10,
TSSOP8,
DFN2626-10
2
PCF85263B
X
2
SPI
230
X
X
-
time stamp, battery
backup, stopwatch 1⁄100s
TSSOP10,
DFN2626-10
PCF85363A
X
2
I2C
230
X
X
-
time stamp, battery
backup, stopwatch 1⁄100s,
64 Byte RAM
TSSOP10,
DFN2626-10
PCF85363B
X
2
SPI
230
X
X
-
time stamp, battery
backup, stopwatch 1⁄100s,
64 Byte RAM
TSSOP10,
DFN2626-10
PCF8523
X
2
I2C
150
X
-
-
lowest power 150 nA in
operation, FM+ 1 MHz
SO8, HVSON8,
TSSOP14, WLCSP
PCF2123
X
1
SPI
100
-
-
-
lowest power 100 nA in
operation
TSSOP14, HVQFN16
PCF2127
X
1
I2C and
SPI
500
X
X
-
temperature
SO16
compensated, quartz built
in, calibrated, 512 Byte
RAM
PCA8565A
X
Real-time clock/calendar
39 of 47
© NXP Semiconductors N.V. 2014. All rights reserved.
PCF85263A
I2C
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Selection of Real-Time Clocks …continued
Rev. 3 — 1 September 2014
All information provided in this document is subject to legal disclaimers.
Type name
Alarm, Timer, Interrupt Interface IDD,
Battery Timestamp,
Watchdog
output
typical (nA) backup tamper input
AEC-Q100
compliant
Special features
PCF2127A
X
1
I2C and
SPI
500
X
X
-
temperature
SO20
compensated, quartz built
in, calibrated, 512 Byte
RAM
PCF2129
X
1
I2C and
SPI
500
X
X
-
temperature
SO16
compensated, quartz built
in, calibrated
PCF2129A
X
1
I2C and
SPI
500
X
X
-
temperature
SO20
compensated, quartz built
in, calibrated
PCA2129
X
1
I2C and
SPI
500
X
X
grade 3
temperature
SO16
compensated, quartz built
in, calibrated
PCA21125
X
1
SPI
820
-
-
grade 1
high robustness,
Tamb40 C to 125 C
NXP Semiconductors
PCA8565A
Product data sheet
Table 37.
Packages
TSSOP14
PCA8565A
Real-time clock/calendar
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Real-time clock/calendar
21. Abbreviations
Table 38.
Acronym
Abbreviations
Description
AEC
Automotive Electronics Council
BCD
Binary Coded Decimal
CMOS
Complementary Metal Oxide Semiconductor
HBM
Human Body Model
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
MM
Machine Model
MOS
Metal Oxide Semiconductor
MSB
Most Significant Bit
POR
Power-On Reset
RTC
Real Time Clock
SCL
Serial CLock line
SDA
Serial Data Line
22. References
[1]
AN10706 — Handling bare die
[2]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[3]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[4]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[5]
JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[6]
JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[7]
JESD78 — IC Latch-Up Test
[8]
JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[9]
UM10204 — I2C-bus specification and user manual
[10] UM10301 — User Manual for NXP Real Time Clocks PCF85x3, PCA8565 and
PCF2123, PCA2125
[11] UM10569 — Store and transport requirements
PCA8565A
Product data sheet
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Rev. 3 — 1 September 2014
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23. Revision history
Table 39.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA8565A v.3
20140901
Product data sheet
-
PCA8565A v.2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Removed obsolete product type
PCA8565A v.2
20091204
Product data sheet
-
PCA8565A v.1
PCA8565A v.1
20080222
Product data sheet
-
-
PCA8565A
Product data sheet
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24. Legal information
24.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
24.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
24.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA8565A
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 September 2014
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
24.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
25. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA8565A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
44 of 47
PCA8565A
NXP Semiconductors
Real-time clock/calendar
26. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Register overview . . . . . . . . . . . . . . . . . . . . . . . .6
Control_status_1 - control and status register 1
(address 00h) bit description . . . . . . . . . . . . . . .7
Control_status_2 - control and status register 2
(address 01h) bit description . . . . . . . . . . . . . . .7
Register reset values[1] . . . . . . . . . . . . . . . . . . .8
VL_seconds - seconds and clock integrity status
register (address 02h) bit description . . . . . . . .9
Seconds coded in BCD format . . . . . . . . . . . . .9
Minutes - minutes register (address 03h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .10
Hours - hours register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .10
Days - days register (address 05h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .10
Weekdays - weekdays register (address 06h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 11
Weekday assignments . . . . . . . . . . . . . . . . . . . 11
Century_months - century flag and months
register (address 07h) bit description . . . . . . . . 11
Month assignments in BCD format . . . . . . . . .12
Years - years register (08h) bit description . . . .12
Minute_alarm - minute alarm register
(address 09h) bit description . . . . . . . . . . . . . .15
Hour_alarm - hour alarm register
(address 0Ah) bit description . . . . . . . . . . . . . .15
Day_alarm - day alarm register (address 0Bh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .16
Weekday_alarm - weekday alarm register
(address 0Ch) bit description . . . . . . . . . . . . . .16
Timer_control - timer control register
(address 0Eh) bit description . . . . . . . . . . . . . .17
Timer - timer register (address 0Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Timer register bits value range . . . . . . . . . . . . .17
CLKOUT_control - CLKOUT control register
(address 0Dh) bit description . . . . . . . . . . . . . .18
Flag location in register Control_2 . . . . . . . . . .19
Example to clear only AF (bit 3) in register
Control_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
INT operation (bit TI_TP = 1)[1] . . . . . . . . . . . . .20
First increment of time circuits after STOP
bit release . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .29
Static characteristics . . . . . . . . . . . . . . . . . . . .30
Dynamic characteristics . . . . . . . . . . . . . . . . . .32
Dimensions of PCA8565AU . . . . . . . . . . . . . .36
Pin description . . . . . . . . . . . . . . . . . . . . . . . . .36
Alignment mark description . . . . . . . . . . . . . . .36
Selection of Real-Time Clocks . . . . . . . . . . . . .39
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .41
Revision history . . . . . . . . . . . . . . . . . . . . . . . .42
PCA8565A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
45 of 47
PCA8565A
NXP Semiconductors
Real-time clock/calendar
27. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Block diagram of PCA8565A . . . . . . . . . . . . . . . . .3
Pin configuration for PCA8565A . . . . . . . . . . . . . .4
POR override sequence . . . . . . . . . . . . . . . . . . . .9
Voltage-low detection. . . . . . . . . . . . . . . . . . . . . .10
Data flow for the time function . . . . . . . . . . . . . . .13
Access time for read/write operations . . . . . . . . .13
Alarm function block diagram. . . . . . . . . . . . . . . .15
AF timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . .19
STOP bit functional diagram . . . . . . . . . . . . . . . .21
STOP bit release timing . . . . . . . . . . . . . . . . . . . .21
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Definition of START and STOP conditions. . . . . .23
System configuration . . . . . . . . . . . . . . . . . . . . . .24
Acknowledgement on the I2C-bus . . . . . . . . . . . .24
Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Master transmits to slave receiver
(WRITE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Master reads after setting word address
(write word address; READ data) . . . . . . . . . . . .26
Master reads slave immediately after first
byte (READ mode). . . . . . . . . . . . . . . . . . . . . . . .26
Interface watchdog timer . . . . . . . . . . . . . . . . . . .27
Device diode protection . . . . . . . . . . . . . . . . . . . .28
I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .33
Application diagram . . . . . . . . . . . . . . . . . . . . . . .33
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . . .35
Alignment marks . . . . . . . . . . . . . . . . . . . . . . . . .36
Wafer layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PCA8565A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
46 of 47
PCA8565A
NXP Semiconductors
Real-time clock/calendar
28. Contents
1
2
3
4
4.1
5
6
7
7.1
7.2
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.4
8.4.1
8.4.1.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.7
8.7.1
8.7.2
8.8
8.9
8.9.1
8.9.1.1
8.9.2
8.9.3
8.10
8.11
9
9.1
9.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Register organization . . . . . . . . . . . . . . . . . . . . 6
Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7
Register Control_status_1 . . . . . . . . . . . . . . . . 7
Register Control_status_2 . . . . . . . . . . . . . . . . 7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-On Reset (POR) override . . . . . . . . . . . 8
Time and date registers . . . . . . . . . . . . . . . . . . 9
Register VL_seconds . . . . . . . . . . . . . . . . . . . . 9
Voltage-low detector and clock monitor . . . . . . 9
Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 10
Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 10
Register Days . . . . . . . . . . . . . . . . . . . . . . . . . 10
Register Weekdays. . . . . . . . . . . . . . . . . . . . . 11
Register Century_months . . . . . . . . . . . . . . . . 11
Register Years . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting and reading the time. . . . . . . . . . . . . . 13
Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Minute_alarm . . . . . . . . . . . . . . . . . . 15
Register Hour_alarm . . . . . . . . . . . . . . . . . . . 15
Register Day_alarm . . . . . . . . . . . . . . . . . . . . 16
Register Weekday_alarm . . . . . . . . . . . . . . . . 16
Timer function . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register Timer_control . . . . . . . . . . . . . . . . . . 16
Register Timer . . . . . . . . . . . . . . . . . . . . . . . . 17
Register CLKOUT_control and clock output. . 17
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 18
Bits TF and AF . . . . . . . . . . . . . . . . . . . . . . . . 18
Clearing the alarm flag (AF) . . . . . . . . . . . . . . 19
Bits TIE and AIE . . . . . . . . . . . . . . . . . . . . . . . 19
Countdown timer interrupts. . . . . . . . . . . . . . . 20
External clock (EXT_CLK) test mode . . . . . . . 20
STOP bit function . . . . . . . . . . . . . . . . . . . . . . 21
Characteristics of the I2C-bus . . . . . . . . . . . . 23
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
START and STOP conditions . . . . . . . . . . . . . 23
9.3
9.4
9.5
9.5.1
9.5.2
9.5.3
10
11
12
13
14
15
16
16.1
17
18
19
19.1
20
20.1
21
22
23
24
24.1
24.2
24.3
24.4
25
26
27
28
System configuration . . . . . . . . . . . . . . . . . . .
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . .
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and calendar READ or WRITE cycles .
Interface watchdog timer . . . . . . . . . . . . . . . .
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Quality information . . . . . . . . . . . . . . . . . . . . .
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Wafer information. . . . . . . . . . . . . . . . . . . . . .
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Clock selection . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
24
25
25
25
26
28
28
29
30
32
33
34
34
35
37
37
37
39
39
41
41
42
43
43
43
43
44
44
45
46
47
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 September 2014
Document identifier: PCA8565A