Application Notes

AN10853
ESD and EMC sensitivity of IC
Rev. 01 — 10 November 2010
Application note
Document information
Info
Content
Keywords
ESD, EMC
Abstract
This application note describes basics of the ESD and EMC sensitivity of
IC
AN10853
NXP Semiconductors
ESD and EMC sensitivity of IC
Revision history
Rev
Date
Description
01
20101110
initial release
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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1. Introduction
Integrated circuits are sensitive to electrostatic discharge (a sudden and short-time flow of
currents) and electromagnetic fields (at which they can be source or victim of both of it).
This application note shall be understood as an introductive basic description of
•
•
•
•
what electrostatic discharge is
how sensitive devices can be protected against electrostatic discharges
what electromagnetic compatibility means
and how electromagnetic sensitivity can be tested.
But by no means, this application note does not substitute any of the corresponding
engineering standards and standard operation procedures.
2. Electrostatic charging and discharging
ElectroStatic Discharge (ESD) is the transfer of an electrostatic charge between objects at
different electrical potentials and occurs with direct contact or when induced by an
electrostatic field. Many pins of NXP devices are protected against ESD up to a certain
level defined in the Quality and Reliability Specification (Ref. 12 “NX2-00001”). However,
we recommend that ESD precautions are complied with when handling such components.
2.1 Triboelectric charging and ESD events
Nearly all electrostatic discharges are caused by static or frictional electricity. This kind of
electricity is produced due to triboelectric charging, which means, that two materials which
came in contact with another are electrically charged while being separated (like through
rubbing) (see Figure 1).
013aaa390
Fig 1.
Triboelectric effect
This happens because the two materials being in contact with another are exchanging
electrons (Figure 2) to equalize their electrochemical potential. When separated, some
materials tend to give electrons away, whereas others tend to keep extra electrons. The
result is that both materials are on different electrical potentials. Friction increases the
possibility to exchange electrons because it enhances the contact surface of the two
materials.
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CONTACT
SEPARATION
-
-
++
+
-
-
++
++
-
-
-
-
++
++
++
+
-
-
-
+3
−3
0
+3
−2
+1
+4
−4
0
NO CHARGING
CHARGING
+4
−5
−1
013aaa391
Fig 2.
Exchange of electrons
The electrostatic attractive force of an electron and a proton seems to be marginal but it is
about 40 orders of magnitude stronger compared to the gravitational force interacting
between them.
Examples of triboelectric charging are:
•
•
•
•
Walking on a rug
Ascending from a fabric covered car seat
Combing dry hair with a plastic comb
Removing a plastic packing foil
An ESD event is the electrical discharge between two objects of different electrostatic
potential,
• like in thunderstorms between the water droplets in the cloud and the earth
(see Figure 3)
• touching a door handle after charging while walking on a rug (see Figure 4)
• during product assembling without sufficient ESD protection.
.
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The water droplets are rubbing
against each other producing
electrostatic charge
Discharge is done
by lightning
Hot air is moving up and
entraints water droplets
013aaa392
Fig 3.
Electrostatic charging and discharging in a thunderstorm
013aaa402
Fig 4.
Electrostatic discharging of a human body
2.1.1 ESD order of magnitude
Electrostatic charges can be stored in many things; for example, man-made fibre clothing,
moving machinery, objects with air blowing across them, plastic storage bins, sheets of
paper stored in plastic envelopes, paper from electrostatic copying machines, and people
(see Figure 5).
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Air blowing over table top
Plastic storage bins
Plastic table top
Nylon overall
plastic trays
Plastic envelopes
Nylon carpet or plastic flooring
013aaa153
Fig 5.
Dangerous environment for handling electronic components
The charges are caused by friction between two surfaces, where at least one is
non-conductive. The magnitude and polarity of the charges depend on the different
affinities for electrons of the two materials rubbing together, the friction force, and the
humidity of surrounding air (see Table 1).
Table 1.
Static generation
Means of static generation
walking across carpet
Humidity
Unit
10 % to 20 %
65 % to 90 %
35000
1500
V
walking over vinyl floor
12000
250
V
worker handling components at bench
6000
100
V
rubbing of vinyl sheet protectors
7000
600
V
lifting common poly bag from bench
20000
1200
V
sliding on chair padded with polyurethane foam
18000
1500
V
2.1.2 ESD sensitivity of ICs
The sensitivity of an IC depends to some extend on the product package:
• Packaged IC are very sensitive to ESD because they are single parts and peak
effects can occur on the pins.
• Bare die and sawn wafer are less sensitive than packaged IC because they are single
parts but charges are dissipated to the entire surface so peak effects on pins may not
occur.
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• Wafer are less sensitive than bare die and sawn wafer because charges are
dissipated to the entire surface of the wafer and therefore affecting all IC in the same
way. Peak effects on pins may not occur. Also, touching one single pin at packaged
parts is much easier than on bare die.
• Due to the constantly shrinking IC process technology, the silicon die are becoming
smaller and smaller. The smaller the geometry of the silicon die the lower is its ESD
robustness. Figure 6 shows the size of the IC area which is needed to get a 2 kV HBM
ESD protection compared to the chip size and the thickness of the gate oxide.
50 nm
IC area
Gate Oxide Thickness
Required IC area to achieve 2 kV HBM ESD protection
12.5 nm
Gate Oxide Thickness
8 nm
4.15 nm
1.5 μm
800 nm
350 nm
180 nm
3 nm
1.6 nm
140 nm
90 nm
<1.5 nm
65 nm
Process feature size
013aaa393
Fig 6.
AN10853
Application note
Required IC area to achieve 2 kV HBM ESD protection
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2.2 ESD protection
2.2.1 Electrostatic Protected Area (EPA): work area for handling
electrostatic-sensitive devices
Figure 7 shows a working area suitable for safely handling electrostatic-sensitive devices.
The surface of the workbench is conductive and anti-static. The floor should also be
covered with anti-static material.
E
AR
ING
DL D
AN
E
L H ORIZ NLY
IA
EC UTH EL O
SP
A
N
ON
RS
PE
A
Conductive
compartment Electrostatic
trays
voltage sensor
Cotton overall
Distribution
supply box
Safety
isolation
transformer
RC
CB
Conductive boots
or heel grounding
protectors
Supply
earth
Conductive
bench top
Conductive stool
≥ 100 kΩ
< 1 GΩ
Common
reference
point
Strap (resistance
between 0.5 MΩ and 10.0 MΩ)
≥ 10 kΩ
< 1 GΩ
Ground
Conductive floor mat
013aaa154
Fig 7.
AN10853
Application note
Essential features of an ESD-protected work area
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The following precautions should be observed:
• At the entrance of an Electrostatic Protected Area (EPA) the electrostatic conductivity
has to be checked (see Figure 8).
013aaa412
Fig 8.
ESD entrance control
• Entrance and exit of an EPA has to be labeled with warning signs (see Figure 9).
013aaa413
a. Entering ESD protected area
Fig 9.
013aaa414
b. Leaving ESD protected area
Warning signs of an Electrostatic Protected Area (EPA)
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• People at a workbench should be earthed via a wrist straps and a resistor (see
Figure 10).
013aaa403
Fig 10. Wrist strap
• Use gloves, protective footwear, and cotton garment (see Figure 11).
013aaa415
Fig 11. Protective clothes
• If needed, neutralized or reduced electrostatic fields to less than 1000 V with an
ionizer.
• All mains-powered equipment should be connected to the mains via an earth-leakage
switch.
• Equipment cases should be grounded.
• Relative humidity should be maintained between 45 % and 60 %.
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• Keep static materials, such as plastic envelopes and plastic trays etc., away from the
workbench. If there are any static materials on the workbench, remove them before
handling the semiconductor devices.
• Refer to the current version of Ref. 4 “IEC 61340-5”, that explains in more detail how
to arrange an ESD protective area for handling ESD sensitive devices.
2.2.2 Receipt and storage of components
Electrostatic-sensitive devices are packed for dispatch in anti-static/conductive
containers, usually boxes, tubes or blister tapes wrapped in a static shielding bag (see
Figure 12 and Figure 13).
013aaa404
Fig 12. Bare die in ESD protected tray
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013aaa433
Fig 13. Static shielding bag
Warning labels on both primary and secondary packing show that the contents are
sensitive to electrostatic discharge (see Figure 14 and Figure 15).
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ESD and EMC sensitivity of IC
013aaa405
Fig 14.
Warning label for an electrostatic sensitive device, denoting that the device is
susceptible to damage
013aaa394
Fig 15. Typical warning label of ESD sensitive devices
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Such devices should be kept in their original packing whilst in storage. If a bulk container
is partially unpacked, the unpacking should be done at a protected working area. Any
components that are stored temporarily should be packed in conductive or anti-static
packing or carriers. The environment humidity must be controlled and has to be between
45 % and 60 % of relative humidity otherwise a ionizer must be used.
2.2.3 PCB assembly
Electrostatic-sensitive devices must be removed from their protective packing with
grounded component-pincers or short-circuit clips. Short-circuit clips must remain in place
during mounting, soldering, cleaning and drying processes. Do not remove more
components from the storage packing than are needed at any one time. Production and
assembly documents should state that the product contains electrostatic sensitive devices
and that special precautions need to be taken. During assembly, ensure that the
electrostatic-sensitive devices are the last of the components to be mounted and that this
is done at a protected work area.
All tools used during assembly, including soldering tools and solder baths, must be
grounded. All hand-tools should be of conductive or anti-static material and, where
possible, should not be insulated.
2.2.4 Testing PCBs
Completed PCBs must be tested at a protected work area. Place the soldered side of the
circuit board on conductive or anti-static foam and remove the short-circuit clips. Remove
the circuit board from the foam, holding the board only at the edges. Make sure the circuit
board does not touch the conductive surface of the workbench. After testing, replace the
PCB on the conductive foam to await packing.
Assembled circuit boards containing electrostatic-sensitive devices should always be
handled in the same way as unmounted components. They should also carry warning
labels and be packed in conductive or anti-static packing.
2.2.5 Internal ESD protection circuits
Internal device protection diodes are connected to the pins to protect the IC against
destructive ElectroStatic Discharge (ESD) and load disconnection spikes. If an ESD event
occurs, the ESD protection circuits will shunt the charge in a controlled way, such that
neither the functional parts nor the shunt path will be damaged by the discharge.
The device protection diodes are designed such that they allow the assembling of the IC
but they are not sufficient to protect the assembled IC on the circuit board in any case.
Therefore additional device protection circuits in the application may be necessary.
ESD protection diagrams are typically shown as overview circuit diagrams or
particularized circuit diagrams (see Figure 16):
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VDD
VDD
V
DD
OSCI
VSS
SYNC, SA0, CLK,
OSC, A0 to A2
CLKOE
OSCO
SCL, SDA
VSS
CLKOUT
TEST
VLCD
SCL
INT
VSS
BP0 to BP3,
S0 to S59
SDI
VLCD
CE
VSS
SDO
VSS
VSS
013aaa160
013aaa159
a. Overview circuit diagram.
b. Particularized circuit diagram.
Fig 16. ESD protection circuit
Figure 17 shows typical internal device protection diode or transistor circuits of input and
output pins:
VLCDOUT
VDD or VLCD
VLCD
VSS
VSS1
VSS
013aaa165
013aaa161
mgu197
Fig 17. Protection of input and output pins (2 diodes/2 transistors)
Figure 18 shows internal device protection diode circuits of input and output pins but
allowing an external supply that is unrelated to the protection circuit:
VDD
VDD
INT
VSS
013aaa166
VSS
013aaa162
Fig 18. Protection of input and output pins with an unprotected external supply
Figure 19 shows the protection of supply rails where usually an ESD diode with a large
current flow capability is put across the supply rails:
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VDD or VLCD
VSS
013aaa163
Fig 19. Protection of supplies
2.2.6 Verification of ESD protection
The ESD protection is verified by applying a defined energy on the terminals or leads of
the IC. There are three models commonly in use:
2.2.6.1
Human Body Model (HBM)
It simulates the electrical charging and then discharging of a person via the protection
circuits.
The main criteria for this test is:
•
•
•
•
•
•
Each sample for the stress test has to consist of 3 devices
During the test, the devices don’t need to operate fully, but they must not be damaged
The test is performed at room temperature (25 C)
The test is made at different voltage levels (250 V, 500 V, 1000 V, 2000 V, 4000 V)
The rise time is specified to be in a range of 2 ns to 10 ns
The pulse duration is in a range of 100 ns to 200 ns
After each test at a certain voltage level, the stressed devices are tested according the
requirements used in the parametric and functional tests. A failure is, when a device
doesn’t pass the parametric and functional tests anymore (device is destructed); the pass
level indicates the highest voltage stress level after which all tested devices have still
passed the parametric and functional tests without false.
Larm
Rskin
Cbody
013aaa164
Rskin = 1500 , Cbody = 100 pF, Larm = 7.5 H.
Fig 20. Schematic HBM ESD test circuit
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S1
R1
C1
S2
100 pF
DUT
socket
R2
High
Voltage
Pulse
Generator
short
Terminal A
Terminal B
013aaa411
DUT: Device Under Test.
Fig 21. Typical equivalent HBM ESD test circuit
A human body can easily reach the voltages used in this test (see Table 1). The HBM
ESD test results are classified as shown in Table 2.
Table 2.
2.2.6.2
HBM ESD classification table
Class
Voltage range
0
< 250 V
1A
250 V to < 500 V
1B
500 V to < 1000 V
1C
1000 V to < 2000 V
2
2000 V to < 4000 V
3A
4000 V to < 8000 V
3B
 8000 V
Machine Model (MM)
It simulates abrupt discharges, which are caused by contact with charged equipment.
Therefore, the circuits are tested with rather moderate voltage, but with higher currents, as
could occur with coupling of energy spikes.
The main criteria for this test is:
•
•
•
•
•
The stress test has to be performed with 3 devices
During the test, the devices don’t need to operate fully, but they must not be damaged
The test is performed at room temperature (25 C)
The test is made at different voltage levels (100 V, 200 V, 400 V)
Each sample will be stressed at one voltage level using 1 positive and 1 negative
pulse with a minimum of 0.5 second between pulses per pin
• The test is made with defined oscillation frequency and defined positive current peaks
After each test at a certain voltage level, the stressed devices are tested according the
requirements used in the parametric and functional tests. A failure is, when a device does
not pass the parametric and functional tests anymore (device is destructed); the pass
level indicates the highest voltage stress level after which all tested devices have still
passed the parametric and functional tests without false.
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S1
C1
200 pF
S2
DUT
socket
R2
High
Voltage
Pulse
Generator
short
Terminal A
R1
Terminal B
013aaa167
DUT: Device Under Test.
Fig 22. Typical equivalent MM ESD test circuit
The MM ESD test results are classified as shown in Table 3.
Table 3.
2.2.6.3
MM ESD classification table
Class
Voltage range
M1
< 100 V
M2
100 V to < 200 V
M3
200 V to < 400 V
M4
 400 V
Charged-Device Model (CDM)
It models the discharge of a charged IC to a grounded surface.
The main criteria for this test is:
• The stress test has to be performed with 3 devices
• The test is performed at room temperature (25 C) with an ambient humidity of less or
equal 60 %
• The test is made at different voltage levels (100 V, 200 V, 500 V, 1000 V, 2000 V)
• Each sample will be stressed at one voltage level using 3 positive and 3 negative
discharges to each pin
After each test at a certain voltage level, the stressed devices are tested according the
requirements used in the parametric and functional tests. A failure is, when a device
doesn’t pass the parametric and functional tests anymore (device is destructed); the pass
level indicates the highest voltage stress level after which all tested devices have still
passed the parametric and functional tests without false.
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50 Ω semi-rigid
coaxial cable
top ground
plane
support arm
FR-4
radial 1Ω
resistor
pogo probe
device under
test
insulating
fixture
field-charging
electrode
300 MΩ charging
resistor
high voltage
power supply
001aak452
Fig 23. Field induced CDM simulator
The CDM ESD test results are classified as shown in Table 4.
Table 4.
2.2.6.4
CDM ESD classification table
Class
Voltage range
C1
< 125 V
C2
125 V to < 250 V
C3
250 V to < 500 V
C4
500 V to < 1000 V
C5
1000 V to < 1500 V
C6
1500 V to < 2000 V
C7
 2000 V
Latch-Up (LU) test
Latch-up is the transition of a semiconductor device in a low-impedance state which can
lead to a short circuit and may destroy the device or bring it into an undefined state from
which it can not be recovered other than switching the power supply off. The effect
compares to the function of a thyristor. An ESD or a voltage peak may be the root-cause
for generating such a large current. The latch-up test shows the quality of the protection of
the device.
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Latch-up tests are temperature sensitive. Therefore, there are two classes of latch-up
tests:
• Class I: testing at room temperature
• Class II: testing at
– maximum operating ambient temperature (Tamb(max))
or
– maximum operating case temperature (Tcase(max))
or
– maximum operating junction temperature (Tj(max))
In addition, there are two test methods:
• I-test (see testing circuit in Figure 24) where positive and negative current pulses are
supplied to the input or input/output pin under test
• Power supply pin overvoltage test (see testing circuit in Figure 25) where overvoltage
pulses are supplied to the supply pin under test
Trigger source
Isource
Pin under test
Vsupply
Vsupply
Ground
A
Isupply
measurment
013aaa189
Fig 24. Typical equivalent circuit for input and input/output latch-up testing
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Vsupply
A
Isupply
measurment
Vsupply
Ground
013aaa190
Fig 25. Typical equivalent circuit for supply overvoltage latch-up testing
The main criteria for this test is:
• Ground pins will not be latch-up tested
• The stress test has to be performed with 6 devices using the I-test and overvoltage
test
There are two pass levels:
• Pass level A: devices passed 1.4  Inom or Inom + 10 mA (whichever is greater) without
latching and passing the parametric and functional tests without false. The pass level
indicates the highest current stress level where all tested devices have passed.
• Pass level B: devices passed below the values of level A but above the product
maximum ratings and passing the parametric and functional tests without false. The
pass level indicates the highest current stress level where all tested devices have
passed.
A failure is, when a device neither passed level A nor level B.
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3. ElectroMagnetic Compatibility (EMC)
All electrical and electronic products, apparatus, appliances, equipment, and installations
marketed in countries of the European community must comply with a strict EMC
directive. The EMC directive itself does not contain any technical requirements or limits
but makes reference to generic or product-specific EMC requirements which will apply for
both RF emission as well as immunity.
In the EMC directive, the European community gives the following definitions:
Electromagnetic compatibility — means the ability of a device, unit of equipment or
system to function satisfactorily in its electromagnetic environment without introducing
intolerable electromagnetic disturbances to anything in that environment.
Electromagnetic disturbance — means any electromagnetic phenomenon which may
degrade the performance of a device, unit of equipment or system. An electromagnetic
disturbance may be electromagnetic noise, an unwanted signal or a change in the
propagation medium itself.
Immunity — means the ability of a device, unit of equipment or system to perform without
degradation of quality in the presence of an electromagnetic disturbance.
EMC differentiates between two different conditions:
1. Emission of unwanted electromagnetic energy by a source, and what kind of
countermeasures can be taken to reduce or eliminate such emissions.
2. Susceptibility to electromagnetic energy by a victim, and what kind of protective
measures can be taken to reduce or eliminate the susceptibility.
In terms of EMC, the victim is always an electronic device whereas the source can be an
electronic device or a natural phenomenon such as a lightning.
3.1 Coupling modes
The EMC standards are covering the electromagnetic interference modes of conductive
and radiative coupling (see Figure 26).
radiative
source
victim
conductive
013aaa418
Fig 26. Conductive and radiative coupling
Conductive coupling requires a direct contact with a conducting hardware (transmission
line, wire, cable, PCB trace) between the source and the victim.
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Radiative coupling: The source emits an electromagnetic wave which is received by the
victim.
3.2 EMC test methods and equipment
Devices will be tested for its emission and immunity of conductive and radiative coupling
(see Table 5).
Table 5.
EMC test methods
Test type
Coupling method
Method name
Reference
conducted emission
direct coupling via 150  / 1  network
150  / 1  method
IEC61967-4
conducted immunity
direct RF-power injection via DC block capacitor
Direct Power Injection (DPI)
IEC62132-4
radiated emission
E- and H-field radiation of entire IC
TEM-cell method
IEC61967-2
radiated immunity
E- and H-field radiation on entire IC
TEM-cell method
IEC62132-2
Conducted tests
Radiated tests
Emission tests are made with a TEM cell (see Figure 27) and immunity tests with GTEM
cell (see Figure 28).
013aaa435
Fig 27. TEM cell for emission tests
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013aaa436
Fig 28. GTEM cell for immunity tests
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High frequency absorber
Signal
generator
Amplifier
PC
Millivoltmeter
E-field
EMC test board
DUT
Radiation
50 Ω
Metall septum,
electrically conducting
Metall cover,
electrically conducting
013aaa434
50 Ω termination field
DUT: Device Under Test.
Fig 29. Schematic test configuration in a GTEM cell
3.3 EMC test results
60.0
Voltage (dBμV)
50.0
40.0
30.0
20.0
10.0
0
-10.0
0
200.0 M
400.0 M
600.0 M
Frequency (Hz)
800.0 M
1.0 G
013aaa437
12 dBV is the reference limit.
Fig 30. Example result of a radiated emission test
AN10853
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 November 2010
© NXP B.V. 2010. All rights reserved.
25 of 29
AN10853
NXP Semiconductors
ESD and EMC sensitivity of IC
013aaa438
800
Efield
(V/m)
600
400
200
0
0
200
400
600
800
1000
Frequency (MHz)
400 V/m is the reference limit.
Fig 31. Example result of a radiated immunity test
AN10853
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 November 2010
© NXP B.V. 2010. All rights reserved.
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NXP Semiconductors
ESD and EMC sensitivity of IC
4. References
[1]
AN10706 — Handling bare die
[2]
AN10897 — A guide to designing for ESD and EMC
[3]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[4]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[5]
IEC 61967 — Integrated circuits – Measurement of electromagnetic emissions,
150 kHz to 1 GHz
Part 1: General conditions and definitions
Part 2: Measurement of radiated emissions – TEM cell and wideband TEM cell
method
Part 3: Measurement of radiated emissions – Surface scan method
Part 4: Measurement of conducted emissions – 1 /150  direct coupling method
Part 5: Measurement of conducted emissions – Workbench Faraday Cage method
Part 6: Measurement of conducted emissions – Magnetic probe method
[6]
IEC 62132 — Measurement of electromagnetic immunity, 150 kHz to 1 GHz
Part 1: General conditions and definitions
Part 2: Measurement of radiated immunity – TEM cell and wideband TEM cell
method
Part 3: Bulk current injection (BCI) method
Part 4: Direct RF power injection method
Part 5: Workbench Faraday cage method
[7]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[8]
JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[9]
JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[10] JESD78 — IC Latch-Up Test
[11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[12] NX2-00001 — NXP Semiconductors Quality and Reliability Specification
[13] NX3-00092 — NXP store and transport requirements
AN10853
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 November 2010
© NXP B.V. 2010. All rights reserved.
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NXP Semiconductors
ESD and EMC sensitivity of IC
5. Legal information
5.1
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
5.2
Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
AN10853
Application note
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express, implied
or statutory, including but not limited to the implied warranties of
non-infringement, merchantability and fitness for a particular purpose. The
entire risk as to the quality, or arising out of the use or performance, of this
product remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be liable
to customer for any special, indirect, consequential, punitive or incidental
damages (including without limitation damages for loss of business, business
interruption, loss of use, loss of data or information, and the like) arising out
the use of or inability to use the product, whether or not based on tort
(including negligence), strict liability, breach of contract, breach of warranty or
any other theory, even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by customer
for the product or five dollars (US$5.00). The foregoing limitations, exclusions
and disclaimers shall apply to the maximum extent permitted by applicable
law, even if any remedy fails of its essential purpose.
5.3
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 November 2010
© NXP B.V. 2010. All rights reserved.
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AN10853
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ESD and EMC sensitivity of IC
6. Contents
1
2
2.1
2.1.1
2.1.2
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.6.1
2.2.6.2
2.2.6.3
2.2.6.4
3
3.1
3.2
3.3
4
5
5.1
5.2
5.3
6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrostatic charging and discharging . . . . . 3
Triboelectric charging and ESD events . . . . . . 3
ESD order of magnitude . . . . . . . . . . . . . . . . . . 5
ESD sensitivity of ICs . . . . . . . . . . . . . . . . . . . . 6
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrostatic Protected Area (EPA): work area for
handling electrostatic-sensitive devices . . . . . . 8
Receipt and storage of components . . . . . . . . 11
PCB assembly . . . . . . . . . . . . . . . . . . . . . . . . 14
Testing PCBs . . . . . . . . . . . . . . . . . . . . . . . . . 14
Internal ESD protection circuits . . . . . . . . . . . 14
Verification of ESD protection . . . . . . . . . . . . . 16
Human Body Model (HBM). . . . . . . . . . . . . . . 16
Machine Model (MM) . . . . . . . . . . . . . . . . . . . 17
Charged-Device Model (CDM) . . . . . . . . . . . . 18
Latch-Up (LU) test . . . . . . . . . . . . . . . . . . . . . 19
ElectroMagnetic Compatibility (EMC) . . . . . . 22
Coupling modes . . . . . . . . . . . . . . . . . . . . . . . 22
EMC test methods and equipment . . . . . . . . . 23
EMC test results . . . . . . . . . . . . . . . . . . . . . . . 25
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Legal information. . . . . . . . . . . . . . . . . . . . . . . 28
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 November 2010
Document identifier: AN10853
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