Design and Simulation of Integrated, High-Efficiency Power Amplifier Modules Marc J. Franco, PhD WML: Measurement, Design, and Linearization Techniques for High-Efficiency Amplifiers Introduction • Handset power amplifier design is challenged by continuous cost and size reduction • Part of cost reduction can be achieved by faster time to market and less design iterations • By using advanced design and simulation techniques, it is possible to achieve first pass success Design Goals • 12 mm2 footprint laminate • RFMD GaAs HBT die, wirebonded • 824 to 915 MHz operating frequency band • 35 dBm minimum output saturated power, ± 0.1 dB across the band, at 2 dBm input level • Power added efficiency (PAE) ≥ 59%, ± 1% across the band • 3.4 V nominal collector supply voltage • Second harmonic level < -10 dBm, all others <-15 dBm • Achieve the above in one design iteration Power Amplifier Module Technology Bond wire GaAs die SMD capacitor Plastic molding Solder mask Copper trace Metalized via Laminate substrate Solder Handset board Power Amplifier Module Simplified Schematic Design Methodology • This presentation covers only the major steps • Output stage fundamental load pull • Output stage harmonic load pull • Output matching network topology and die schematic Output Stage Fundamental Load Pull Pout 35.7 dBm PAE 71.1 % • All work done in software using HBT models (no measurements required) • The fundamental is load pulled while harmonics are terminated into 50 ohms • The maximum PAE and Pout usually do not coincide • Pout must be used to choose the fundamental load line since the design must guarantee certain output power • The typical loss of the output matching network must be taken into account (~ 0.7 dB) Constant PAE (solid line) and Pout • In this case, 35 dBm are required, so 35.7 dBm is the target Pout (dotted line) contours for the fundamental frequency, low band load pull. PAE step: 0.5%, Pout step: 0.1 dB, • The resulting load line is ~ 2.2+j1.1 Ohms and the PAE is 71.1% chart normalized to 5 ohms Output Stage 2nd Harmonic Load Pull PAE 76.1% Pout 36.1 dBm • Load pull the second harmonic using the previously found fundamental load impedance and 50 ohms for the rest of the harmonics • Large shaded region keeps PAE within 1% PAE increase • Double shaded region keeps PAE within 1% and Pout within 0.1 dB • The PAE increases by 5 % by terminating the second harmonic into the double shaded region impedance range Constant PAE (solid line) and Pout (dotted line) contours for second harmonic load pull. PAE step: 1%, Pout step: 0.1 dB • Pout also increases slightly Output Stage 3rd Harmonic Load Pull Pout PAE • Load pull the third harmonic using the previously found fundamental and 2nd harmonic impedances and 50 ohms for the higher harmonics • An almost shorted 3rd harmonic is preferred; a 0.5-j3.2 Ohm termination is chosen PAE increase PAE 77.3% Pout 36.1 dBm Constant PAE (solid line) and Pout (dotted line) contours for third harmonic load pull. PAE step: 1%, Pout step: 0.1 dB • The PAE increases by 2.2 % • Pout remains approx. constant • High impedance 2nd harmonic termination and low impedance 3rd harmonic termination indicates inverse class F operation Simulated Output Stage Load Line Fundamental 2nd harmonic (entire band) 3rd harmonic The output matching network is designed so all the impedances fall in the optimum regions obtained in the previous load pulls PA module simplified schematic Laminate 2nd harmonic termination • A two-section output matching network is used due to size constraints Output matching network Out In Bias3 Bias2 Bias1 GaAs die 3.4 V Collector biasing choke 3rd harmonic termination • The 3rd harmonic is terminated by series resonating an on-die capacitor with a bond wire • The 2nd harmonic is terminated by parallel resonating the collector bias inductor with the available shunt capacitance Simulation Technique • The GaAs die is simulated in ADS Momentum (2D EM) • The laminate, some of the passive components and the bond wires are simulated in Ansoft HFSS (3D EM) • The previous EM simulations are incorporated as Sparameter sets to a harmonic balance simulation in ADS Load Line Measurement and Simulation 3rd harmonic Fundamental 4th harmonic • Good agreement between simulation and measurement • Fundamental load line impedance maintained across the 824 to 915 MHz band • Second and fourth harmonics terminated into a high impedance 5th harmonic 2nd harmonic Load line measurement (dotted line) and simulation (solid line) including the output active device reactance • Third and fifth harmonics terminated into a low impedance • Harmonic termination indicates inverse class-F operation Output-stage Collector Waveforms 10 4 Coll. current 8 3 6 2 4 1 2 0 Coll. voltage -1 0 0.0 0.5 1.0 1.5 2.0 2.5 • Simulated output-stage collector current and voltage waveforms • The current resembles a square wave, while the voltage is approximately a half-sine wave, in accordance with finite-harmonic inverse class F power amplifier operation Output Power 36.0 35.8 35.6 35.4 35.2 35.0 34.8 34.6 34.4 34.2 34.0 824 834 844 854 864 874 884 894 904 915 • Output power measurements (solid lines) and simulation (dotted line) as a function of frequency • Excellent agreement between simulation and measurement • Good flatness across the band of operation • Meets design goals Power Added Efficiency 62 61 60 59 58 57 56 55 824 834 844 854 864 874 884 894 904 915 • Power added efficiency measurements (solid lines) and simulation (dotted line) as a function of frequency • Excellent agreement between simulation and measurement • Good flatness across the band of operation • Meets design goals Small Signal Gain Measurement [dB] Simulated [dB] 60 40 20 0 -20 -40 -60 0 1 2 3 4 5 6 7 Freq, GHz • Measured and simulated small signal gain as a function of frequency • Excellent agreement between simulation and measurement • Enables accurate harmonics level prediction Harmonic Levels 2nd harmonic 3rd harmonic -10 -10 -15 -15 -20 -20 Measured -25 -15 -20 -30 Simulated dBm -30 -35 -35 -40 -40 -45 -45 -45 -50 -50 -50 -55 -55 -55 -60 -60 0.834 0.844 0.854 0.864 0.874 0.884 0.894 0.904 0.824 0.914 -60 0.834 0.844 0.854 0.864 0.874 0.884 0.894 0.904 0.914 0.824 5th harmonic -15 -15 -15 -20 -20 -20 -25 -25 -25 Measured dBm dBm Simulated -35 -40 -45 -45 -45 -50 -50 -55 -55 -60 -60 0.844 0.854 0.864 0.874 Freq. [GHz] 0.884 0.894 0.904 0.914 0.824 0.884 0.894 0.904 0.914 0.894 0.904 0.914 -35 -40 Simulated 0.874 -30 -30 -35 0.864 7th harmonic -10 0.834 0.854 6th harmonic -10 0.824 0.844 Freq. [GHz] -10 -40 0.834 Freq. [GHz] Freq. [GHz] -30 Measured -35 -40 0.824 Simulated -25 Measured dBm dBm Simulated -25 -30 dBm 4th harmonic -10 Measured Simulated -50 -55 -60 0.834 0.844 0.854 0.864 0.874 Freq. [GHz] 0.884 0.894 0.904 0.914 0.824 Measured 0.834 0.844 0.854 0.864 0.874 Freq. [GHz] 0.884 Stability Large signal K factor CENTER FREQUENCY RBW 3 MHz Marker 2 [T1 ] Output spectrum @ VSWR=4:1, 25ºC 1.5 GHz Ref 20 dBm * VBW * Att 15 dB 2 MHz SWT 5 ms -45.46 dBm 1.004807692 GHz Marker 1 [T1 ] 20 8.71 dBm 1 880.000000000 MHz 10 1 RM * CLRWR A GAT TRG 0 -10 -20 -30 EXT -40 2 -50 -60 -70 -80 Center Date: 1.5 GHz 21.JUL.2009 300 MHz/ Span 3 GHz 23:14:36 • The large signal K factor was found to be lower than unity across a narrow phase angle range @ VSWR 4:1 and above • Measurements confirmed this instability EDGE Spectrum * RBW 20 kHz CENTER FREQUENCY * VBW 200 kHz 8 80 M H z Ref 9.2 dBm * Att 10 dB * SWT 500 ms * 0 -10 A -20 SGL 1 RM * CLRWR GAT -30 TRG -40 -50 -60 -70 -80 -90 Center 880 MHz 125 kHz/ Span 1.25 MHz Tx Channel EXT Bandwidth 30 kHz Adjacent Channel Bandwidth 30 kHz Spacing 200 kHz Alternate Channel Bandwidth 30 kHz Spacing 400 kHz 2nd Alternate Channel Bandwidth Spacing Date: 11.MAY.2010 30 kHz 600 kHz 16:52:37 Power -8.62 dBm Lower Upper -36.49 dB -37.53 dB Lower Upper -61.72 dB -61.13 dB Lower Upper -70.61 dB -70.63 dB • Inverse class F PAs can also be used for linear amplification if backed-off appropriately Conclusion • The design, simulation and measurement of an RF power amplifier module was demonstrated • The design methodology was presented for inverse class-F operation, but it can be used for other high efficiency nonlinear modes of operation • All the design goals were met in one design iteration • By using advanced simulation tools (EM 2D, EM 3D and harmonic balance), it is possible to accurately predict and optimize PA performance in software before any hardware is built