Fundamental Failure Mechanisms Limiting Maximum Voltage Operation in AlGaN/GaN HEMTs Michael D. Hodge, Ramakrishna Vetury, and Jeffrey B. Shealy Purpose • Propose a method of determining Safe Operating Area (SOA) of GaN Power Devices in a high voltage OFFstate. • Describe fundamental failure mode limiting OFF-state SOA • Describe a new test method to safely extract failure times for device operation close to catastrophic failure • Discuss physical causal mechanisms of fundamental failure mode Outline • Introduction • GaN Switch Operation • Test Methodology • Stress Observations • Discussion of Observed Degradation • SOA Prediction • Summary Introduction • AlGaN/GaN HEMTs applications • RF • High Power RF Generation • RF control • High Frequency • Power Management • Acceleration factors defining SOA not completely understood • Combination of temperature, voltage, current, and RF • Dominant failure mechanisms in OFF-state not well understood in literature • Development stress methods close to catastrophic failure GaN Material Advantages Ruggedness Power Handling Low Loss, Low Noise UNREALIZED Potential Reported Reliability Failure Mechanism in GaN HEMTs Related to Inverse Piezoelectric Effect (IPE) Hot Electron Induced Degradation (HEI) • Requires • Requires • High electric field • Process related pits? • Impact • Physical defect (crack or surface pit) • Symptoms • RON, IDMAX, IDSS, Gm, IG • Questions • Time dependence not completely understood • Hot electrons • Impact • Create traps in buffer and/or barrier layers • Symptoms • RON, IDMAX, IDSS, Gm, IG • Questions • Trap parameters not complete defined Experimental Device – AlGaN GaN Switch Source Connected FP Source Connected FP Gate Gate SiN Source L Sourc GS e Gate SiN LG LGD Drain Drain Source SiN LGS LDS PA FET AlGaN/GaN PA FET SiN LG LGD LDS AlGaN/GaN Switch FET • AlGaN/GaN PA FET • AlGaN/GaN Switch FET • Asymmetric Device • Symmetric Device • Gate off-center in channel • Lgs<Lgd • Gate centered in channel • Lgs=Lgd • Source connected FP • No Field Plating Drain Switch Operation IDS VBD VSOA OFF-State VG IDS VTH VGS ON-State VG = 0V VDS • DC bias only applied to gate terminal • Used to control device state • OFF-State • Gate is biased far away from VTH • Ensure device does not cross VTH or exceed SOA over range of RF swing • ON-State • No bias on Gate – FET is fully ON • FET sized to remain in linear region over RF swing OFF-State - Safe Operation Limits VSOA OFF-State VG VTH VGS LDS VBD SOA Limit A IDS Technology Limit B C VDG • Red Line – Catastrophic breakdown for a given layout • Blue Line – SOA for a given channel geometry Test Method Compliance Voltage SPA Set Current Actual FET Leakage Low Voltage Med Voltage Close to VBD Voltage VG<VTH Current Drain Current LV MV HV Drain Voltage Time • Semiconductor parametric analyzer (SPA) set to forced current mode. • Voltage compliance set to desired stress value • Forced current set just above device leakage for a given voltage. As determined by characterization. • SPA increases voltage to achieve set current • Voltage compliance is reached and SPA fixes voltage. Experimental Summary • Constant Voltage Stress • Via SPA forced drain current mode • Protects device from catastrophic breakdown • Allows stress close to device breakdown • Stress Conditions • VGS = -10V • VDS Compliance = 180V - 205V • T = 1 hour intervals • ON-State Characterization • RON, IDSS, IDMAX • Measured at 5 points of interest • OFF-State Characterization • VBD • Performed before and after each stress Stress Observations – Breakdown Voltage Walk-out Phenomena 1 Initial Walk-out VGS=-10V Walk-out 2 • Breakdown voltage “walk-out” • Voltage required for given OFF-state drain current increases • Reported in literature in GaAs MESFETs1 and pHEMTs2 • Attributed to trapped carriers in gate-drain region. 1) P. Ladbrooke et. al. IEEE Trans. Electron Devices, 35(3), March 1988, pp. 257-267. 2) P. Menozzi et. al. IEEE Trans. Electron Devices, 43(4), April 1996, pp. 543-546. Stress Observations – Breakdown Voltage Walk-in Phenomena Walk-out Walk-in VGS=-10V 3 Walk-in 2 • Breakdown voltage “walk-in” • Voltage required for given OFF-state drain current decreases • Similar in behavior observed literature on GaN PAs1,2 1) D. Marcon et. al., 2010 IEEE Electron Devices Meeting (IEDM), San Francisco CA, Dec. 2010, pp. 20.3.1 - 20.3.4. 2) M. Meneghini et. al., IEEE Electron Devices Meeting (IEDM), Washington DC, Dec. 2011, pp. 19.5.1 - 19.5.4. “Walk-out” Drain Voltage (V) [Id=100 uA/mm)] Drain Current (uA/mm) [Vd=165V] Walk-out and Walk-in Time Dependence “Walk-in” Time (Hours) • Evolution of “walk-out” and “walk-in” over time In-situ Terminal Leakage Currents E “Walk-out” A 190V 200V D “Walk-in” B C 205V • Dominant Leakage path is drain to gate • After T=10 Hours source leakage increases • Data suggests a degradation of gate Schottky diode Compliance Voltage OFF-State – Breakdown Voltage Characterization Initial 15 Drain Current (uA/mm) Final 14 Walk-out 37 Walk-in Drain Voltage (V) • OFF-State characterization around key stress points • Clear evidence of “walk-out” and “walk-in” phenomena 4 100 1500 -100 1300 -300 1100 IG (uA/mm) @ VDS=20V -500 900 IG (uA/mm) @ VDS=165V -700 700 ID (uA/mm) @ VDS=20V -900 500 ID (uA/mm) @ VDS=165V -1100 300 -1300 100 -1500 -100 0 5 10 Time (Hours) 15 20 • OFF-State Characterization leakage current at VDS=20V and VDS=165V • T=10 Hours – leakage at high bias increases • T=15 Hours – leakage at low bias increases Drain Current (uA/mm) Gate Current (uA/mm) OFF-State – Breakdown Voltage Characterization Drain Current (mA/mm) ON-State Characterization – VGS-IDS Sweep Observations • Significant change to sub-threshold leakage • Increase two orders of magnitude once stress IDS increases. |Gate Current| (uA/mm) • Possible degradation of gate diode. • Minimal change in ON-State. • ON-state parametric change <7%. Gate Voltage (V) 0.11 25 0.09 0 0.07 -25 0.05 -50 0.03 -75 0.01 -100 -150 0 Gate Current (uA/mm) -0.01 IG (uA/mm) @ VGS=-8V ID (mA/mm) @ VGS=-8V -125 5 10 Time (Hours) 15 -0.03 0 800 -5 750 -10 700 -15 650 IG (uA/mm) @ VGS=1V ID (mA/mm) @ VGS=1V 5 10 Time (Hours) • Subthreshold shows clear “walk-out” and “walk-in” signature. • Small change in ON-State. 850 0 Observations 20 5 -20 Drain Current (mA/mm) 50 15 600 20 • IDMAX decreases by < 4% Drain Current (mA/mm) Gate Current (uA/mm) ON-State – Time Dependence • IG leakage increases uniformly over bias Gate-Drain/Source Diode Characterization 140 VGS=-10V Drain Leakage (uA/mm) 120 100 80 Gate-Drain (Pre-Stress) Gate-Drain (Walk-out) Gate-Drain (Walk-in) Gate-Source (After Gate-Drain Walk-in) 60 40 20 0 0 50 100 Drain Voltage (V) 150 200 • Test Sequence • 1. OFF-state characterization 1. Gate-Source diode unchanged 2. Gate-Drain diode stressed to walk-in 2. Gate-Drain diode changed 3. OFF-state characterization • 1. Observation Conclusion Damage localized to Gate-Drain region. Motivation to Determine SOA SOA Limit LDS A Technology Limit B C VDG • Voltage stress leads to loss of gate control • Evidenced by increase in leakage current • Preliminary PEM images reveal localized hot spots along gate. • Necessary to determine time dependence of failure versus applied voltage. • Will lead to the determination of actual SOA (Blue Line/Region) Voltage Acceleration - Literature (1) 1. Dieci et. al. on Commercial GaAs HFETs • OFF-State stress reveals a VDG “threshold” • Below VDG threshold device lifetimes very high • Based on a derived physical model FOM 2. Marcon et. al. on GaN-on-Si HEMT PA • TTF vs Applied Voltage follows a power law trend 1) D. Dieci et. al., IEEE Trans. Electron Device, 48(9), Sept. 2001, pp. 1929-1937. 2) D. Marcon et. al., 2010 IEEE Electron Devices Meeting (IEDM), San Francisco CA, Dec. 2010, pp. 20.3.1 - 20.3.4. (2) Determination of SOA in GaN RF Switches 500 Physcial Model FOM 450 400 350 300 250 200 150 100 50 0 185 190 195 VDG (V) 200 205 FOM = tF * |Ig|1/2 [h*(uA/mm)1/2] • GaN RF Switch FOM Definitions • tF = time to walk-in (hours) • |Ig| = Average of the magnitude of gate leakage (uA/mm) • Preliminary results are similar to Dieci et al. • Suggests a threshold acceleration based on VDG Conclusions • Method of OFF-State stress close to catastrophic breakdown proposed. • Observation of two distinct mechanisms • Breakdown voltage walk-out • Breakdown voltage walk-in • Degradation appears to be limited to OFF-State parameters • Appears linked to gate diode Schottky properties • Further experimentation shows damage is located on stressed side of gate diode. • By varying the stress voltage a VDG acceleration factor can be determined