LP3929 High Speed Bi-Directional Level Shifter and Ultra LowDropout CMOS Voltage Regulator and Line Protection General Description Key Specifications The LP3929 is designed for portable and wireless applications requiring level translation and power supply generation in a compact footprint. The device level translates 1.8 V LVCMOS on the host (A) side to 2.85 V LVCMOS levels on the card (B) side for a miniSD / SD 4-bit bi-directional data bus. Independent direct control of the CMD, Data0 and Data1-3 paths support mini SD state machine requirements. A shutdown pin is provided for the level shifters and regulator. The f_CLK_A is a feedback clock to the host which can be used to overcome level shifter bus delay. The built-in low-dropout voltage regulator is ideal for mobile phone and battery powered wireless applications. It provides up to 200 mA from a 3.05 V to 5.5 V input. It is stable with small 1.0 µF ±30% ceramic and high quality tantalum output capacitors, requiring smallest possible PC board area. The card (B port) side channels have integration of ASIP (Application Specific Integrated Passives) - on chip integrated pull-up, pull-down, series resistors and capacitors for EMC filtering. It is designed to tolerate IEC61000-4-2 level 4 ESD: ±15 kV air discharge, ±8 kV direct contact. Level Shifter: ■ 6-signal Level Shifter (5 bi-directional and 1 uni-direction) ■ 3 ns (typ) propagation delay ■ Channel-to-channel skew < 1 ns (max) Low-Dropout Regulator: ■ 3.05 V to 5.5 V input range ■ 2.85 V at 200 mA ■ Fast Turn-On time: 30 µs (typ) ■ 110 mV (max) dropout with 200 mA load ■ Thermal shutdown at 160°C (typ) Protection Block (B Side): ■ Robust IEC ESD Protection: ±15 kV Air Gap, ±8 kV Direct Contact ■ ASIP / EMI Filtering Features ■ Ultra small micro SMD 24 bump package ■ 6-signal level translation 1.8 V to 2.85 V ■ LDO stable with ceramic and high quality tantalum capacitors Typical Application Circuit 20186801 © 2007 National Semiconductor Corporation 201868 www.national.com LP3929 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator and Line Protection December 14, 2007 LP3929 Block Diagram 20186802 www.national.com 2 LP3929 Package Outline and Connection Diagrams 20186812 Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” will designate the date code. The “TT” is a NSC internal code for die traceability; engineering sample parts will be marked as "ES". Both will vary considerably. The pin 1 marking identifier is the location of corner bump A1. Top View - TME24 Device Marking 20186811 Top View - Bump Underneath 24 Bump micro SMD Package See NSC Package Number TME24AAA Ordering Information For 24 Bump micro SMD Package Output Voltage Grade LP3929 Supplied As 250 Units, Tape & Reel LP3929 Supplied As 3000 Units, Tape & Reel 2.85 V LP3929TME-AACQ LP3929TMEX-AACQ STD Tape and Reel Information 20186810 Top View: Tape and Reel Information 3 www.national.com LP3929 Pin Descriptions Pin Name micro SMD Bump Identifier Port / Direction Type Function D0_A D1 Host / Bidirectional Push-Pull 1.8 V I/O Channel (Note 14) D1_A E1 Host / Bidirectional Push-Pull 1.8 V I/O Channel (Note 14) D2_A A1 Host / Bidirectional Push-Pull 1.8 V I/O Channel (Note 14) D3_A B1 Host / Bidirectional Push-Pull 1.8 V I/O Channel (Note 14) CMD_A D2 Host / Bidirectional Push-Pull 1.8 V I/O Channel (Note 14) CLK_A C1 Host / Input High Z fCLK_A E2 Host / Output Push-Pull DIR_0 A3 Host / Input High Z 1.8 V Input CLK Channel (Note 14) 1.8 V Output CLK Channel 1.8 V Input Direction Control D0 Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) DIR_1-3 E3 Host / Input High Z 1.8 V Input Direction Control D1-D3 Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) CMD_DIR A2 Host / Input High Z 1.8 V Input Direction Control CMD Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) EN C2 Host / Input High Z Device Enable with high impedance pull-down resistor (200 kΩ): VDDA = Device Active (on), VSS = Device Disabled (off) D0_B D5 Card / Bidirectional Push-Pull 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) D1_B E5 Card / Bidirectional Push-Pull 2.85 V I/O Channel with high impedance pull-up to VDDB D2_B A5 Card / Bidirectional Push-Pull D3_B B5 Card / Bidirectional Push-Pull CMD_B D4 Card / Bidirectional Push-Pull CLK_B C5 Card / Output Push-Pull VBAT A4 Host / Input Power 3.05 V to 5.5 V VDDA B3 Host / Input Power 1.71 V to 1.92 V, 1.8 V (typ) VDDB B4 Card / Output Power 2.85 V (LDO output) VSS C3 Ground VSS C4 Ground WP E4 Host / Card Input Pull-up Pull-up to VDDA (100 kΩ) CD D3 Host / Card Input Pull-up Pull-up to VDDA (100 kΩ) (70 kΩ) 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) 2.85 V I/O Channel with high impedance pull-down to VSS (470 kΩ) 2.85 V I/O Channel with high impedance pull-up to VDDB (15 kΩ) www.national.com 4 2.85 V Output CLK Channel LP3929 TABLE 1. Operation Modes Inputs Mode EN CMD_DIR DIR_0 DIR_1-3 L X X X Level shifter / LDO = off (Shutdown Mode) H L L L All channels (D0-D3 and CMD): B → A Direction H L L H A → B Direction: D1-D3, B → A Direction: CMD and D0 H L H L A → B Direction: D0, B → A Direction: CMD and D1-D3 H L H H A → B Direction: D0-D3, B → A Direction: CMD H H L L A → B Direction: CMD, B → A Direction: D0-D3 H H L H A → B Direction: CMD and D1-D3, B → A Direction: D0 H H H L A → B Direction: CMD and D0, B → A Direction: D1-D3 H H H H All channels (D0-D3 and CMD): A → B Direction H = VDDA, L = VSS 5 www.national.com LP3929 Maximum Power Dissipation Capacity at 25°C micro SMD ESD Rating HBM - MIL-STD-883E 3015.7 std. MM - JESD22-A115-A std. CDM - 500V (JESD22-C 101) Std. Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VBAT) Supply Voltage (VDDA) LVCMOS A Port Input Voltage LVCMOS A Port I/O Voltage LVCMOS A Port I/O Voltage Junction Temperature Storage Temperature Lead Temperature (Note 13) Pad Temperature (Note 13) Derate micro SMD Package above 25°C −0.3V to +6.0V −0.3V to +3.3V −0.3V to VDDA + 0.3V −0.3V to VDDA + 0.3V −0.3V to VDDB + 0.3V 150°C −65°C to +150°C 235°C 235°C 2.8 W ± 2kV ± 200V ± 500V IEC61000-4-2 std., 330Ω, 150pF, Air Gap, B Side (Note 2) ± 15kV IEC61000-4-2 std., 330Ω, 150pF, Direct Contact, B Side (Note 2) ± 8kV Operating Conditions VBAT to VSS VDDA to VSS Ambient Temperature 22.9 mW/°C 3.05V to 5.5V 1.71V to 1.92V −30°C to +85°C Electrical Characteristics Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30°C to +85°C. (Notes 3, 4) Symbol Parameter Conditions Min Typ Max Units LVCMOS A (Host) Port (VDDA = 1.71V to 1.92V) VIH VIL IIH Input Voltage High Level 0.65×VDDA 1.92 V VDDA = 1.71V 1.1115 1.92 V VDDA = 1.92V 1.248 1.92 V 0 0.30×VDDA V VDDA = 1.71V 0 0.513 V VDDA = 1.92V 0 0.576 V Input Voltage Low Level Input Current High Level VIH = VDDA −1 0 +1 µA EN = VSS −1 0 +1 µA EN = VDDA −1 0 +10 µA −1 0 +1 µA IIL Input Current Low Level VIL = VSS VOH Output Voltage High Level IOH = −4 mA 1.26 1.8 VDDA V VOL Output Voltage Low Level IOL = 4 mA VSS 0 0.45 V VDDB V LVCMOS B (Card) Port (VDDB = 2.85V) VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level 0.65×VDDB D0_B to D2_B D3_B IIL Input Current Low Level VIL = VSS Short Circuit Current IOS − V 0.2 +2 µA 0 6.5 + 13 µA CMD_B −5 0.3 +5 µA D0_B to D2_B − 80 −40 0 µA D3_B −1 0.1 +1 µA − 300 − 200 − 20 µA CMD_B IOS + 0.35×VDDB −2 0 VIH = VDDB VOUTlow = VDDB VOUThigh = VSS VOH Output Voltage High Level IOH = − 2 mA VOL Output Voltage Low Level IOL = 2 mA www.national.com 45 µA − 20 µA 0.75×VDDB V 0.25×VDDB 6 V Symbol Parameter Conditions Min Typ Max Units 4 7 mA Supply Current IDD Supply Current All Channels Static: A → B mode, LDO unloaded VBAT VDDA 95 200 µA IDDZ Supply Current — Shutdown EN = VSS VBAT 0.1 2 µA VDDA 0.2 2 µA COUT Output Capacitance (Note 15) B (card) port 15 20 pF Level Shifter AC Switching Characteristics Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30°C to +85°C. (Notes 3, 5, 15, 16) Symbol tPLH tPHL tRISE tFALL Typ Max Units Propagation Delay A to B or B to A Parameter CLB = 15 pF, CLA = 20 pF, 50%-50% Conditions Min 3 7 ns Propagation Delay CLK_A to fCLK_A CLA = 20 pF, 50%-50% 5 14 ns Propagation Delay A to B or B to A CLB = 15 pF, CLA = 20 pF, 50%-50% 3 7 ns Propagation Delay CLK_A to fCLK_A CLA = 20 pF, 50%-50% 5 14 ns Rise Time A Side Output Figure 2 CLA = 20 pF, 20%-70% 1.1 3 ns Rise Time B Side Output with ASIP Figure 2 CLB = 15 pF, 20%-70% 1.6 3 ns Fall Time A Side Output Figure 2 CLA = 20 pF, 20%-70% 1.0 3 ns Fall Time B Side Output with ASIP Figure 2 CLB = 15 pF, 20%-70% 1.9 3 ns <0.5 1.0 ns Enable Time 30 200 µs tDIS Disable Time 18 50 ns tTA Level-Shifter Direction Switch Response (Turn Around) Time 13 20 ns tSKEW Skew between D0–D3, CLK and CMD outputs (either edge) tEN 7 www.national.com LP3929 Electrical Characteristics Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30°C to +85°C. (Notes 3, 4) LP3929 LDO Electrical Characteristics Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30°C to +85°C. (Note 3) Symbol Parameter Conditions Min Typ Max Units 2.76 2.85 2.93 V 2 3 % of VOUT(nom) 0.15 %/V 0.01 %/mA VOUT Output Voltage, VOUT = VDDB IOUT = 200mA, VBAT = 3.05V to 5.5V ΔVOUT Output Voltage Tolerance IOUT = 1 mA Line Regulation Error (Note 6) VBAT = (VOUT(nom) + 0.5V) to 5.5V, IOUT = 1 mA −0.15 Load Regulation Error (Note 7) IOUT = 1 mA to 200 mA Output AC Line Regulation VBAT = VOUT(nom) + 1V, IOUT = 100 mA, COUT = 1.0 µF 1.5 mVPP Power Supply Rejection Ratio (Note 15) VBAT = VOUT(nom) + 1V, f = 1 kHz, IOUT = 50 mA 40 dB VBAT = VOUT(nom) + 1V, f = 10 kHz, IOUT = 50 mA 30 IOUT = 1 mA 1 IOUT = 50 mA 20 IOUT = 100 mA 35 PSRR ΔVDO Dropout Voltage (Note 8) −2 −3 −0.01 IOUT = 200 mA 60 VBAT = 5.5V, Output Grounded (Steady State) 750 Output Noise Density f = 1 kHz, COUT = 1.0 µF 0.6 en Output Noise Voltage BW = 10 Hz to 100 kHz, COUT = 1.0 µF Output Capacitor Output Filter Capacitance (Note 10) VBAT = 3.05V to 5.5V, IOUT = 1mA to 200 mA 0.7 Output Filter Capacitance ESR (Note 11) VBAT = 3.05V to 5.5V, IOUT = 1mA to 200mA 5 ISC Short Circuit Current Limit TON Turn-On Time (Notes 9, 15) ρn (1/f) Thermal Thermal Shutdown Temperature Shutdown (Notes 12, 15) 30 mV 110 mA 200 45 VBAT = 3.05V to 5.5V, IOUT = 1mA to 200mA Thermal Shutdown Hysteresis (Note 15) 1.0 µs µV/√Hz µVrms 22 µF 500 mΩ 160 °C 20 °C Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: IEC61000-4-2 level 4 ESD tolerance applies to VDDB, D0_B–D3_B, CMD_B, CLK_B, WP and CP pins only. Device is tested in application (common ground, bypass capacitors of 1.0 µF present on VBAT, VDDA and VDDB). Note 3: Typical values are given for VDDA = 1.8V, VBAT = 3.6V, TA = 25°C Note 4: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are reference to ground unless otherwise specified. Note 5: Input signal for test purpose is defined as: A side – 0V to 1.8V with 2ns rise time (20%-70%) and B side – 0V to 2.85V with 2ns rise time (20%-70%) Note 6: The output voltage changes slightly with line voltage. An increase in the line voltage results in a slight increase in the output voltage and vice versa. Note 7: The output voltage changes slightly with load current. An increase in the load current results in a slight decrease in the output voltage and vice versa. Note 8: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for input voltages below 2.7V. Note 9: Turn-on time is that between when the enable input is high an the output voltage just reaching 95% of its nominal value. Note 10: Range of capacitor value for which the device will remain stable. This electrical specification is guaranteed by design. Note 11: Range of capacitor ESR values for which the device will remain stable. This electrical specification is guaranteed by design. Note 12: The built-in thermal shut-down of the LDO is also used to put all A and B outputs in tri-state mode. Note 13: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112). Note 14: Unused inputs must be terminated. Note 15: This electrical specification is guaranteed by design. Note 16: The SD/MMC card specification calls for a total of 30 pF capacitance. A load of 15 pF is internal to the LP3929, so the external load capacitance on the B side should comprise the remaining (15 pF or less). www.national.com 8 LP3929 20186805 FIGURE 1. A to B Timing Diagram (propagation delay, skew) 20186806 FIGURE 2. Output Transition Time (A and B Side) 9 www.national.com LP3929 20186807 FIGURE 3. B to A Direction (37 MHz Example) Typical Performance Characteristics Unless otherwise specified: CVBAT = 1 µF, CVDDA = 1 µF, CVDDB = 1 µF, VBAT = 3.85 V, VDDA = 1.8 V, TA = 25°C. ASIP / EMI Filter Response Power Supply Rejection Ration (VBAT = 3.85V) 20186809 20186808 www.national.com 10 EXTERNAL CAPACITORS Like any low-dropout regulator, the LP3929 requires external capacitors for regulator stability. The LP3929 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. INPUT CAPACITOR An input capacitance of 1 µF is required between the LP3929 VBAT pin and ground (the amount of the capacitance may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the VBAT pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance, bias voltage and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will be 1 µF over the entire operating conditions. OUTPUT CAPACITOR The LP3929 is designed specifically to work with very small ceramic output capacitors, any ceramic capacitor (dielectric types Z5U, Y5V or X7R) in 1.0 µF to 2.2 µF range with 5 mΩ to 500 mΩ ESR range is suitable in the LP3929 application circuit. It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see section Capacitor Characteristics). The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR (Equivalent Series Resistance) value which is within a stable range. The output capacitor should be placed as near as possible to the VDDB pin. FAST ON-TIME The LP3929 utilizes a speed up circuitry to ramp up the internal VREF voltage to its final value to achieve a fast output turn on time. NO-LOAD STABILITY The LDO of the LP3929 will remain stable and in regulation with no external load connected to the LDO output VDDB. This is especially important in CMOS RAM keep-alive applications. CAPACITOR CHARACTERISTICS The LP3929 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the range of 1 µF to 4.7 µF range, ceramic capacitors are the smallest, least expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The ESR of a typical 1 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability by the LP3929. The ceramic capacitor’s capacitance can vary with temperature. Most large value ceramic capacitors (2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C. A better choice for temperature coefficient in ceramic capacitor is X7R, which holds the capacitance within ±15%. MICRO SMD ASSEMBLY For assembly recommendations of micro SMD package please refer to National Semiconductor Application Note AN-1112. MICRO SMD LIGHT SENSITIVITY Exposing the micro SMD device to direct sunlight will cause misoperation of the device. Light sources such as Halogen lamps can effect electrical performance if brought near to the device. The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has very little effect on performance. 11 www.national.com LP3929 Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1 µF to 4.7 µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed. Application Information LP3929 Physical Dimensions inches (millimeters) unless otherwise noted micro SMD, 24 Bump NS Package Number: TME24AAA The dimensions for X1, X2 and X3 are as follows: X1 = 2.015mm ± 30μm X2 = 2.015mm ± 30μm X3 = 0.600mm ± 75μm www.national.com 12 LP3929 Notes 13 www.national.com LP3929 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator and Line Protection Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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