INTERSIL 5962R9582401VQC

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8
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8
1-
HS-80C85RH
®
Radiation Hardened 8-Bit CMOS
Microprocessor
File Number
August 2000
3036.3
Features
• Electrically Screened to SMD # 5962-95824
The HS-80C85RH is an 8-bit CMOS microprocessor
fabricated using the Intersil radiation hardened self-aligned
junction isolated (SAJI) silicon gate technology. Latch-up
free operation is achieved by the use of epitaxial starting
material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed . . . . . . . . . . . 1 x 105RAD(Si)
- Transient Upset . . . . . . . . . . . . . . . . >1 x 108RAD(Si)/s
- Latch-up Free . . . . . . . . . . . . . . . . . >1 x 1012RAD(Si)/s
The HS-80C85RH is a functional logic emulation of the
HMOS 8085 and its instruction set is 100% software
compatible with the HMOS device. The HS80C85RH is
designed for operation with a single 5 volt power supply. Its
high level of integration allows the construction of a radiation
hardened microcomputer system with as few as three ICs
(HS-80C85RH CPU, HS83C55RH ROM I/O, and the
HS-81C55/56RH RAM I/O.
• Low Standby Current . . . . . . . . . . . . . . . . . . . . 500µA Max
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
• On-Chip Clock Generator and System Controller
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95824. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
• Low Operating Current. . . . . . . . . . 5.0mA/MHz (X1 Input)
• Electrically Equivalent to Sandia SA 3000
• 100% Software Compatible with INTEL 8085
• Operation from DC to 2MHz, Post Radiation
• Single 5V Power Supply
• Four Vectored Interrupt Inputs
• Completely Static Design
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range. . . . . . . . . . . -55oC to 125oC
Ordering Information
ORDERING NUMBER
1
INTERNAL
MKT. NUMBER
TEMP. RANGE
(oC)
5962R9582401QQC
HS1-80C85RH-8
-55 to 125
5962R9582401QXC
HS9-80C85RH-8
-55 to 125
5962R9582401VQC
HS1-80C85RH-Q
-55 to 125
5962R9582401VXC
HS9-80C85RH-Q
-55 to 125
HS9-80C85RH/Proto
HS9-80C85RH/Proto
-55 to 125
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HS-80C85RH
Pinouts
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) INTERSIL OUTLINE K42.A
TOP VIEW
40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835, CDIP2-T40
TOP VIEW
X1 1
40 VDD
X2 2
39 HOLD
38 HLDA
37 CLOCK OUT
RESET OUT 3
SOD 4
SID 5
36 RESET IN
35 READY
TRAP 6
X1
1
42
VDD
X2
RESET
OUT
SOD
SID
2
41
HOLD
3
40
4
39
5
38
TRAP
6
37
7
36
HLDA
CLOCK
OUT
RESET
IN
READY
IO/ M
8
35
S1
9
34
RD
RST 7.5 7
34 IO/ M
RST 6.5 8
33 S1
RST 7.5
RST 6.5
RST 5.5 9
32 RD
RST 5.5
INTR 10
31 WR
INTR
10
33
INTA 11
WR
30 ALE
INTA
11
32
ALE
AD0 12
29 S0
AD0
12
31
AD1 13
28 A15
AD1
13
30
AD2 14
27 A14
AD2
14
29
S0
A15
A14
AD3 15
26 A13
AD3
15
28
A13
AD4 16
25 A12
AD4
16
27
A12
AD5 17
24 A11
NC
17
26
A11
AD6 18
23 A10
22 A9
18
19
25
24
A10
AD7 19
NC
AD5
GND 20
21 A8
AD6
20
23
A8
AD7
21
22
GND
A9
Functional Diagram
RST
5.5
INTA
INTR
RST
6.5
RST
7.5 TRAP
SID
INTERRUPT CONTROL
SOD
SERIAL I/O CONTROL
ACCUMULATOR (8)
TEMP REG
(8)
FLAG (5)
FLIP FLOPS
INSTRUCTION
REGISTER (8)
POWER
SUPPLY
C REG (8)
D REG (8)
E REG (8)
H REG (8)
L REG (8)
STACK POINTER (16)
INSTRUCTION
DECODER
AND MACHINE
CYCLE
ENCODING
ARITHMETIC
LOGIC
UNIT
(ALU) (8)
B REG (8)
PROGRAM COUNTER (16)
INCREMENTER
DECREMENTER
ADDRESS LATCH (16)
VDD
REGISTER ARRAY
8-BIT
INTERNAL DATA BUS
GND
X1
CLK
X2
GEN
TIMING AND CONTROL
CONTROL
READY
CLK
OUT
S0
WR
RD
STATUS
ALE
IO/M
S1
RESET
DMA
HLDA
HOLD
RESET
IN
2
RESET
OUT
ADDRESS
DATA ADDRESS
BUFFER (8)
BUFFER (8)
A15-A8
ADDRESS
BUS
AD1-AD0
ADDRESS
BUS
HS-80C85RH
Pin Description
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
A8 - A15
21-28
O
Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,
three-stated during Hold and Halt modes and during RESET.
AD0-7
12-19
I/O
Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the bus
during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second
and third clock cycles.
ALE
32
O
Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the address
to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guarantee setup and
hold times for the address information. The falling edge of ALE can also be used to strobe the status
information. ALE is never three-stated.
S0, S1, and
IO/M
31, 35,
and 36
O
Machine Cycle Status:
IO/M
S1
S0
STATUS
0
0
1
Memory write
0
1
0
Memory write
1
0
1
I/O write
1
1
0
I/O read
0
1
1
Opcode fetch
1
1
1
Opcode fetch
1
1
1
Interrupt acknowledge
T
0
0
Halt
T
X
X
Hold
T
X
X
Reset
T = three-State (high impedance)
X = Unspecified
S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of a machine
cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of
these lines.
RD
34
O
Read Control: A low level on RD indicates the selected memory or I/O device is to be read and that the
Data Bus is available for the data transfer, three-stated during Hold and Halt modes and during RESET.
WR
33
O
Write Control: A low level on WR indicates the data on the Data Bus is to be written into the selected
memory or I/O location. Data is set up at the trailing edge of WR, three-stated during Hold and Halt modes
and during RESET.
READY
35
I
Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready
to send or receive data. If READY is low, the CPU will wait an integral number of clock cycles for READY
to go high before completing the read or write cycle. READY must conform to specified setup and hold
times.
HOLD
39
I
Hold: Indicates that another master is requesting the use of the address and data buses. The CPU, upon
receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus
transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is
removed. When the HOLD is acknowledged, the Address, Data Bus, RD, WR, and IO/M lines are
3-stated.
HLDA
38
O
Hold Acknowledge: Indicates that the CPU has received the HOLD request and that it will relinquish the
bus in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the bus
one half clock cycle after HLDA goes low.
INTR
10
I
Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to the last
clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will
be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL
instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by
software. It is disabled by Reset and immediately after an interrupt is accepted.
3
HS-80C85RH
Pin Description
(Continued)
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
INTA
11
O
Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruction cycle
after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some other interrupt port.
RST 5.5
RST 6.5
RST 7.5
9
8
7
I
Restart Interrupts: These three inputs have the same timing as INTR except they cause an internal
RESTART to be automatically inserted.
The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher priority than
INTR. In addition, they may be individually masked out using the SIM instruction.
TRAP
6
I
Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as INTR or
RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.
(See Table 6.)
RESET IN
36
I
Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops. The data
and address buses and the control lines are three-stated during RESET and because of the
asynchronous nature of RESET the processor’s internal registers and flags may be altered by RESET
with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C network
for power-on RESET delay (see Figure 1). Upon power-up, RESET IN must remain low for at least 10
“clock cycle” after minimum VDD has been reached. For proper reset operation after the power-up
duration, RESET IN should be kept low a minimum of three clock periods. The CPU is held in the reset
condition as long as RESET IN is applied.
RESET OUT
3
O
Reset Out: Reset Out indicates CPU is being reset. Can be used as a system reset. The signal is
synchronized to the processor clock and lasts an integral number of clock periods.
X1
X2
1
2
I
O
X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator. X, can
also be an external clock Input from a logic gate. The input frequency is divided by 2 to give the
processor’s internal operating frequency.
CLK
37
O
Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period.
SID
5
I
Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM instruction
is executed.
SOD
4
O
Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction.
VCC
40
I
Power: +5V supply.
GND
20
I
Ground: Reference.
RESET IN
R1
C1
VDD
TYPICAL POWER-ON RESET RC VALUES (NOTE)
R1 = 75kΩ
C1 = 1µF
NOTE: Values may have to vary due to applied power supply ramp up time.
FIGURE 1. POWER-ON RESET CIRCUIT
4
HS-80C85RH
Waveforms
X1 INPUT
t2
tr
CLK
OUTPUT
tf
t1
tXKR
tCYC
tXKF
FIGURE 2. CLOCK
T1
T2
T3
T1
CLK
tLCK
A8-15
tCA
ADDRESS
tRAE
tAD
AD0-AD7
tRDH
DATA IN
ADDRESS
tLL
tLA
tAFR
ALE
tCL
tLDR
tAL
tRD
tCC
RD/INTA
tLC
tAC
FIGURE 3. READ
T1
T2
T3
T1
CLK
tLCK
A8-15
ADDRESS
tLDW
AD0-AD7
tCA
DATA OUT
ADDRESS
tLL
tLA
ALE
tDW
tWD
tWDL
tAL
tCC
tLC
WR
tCL
tAC
FIGURE 4. WRITE
5
HS-80C85RH
Waveforms
(Continued)
T2
T2
THOLD
THOLD
T1
CLK
HOLD
tHDS
tHACK
tHDH
HLDA
tHABF
tHABE
BUS
(ADDRESS, CONTROLS)
FIGURE 5. HOLD
T1
CLK
T2
TWAIT
T3
tLCK
A8-15
T3
tCA
ADDRESS
tRAE
tAD
AD0-AD7
tLL
tRDH
DATA IN
ADDRESS
tLA
tAFR
tCL
tLDR
ALE
tAL
tRD
tCC
tLC
RD/INTA
tLRY
tAC
tARY
tRYS tRYH
tRYS tRYH
READY
NOTE: READY must remain stable during setup and hold times.
FIGURE 6. READ OPERATION WITH WAIT CYCLE (TYPICAL) - SAME READY TIMING APPLIES TO WRITE
T1
T2
T3
T4
T5
T6
THOLD T1
A8-15
CALL INST.
A0-7
BUS FLOATING (NOTE)
RD
INTR
tHABE
INTR
tINS
tINH
HOLD
HLDA
tHDH
tHDS
tHACK
tHABF
NOTE: IO/M is also floating during this time.
FIGURE 7. INTERRUPT AND HOLD
6
T2
HS-80C85RH
TABLE 1. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
(NOTE 1)
CONDITIONS
SYMBOL
TEMPERATURE (oC)
MIN
MAX
UNITS
Input Capacitance
CIN
VDD = Open, f = 1MHz
TA = 25
-
12
pF
I/O Capacitance
CI/O
VDD = Open, f = 1MHz
TA = 25
-
13
pF
COUT
VDD = Open, f = 1MHz
TA = 25
-
12
pF
Output Capacitance
NOTE:
1. All measurements referenced to device ground.
TABLE 2. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY
PRIORITY
ADDRESS BRANCHED TO (1) WHEN
INTERRUPT OCCURS
TRAP
1
24H
Rising edge and high level until sampled.
RST 7.5
2
3CH
Rising edge (latched).
RST 6.5
3
34CH
High level until sampled.
RST 5.5
4
2CH
High level until sampled.
INTR
5
See Note 2
High level until sampled.
NAME
TYPE TRIGGER
NOTES:
2. The processor pushes the PC on the stack before branching to the indicated address.
3. The address branched to depends on the instruction provided to the CPU when the interrupt is acknowledged.
TABLE 3. BUS TIMING SPECIFICATION AS A tCYC DEPENDENT
SYMBOL
HS-8OC85RH
SYMBOL
HS-8OC85RH
tAL
(1/2)T- 175
Minimum
tCC
(3/2 + N)T - 175
Minimum
tLA
(1/2)T- 175
Minimum
tCL
(1/2)T - 190
Minimum
tLL
(1/2)T-50
Minimum
tARY
(3/2)T - 500
Maximum
tLCK
(1/2)T- 125
Minimum
tHACK
(1/2)T - 160
Minimum
tLC
(1/2)T- 100
Minimum
tHABF
(1/2)T +125
Maximum
tAD
(5/2 + N)T - 375
Maximum
tHABE
(1/2)T +125
Maximum
tRD
(3/2 + N)T - 375
Maximum
tAC
(2/2)T - 200
Minimum
tRAE
(1/2)T- 130
Minimum
t1
(1/2)T-210
Minimum
tCA
(1/2)T - 100
Minimum
t2
(1/2)T- 150
Minimum
tDW
(3/2 + N)T - 175
Minimum
tRV
(3/2)T - 200
Minimum
tWD
(1/2)T-100
Minimum
tLDR
(4/2)T - 325
Maximum
NOTE: N is equal to the total WAIT states T = tCYC.
7
HS-80C85RH
TABLE 4. INSTRUCTION SET SUMMARY (Continued)
TABLE 4. INSTRUCTION SET SUMMARY
MNEMONIC
INSTRUCTION CODE
D7 D6 D5 D4 D3 D2 D1 D0
OPERATIONS
DESCRIPTION
MOVE, LOAD, AND STORE
1
D
D
D
S
S
S Move register to
register
MNEMONIC
INSTRUCTION CODE
D7 D6 D5 D4 D3 D2 D1 D0
OPERATIONS
DESCRIPTION
RNZ
1
1
0
0
0
0
0
0
Return on no zero
RP
1
1
1
1
0
0
0
0
Return on positive
RM
1
1
1
1
1
0
0
0
Return on minus
RPE
1
1
1
0
1
0
0
0
Return on parity
even
1
1
1
0
0
0
0
0
Return on parity
odd
1
1
A
A
A
1
1
1
Restart
MOVr1,
r2
0
MOV M.r
0
1
1
1
0
S
S
S Move register to
memory
MOV r.M
0
1
D
D
D
1
1
0
Move memory to
register
RPO
MVl r
0
0
D
D
D
1
1
0
Move immediate
register
RESTART
MVl M
0
0
1
1
0
1
1
0
Move immediate
memory
LXl B
0
0
0
0
0
0
0
1
Load immediate
register Pair B & C
IN
1
1
0
1
1
0
1
1
Input
OUT
1
1
0
1
0
0
1
1
Output
LXl D
0
0
0
1
0
0
0
1
Load immediate
register Pair D & E
INCREMENT AND DECREMENT
LXl H
0
0
1
0
0
0
0
1
Load immediate
register Pair H & L
INR r
0
0
D
D
D
1
0
0
Increment register
DCR r
0
0
D
D
D
1
0
1
Decrement register
STAX B
0
0
0
0
0
0
1
0
Store A indirect
INR M
0
0
1
1
0
1
0
0
Increment memory
STAX D
0
0
0
1
0
0
1
0
Store A indirect
DCR M
0
0
1
1
0
1
0
1
Decrement
memory
INX B
0
0
0
0
0
0
1
1
Increment B & C
registers
INX D
0
0
0
1
0
0
1
1
Increment D & E
registers
POP B
1
1
0
0
0
0
0
1
Pop register Pair
B & C off stack
POP D
1
1
0
1
0
0
0
1
Pop register Pair
D & E off stack
POP H
1
1
1
0
0
0
0
1
Popregister Pair
H & L off stack
POP
PSW
1
1
1
1
0
0
0
1
Pop A and Flags
off stack
LDAX B
0
0
0
0
1
0
1
0
Load A indirect
LDAX D
0
0
0
1
1
0
1
0
Load A indirect
STA
0
0
1
1
0
0
1
0
Store A direct
LDA
0
0
1
1
1
0
1
0
Load A direct
SHLD
0
0
1
0
0
0
1
0
Store H & L direct
LHLD
0
0
1
0
1
0
1
0
Load H & L direct
XCHG
1
1
1
0
1
0
1
1
Exchange D & E,
H & L Registers
STACK OPS
RST
INPUT/OUTPUT
PUSH B
1
1
0
0
0
1
0
1
Push register Pair
B & C on stack
PUSH D
1
1
0
1
0
1
0
1
Push register Pair
D & E on stack
XTHL
1
1
1
0
0
0
1
1
Exchange top ot
stack, H & L
PUSH H
1
1
1
0
0
1
0
1
Push register Pair
H & L on stack
SPHL
1
1
1
1
1
0
0
1
H & L to stack
pointer
PUSH
PSW
1
1
1
1
0
1
0
1
Push A and Flags
on stack
LXI SP
0
0
1
1
0
0
0
1
Load immediate
stack pointer
INX SP
0
0
1
1
0
0
1
1
Increment stack
pointer
DCX SP
0
0
1
1
1
0
1
1
Decrement stack
pointer
JMP
1
1
0
0
0
0
1
1
Jump
unconditional
JC
1
1
0
1
1
0
1
0
Jump on carry
JNC
1
1
0
1
0
0
1
0
Jump on no carry
JZ
1
1
0
0
1
0
1
0
Jump on zero
JNZ
1
1
0
0
0
0
1
0
Jump on no zero
JP
1
1
1
1
0
0
1
0
Jump on positive
CZ
1
1
0
0
1
1
0
0
Call on zero
CNZ
1
1
0
0
0
1
0
0
Call on no zero
CP
1
1
1
1
0
1
0
0
Call on positive
CM
1
1
1
1
1
1
0
0
Call on minus
CPE
1
1
1
0
1
1
0
0
Call on parity even
CPO
1
1
1
0
0
1
0
0
Call on parity odd
RET
1
1
0
0
1
0
0
1
Return
RC
1
1
0
1
1
0
0
0
Return on carry
RNC
1
1
0
1
0
0
0
0
Return on no carry
RZ
1
1
0
0
1
0
0
0
Return on zero
RETURN
8
JUMP
HS-80C85RH
TABLE 4. INSTRUCTION SET SUMMARY (Continued)
MNEMONIC
INSTRUCTION CODE
D7 D6 D5 D4 D3 D2 D1 D0
OPERATIONS
DESCRIPTION
TABLE 4. INSTRUCTION SET SUMMARY (Continued)
MNEMONIC
INSTRUCTION CODE
D7 D6 D5 D4 D3 D2 D1 D0
OPERATIONS
DESCRIPTION
JM
1
1
1
1
1
0
1
0
Jump on minus
ADD M
1
0
C
0
0
1
1
0
Add memory to A
JPE
1
1
1
0
1
0
1
0
Jump on parity
even
ADC M
1
0
0
0
1
1
1
0
Add memory to A
with carry
JPO
1
1
1
0
0
0
1
0
Jump on parity odd
ADl
1
1
0
0
0
1
1
0
Add immediate to A
PCHL
1
1
1
0
1
0
0
1
H & L to program
counter
ACl
1
1
0
0
1
1
1
0
Add immediate to
A with carry
DAD B
0
0
0
0
1
0
0
1
Add B & C to H & L
Call unconditional
DAD D
0
0
0
1
1
0
0
1
Add D & E to H & L
CALL
CALL
1
1
0
0
1
1
0
1
CC
1
1
0
1
1
1
0
0
Call on carry
DAD H
0
0
1
0
1
0
0
1
Add H & L to H & L
CNC
1
1
0
1
0
1
0
0
Call on no carry
DAD SP
0
0
1
1
1
0
0
1
Add stack pointer
to H & L
ANA r
1
0
1
0
0
S
S
S And register with A
XRA r
1
0
1
0
1
S
S
S Exclusive OR
register with A
ORA r
1
0
1
1
0
S
S
S OR register with A
CMP r
1
0
1
1
1
S
S
S Compare register
with A
ANA M
1
0
1
0
0
1
1
0
And memory with A
XRA M
1
0
1
0
1
1
1
0
Exclusive OR
memory with A
ORA M
1
0
1
1
0
1
1
0
OR memory with A
CMP M
1
0
1
1
1
1
1
0
Compare memory
with A
ANI
1
1
1
0
0
1
1
0
And immediate
with A
LOGICAL
SUBTRACT
SUB r
1
0
0
1
0
S
S
S Subtract register
from A
SBB r
1
0
0
1
1
S
S
S Subtract register
from A with borrow
SUB M
1
0
0
1
0
1
1
0
Subtract memory
from A
SBB M
1
0
0
1
1
1
1
0
Subtract memory
from A with borrow
SUl
1
1
0
1
0
1
1
0
Subtract
immediate from A
SBl
1
1
0
1
1
1
1
0
Subtract
immediate from A
with borrow
0
0
1
0
1
1
1
1
Complement A
SPECIALS
XRI
1
1
1
0
1
1
1
0
Exclusive OR
immediate with A
CMA
ORl
1
1
1
1
0
1
1
0
OR immediate
with A
STC
0
0
1
1
0
1
1
1
Set carry
CMC
0
0
1
1
1
1
1
1
Complement carry
CPl
1
1
1
1
1
1
1
0
Compare
immediate with A
DAA
0
0
1
0
0
1
1
1
Decimal adjust A
El
1
1
1
1
1
0
1
1
Enable Interrupts
ROTATE
CONTROL
RLC
0
0
0
0
0
1
1
1
Rotate A left
DI
1
1
1
1
0
0
1
1
Disable Interrupt
RRC
0
0
0
0
1
1
1
1
Rotate A right
NOP
0
0
0
0
0
0
0
0
No-operation
RAL
0
0
0
1
0
1
1
1
Rotate A left
through carry
HLT
0
1
1
1
0
1
1
0
Halt
RIM
0
0
1
0
0
0
0
0
RAR
0
0
0
1
1
1
1
1
Rotate A right
through carry
Read Interrupt
Mask
SlM
0
0
1
1
0
0
0
0
Set Interrupt Mask
INX H
0
0
1
0
0
0
1
1
Increment H & L
registers
DCX B
0
0
0
0
1
0
1
1
Decrement B & C
DCX D
0
0
0
1
1
0
1
1
Decrement D & E
DCX H
0
0
1
0
1
0
1
1
Decrement H & L
NOTES:
4. DDS or SSS: B000, C001, D010, E011, H100, L101, Memory
110, A111
5. Two possible cycle times (6/12) indicate instruction cycles
dependent on condition flags.
† All mnemonics copyrighted, Intel Corporation 1976
ADD
ADD r
1
0
0
0
0
S
S
S Add register to A
ADC r
1
0
0
0
1
S
S
S Add register to A
with carry
9
HS-80C85RH
Functional Description
Interrupt and Serial I/O
The HS-80C85RH is a complete 8-bit parallel central
processing unit implemented in a self aligned, silicon gate,
CMOS technology. Its static design allows the device to be
operated at any external clock frequency from a maximum of
4MHz down to DC. The processor clock can be stopped in
either the high or low state and held there indefinitely. This
type of operation is especially useful for system debug or
power critical applications. The device is designed to fit into
a minimum system of three ICs: CPU (HS-80C85RH),
RAM/IO (HS-81C55/56RH) and ROM/IO Chip
(HS-83C55RH).
The HS-80C85RH has 5 interrupt inputs: INTR, RST 5.5, RST
6.5, RST 7.5, and TRAP INTR is maskable (can be enabled or
disabled by El or Dl software instructions), and causes the CPU
to fetch in an RST instruction, externally placed on the data
bus, which vectors a branch to any one of eight fixed memory
locations (Restart addresses). The decimal addresses of these
dedicated locations are: 0, 8, 16, 24, 32, 40, 48, and 56. Any of
these addresses may be used to store the first instruction(s) of
a routine designed to service the requirements of an
interrupting device. Since the (RST) is a call, completion of the
instruction also stores the old program counter contents on the
STACK. Each of the three RESTART inputs, 5.5, 6.5, and 7.5,
has a programmable mask. TRAP is also a RESTART interrupt
but it is nonmaskable.
Since the HS-80C85RH is implemented in CMOS, all of the
advantages of CMOS technology are inherent in the device.
These advantages include low standby and operating
power, high noise immunity, moderately high speed, wide
operating temperature range, and designed-in radiation
hardness. Thus the HS-80C85RH is ideal for weapons and
space applications.
The HS-80C85RH has twelve addressable 8-bit registers.
Four of them can function only as two 16-bit register pairs.
Six others can be used interchangeably as 8-bit registers or
as 16-bit register pairs. The HS-80C85RH register set is as
follows:
MNEMONIC
REGISTER
CONTENTS
ACC or A
Accumulator
8 bits
PC
Program Counter
16-bit Address
BC, DE, HL
General-Purpose
Registers; Data
Pointer (HL)
8 bits x 6 or
16 bits x 3
SP
Stack Pointer
16-bit Address
Flags or F
Flag Register
5 Flags (8-bit space)
The HS-80C85RH uses a multiplexed Data Bus. The
address is split between the higher 8-bit Address Bus and
the lower 8-bit Address/Data Bus. During the first T state
(clock cycle) of a machine cycle the low order address is
sent out on the Address/Data bus. These lower 8 bits may
be latched externally by the Address Latch Enable signal
(ALE). During the rest of the machine cycle the data bus is
used for memory or I/O data.
The HS-80C85RH provides RD, WR, S0, S1, and IO/M
signals for bus control. An Interrupt Acknowledge signal
(INTA) is also provided. HOLD and all Interrupts are
synchronized with the processor’s internal clock. The
HS-80C85RH also provides Serial Input Data (SID) and
Serial Output Data (SOD) lines for simple serial interface.
In addition to these features, the HS-80C85RH has three
maskable, vector interrupt pins, one nonmaskable TRAP
interrupt, and a bus vectored interrupt, INTR.
10
The three maskable interrupts cause the internal execution
of RESTART (saving the program counter in the stack and
branching to the RESTART address) if the interrupts are
enabled and if the interrupt mask is not set. The
nonmaskable TRAP causes the internal execution of a
RESTART vector independent of the state of the interrupt
enable or masks. (See Table 9.)
There are two different types of inputs in the restart
interrupts. RST 5.5 and RST 6.5 are high level-sensitive and
are recognized with the same timing as INTR. RST 7.5 is
rising edge sensitive.
For RST 7.5, only a pulse is required to set an internal flip-flop
which generates the internal interrupt request (a normally high
level signal with a low going pulse is recommended for
highest system noise immunity). The RST 7.5 request flip-flop
remains set until the request is serviced. Then it is reset
automatically. This flip-flop may also be reset by using the
SlM instruction or by issuing a RESET IN to the 80C85RH.
The RST 7.5 internal flip-flop will be set by a pulse on the RST
7.5 pin even when the RST 7.5 interrupt is masked out.
The status of the three RST interrupt masks can only be
affected by the SIM instruction and RESET IN.
The interrupts are arranged in a fixed priority that determines
which interrupt is to be recognized if more than one is
pending as follows: TRAP-highest priority, RST 7.5, RST
6.5, RST 5.5, INTR-lowest priority. This priority scheme does
not take into account the priority of a routine that was started
by a higher priority interrupt. RST 5.5 can interrupt an RST
7.5 routine if the interrupts are re-enabled before the end of
the RST 7.5 routine.
The TRAP interrupt is useful for catastrophic events such as
power failure or bus error. The TRAP input is recognized just
as any other interrupt but has the highest priority. It is not
affected by any flag or mask. The TRAP input is both edge
and level sensitive. The TRAP input must go high and
remain high until it is acknowledged. It will not be recognized
again until it goes low, then high again. This avoids any false
triggering due to noise or logic glitches. Figure 8 illustrates
HS-80C85RH
the TRAP interrupt request circuitry within the HS-80C85RH.
Note that the servicing of any interrupt (TRAP, RST 7.5, RST
6.5, RST 5.5, INTR) disables all future interrupts (except
TRAPs) until an EI instruction is executed.
EXTERNAL INSIDE THE
80C85RH
TRAP
INTERRUPT
TRAP
REQUEST
RESET IN
TRAP
SCHMITT
TRIGGER
RESET
VDD
INTERRUPT
REQUEST
CLK
Q
D
F/F
CLEAR
D
1. A 20pF capacitor should be connected from X2 to ground
to assure oscillator start-up at the correct frequency.
2. A 10MΩ resistor is required between X1 and X2 for bias
point stabilization. In addition, the crystal should have the
following characteristics:
1) Parallel resonance at twice the desired internal clock
frequency
2) CL (load capacitance) ≤ 30pF
3) CS (shunt capacitance) ≤ 7pF
4) RS (equivalent shunt resistance) ≤ 75Ω
5) Drive level: 10mW
6) Frequency tolerance: ±0.005% (suggested)
A parallel-resonant LC circuit may be used as the frequencydetermining network for the HS-80C85RH, providing that its
frequency tolerance of approximately ±10% is acceptable.
The components are chosen from the formula:
TRAP F.F.
INTERNAL
TRAP
ACKNOWLEDGE
FIGURE 8. TRAP AND RESET IN CIRCUIT
The TRAP interrupt is special in that is disables interrupts, but
preserves the previous interrupt enable status. Perform- ing
the first RIM instruction following a TRAP interrupt allows you
to determine whether interrupts were enabled or disabled
prior to the TRAP. All subsequent RIM instructions provide
current interrupt enable status. Performing a RIM instruction
following INTR, or RST 5.5-7.5 will provide current interrupt
enable status, revealing that interrupts are disabled.
The serial I/O system is also controlled by the RIM and SIM
instructions. SID is read by RIM, and SIM sets the SOD data.
Driving the X1 and X2 Inputs
You may drive the clock inputs of the HS-80C85RH with a
crystal, an LC tuned circuit, an RC network, or an external clock
source. The driving frequency may be any value from DC to
4MHz and must be twice the desired internal clock frequency.
The following guidelines should be observed when a crystal
is used to drive the HS-80C85RH clock input:
1
f = ---------------------------------------------------2π L ( Cext + Cint )
To minimize variations in frequency, it is recommended that
you choose a value for Cext that is at least twice that of Cint,
or 30pF. The use of an LC circuit is not recommended for
frequencies higher than approximately 4MHz.
An RC circuit may be used as the frequency-determining
network for the HS-80C85RH if maintaining a precise clock
frequency is of no importance. Variations in the on-chip timing
generation can cause a wide variation in frequency when
using the RC mode. Its advantage is its low component cost.
The driving frequency generated by the circuit shown is
approximately 3MHz. It is not recommended that frequencies
greatly higher or lower than this be attempted.
Figure 9 shows the recommended clock driver circuits.
For driving frequencies up to and including 4MHz you may
supply the driving signal to X1 and leave X2 open-circuited
(Figure 9D).
80C85RH
X1
X1
1
20pF
REXT =
10MΩ
2
-6K
2
X2
FIGURE 9A. QUARTZ CRYSTAL CLOCK DRIVER
X1
1
20pF
CINT =
15pF
80C85RH
X2
FIGURE 9B. RC CIRCUIT CLOCK DRIVER
LOW TIME > 60ns
80C85RH
X1
1
LEXT
CINT =
15pF
CEXT
2
X2
(NOTE)
X2
NOTE: X2 Left Floating.
FIGURE 9C. LC TUNED CIRCUIT CLOCK DRIVER
FIGURE 9D. 0-4MHz INPUT FREQUENCY EXTERNAL CLOCK
DRIVER CIRCUIT
FIGURE 9. CLOCK DRIVER CIRCUITS
11
HS-80C85RH
HS-80C85RH Caveats
Generating An HS-80C85RH Wait State
1. An important caveat that is applicable to CMOS devices
in general is that unused inputs should never be left
floating. This rule also applies to inputs connected to a
three-state bus. The need for external pull-up resistors
during three-state bus conditions is eliminated by the
presence of regenerative latches on the following
HS-80C85RH output pins: AD0-AD7, A8-A15, and IO/M.
Figure 10 depicts an output and corresponding
regenerative latch. When the output driver assumes the
high impedance state, the latch holds the bus in whatever
logic state (high or low) it was before the three-state
condition. A transient drive current of approximately
±1.0mA at 0.5VDD for 10ns is required to switch the
latch. Thus, CMOS device inputs connected to the bus
are not allowed to float during three-state conditions.
2. The RD and WR pins of the HS-80C85RH contain internal
dynamic pull-up transistors to avoid spurious selection of
memory devices when the RD and WR pins assume the
high impedance state. This eliminates the need for
external resistive pull-ups on these pins.
If your system requirements are such that slow memories or
peripheral devices are being used, the circuit shown in
Figure 11 may be used to insert one WAIT state in each
HS-80C85RH machine cycle.
The D flip-flops should be chosen so that:
1. CLK is rising edge-triggered
2. CLEAR is low-level active
The READY line is used to extend the read and write pulse
lengths so that the 80C85RH can be used with slow
memory. HOLD causes the CPU to relinquish the bus when
it is through with it by floating the Address and Data Buses.
ALE
(NOTE)
VDD
CLEAR
CLK
“D”
F/F
D
80C85RH
CLK
OUTPUT
Q
CLK
D
“D”
F/F
TO
80C85RH
READY
INPUT
Q
3. The RESET IN and X1 inputs on the HS-80C85RH are
schmit trigger inputs. This eliminates the possibility of
internal oscillations in response to slow rise time input
signals at these pins.
NOTE: ALE and CLK (OUT) should be buffered if CLK input of latch
exceeds 80C85RH IOL or IOH.
4. A high frequency bypass capacitor of approximately
0.1µF should be connected between VDD and GND to
shunt power supply transients.
System Interface
5. The HS-80C85RH is functional within 10 input clock
cycles after application of power (assuming that reset has
been asserted from power-on). Start up conditions in the
crystal controlled oscillator mode must also account for
the characteristics of the oscillator.
FIGURE 11. GENERATION OF A WAIT STATE FOR
HS-80C85RH CPU
The HS-80C85RH family includes memory components,
which are directly compatible to the HS-8OC8SRH CPU. For
example, a system consisting of the three radiationhardened chips, HS-80C85RH, HS-81C56RH, and
HS-83C55RH will have the following features:
1. 2K Bytes ROM
2. 256 Bytes RAM
3. 1 Timer/Counter
OUTPUT
PIN
OUTPUT
DRIVER
REGENERATIVE
LATCH
FIGURE 10. OUTPUT DRIVER AND LATCH FOR PINS
AD0-AD7, A8-A15 AND IO/M
4. 4 8-bit I/O Ports
5. 1 6-bit I/O Port
6. 4 Interrupt Levels
7. Serial In/Serial Out Ports
This minimum system, using the standard I/O technique is
as shown in Figure 12.
In addition to standard 1/0, the memory mapped I/O offers
an efficient I/O addressing technique. With this technique, an
area of memory address space is assigned for I/O address,
thereby, using the memory address for I/O manipulation.
Figure 13 shows the system configuration of Memory
Mapped I/O using HS-80C85RH.
The HS-80C85RH CPU can also interface with the standard
radiation-hardened memory that does not have the
multiplexed address/data bus. It will require use of the
HS-82C12RH (8-bit latch) as shown in Figure 14.
12
HS-80C85RH
VSS
VDD
RESET IN
X1
X2
TRAP
HOLD
RST 7.5
HLDA
RST 6.5
SOD
HS-80C85RH
RST 5.5
SID
INTR
S1
RESET
S0
INTA ADDR/
OUT
ADDR DATA ALE RD WR IO/M
RDY CLK
(8)
VSS VDD
(8)
CE
WR
RD
ALE
(8)
PORT
B
(8)
PORT
C
IN
TIMER
OUT
(6)
PORT
A
(8)
DATA/
ADDR
PORT
IO/M
B
RESET
RDY (NOTE)
IOR
CLK
(8)
HS-81C56RH
PORT
A
DATA/
ADDR
IO/M
RESET
HS-83C55RH
IOW
RD
ALE
CE
A0-10
VDD
VSS VDD
VDD
NOTE: Optional connection.
FIGURE 12. HS-80C85RH MINIMUM SYSTEM (STANDARD I/O TECHNIQUE)
A8-15
AD0-7
ALE
HS-80C85RH
RD
WR
IO/M
CLK
RESET OUT
READY
(6)
(8)
(8)
(8)
RST
CLK
RD
IOW
ALE
IO/M
AD0-7
CE
HS-83C55RH
(ROM +I/O)
(NOTE) RDY
HS-81C56RH
(RAM + I/O + COUNTER/TIMER)
A8-10
IO/M
TIMER OUT
AD0-7
RESET
TIMER
(NOTE) IN
WR
RD
ALE
CE
VDD
(8)
NOTE: Optional connection.
FIGURE 13. HS-80C85RH MINIMUM SYSTEM (MEMORY MAPPED I/O)
13
HS-80C85RH
VSS VDD
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
INTA
ADDR
(8)
X1
X2
RESET IN
HOLD
HLDA
SOD
HS-80C85RH
SID
S1
RESET
S0
ADDR/
DATA ALE RD WR IO/M OUT RDY CLK
(8)
IO/M (CS)
WR
RD
STANDARD
MEMORY
HS-82C12RH
DATA
ADDR (CS)
CLK
RESET
(16)
IO/M (CS)
I/O PORTS,
CONTROLS
WR
RD
DATA
STANDARD
I/O
ADDR
VDD
VDD
VDD
FIGURE 14. HS-80C85RH SYSTEM (USING STANDARD MEMORIES)
14
HS-80C85RH
Basic System Timing
A machine cycle normally consists of three T states, with the
exception of OPCODE FETCH, which normally has either
four or six T states (unless WAIT or HOLD states are forced
by the receipt of READY or HOLD inputs). Any T state must
be one of ten possible states, shown in Table 11.
The HS-80C85RH has a multiplexed Data Bus. ALE is used
as a strobe to sample the lower 8-bits of address on the Data
Bus. Figure 15 shows an instruction fetch, memory read and
I/O write cycle (as would occur during processing of the OUT
instruction). Note that during the I/O write and read cycle that
the I/O port address is copied on both the upper and lower
half of the address.
TABLE 6. HS-80C85RH MACHINE STATE CHART
STATUS AND BUSES
CONTROL
MACHINE
STATE S1, S0 IO/M A8-15 AD0-7 RD, WR INTA ALE
There are seven possible types of machine cycles. Which of
these seven takes place is defined by the status of the three
status lines (lO/M, S1, S0) and the three control signals (RD,
WR, and INTA). (See Table 10.) The status lines can be
used as advanced controls (for device selection, for
example), since they become active at the T1 state, at the
outset of each machine cycle. Control lines RD and WR are
used as command lines since they become active when the
transfer of data is to take place.
TABLE 5. HS-80C85RH MACHINE CYCLE CHART
STATUS
MACHINE CYCLE
CONTROL
IO/M S1 S0 RD WR INTA
T1
X
X
X
X
1
1
1†
T2
X
X
X
X
X
X
0
TWAIT
X
X
X
X
X
X
0
T3
X
X
X
X
X
X
0
T4
1
0††
X
TS
1
1
0
T5
1
0††
X
TS
1
1
0
T6
1
0††
X
TS
1
1
0
TRESET
X
TS
TS
TS
TS
1
0
THALT
0
TS
TS
TS
TS
1
0
THOLD
X
TS
TS
TS
TS
1
0
Opcode Fetch (OF)
0
1
1
0
1
1
Memory Read (MR)
0
1
0
0
1
1
Memory Write (MW)
0
0
1
1
0
1
0 = Logic “0”
1 = Logic “1”
I/O Read
(IOR)
1
1
0
0
1
1
I/O Write
(IOW)
1
0
1
1
0
1
† ALE not generated during 2nd and 3rd machine cycles of DAD
1
1
1
1
1
0
Acknowledge (INA)
of INTR
Bus Idle
(BI)
DAD Ack. of
0
1
0
1
1
1
RST, TRAP
1
1
1
1
1
1
TS
0
0
HALT
TS TS
instruction.
†† IO/M = 1 during T4, T6 of INA machine cycle.
1
M1
CLK
A8-A15
AD0-7
T1
T2
M2
T3
T4
PCH (HIGH ORDER ADDRESS)
ALE
T1
T2
M3
T3
(PC + 1)H
(PC+1)L
PCL
(LOW ORDER
ADDRESS)
TS = High Impedance
X = Unspecified
DATA FROM
MEMORY
(INSTRUCTION)
T1
T2
T3
T
IO PORT
IO PORT
DATA TO
MEMORY OR
PERIPHERAL
DATA FROM
MEMORY (I/O
PORT ADDRESS)
RD
WR
IO/M
STATUS
S1-S0 (FETCH)
10 (READ)
FIGURE 15. 80C85RH BASIC SYSTEM TIMING
15
01 WRITE
11
HS-80C85RH
Die Characteristics
DIE DIMENSIONS:
Substrate:
229 mils x 240 mils x 14 mils ±1 mil
Radiation Hardened Silicon Gate,
Dielectric Isolation
INTERFACE MATERIALS:
Backside Finish:
Glassivation:
Silicon
Type: SiO2
Thickness: 8kÅ ±1kÅ
ASSEMBLY RELATED INFORMATION:
Top Metallization:
Substrate Potential:
Type: SiAl
Thickness: 11kÅ ±2kÅ
Unbiased (DI)
(36) RESET IN
(37) CLOCK OUT
(38) HLDA
(39) HOLD
(40) VDD
(1) X1
(2) X2
HS-80C85RH
(3) RESET OUT
(4) SOD
(5) SID
Metallization Mask Layout
TRAP (6)
(35) READY
RST 7.5 (7)
(34) IO/M
RST 6.5 (8)
RST 5.5 (9)
(33) S1
(32) RD
INTR (10)
INTA (11)
(31) WR
AD0 (12)
(30) ALE
(29) S0
(28) A15
AD1 (13)
AD2 (14)
(27) A14
(26) A13
(25) A12
AD3 (15)
16
A11 (24)
A10 (23)
A9 (22)
A8 (21)
AD7 (19)
GND (20)
AD6 (18)
AD5 (17)
AD4 (16)