5 4 3 2 1 LAN9252-DIG-IO-EVB LAN9252(Config 4-DIG-I/O) D Page No. C Schematic Page 1 Title 2 3 Block Diagram Power Supply & RST 4 LAN9252 (part1) 5 Copper Mode Interface 6 SFP Interface 7 STRAP,GPIO,I2C & FXLOS LAN9252 (part2) 8 9 D C DIG-I/O B B A A Chennai India Part Number: LAN9252-DIG-IO-EVB Size: Project Name:LAN9252-DIG-IO-EVB Date: 5 4 3 2 B Page: Board Name: TITLE Rev EVB3-9252-DIG-I/O-RevB Sheet Wednesday, October 22, 2014 1 1 of B 9 5 4 3 2 1 D D LAN9252-DIG-IO-EVB BLOCK DIAGRAM DIG I/O CKT C C 5V 3V3 RST POWER GND LAN9252 STRAPS Crystal GPIO/LED's EEPROM B B FIBER(SFP) PORT0: INT PHY PORT0: CU INT PHY PORT1: CU FIBER(SFP) PORT1: A A Chennai India Part Number: LAN9252-DIG-IO-EVB Size: Project Name:LAN9252-DIG-IO-EVB Date: 5 4 3 2 B Page: Board Name: Block Diagram Rev EVB3-9252-DIG-I/O-RevB Sheet Wednesday, October 22, 2014 1 2 of B 9 5 4 3 2 1 D D POWER SUPPLY 5V_SW 3 EN12_1 2A/0.05DCR 2 R1 Switch, SPDT, Slide P/N:1101M2S3CQE2 J1 2 1 0E C2 10uF 25V VIN ENABLE VOUT TRIM 3_Amp GND C3 4 5 3 OKR-T/3-W12-C 0.1uF R2 VOUT_3V3 DNP C1 R3 3.30K 1% R4 470E 1% (Ra) (Rb) R4A 33E 1% C4 C5 10uF 0.1uF 1K 4.7uF 1 3 U1 FB1 2 A 1 D1 GRN C 5V_EXT 3V3 3V3 "3V3 Present" SW1 1 TP2 ORANGE 3 V REGULATOR, 3A ( 3V3 fixed when Rb=470E) 5V 2 TP1 RED C C RESET Options 3V3 3V3 3V3 Reset Generator 2 B RESET# RESET NDS355AN_NMOS 1 D RST# Q1 3 R8 1K 1 G 5 MR# 2 3V3 VDD 4 5 U2 2 1/10W 1% 3 sw_pb_2P 1 R7 100 GND SW2 R5 4.75K 1% 0.1uF 2 1 C6 R6 10.0K 1/10W 1% Note: 1.POR -> Reset to ASIC & SOC (Default) 2.RESET O/P from ASIC -> Reset to EX-PHY (PORT2) & SOC :Only Ethercat sku 3.RESET from SOC (GPIO/RST-O/P) -> Reset to ASIC 4.RESET from Push Botton -> Reset to ASIC & SOC RED U3 S 2 4 1 R9 TPS3125 2.2K 74LVC1G14 C B 2 D2 "Reset" 1 3 SOT23_5 Threshold = 2.64V Delay = 180ms A A A TP3 BLACK TP4 BLACK Chennai India Part Number: LAN9252-DIG-IO-EVB Size: Project Name:LAN9252-DIG-IO-EVB Date: 5 4 3 2 B Page: Board Name: Power Supply & RST Rev EVB3-9252-DIG-I/O-RevB Sheet Tuesday, October 21, 2014 1 3 of B 9 5 4 3 2 1 Power Supply Filtering 3V3 VDD33TXRX1 3V3 FB2 D C25 0.1uF C20 C21 C22 470pF 0.1uF 0.1uF C19 1uF C16 C17 0.1uF 0.1uF 0.1uF C14 C15 0.1uF DNP C13 C12 C11 FB5 2A/0.05DCR BLM18EG221SN1D 56 59 6 24 38 14 20 32 37 47 58 5 U4A 51 64 VDD12TX1 VDD12TX2 0.1uF 1.0uF Low ESR 2A/0.05DCR BLM18EG221SN1D C24 C18 DNP C23 0.1uF TP72 SMT VDDCR 0.1uF 2A/0.05DCR 3V3 1.0uF 3V3 FB4 0.1uF 3V3 VDD33TXRX2 FB3 0.1uF 0.1uF C10 DNP C9 C8 1.0uF 1.0uF VDDCR VDD12TX1 VDD12TX2 VDD33TXRX1 VDD33TXRX2 2A/0.05DCR D DNP C7 18pF REG_EN R10 12.1K 1% RBIAS RST# TP71 WHITE DNP IRQ ATEST/FXLOSEN 7 57 11 44 8 41 B I2C2_SCL I2C2_SDA 43 42 GPIO0 GPIO1 GPIO2 48 46 45 VDD12TX1 VDD12TX2 VDDCR1 VDDCR2 VDDCR3 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 FXSDENA/FXSDA/FXLOSA INT PORT0 C27 OSCVDD12 OSCI OSCO OSCVSS REG_EN RBIAS RST# TXNA TXPA RXNA RXPA 9 FXSDA/FXLOSA 52 53 54 55 TXNA TXPA RXNA RXPA 63 62 61 60 TXNB TXPB RXNB RXPB 10 FXSDB/FXLOSB IRQ ATEST/FXLOSEN TESTMODE I2CSCL/EESCL/TCK I2CSDA/EESDA/TMS INT PORT1 (Only for Lan9252) 1 3V3 3 1 2 4 OTHER SIGNALS OSCI OSCO I2C 25.000MHz 25ppm Y1 OSC POWER 18pF 2 C26 VDD33BIAS VDD33 C Note: OSCVSS need to connect to Chip gnd. VDD33TXRX1 VDD33TXRX2 C TXNB TXPB RXNB RXPB FXSDENB/FXSDB/FXLOSB B LINKACTLED0/TDO/LEDPOL0/CHIP_MODE0 LINKACTLED1/TDI/LEDPOL1/CHIP_MODE1 RUNLED/LEDPOL2/E2PSIZE GND GPIO 65 LAN9252 A A Chennai India Part Number: LAN9252-DIG-IO-EVB Size: Project Name:LAN9252-DIG-IO-EVB Date: 5 4 3 2 B Page: Board Name: LAN9252 (Part1) Rev EVB3-9252-DIG-I/O-RevB Sheet Tuesday, October 21, 2014 1 4 of B 9 5 4 3 2 1 VDD33TXRX1 FX_SFP-RXPA DNP R22 R23 0E 0E RXNA 2 COP-RXPA 3 10 75 A 1 75 TXCT 4&5 TD- 2 RCV 5 FX_SFP-RXNA TD+ 6 COP-RXNA DNP C29 10pF 50V 5% DNP C30 10pF 50V 5% DNP C31 10pF 50V 5% 50V 10% 7 8 75 3 75 7&8 RXCT 6 RD- 1000 pF NC CHS GND 13 C 14 GND DNP C28 10pF 50V 5% C32 0.022uF RD+ Note: Capacitors C28 through C31 are optional for EMI purposes and are not populated on the LAN9252 evaluation board. These capacitors are required for operation in an EMI constrained environment. 2 kV YEL R24 C A1 0E 0E COP-TXNA D 12 DNP R20 R21 RXPA 4 RJ45 C1 FX_SFP-TXNA 1 COP-TXPA 11 0E 0 GRN XMIT MTG1 TXNA DNP R18 R19 FX_SFP-TXPA R15 0E MTG 0E 0E R14 49.9 1/10W 1% 16 DNP R16 R17 R13 49.9 1/10W 1% 15 TXPA R12 49.9 1/10W 1% C R11 49.9 1/10W 1% GND1 D T1 Pulse J0011D01BNL 9 PORT0 0E RES1210 VDD33TXRX2 PORT1 1 COP-TXPB 4 3 75 9 75 TXCT 4&5 TD- 2 RCV 5 FX_SFP-RXNB B 1 6 COP-RXNB DNP C34 10pF 50V 5% DNP C35 10pF 50V 5% DNP C36 10pF 50V 5% 50V 10% 7 8 75 75 6 RD- 1000 pF NC CHS GND 13 A 3 7&8 RXCT GND DNP C33 10pF 50V 5% C37 0.022uF RD+ 2 kV YEL A A1 0E 0E COP-RXPB RJ45 12 DNP R36 R37 FX_SFP-RXPB 2 C1 0E 0 COP-TXNB 11 DNP R34 R35 FX_SFP-TXNB TD+ MTG1 0E 0 A C GRN XMIT MTG RXNB R29 0E 16 RXPB FX_SFP-TXPB R28 49.9 1/10W 1% 15 DNP R32 R33 TXNB 0E 0E R27 49.9 1/10W 1% GND1 TXPB R26 49.9 1/10W 1% 14 DNP R30 R31 B R25 49.9 1/10W 1% 10 T2 Pulse J0011D01BNL Chennai India Note: Capacitors C33 through C36 are optional for EMI purposes and are not populated on the LAN9252 evaluation board. These capacitors are required for operation in an EMI constrained environment. R38 0E RES1210 Part Number: LAN9252-DIG-IO-EVB Size: Project Name:LAN9252-DIG-IO-EVB Date: 5 4 3 2 B Page: Board Name: Copper Mode Interface Rev EVB3-9252-DIG-I/O-RevB Sheet Tuesday, October 21, 2014 1 5 of B 9 5 4 3V3 R39 82 D R40 82 R41 49.9 R42 49.9 3 Note:Place capacitors, and resistors close to FOT 3V3 Fiber Port 0 :SFP Interface R43 82 FX_SFP-RXNA C38 FX_SFP-RXPA C40 0.1uF FX_SFP-TXPA C42 0.1uF R44 82 R45 49.9 2 1 Note:Place capacitors, and resistors close to FOT Fiber Port 1 :SFP Interface R46 49.9 0.1uF FX_SFP-RXNB C39 0.1uF FX_SFP-RXPB C41 0.1uF FX_SFP-TXPB C43 0.1uF D R47 3V3 R48 3V3 SFP_VCCT 100 SFP_VCCT2 100 0.1uF L2 SFP_VCCR C45 + C47 C48 10uF 16V 0.1uF + 0.1uF C49 0.1uF R51 130 SFP_VCCR2 SFP_TD2SFP_TD2+ R50 130 SFP_RD+ SFP_RD- R49 130 SFP_TDSFP_TD+ FX_SFP-TXNB C46 10uF 16V DNP 1uH 1uH R52 130 C50 10uF 16V DNP SFP_RD2+ SFP_RD2- C44 FX_SFP-TXNA L1 + C51 C52 10uF 16V 0.1uF L3 L4 B R53 4.7K R54 4.7K C55 VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 + Note:Place resistors close to 0.1uF ASIC J3 FTLF1217P2 R55 4.7K VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 C54 10uF 16V 31 30 29 28 27 26 25 24 23 22 21 31 30 29 28 27 26 25 24 23 22 21 C56 10uF 16V + C57 0.1uF SFP_VCCT2 1 2 3 4 5 6 7 8 9 10 SFP_VCCT 31 30 29 28 27 26 25 24 23 22 21 1uH 1 2 3 4 5 6 7 8 9 10 J2 FTLF1217P2 VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 ASIC 31 30 29 28 27 26 25 24 23 22 21 0.1uF C 20 19 18 17 16 15 14 13 12 11 VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 Note:Place resistors close to C53 1uH 20 19 18 17 16 15 14 13 12 11 C + R57 4.7K R56 4.7K FXSDA/FXLOSA R58 4.7K R59 4.7K B R60 4.7K FXSDB/FXLOSB A A Chennai India Part Number: LAN9252-DIG-IO-EVB Size: Project Name:LAN9252-DIG-IO-EVB Date: 5 4 3 2 B Page: Board Name: SFP Interface Rev EVB3-9252-DIG-I/O-RevB Sheet Tuesday, October 21, 2014 1 6 of B 9 5 4 3 2 1 GPIO [0:2] & LED_POL_Strap 3V3 J8 R67 R68 R66 8 VCC SDA SCL WP SW DIP-4/SM 24FC512 5 I2C2_SDA 6 I2C2_SCL TH IC. Different sizes can be mounted *(2-3) GPIO2 I2C EEPROM Lower size Below 16K(2K X 8) (24FC04) 3 1 3 *(1-2) 1 A0 A1 A2 2 2 2 3 1 C D GND 1 2 3 I2C2_1 I2C2_2 I2C2_3 I2C2_7 7 R74 1K J9 *(2-3) 2K R65 4.7K 1 2 3 4 4 8 7 6 5 R73 1K U5 SW3 2 2 LED1_CATHODE 2 J7 0.1uF 2K R64 4.7K R71 10.0K Default: All 4 signals ON GPIO0 C58 LED1_ANODE 1 1 R70 10.0K LED0_CATHODE LED2_CATHODE R72 1K 3V3 GPIO2 *(2-3) 2 2 1 LED0_ANODE LED2_ANODE R69 10.0K GPIO1 R63 J5 *(1-2) 3V3 GPIO0 3 1 3 J6 *(2-3) I2C EEPROM 3V3 GPIO1 2 J4 1 3 1 D GPIO2 4.7K 3V3 GPIO0 4.7K 3V3 Signals Functions GPIO1 C GPIO0 = LINKACTLED0/TDO/LEDPOL0/CHIP_MODE0 I2C EEPROM Higher size Above 16K(2K X 8) (24FC512 ) GPIO1 =LINKACTLED1/TDI/LEDPOL1/CHIP_MODE1 GPIO2 = RUNLED/LEDPOL2/E2PSIZE LINK/ACT for PORT0 LED0_ANODE LED0_CATHODE D3 1 GRN A 2 C CHIP_MODE[1:0] Strap Details CHIP_MODE[1:0] LINK/ACT for PORT1 LED1_ANODE LED1_CATHODE D4 1 GRN A 2 C LED2_ANODE LED2_CATHODE D5 1 GRN A Port 0 = PHY A, Port 1 = PHY B 00[Default] 01 RUNLED 2 C 10 11 B Port Description 3V3 2 PORT MODE RESERVED RESERVED Port 0 = PHY A, Port 1 = PHY B, Port 2 = MII Port 0 = MII, Port 1 = PHY B, Port 2 = PHY A 3 PORT DOWNSTREAM MODE FX_Mode_Strap_1 & 2 FX_Los_Strap_1 & 2 MODE DNP R77 10K FXSDA/FXLOSA R79 10K FXSDB/FXLOSB CHIP_MODE0 CHIP_MODE1 0 1 J4,J7 (1&2) The LED is set as active low, R77 R79 The LED is set as active high. Poupulate DNP 0 J5,J8 (2&3) Default E2PSIZE 1 J5,J8 (1&2) 0 J6,J9 (2&3) 1 A J6,J9 (1&2) Default R76 10K DNP R78 10K R80 10K 3V3 B LED Polarity Strap Connector J4,J7 (2&3) Default Logic 10K ATEST/FXLOSEN 3 PORT UPSTREAM MODE Strap Details Signal Name 3V3 DNP R75 The LED is set as active high. Ref.Voltage 3V3 Poupulate Poupulate 1V5 DNP Poupulate (Default) (Default) The LED is set as active low, The LED is set as active high. EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8) The LED is set as active low, EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only) [Default] (Default) 0 Function PORT MODE PORT0 Copper (Default) Fiber Above 2 V selects FX-LOS for ports 0 and 1 Level of 1.5 V selects FX-LOS for port 0 and FX-SD/copper twisted pair for port 1 further determined by FXSDB Level of 0V Selects FX-SD / copper twisted pair for ports A and B further determined by FXSDA and FXSDB. PORT1 Poupulate Copper (Default) Fiber DNP R76 R75 R75 R76 R80 R78 R78 R80 Note: --To use GPIOs as LED * Short 2-3 of both jumpers (ex. for GPIO0 short 2-3 of J4 & J7) A Chennai India Part Number: LAN9252-DIG-IO-EVB Size: Project Name:LAN9252-DIG-IO-EVB Date: 5 4 3 2 B Page: Board Name: STRAP,GPIO,I2C & FXLOS Rev EVB3-9252-DIG-I/O-RevB Sheet Tuesday, February 24, 2015 1 7 of B 9 5 4 3 2 1 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 DIG-IO D D 19 OUTVALID C 1 20 A0 A1 A2 A3 A4 A5 A6 A7 DIR VCC U6 2 3 4 5 6 7 8 9 DIGIO0 DIGIO1 DIGIO2 DIGIO3 DIGIO4 DIGIO5 DIGIO6 DIGIO7 OE OUT_BUF_DIGIO0 OUT_BUF_DIGIO1 OUT_BUF_DIGIO2 OUT_BUF_DIGIO3 OUT_BUF_DIGIO4 OUT_BUF_DIGIO5 OUT_BUF_DIGIO6 OUT_BUF_DIGIO7 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 U4B A4/DIGIO12/GPI12/GPO12/MII_RXD0 A3/DIGIO11/GPI11/GPO11/MII_RXDV A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/MII_LINKPOL/LEDPOL6 A1/ALELO/OE_EXT/MII_CLK25 DIGIO15 DIGIO14 DIGIO13 R89 10K 31 30 28 OUTVALID 19 1 20 A0 A1 A2 A3 A4 A5 A6 A7 DIR VCC U7 2 3 4 5 6 7 8 9 DIGIO8 DIGIO9 DIGIO10 DIGIO11 DIGIO12 DIGIO13 DIGIO14 DIGIO15 OE 74LC245A/SO B0 B1 B2 B3 B4 B5 B6 B7 18 17 16 15 14 13 12 11 OUT_BUF_DIGIO8 OUT_BUF_DIGIO9 OUT_BUF_DIGIO10 OUT_BUF_DIGIO11 OUT_BUF_DIGIO12 OUT_BUF_DIGIO13 OUT_BUF_DIGIO14 OUT_BUF_DIGIO15 18 LATCH0 34 33 15 16 21 22 23 19 40 39 36 50 49 35 12 13 17 DIGIO9 DIGIO8 DIGIO7 DIGIO6 DIGIO5 DIGIO4 LATCH_IN DIGIO2 DIGIO1 DIGIO0 OUTVALID DIGIO3 WD_TRIG SOF EOF WD_STATE C SYNC/LATCH1 SYNC/LATCH0 A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1 D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0 D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1 D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0 D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN D9/AD9/LATCH_IN/SCK D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK D5/AD5/OUTVALID/SCS# D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK D3/AD3/WD_TRIG/SIO3 D2/AD2/SOF/SIO2 D1/AD1/EOF/SO/SIO1 D0/AD0/WD_STATE/SI/SIO0 LAN9252 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 B GND B LATCH1 DIGIO12 DIGIO11 DIGIO10 OE_EXT 10 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K R90 R91 R92 R93 R94 R95 R96 R97 3V3 27 26 29 25 RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3 WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2 CS/DIGIO13/GPI13/GPO13/MII_RXD1 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 3V3 18 17 16 15 14 13 12 11 10 74LC245A/SO B0 B1 B2 B3 B4 B5 B6 B7 GND 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K R81 R82 R83 R84 R85 R86 R87 R88 3V3 Note: Placement Instruction Place the TPs in 100 mil distance from the respective IN_DIGIOx or OUT_DIGIOx PINS of J10 & J11 Placement should be such a way that, jumpers should be able to added between the test points and J10 or J11 connectors A A Chennai India Part Number: LAN9252-DIG-IO-EVB Size: Project Name:LAN9252-DIG-IO-EVB Date: 5 4 3 2 B Page: Board Name: LAN9252-Part2 Rev EVB3-9252-DIG-I/O-RevB Sheet Wednesday, October 22, 2014 1 8 of B 9 5 4 3 J10 3 OUT_DIGIO0 IN_DIGIO1 DIGIO1 4 5 6 OUT_DIGIO1 IN_DIGIO2 DIGIO2 7 8 9 OUT_DIGIO2 IN_DIGIO3 DIGIO3 10 11 12 OUT_DIGIO3 Default SW4 & SW5 are in OFF position (Pullup active) For Pull Down, move SW4 & SW5 to ON position D 3V3 Digital OUTPUTS OUT_DIGIO0 13 14 15 IN_DIGIO5 DIGIO5 16 17 18 IN_DIGIO6 DIGIO6 19 20 21 IN_DIGIO7 DIGIO7 22 23 24 R98 R99 R100 R101 R102 R103 R104 R105 IN_DIGIO4 DIGIO4 OUT_DIGIO1 OUT_DIGIO4 OUT_DIGIO2 OUT_DIGIO3 10K 10K 10K 10K 10K 10K 10K 10K D 1 2 OUT_DIGIO5 SW4 OUT_DIGIO4 1 2 3 4 5 6 7 8 IN_DIGIO0 IN_DIGIO1 IN_DIGIO2 IN_DIGIO3 IN_DIGIO4 IN_DIGIO5 IN_DIGIO6 IN_DIGIO7 OUT_DIGIO6 OUT_DIGIO7 HDR_3x8 3 6 OUT_DIGIO6 OUT_DIGIO7 9 IN_DIGIO11 DIGIO11 10 11 12 OUT_DIGIO10 OUT_DIGIO9 OUT_DIGIO11 OUT_DIGIO12 OUT_DIGIO10 R106 R107 R108 R109 R110 R111 R112 R113 7 8 OUT_DIGIO9 Default: All 8 Signals OFF OUT_DIGIO13 OUT_DIGIO11 IN_DIGIO12 DIGIO12 13 14 15 IN_DIGIO13 DIGIO13 16 17 18 OUT_DIGIO13 IN_DIGIO14 DIGIO14 19 20 21 OUT_DIGIO14 IN_DIGIO15 DIGIO15 22 23 24 OUT_DIGIO15 OUT_DIGIO14 10K 10K 10K 10K 10K 10K 10K 10K IN_DIGIO10 DIGIO10 B OUT_DIGIO5 SW DIP-8 OUT_DIGIO8 3V3 4 5 IN_DIGIO9 DIGIO9 16 15 14 13 12 11 10 9 OUT_DIGIO8 J11 1 2 IN_DIGIO8 DIGIO8 C 1 Digital INPUTS 1-2 side short of J10 = Input Mode (Default) 2-3 side short of J10 = Output Mode I/P O/P IN_DIGIO0 DIGIO0 2 OUT_DIGIO12 SW5 OUT_DIGIO15 1 2 3 4 5 6 7 8 IN_DIGIO8 IN_DIGIO9 IN_DIGIO10 IN_DIGIO11 IN_DIGIO12 IN_DIGIO13 IN_DIGIO14 IN_DIGIO15 1K R114 1K R115 1K R116 1K R117 1K R118 1K R119 1K R120 1K R121 1K R122 1K R123 1K R124 1K R125 1K R126 1K R127 1K R128 1K R129 D6 1 GRN D7 1 GRN D8 1 GRN D9 1 GRN D10 1 GRN D11 1 GRN D12 1 GRN D13 1 GRN D14 1 GRN D15 1 GRN D16 1 GRN D17 1 GRN D18 1 GRN D19 1 GRN D20 1 GRN D21 1 GRN 2 A C A C A C A C A C A C A C A C A C A C A C A C A C A C A C A C 2 2 2 2 2 2 2 2 2 C 2 2 2 2 2 2 16 15 14 13 12 11 10 9 SW DIP-8 HDR_3x8 B Default: All 8 Signals OFF 1-2 side short of J11 = Input Mode (Default) 2-3 side short of J11 = Output Mode 3V3 WD_STATE R130 DIG-IO JUMPER OPTIONS 1K D22 1 GRN A DIGIO0 DIGIO1 DIGIO2 DIGIO3 DIGIO4 DIGIO5 DIGIO6 DIGIO7 DIGIO8 DIGIO9 DIGIO10 DIGIO11 DIGIO12 DIGIO13 DIGIO14 DIGIO15 2 C LED for WD_STATE J12 4 J10 & J11 1 2 3 TP13 to 20 TP29 to 36 WD_STATE EOF SOF LATCH0 LATCH1 WD_TRIG OE_EXT OUTVALID LATCH_IN 5 Short 1-2 = Input Mode 1 2 Short 2-3 = Output Mode 2 3 Short 1-4 & 3-5 = Bidirectional Mode 4 1 2 3 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 3V3 R131 100K SW6 R132 R133 R134 R135 R136 TP5 to 12 TP21 to 28 5 LATCH_IN sw_pb_2P Default Short: Pins 15-16 - OE_EXT 10K 10K 10K 10K 10K A A C59 0.1uF Chennai India Part Number: LAN9252-DIG-IO-EVB Size: Project Name:LAN9252-DIG-IO-EVB Date: 5 4 3 2 B Page: Board Name: DIG-I/O Rev EVB3-9252-DIG-I/O-RevB Sheet Tuesday, February 24, 2015 1 9 of B 9