INTERSIL CDP1883C

CDP1883,
CDP1883C
TM
CMOS 7-Bit Latch
and Decoder Memory Interfaces
March 1997
Features
Description
• Performs Memory Address Latch and Decoder Functions Multiplexed or Non-Multiplexed
The CDP1883 is a CMOS 7-bit memory latch and decoder
circuit intended for use in CDP1800-series microprocessor
systems. It can serve as a direct interface between the multiplexed address bus of this system and up to four 8K x 8-bit
memories to implement a 32K-byte memory system. With
four 4K x 8-bit memories, a 16K-byte system can be
decoded.
• Interfaces Directly with the CDP1800-Series Microprocessors
• Allows Decoding for Systems Up to 32K Bytes
Ordering Information
5V
10V
CDP1883CE CDP1883E
TEMP.
RANGE
-40oC to
+85oC
PACKAGE
PDIP
PKG.
NO.
E20.3
The device is also compatible with non-multiplexed address
bus microprocessors. By connecting the clock input to VDD ,
the latches are in the data-following mode and the decoded
outputs can be used in general-purpose memory-system
applications.
The CDP1833 is compatible with CDP1800-series microprocessors operating at maximum clock frequency.
The CDP1883 and CDP1883C are functionally identical.
They differ in that the CDP1883 has a recommended operating voltage range of 4V to 10.5V and the C version has a
recommended operating voltage range of 4V to 6.5V.
The CDP1883 and CDP1883C are supplied in 20 lead dualin-line plastic packages (E Suffix).
Pinout
CDP1883, CDP1883C
(PDIP)
TOP VIEW
CLOCK
1
20 VDD
MA0
2
19 A8
MA1
3
18 A9
MA2
4
17 A10
MA3
5
16 A11
MA4
6
15 A12
MA5
7
14 CS0
MA6
8
13 CS1
CE
9
12 CS2
VSS 10
11 CS3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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129
File Number
1507.2
CDP1883, CDP1883C
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (V DD)
(All Voltages Referenced to VSS Terminal)
CDP1883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1883C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Resistance (Typical)
θJA ( oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
Storage Temperature Range (TSTG) . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges:
CDP1883
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
VSS
VDD
VSS
VDD
V
DC Operating Voltage Range
Input Voltage Range
At TA = -40oC to +85oC, VDD ± 5%, Except as Noted:
Static Electrical Specifications
CONDITIONS
PARAMETER
Quiescent Device
Current
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage
Low-Level (Note 2)
Output Voltage
High-Level (Note 2)
Input Low Voltage
Input High Voltage
Input Leakage Current
Operating Current
(Note 3)
CDP1883C
CDP1883
CDP1883C
SYMBOL
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
IDD
-
0, 5
5
-
1
10
-
5
50
µA
-
0, 10
10
-
10
100
-
-
-
µA
0.4
0, 5
5
1.6
3.2
-
1.6
3.2
-
mA
0.5
0, 10
10
3.2
6.4
-
-
-
-
mA
4.6
0, 5
5
-1.15
-2.3
-
-1.15
-2.3
-
mA
9.5
0, 10
10
-2.3
-4.6
-
-
-
-
mA
-
0, 5
5
-
0
0.1
-
0
0.1
V
-
0, 10
10
-
0
0.1
-
-
-
V
-
0, 5
5
4.9
5
-
4.9
5
-
V
-
0, 10
10
9.9
10
-
-
-
-
V
0.5, 4.5
-
5
-
-
1.5
-
-
1.5
V
0.5, 9.5
-
10
-
-
3
-
-
-
V
0.5, 4.5
-
5
3.5
-
-
3.5
-
-
V
0.5, 9.5
-
10
7
-
-
-
-
-
V
Any
Input
0, 5
5
-
-
±1
-
-
±1
µA
0, 10
10
-
-
±2
-
-
-
µA
0, 5
0, 5
5
-
-
2
-
-
2
mA
0, 10
0, 10
10
-
-
4
-
-
-
mA
IOL
IOH
VOL
VOH
VIL
V IH
IIN
IDD1
130
CDP1883, CDP1883C
At TA = -40oC to +85oC, VDD ± 5%, Except as Noted: (Continued)
Static Electrical Specifications
CONDITIONS
PARAMETER
SYMBOL
VO
(V)
VIN
(V)
CDP1883
VDD
(V)
CDP1883C
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
Minimum Data
Retention Voltage
VDR
VDD = VDR
-
2
2.4
-
2
2.4
V
Data Retention Current
IDR
VDD = 2.4V
-
0.01
1
-
0.5
5
µA
Input Capacitance
C IN
-
-
-
-
5
7.5
-
5
7.5
pF
COUT
-
-
-
-
10
15
-
10
15
pF
Output Capacitance
NOTES:
1. Typical values are for TA = +25oC.
2. IOL = IOH = µA
3. Operating current measured at 200kHz for V DD = 5V and 400kHz for V DD = 10V, with outputs open circuit.
Functional Diagram
MA0
2
Q
19
A8
Q
18
A9
Q
17
A10
Q
16
A11
Q
15
A12
D
Q
14
CS0
C
Q
13
CS1
D
Q
C
Q
12
CS2
11
CS3
D
C
MA1
3
D
C
MA2
4
D
C
MA3
5
D
C
MA4
6
D
C
MA5
MA6
CLOCK
7
8
1
VDD = 20
CE
9
VSS =
131
10
CDP1883, CDP1883C
Signal Descriptions/Pin Functions
TRUTH TABLE
CLOCK: Latch Input Control - a high on the clock input will
allow data to pass through the latch to the output pin. Data is
latched on the high-to-low transition of the clock input. This
pin is connected to TPA in CDP1800-series systems and
tied to VDD for other applications.
INPUTS
MA0 - MA4: Address inputs to the high-byte address
latches.
MA5 - MA6: High byte address inputs decoded to produce
chip selects CS0 - CS3.
CE: CHIP ENABLE input - A low on this pin will enable the
chip select decoder. A high on this pin forces CS0, CS1,
CS2, and CS3 outputs to a high (false) state.
A8 - A12: Latched high-byte address outputs.
CS0 - CS3: One of four latched and decoded Chip Select
outputs.
VDD , VSS: Power and ground pins, respectively.
TRUTH TABLE
INPUTS
OUTPUTS
CE
CLK
MA5
MA6
CS0
CS1
CS2
CS3
0
1
0
0
0
1
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
X
X
1
X
X
X
1
1
CE
CLK
MA0 - 4
A8 - A12
X
1
1
1
X
1
0
0
X
0
X
Previous State
X = Don’t Care
Application Information
The CDP1883 and CDP1883C can be interfaced, without
external components, with CDP1800-series microprocessor
systems. These microprocessors feature a multiplexed
address bus and provide an address latch signal (TPA) that
is used as the clock input of the CDP1883. See Figure 2 and
Figure 3.
This signal is used to latch 7 bits of the high-order address.
The lower five high-order address inputs are latched and
held to be used with the eight lower-order address inputs to
access an 8K x 8-bit memory. The two upper high-order
address inputs are latched and decoded for use as chip
selects.
The latched address and decoding functions of the
CDP1883 and CDP1883C allow them to operate with 32Kbyte memory systems. In addition, smaller memory systems
can be configured with 4K x 8-bit or smaller memories, or a
mix of memory sizes up to 8K x 8-bit.
Previous State
1
OUTPUTS
1
132
CDP1883, CDP1883C
Dynamic Electrical Specifications TA = -40oC to +85oC, VDD ± 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF.
See Figure 1
CDP1883
PARAMETER
Minimum Setup Time,
Memory Address to CLOCK
Minimum Hold Time,
Memory Address After CLOCK
Minimum CLOCK Pulse Width
tMACL
tCLMA
tCLCL
CDP1883C
VDD
(V)
MIN
5
-
10
35
-
10
35
ns
10
-
8
25
-
-
-
ns
5
-
8
25
-
8
25
ns
10
-
8
25
-
-
-
ns
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
5
-
75
150
-
75
150
ns
10
-
45
100
-
-
-
ns
5
-
100
175
-
100
175
ns
10
-
65
125
-
-
-
ns
5
-
100
175
-
100
175
ns
10
-
65
125
-
-
-
ns
5
-
100
175
-
100
175
ns
10
-
75
125
-
-
-
ns
5
-
80
125
-
80
125
ns
10
-
40
60
-
-
-
ns
(NOTE 1) (NOTE 2)
TYP
MAX
MIN
(NOTE 1) (NOTE 2)
TYP
MAX
UNITS
PROPAGATION DELAY TIMES
Chip Enable to Chip Select
CLOCK to Chip Select
CLOCK to Address
tCECS
tCLCS
tCLA
Memory Address to Chip Select
Memory Address to Address
tMACS
tMAA
NOTES:
1. Typical values are for TA = 25oC.
2. Maximum limits of minimum characteristics are the values above which all devices function.
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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133
CDP1883, CDP1883C
VALID CHIP ENABLE
CE
tCECS
tCECS
CS0, CS1, CS2, CS3
(A) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY
MA0 - MA5
tMACL
tCLMA
CLOCK
tCLCL
tCLCS
tMACS
tMACS
CS0, CS1, CS2, CS3
tCLA
tMAA
tMAA
A8 - A12
(B) MEMORY ADDRESS SETUP AND HOLD TIME
FIGURE 1. CDP1883 TIMING WAVEFORMS
ADDRESS BUS
A0 - A6
A0 - A7
WAIT
CLR
TPA
CDP1800
SERIES
CPU
A0 - A7
CLK
TPA
CDP1837C
4K x 8
ROM
CDP1883
LATCH/
DECODER
A8 - A12
CDM6264
8K x 8
RAM
CS0
CEO
CE
CS1
CE
CS2
CS3
MRD
OE
MRD
WE
MWR
DATA BUS
FIGURE 2. MINIMUM CDP1800-SYSTEM USING THE CDP1883 INTERFACE WITH AN 8K X 8-BIT MEMORY
134
CDP1883
LATCH/
DECODER
CS3
CLK
CE
CS2
CS1
CS0
MA0 - MA6
A8 - A12
WAIT
ADDRESS BUS
CLR
A8 - A12
TPA
A8 - A12
CE
CE
ADDRESS BUS
CDP1800
SERIES
CPU
A0 - A7
CDM5364
8K x 8
ROM
A8 - A12
A0 - A7
CDM5364
8K x 8
ROM
CE
A0 - A7
CDM5364
8K x 8
ROM
MRD
DATA BUS
FIGURE 3. 32K-BYTE ROM SYSTEM USING THE CDP1883
135
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM