CAN TJF1052i Galvanically isolated high-speed CAN transceiver Rev. 2 — 15 January 2015 Product data sheet 1. General description The TJF1052i is a high-speed CAN transceiver that provides a galvanically isolated interface between a Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus. The TJF1052i is specifically targeted at industrial applications, where galvanic isolation barriers are needed between the high- and low-voltage parts. Safety: Isolation is required for safety reasons, eg. to protect humans from electric shock or to prevent the electronics being damaged by high voltages. Signal integrity: The isolator uses proprietary capacitive isolation technology to transmit and receive CAN signals. This technology enables more reliable data communications in noisy environments, such as electric pumps, elevators or industrial equipment. Performance: The transceiver is designed for high-speed CAN applications, supplying the differential transmit and receive capability to a CAN protocol controller in a microcontroller. Integrating the galvanic isolation along with the transceiver in the TJF1052i removes the need for stand-alone isolation. It also improves reliability and system performance parameters such as loop delay. The TJF1052i belongs to the third generation of high-speed CAN transceivers from NXP Semiconductors, offering significant improvements over first- and second-generation devices. It offers improved ElectroMagnetic Compatibility (EMC) and ElectroStatic Discharge (ESD) performance, and also features ideal passive behavior to the CAN bus when the transceiver supply voltage is off. The TJF1052i implements the CAN physical layer as defined in the current ISO11898 standard (ISO11898-2:2003). Pending the release of the updated version of ISO11898-2 including CAN FD, additional timing parameters defining loop delay symmetry are specified. This implementation enables reliable communication in the CAN FD fast phase at data rates up to 2 Mbit/s. The TJF1052i is an excellent choice for all types of industrial CAN networks where isolation is required for safety reasons or to enhance signal integrity in noisy environments. 2. Features and benefits 2.1 General Isolator and Transceiver integrated into a single SO16 package, reducing board space ISO 11898-2:2003 compliant Loop delay symmetry timing enables reliable communication at data rates up to 2 Mbit/s in the CAN FD fast phase TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver Flawless cooperation between the Isolator and the Transceiver Fewer components improves reliability in applications Guaranteed performance (eg. max loop delay <220 ns) Electrical transient immunity of 45 kV/s (typ) Suitable for use in 12 V and 24 V systems; compatible with 3 V to 5 V microcontrollers Bus common mode voltage (Vcm) = 25 V Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI) Dark green product (halogen free and Restriction of Hazardous Substances (RoHS) compliant) 2.2 Power management Functional behavior predictable under all supply conditions Transceiver disengages from the bus when not powered up (zero load) 2.3 Protection Up to 5 kV (RMS) rated isolation Three versions available (1 kV, 2.5 kV and 5 kV) Voltage compliant with UL 1577, IEC 61010 and IEC 60950 5 kV (RMS) rated isolation voltage compliant with UL 1577, IEC 61010 and IEC 60950 High ESD handling capability on the bus pins Transmit Data (TXD) dominant time-out function Undervoltage detection on supply pins 3. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit IDD1 supply current 1 VTXD = 0 V; bus dominant - - 2.6 mA VTXD = VDD1; bus recessive - - 5.6 mA VTXD = 0 V; bus dominant; 60 load - - 70 mA VTXD = VDD1; bus recessive - - 10 mA 1.3 - 2.7 V IDD2 supply current 2 Vuvd(swoff)(VDD2) switch-off undervoltage detection voltage on pin VDD2 VESD electrostatic discharge voltage 8 - +8 kV VCANH voltage on pin CANH 58 - +58 V VCANL voltage on pin CANL 58 - +58 V Tvj virtual junction temperature 40 - +125 C Tamb ambient temperature 40 - +105 C TJF1052I Product data sheet IEC 61000-4-2 at pins CANH and CANL All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 2 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 4. Ordering information Table 2. Ordering information Type number TJF1052IT/5 TJF1052IT/2 TJF1052IT/1 Package Name Description Version SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 Table 3. Voltage ratings Type number Rated insulation voltage according to UL 1577, IEC 61010 and IEC 60950 TJF1052iT/5 5 kV (RMS) TJF1052iT/2 2.5 kV (RMS) TJF1052iT/1 1 kV (RMS) 5. Block diagram VDD1 VDD2 1 11, 16 VDD2 TEMPERATURE PROTECTION TJF1052I 13 3 TIME-OUT ISOLATION BARRIER TXD RXD SLOPE CONTROL AND DRIVER 12 CANH CANL MODE CONTROL MUX AND DRIVER 5 WAKE-UP FILTER 2, 7, 8 14 GND1 Fig 1. TJF1052I Product data sheet STB 9, 10, 15 GND2 015aaa386 Block diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 3 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 6. Pinning information 6.1 Pinning VDD1 1 16 VDD2 GND1 2 15 GND2 TXD 3 14 STB n.c. 4 RXD 5 n.c. 6 GND1 7 11 VDD2 10 GND2 GND1 8 9 TJF1052I 13 CANH 12 CANL GND2 015aaa387 Fig 2. Pin configuration diagram 6.2 Pin description Table 4. Symbol TJF1052I Product data sheet Pin description Pin Description VDD1 1 supply voltage 1 GND1 2 ground supply 1[1] TXD 3 transmit data input n/c 4 not connected RXD 5 receive data output; reads out data from the bus lines n/c 6 not connected GND1 7 ground supply 1[1] GND1 8 ground supply 1[1] GND2 9 ground supply 2[1] GND2 10 ground supply 2[1] VDD2 11 supply voltage 2 CANL 12 LOW-level CAN bus line CANH 13 HIGH-level CAN bus line STB 14 Standby mode control input[2] GND2 15 ground supply 2[1] VDD2 16 supply voltage 2 [1] All GND1 pins (pins 2, 7 and 8) should be connected together and to ground domain 1. All GND2 pins (pins 9, 10 and 15) should be connected together and to ground domain 2. Refer to the application notes for further information. [2] Setting STB HIGH disables the CAN bus connection. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 4 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 7. Functional description 7.1 Operation 7.1.1 Normal mode During normal operation, the TJF1052i transceiver transmits and receives data via bus lines CANH and CANL (see Figure 1 for the block diagram). The differential receiver converts the analog data on the bus lines into digital data, which is output on pin RXD. The slopes of the output signals on the bus lines are controlled internally and are optimized in a way that guarantees the lowest possible EME. The isolator used in the TJF1052i is an AC device that employs on-off keying to guarantee the DC output state at all times. The states of TXD, RXD and the CAN bus at start-up, shut-down and during normal operation are described in Table 5. Care should be taken regarding power sequencing if the device is used in networks that support remote wake-up (see Section 12 “Application information”). Table 5. Input/output states at start-up, shut-down and during normal operation TXD RXD VDD1 VDD2 CAN Comments H H >Vuvd(VDD1) >Vuvd(stb)VDD2) recessive Normal mode operation L L >Vuvd(VDD1) >Vuvd(stb)VDD2) dominant Normal mode with TXD dominant time-out active X X unpowered >Vuvd(stb)VDD2) dominant dominant after VDD1 power loss until TXD dominant timeout; recessive while VDD2 is ramping up from an unpowered state X L >Vuvd(VDD1) unpowered disconnected RXD transitions L-to-H when VDD2 restored 7.1.2 Standby mode Standby mode is provided to improve the response of the TJF1052i to an undervoltage on VDD2. The microcontroller cannot switch the transceiver directly to Standby mode. The TJF1052i switches to Standby mode during VDD2 power-up and power-down. See Section 7.2.2 for a description of undervoltage protection on VDD2. 7.2 Fail-safe features 7.2.1 TXD dominant time-out function A ‘TXD dominant time-out’ timer is started when pin TXD goes LOW. If the LOW state on TXD persists for longer than tto(dom)TXD, the transmitter is disabled, releasing the bus lines to recessive state. This function prevents a hardware and/or software application failure from driving the bus lines to a permanent dominant state (blocking all network communications). The TXD dominant time-out timer is reset by a positive edge on TXD. The TXD dominant time-out time also defines the minimum possible bit rate of 40 kbit/s. 7.2.2 Undervoltage protection: VDD2 If the voltage on pin VDD2 falls below the standby threshold, Vuvd(stb)(VDD2), the transceiver switches to Standby mode. In Standby mode, the transceiver is not able to transmit or receive data on the bus lines. The transmitter and the Normal mode receiver are switched off and the bus lines are biased to ground to minimize the supply current. The TJF1052i TJF1052I Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 5 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver will remain in Standby mode until VDD2 rises above Vuvd(stb)(VDD2) (max). The low-power receiver continues to monitor the bus while the TJF1052i is in Standby mode. Data on the bus is still reflected onto RXD, but the transfer speed is reduced. If the voltage on VDD2 falls below the switch-off threshold, Vuvd(swoff)(VDD2), the transceiver switches off and disengages from the bus (zero load). It is guaranteed to switch on again in Standby mode when VDD2 rises above Vuvd(swoff)(VDD2) (max). 7.2.3 Undervoltage protection: VDD1 If the voltage on pin VDD1 falls below the undervoltage detection threshold, Vuvd(VDD1), the CAN bus switches to dominant state and the TXD dominant timeout timer is started. RXD will not go high again until the supply voltage has been restored on VDD1 (VDD1 > Vuvd(VDD1)). 7.2.4 Overtemperature protection The output drivers are protected against overtemperature conditions. If the virtual junction temperature exceeds the shutdown junction temperature, Tj(sd), the output drivers are disabled. They are enabled again when the virtual junction temperature falls below Tj(sd) and TXD is HIGH. Including the TXD condition ensures that output driver oscillation due to temperature drift is avoided. 7.3 Insulation characteristics and safety-related specifications Table 6. Symbol Isolator characteristics Parameter Conditions Min Typ Max Unit dL(IO1) minimum air gap [1] 8.6 - - mm dL(IO2) minimum external tracking [2] 8.1 - - mm TA = 125 C [3] 100 - - G TA = 150 C [3] 10 - - G 2 - - - 2 - - - insulation resistance Rins - pollution degree - material group (IEC 60664) - [1] Based on the measured data in the package outline. dL(IO1) is the clearance distance. Note that the clearance distance cannot be larger than the creepage distance (dL(IO2)). [2] Based on the measured data in the package outline. dL(IO2) is the creepage distance. According to IEC 60950-1, normative annex F (also IEC60664 chapter 6.2, Example 11), the effective minimum external tracking is 1.0 mm less due to the presence of an intervening, unconnected conductive part. [3] Guaranteed by design at a voltage differential of 500 V with the pins on each side of the isolation barrier connected together, simulating a 2-pin device. TJF1052I Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 6 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver Table 7. Working voltages and isolation Insulation Characteristics Parameter Standard TJF1052i/1 TJF1052i/2 TJF1052i/5 max. working insulation voltage per IEC 60664 (VIORM)[1] IEC 60664 300 VRMS 450 VRMS 800 VRMS 420 Vpeak 630 Vpeak 1125 Vpeak max. transient overvoltage per IEC 60664 (VIOTM)[2] tTEST = 1.2/50 s (certification) IEC 60664 2500 Vpeak 4000 Vpeak 6000 Vpeak rated insulation voltage per UL 1577 (VISO) UL 1577 tTEST = 60 s (qualification) 1000 VRMS 2500 VRMS 5000 VRMS tTEST = 1 s (production) 1200 VRMS 3000 VRMS 6000 VRMS Insulation classification in terms of Overvoltage Category[3] Insulation type Max. working voltage TJF1052i/1 TJF1052i/2 TJF1052i/5 basic insulation[4] 150 VRMS I - III I - IV I - IV 300 VRMS I - II I - III I - IV 600 VRMS I I - II I - III 1000 VRMS - - I - II 150 VRMS I - II I - III I - IV 300 VRMS I I - II I - III 600 VRMS - I I - II 1000 VRMS - - I reinforced insulation[4] [1] The working voltage is the input-to-output voltage that can be applied without time limit. Which TJF1052i variant should be selected depends on the overvoltage category and the related insulation voltage. [2] UL stress test is performed at higher than IEC-specified levels. [3] Based on transient overvoltages as indicated in IEC60664; creepage and clearance distances not taken into account. [4] Reinforced insulation should have an impulse withstand voltage one step higher than that specified for basic insulation. Table 8. TJF1052I Product data sheet Safety approvals Standard File number IEC 60950 CB NL-33788 IEC 61010-1 2nd Edition CB NL-33789 UL1577 20131213-E361297 All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 7 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 8. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages and currents are referenced to GND2 unless otherwise specified. Symbol Parameter Conditions Min Max Unit VCANH voltage on pin CANH 58 +58 V VCANL voltage on pin CANL 58 +58 V 0.3 +6.0 V V VDD1 supply voltage 1 VDD2 supply voltage 2 [1] 0.3 +6.0 VI input voltage on pin TXD [1] 0.3 VDD1 + 0.3 V VO output voltage on pin RXD [1] 0.3 VDD1 + 0.3 V [1] - 10 mA 150 +100 V 8 +8 kV 8 +8 kV 4 +4 kV 300 +300 V 750 +750 V 500 +500 V 40 +125 C 40 +105 C 65 +150 C IO output current on pin RXD Vtrt transient voltage on pins CANH and CANL VESD electrostatic discharge voltage IEC 61000-4-2 (150 pF, 330 ) [2] at pins CANH and CANL Human Body Model (HBM); 100 pF, 1.5 k at pins CANH and CANL [3] [4] at any other pin Machine Model (MM); 200 pF, 0.75 H, 10 [5] at any pin Charged Device Model (CDM); field Induced charge; 4 pF [6] at corner pins at any pin Tvj virtual junction temperature Tamb ambient temperature Tstg storage temperature [7] [8] [1] Referenced to GND1. [2] According to IEC TS 62228 (2007), Section 4.3; DIN EN 61000-4-2. [3] According to AEC-Q100-002. [4] 8 kV to GND2 and VDD2; 6 kV to GND1. [5] According to AEC-Q100-003. [6] According to AEC-Q100-011 Rev-C1. The classification level is C4B. [7] An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(vj-a), where Rth(vj-a) is a fixed value used in the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). [8] If UL compliance is required, the maximum storage temperature is limited to 130 C. 9. Thermal characteristics Table 10. Thermal characteristics According to IEC 60747-1. Symbol Parameter Conditions Value Unit Rth(vj-a) thermal resistance from virtual junction to ambient in free air 100 K/W TJF1052I Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 8 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 10. Static characteristics Table 11. Static characteristics Tvj = 40 C to +125 C; VDD1 = 3.0 V to 5.25 V; VDD2 = 4.75 V to 5.25 V unless otherwise specified. Positive currents flow into the IC. All voltages and currents are referenced to GND2 unless otherwise specified[1]. Symbol Parameter Conditions Min Typ Max Unit DC supplies; pin VDD1 and VDD2 IDD1 IDD2 supply current 1 supply current 2 VDD1 = 3 V to 5 V; VDD2 = 5 V; VTXD = 0 V; bus dominant [2] - - 2.6 mA VDD1 = 3 V to 5 V; VDD2 = 5 V; VTXD = VDD1; bus recessive [2] - - 5.6 mA VDD1 = 3 V to 5 V; VDD2 = 5 V; VTXD = 0 V; bus dominant; RL = 60 - - 70 mA VDD1 = 3 V to 5 V; VDD2 = 5 V; VTXD = VDD1; bus recessive - - 10 mA Vuvd(stb)(VDD2) standby undervoltage detection voltage on pin VDD2 3.5 - 4.75 V Vuvd(swoff)(VDD2) switch-off undervoltage detection voltage on pin VDD2 1.3 - 2.7 V Vuvd(VDD1) undervoltage detection voltage on pin VDD1 [2] 1.3 - 2.7 V Vuvhys undervoltage hysteresis voltage [2] 40 - 100 mV 80 - 200 mV - VDD1 V on pin VDD1 on pin VDD2 CAN transmit data input; pin TXD HIGH-level input voltage [2] 2.0 VIL LOW-level input voltage [2] 0 - 0.8 V ILI input leakage current [2] 10 - +10 A VIH CAN receive data output; pin RXD VOH HIGH-level output voltage IOH = 4 mA [2] VDD1 0.4 - - V VOL LOW-level output voltage IOL = 4 mA [2] - - 0.4 V Standby mode control input; pin STB VIH HIGH-level input voltage 0.7VCC - VCC + 0.3 V VIL LOW-level input voltage 0.3 - 0.3VCC V IIH HIGH-level input current VSTB = VCC 1 - +1 A IIL LOW-level input current VSTB = 0 V 15 - 1 A pin CANH 2.75 3.5 4.5 V pin CANL 0.5 1.5 2.25 V 400 - +400 mV Bus lines; pins CANH and CANL VO(dom) Vdom(TX)sym TJF1052I Product data sheet dominant output voltage VTXD = 0 V; t < tto(dom)TXD transmitter dominant voltage symmetry Vdom(TX)sym = VCC VCANH VCANL All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 9 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver Table 11. Static characteristics …continued Tvj = 40 C to +125 C; VDD1 = 3.0 V to 5.25 V; VDD2 = 4.75 V to 5.25 V unless otherwise specified. Positive currents flow into the IC. All voltages and currents are referenced to GND2 unless otherwise specified[1]. Symbol Parameter Conditions Min Typ Max Unit VO(dif)bus bus differential output voltage VTXD = 0 V; t < tto(dom)TXD RL = 45 to 65 1.5 - 3 V 50 - +50 mV 2 0.5VCC 3 V 0.5 - 0.9 V 0.4 - 1.15 V - 165 - mV pin CANH; VCANH = 0 V 100 70 40 mA pin CANL; VCANL = 5 V / 40 V VTXD = VCC recessive; no load VO(rec) Vth(RX)dif recessive output voltage Normal mode; VTXD = VCC; no load differential receiver threshold voltage Vcm(CAN) = 25 V to +25 V [3] Normal mode Standby mode; Vcm(CAN) = 12 V to +12 V Vhys(RX)dif differential receiver hysteresis Vcm(CAN) = 25 V to +25 V voltage Normal mode IO(sc)dom dominant short-circuit output current [4] VTXD = 0 V; t < tto(dom)TXD; VDD2 = 5 V 40 70 100 mA IO(sc)rec recessive short-circuit output current Normal mode; VTXD = VDD1 VCANH = VCANL = 27 V to +32 V 5 - +5 mA IL leakage current VDD2 = 0 V; VCANH = VCANL = 5 V 3 - +3 A 9 15 28 k between VCANH and VCANL 3 - +3 % Ri input resistance Ri input resistance deviation Ri(dif) differential input resistance 19 30 52 k - - 20 pF Ci(cm) common-mode input capacitance [5] Ci(dif) differential input capacitance [5] - - 10 pF [5] - 190 - C Temperature detection Tj(sd) [1] shutdown junction temperature [6] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. [2] Referenced to GND1. [3] Vcm(CAN) is the common mode voltage of CANH and CANL. [4] Standby mode entered when VDD2 falls below Vuvd(stb)(VDD2). [5] Guaranteed by design. [6] RXD is LOW during thermal shutdown. TJF1052I Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 10 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 11. Dynamic characteristics Table 12. Dynamic characteristics Tvj = 40 C to +125 C; VDD1 = 3.0 V to 5.25 V; VDD2 = 4.75 V to 5.25 V unless otherwise specified[1]. Symbol Parameter Conditions Min Typ Max Unit Transceiver timing; pins CANH, CANL, TXD and RXD; see Figure 3 td(TXD-busdom) delay time from TXD to bus dominant Normal mode - 72 120 ns td(TXD-busrec) delay time from TXD to bus recessive Normal mode - 97 120 ns td(busdom-RXD) delay time from bus dominant to RXD Normal mode - 67 130 ns td(busrec-RXD) delay time from bus recessive to RXD Normal mode - 72 130 ns tPD(TXD-RXD) propagation delay from TXD to RXD Normal mode tbit(RXD) bit time on pin RXD tbit(TXD) = 500 ns tto(dom)TXD TXD dominant time-out time VTXD = 0 V; Normal mode CMTI tstartup common-mode transient immunity VI = VDD1 or VI = 0 V start-up time [2] 72 - 220 ns 400 - 550 ns 0.3 1.7 5 ms [3] 20 45 - kV/s [4] - - 500 s [1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. [2] See Figure 4. [3] See Figure 6. [4] The start-up time is the time from the application of power to valid data at the output. Guaranteed by design. TJF1052I Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 11 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver +,*+ 7;' /2: &$1+ &$1/ GRPLQDQW 9 92GLIEXV 9 UHFHVVLYH +,*+ 9'' 5;' 9'' /2: WG7;'EXVGRP WG7;'EXVUHF WGEXVGRP5;' W3'7;'5;' Fig 3. WGEXVUHF5;' W3'7;'5;' DDD CAN transceiver timing diagram 7;' [WELW7;' WELW7;' 5;' WELW5;' DDD Fig 4. TJF1052I Product data sheet Loop delay symmetry timing diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 12 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 12. Application information Isolated CAN applications are becoming more and more common in industrial automation processes. The TJF1052i is the ideal solution for use in DeviceNet networks or in applications that require an isolated CAN node. The device can also be used to isolate high-voltage on-demand pumps and motors in belt elimination projects. If the TJF1052i is used in a HS-CAN network that supports remote bus wake-up, the power-down sequence of the supplies must be managed properly to avoid a dominant pulse on the CAN bus. VDD2 should pass the minimum undervoltage threshold (Vuvd(stb)(VDD2)(min)) before VDD1 falls below its maximum undervoltage detection threshold (Vuvd(VDD1)(max)). Power-up sequencing can happen in any order. Digital inputs and outputs are 3 V compliant, allowing the TJF1052i to interface directly with 3 V and 5 V microcontrollers. isolated supply 5V 5V VDD2 CANH VDD1 CANH TXD TX0 CANL RXD RX0 GND STB Fig 5. VDD MICROCONTROLLER TJF1052I CANL BAT GND2 GND1 015aaa388 Typical application with TJF1052i and a 5 V microcontroller. 12.1 Application hints Further information on the application of the TJF1052i can be found in NXP application hints AH1301 Application Hints - TJA1052i Galvanic Isolated High Speed CAN Transceiver. TJF1052I Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 13 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 13. Test information 9'' 9'' 9'' *1' %$7 9 648$5( :$9( *(1(5$725 7;' QF 5;' QF *1' *1' 7-), 9'' /&ILOWHU *1' 67% &$1+ ȍ &$1/ VXSSO\ 9'' *1' *1' /&ILOWHU 7(67%2$5' *1' *1' 6&23( 38/6( *(1(5$725 DDD Fig 6. CMTI test setup +5 V 47 µF 100 nF VDD1 VDD2 TXD CANH TJF1052I RXD 15 pF GND1 STB RL 100 pF CANL GND2 015aaa389 Fig 7. TJF1052I Product data sheet Timing test circuit for CAN transceiver All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 14 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 010aaa839 103 Working Voltage (VRMS) 102 10 0 Fig 8. TJF1052I Product data sheet 250 500 750 Life Expectancy (Years) 1000 Life expectancy as a function of working voltage All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 15 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 14. Package outline SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c HE y v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 10.5 10.1 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.41 0.40 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT162-1 075E03 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT162-1 (SO16) TJF1052I Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 16 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: TJF1052I Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 17 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 10) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 13 and 14 Table 13. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 14. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 10. TJF1052I Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 18 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 10. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes TJF1052I v.2 20150115 Product data sheet - TJF1052I v.1 Modifications: TJF1052I v.1 TJF1052I Product data sheet • • • • • • • • • • Section 1: text revised (4th paragraph); paragraph added • Table 12: parameter tbit(RXD) added; Table note 1, Table note 2 and Figure 4 added; parameter fdata deleted • • • Figure 3, Figure 6 amended Section 2: minor amendments to text Section 2.1: features added UL1577 certification added (Section 2.3 third bullet; Table 8 file number added) Table 1, Table 9: measurements conditions changed (VCANH, VCANL) Section 7.1.1: minor changes to text Table 6: measurement conditions changed: Rins; Table note 3 revised Table 8: file numbers updated Table 9: measurements conditions changed: VESD;; table note section revised Table 11: Table note 1 added along with references to Table note 2; parameters renamed: IO(sc)dom and IO(sc)rec Section 12.1 “Application hints”: added Section 18.3: ‘Translations’ disclaimer added 20130710 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 - © NXP N.V. 2015. All rights reserved. 19 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. TJF1052I Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 20 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. DeviceNet — is a trademark of the Open DeviceNet Vendor Association. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TJF1052I Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 January 2015 © NXP N.V. 2015. All rights reserved. 21 of 22 TJF1052i NXP Semiconductors Galvanically isolated high-speed CAN transceiver 20. Contents 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 8 9 10 11 12 12.1 13 14 15 16 16.1 16.2 16.3 16.4 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Power management . . . . . . . . . . . . . . . . . . . . . 2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 5 TXD dominant time-out function . . . . . . . . . . . . 5 Undervoltage protection: VDD2 . . . . . . . . . . . . . 5 Undervoltage protection: VDD1 . . . . . . . . . . . . . 6 Overtemperature protection . . . . . . . . . . . . . . . 6 Insulation characteristics and safety-related specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal characteristics . . . . . . . . . . . . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 13 Application hints . . . . . . . . . . . . . . . . . . . . . . . 13 Test information . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Handling information. . . . . . . . . . . . . . . . . . . . 17 Soldering of SMD packages . . . . . . . . . . . . . . 17 Introduction to soldering . . . . . . . . . . . . . . . . . 17 Wave and reflow soldering . . . . . . . . . . . . . . . 17 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 January 2015 Document identifier: TJF1052I