Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MC33689
Rev. 8.0, 9/2012
System Basis Chip with LIN
Transceiver
33689D
The 33689 is a serial peripheral interface (SPI) controlled system
basis chip (SBC) that combines many frequently used functions in an
MCU-based system plus a local interconnect network (LIN)
transceiver. Applications include power window, mirror, and seat
controls. The 33689 has a 5.0 V, 50 mA low dropout regulator with full
protection and reporting features. The device provides full SPIreadable diagnostics and a selectable timing watchdog for detecting
errant operation.
The LIN transceiver waveshaping circuitry can be disabled for
higher data rates. One 50 mA and two 150 mA high side switches with
output protection are available to drive inductive or resistive loads. The
150 mA switches can be pulse-width modulated (PWM).
Two high voltage inputs are available for contact monitoring or as
external wake-up inputs. A current sense operational amplifier is
available for load current monitoring.
The 33689 has three operational modes:
• Normal (all functions available)
• Sleep (VDD OFF, wake-up via LIN bus or wake-up inputs)
• Stop (VDD ON, wake-up via MCU, LIN bus, or wake-up inputs)
EW SUFFIX (PB-FREE)
98ARH99137A
32-PIN SOICW
ORDERING INFORMATION
Device
(Add R2 Suffix for Tape
and Reel)
Features
•
•
•
•
•
•
SYSTEM BASIS CHIP WITH LIN
Full-duplex SPI Interface at frequencies up to 4.0 MHz
LIN transceiver capable to 100 kbps with waveshaping capability
5.0 V low dropout regulator with full fault detection and protection
One 50 mA and two 150 mA protected high side switches
Current sense operational amplifier
Compatible with LIN 2.0 specification package
MC33689DPEW
VDD VPWR
33689
VS1
VS2
VCC
VDD
WDC
5.0 V
HS3
L1
L2
HS1
CS
MCU SCK
MOSI
MISO
SPI
CS
SCLK
MOSI
MISO
INT
RST
IN
OUT
TXD
RXD
HS2
E+
EGND
TGND
AGND
LIN
BUS
Figure 1. 33689 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006-2012. All rights reserved.
Temperature
Range (TA)
Package
-40 °C to 125 °C
32 SOICW
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
5.0 V/50 mA
VS1
VDD
Voltage
Regulator
VS2
Reset
Control
RST
Window
Watchdog
WDC
IN
HS1
MOSI
SPI
and
Mode
Control
HS2
Pre-Driver
HS3
MISO
SCLK
CS
INT
VCC
L1
E-
Current
Sense
Op Amp
L2
E+
OUT
VS1
LIN
TXD
LIN Physical Interface
RXD
GND
TGND
AGND
Figure 2. 33689 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
NC
L1
NC
L2
HS3
HS2
HS1
TGND
TGND
VS2
LIN
GND
VS1
NC
VDD
AGND
TXD
RXD
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
MISO
MOSI
SCLK
TGND
TGND
IN
11
22
RST
12
21
WDC
13
20
14
19
15
18
16
17
E+
EOUT
VCC
INT
CS
Figure 3. 33689 32-SOICW Pin Connections
Table 1. 33689 32-SOICW Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Pin
Pin Name
Formal Name
Pin Function
Definition
1, 3, 14
NC
No Connect
N/A
No internal connection to these pins.
2, 4
L1, L2
Level Inputs 1 and 2
Input
Inputs from external switches or from logic circuitry.
5–7
HS3 – HS1
High-Side Driver
Outputs 3 through 1
Output
8, 9, 24, 25
TGND
Thermal Ground
N/A
Thermal ground pins for the device.
10
VS2
Voltage Supply 2
Input
Supply pin for the high-side switches HS1, HS2, and HS3.
11
LIN
LIN Bus
Input / Output
12
GND
Ground
N/A
Electrical ground pin for the device.
13
VS1
Voltage Supply 1
Input
Supply pin for the 5.0 V regulator, the LIN physical interface, and the
internal logic.
15
VDD
5.0 V Regulator
Output
Output
16
AGND
Analog Ground
N/A
Analog ground pin for voltage regulator and current sense operational
amplifier.
17
VCC
Power Supply In
Input
5.0 V supply for the internal current sense operational amplifier.
18
OUT
Amplifier Output
Output
19
E-
Amplifier Inverted
Input
Input
Inverted input of the internal current sense operational amplifier.
20
E+
Amplifier Non-Inverted
Input
Input
Non-inverted input of the internal current sense operational amplifier.
21
WDC
Watchdog
Configuration
(Active Low)
Reference
High-side (HS) drive power outputs. SPI-controlled for driving system
loads.
Bidirectional pin that represents the single-wire bus transmitter and
receiver.
Output of the 5.0 V regulator.
Output of the internal current sense operational amplifier.
Configuration pin for the watchdog timer.
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33689 32-SOICW Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Pin
Pin Name
Formal Name
Pin Function
Definition
22
RST
Reset Output
(Active LOW)
Output
23
IN
PWM Input Control
Input
External input PWM control pin for high-side switches HS1 and HS2.
26
SCLK
Serial Data Clock
Input
Clock input for the SPI of the 33689.
27
MOSI
Master Out Slave In
Input
SPI data received by the 33689.
28
MISO
Master In Slave Out
Output
29
CS
Chip Select
(Active LOW)
Input
30
INT
Interrupt Output
(Active LOW)
Output
This output pin reports faults to the MCU when an enabled interrupt
condition occurs.
31
RXD
Receiver Output
Output
Receiver output of the LIN interface and reports the state of the bus
voltage.
32
TXD
Transmitter Input
Input
5.0 V regulator and watchdog reset output pin.
SPI data sent to the MCU by the 33689. When CS is HIGH, pin is in the
high-impedance state.
SPI control chip select input pin.
Transmitter input of the LIN interface and controls the state of the bus
output.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
Continuous
VSUPDC
- 0.3 to 27
Transient (Load Dump)
VSUPTR
40
Supply Voltage at VDD and VCC
VDD
- 0.3 to 5.5
V
Output Current at VDD
IDD
Internally Limited
A
VINLOG
- 0.3 to VDD + 0.3
V
Logic Output Voltage at MISO, INT, RST, and RXD
VOUTLOG
- 0.3 to VDD + 0.3
V
Input Voltage at E+ and E-
VE+ / VE-
- 0.3 to 7.0
V
Input Current at E+ and E-
IE+ / IE-
± 20
mA
Output Voltage at OUT
VOUT
- 0.3 to VCC + 0.33
V
Output Current at OUT
IOUT
± 20
mA
DC Input with a 33 kΩ Resistor
VLXDC
-18 to 40
Transient Input with External Component (per ISO7637 Specification) (See
Figure 4, page 6)
VLXTR
±100
DC Voltage
VBUSDC
-18 to 40
Transient Input Voltage with specified External Component (per ISO7637
Specification) (See Figure 4, page 6)
VBUSTR
-150 to 100
Positive
VHS+
VVS2 + 0.3
Negative
VHS-
Internally Clamped
DC Output Voltage at HS3
VHS3
- 0.3 to VVS2 + 0.3
ESD Voltage, Human Body Model (1)
VESD1
ELECTRICAL RATINGS
VPWR Supply Voltage at VS1 and VS2
Logic Input Voltage at MOSI, SCLK, CS, IN, and TXD
V
Input Voltage at L1 and L2
V
Input / Output Voltage at LIN
V
DC Output Voltage at HS1 and HS2
V
V
V
GND Configured as Ground. TGND and AGND Configured as I/O Pins
LIN, L1, and L2
± 4000
All Other Pins
± 2000
ESD Voltage, Charge Device Model
(1)
Corner Pins (Pins 1, 16, 17, and 32)
All other Pins (Pins 2 – 15 and 18 – 31)
VESD2
V
± 750
± 500
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Charge Device Model, Robotic (CZAP = 4.0 pF).
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings(continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
Ambient
TA
- 40 to 125
Junction
TJ
- 40 to 150
Storage Temperature
TSTG
- 55 to 165
°C
Thermal Resistance, Junction-to-Ambient
RθJA
80
°C/ W
TSOLDER
240
°C
THERMAL RATINGS
°C
Operating Temperature
Peak Package Reflow Temperature During Solder Mounting (2)
Notes
2. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause permanent damage to the device.
33689D
1.0 nF
LIN, L1, L2
10 kΩ
Transient Pulse
Generator
(Note)
GND
GND
TGND AGND
Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.
Figure 4. ISO 7637 Test Setup for LIN, L1, and L2 Pins
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Nominal DC
VSUP
5.5
—
18
Load Dump
VSUPLD
—
—
40
VSUPJS
—
—
27
ISUP(NORM)
—
5.0
8.0
mA
Sleep Mode, VDD OFF, VSUP ≤ 13.5 V
ISLEEP
—
35
45
μA
Stop Mode, VDD ON with IOUT < 100 μA, VSUP ≤ 13.5 V
ISTOP
—
60
75
μA
Fall Early Warning, Bit VSUV Set
VSUVEW
5.7
6.1
6.6
Overvoltage Warning, Bit VSOV Set
VSOVW
18
19.75
20.5
VS1 AND VS2 INPUT PINS (DEVICE POWER SUPPLY)
Supply Input Voltage
Jump Start
(3)
V
Supply Input Current (4)
Normal Mode, IOUT at VDD = 10 mA, LIN Recessive State
Input Threshold Voltage (Normal Mode, Interrupt Generated)
Hysteresis (5)
V
VHYS
VSUV Flag
—
1.0
—
V
VSOV Flag
—
220
—
mV
4.75
5.0
5.25
VDD OUTPUT PIN (EXTERNAL 5.0 V OUTPUT FOR MCU USE) (6)
Output Voltage
VDDOUT
IDD from 2.0 mA to 50 mA, 5.5 V < VSUP < 27 V
Dropout Voltage (7)
V
VDDDROP
V
—
0.1
0.2
50
120
200
120
135
160
165
170
—
IDD = 50 mA
Output Current Limitation (8)
Overtemperature Pre-warning (Junction)
IDD
Thermal Shutdown (Junction)
Normal Mode
°C
TPRE
Normal Mode, Interrupt Generated, Bit VDDT Set
mA
°C
TSD
Notes
3. Device is fully functional. All features are operating. An overtemperature fault may occur.
4. Total current (IVS1 + IVS2) at VS1 and VS2 pins is measured at the ground pins.
5.
6.
7.
8.
Parameter guaranteed by design; however, it is not production tested.
Specification with external capacitor 2.0 μF < C < 10 μF and 200 mΩ ≤ ESR ≤ 10 Ω. Normal mode. Low ESR electrolytic capacitor values
up to 47 μF can be used.
Measured when the voltage has dropped 100 mV below its nominal value.
Internally limited. Total 5.0 V regulator current. A 5.0 mA current for the Current Sense Operational Amplifier operation is included.
Digital outputs are supplied from VDD.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
VDD OUTPUT PIN (5.0 V OUTPUT FOR MCU USE) (CONTINUED)
Temperature Threshold Difference
Symbol
20
30
40
4.0
—
—
—
20
150
—
10
150
4.75
5.0
5.25
4.0
8.0
14
Unit
°C
V
VLR1
5.5 V < VSUP < 27 V, IDD = 10 mA
Load Regulation
Max
VSUPR
0.5 V < VDD < VDD (V RSTTH)
Line Regulation
Typ
TDIFF
Normal Mode (TSD - TPRE)
VSUP Range for Reset Active
Min
(9)
mV
VLD1
1.0 mA < IDD < 50 mA
mV
VDD OUTPUT PIN IN STOP MODE
Output Voltage (10)
VDDS
IDD ≤ 2.0 mA
Output Current Capability (11)
IDDS
Line Regulation
VLRS
5.5 V < VSUP < 27 V, IDD = 2.0 mA
Load Regulation
V
mV
—
10
100
—
40
150
4.5
4.7
VDD - 0.2
0.0
—
0.9
—
- 275
—
VLDS
1.0 mA < IDD < 5.0 mA
mA
mV
RST OUTPUT PIN IN NORMAL AND STOP MODES
Reset Threshold Voltage
V RSTTH
Low-Level Output Voltage
VOL
IO = 1.5 mA, 4.5 V < VSUP < 27 V
High-Level Output Current
V
μA
IOH
0.0 V < VOUT < 0.7 VDD
Reset Pulldown Current
IPDRST
Internally Limited, VDD < 4.0 V, VRST = 4.6 V
V
mA
1.5
—
8.0
IN INPUT PIN
Low-Level Input Voltage
VIL
- 0.3
—
0.3 VDD
V
High-Level Input Voltage
VIH
0.7 VDD
—
VDD + 0.3
V
Input Current
IIN
-10
—
10
0.0 V < VIN < VDD
μA
Notes
9. Specification with external capacitor 2.0 μF < C < 10 μF and 200 mΩ ≤ ESR ≤ 10 Ω. Normal mode. Low ESR electrolytic capacitor values
up to 47 μF can be used.
10. When switching from Normal mode to Stop mode or from Stop mode to Normal mode, the voltage can vary within the output voltage
specification.
11. When IDD is above IDDS, the 33689 enters the Reset mode.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
0.0
—
1.0
VDD - 0.9
—
VDD
- 2.0
—
2.0
Unit
MISO SPI OUTPUT PIN
Low-Level Output Voltage
VOL
I OUT = 1.5 mA
High-Level Output Voltage
V
VOH
I OUT = 250 μA
Tri-Stated MISO Output Leakage Current
V
μA
IHZ
0.0 V < VMISO < VDD
MOSI, SCLK, CS SPI INPUT PINS
Low-Level Input Voltage
VIL
- 0.3
—
0.3 VDD
V
High-Level Input Voltage
VIH
0.7 VDD
—
VDD + 0.3
V
-100
—
- 20
μA
IPUCS
Pullup Input Current on CS
VCS = 4.0 V
MOSI, SCLK Input Current
μA
IIN
-10
—
10
0.0
—
0.9
VDD - 0.9
—
VDD
10
—
100
- 6.0
—
—
TA = 25°C, I OUT -150 mA
—
2.0
2.5
TA = 125°C, I OUT -150 mA
—
—
4.5
TA = 125°C, I OUT -120 mA
—
3.0
4.0
ILIM
300
430
600
mA
TOTSD
155
—
190
°C
ILEAK
—
—
10
μA
0.0 V < VIN < VDD
INT OUTPUT PIN
Low-Level Output Voltage
VOL
IO = 1.5 mA
High-Level Output Voltage
V
VOH
IO = - 250 μA
V
WDC PIN
External Resistor Range
R EXT
kΩ
HS1 AND HS2 HIGH-SIDE OUTPUT PINS
Output Clamp Voltage
VCL
I OUT = -100 mA
Output Drain-to-Source ON Resistance
Output Current Limitation
Overtemperature Shutdown
(12)
Output Leakage Current
V
Ω
RDS(ON)
Notes
12. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI Register. Refer to description on page 26.
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TA = 25°C, I OUT - 50 mA
—
5.5
7.0
TA = 125°C, I OUT - 50 mA
—
—
10
TA = 125°C, I OUT - 30 mA
—
10
14
ILIM
60
100
200
mA
Overtemperature Shutdown (13)
TOTSD
155
—
190
°C
Output Leakage Current
ILEAK
—
—
10
μA
Input Voltage – Rail-to-Rail at E+ and E-
VIMC
- 0.1
—
VCC + 0.1
V
Output Voltage Range at OUT
VOUT
0.1
0.3
—
—
IB
—
—
250
nA
Input Offset Voltage
V IO
-15
—
15
mV
Input Offset Current
IO
-100
—
100
nA
5.5 V < VSUP < 6.0 V
2.0
2.5
3.0
6.0 V < VSUP < 18 V
2.5
3.0
3.5
18 V < VSUP < 27 V
2.7
3.2
3.7
5.5 V < VSUP < 6.0 V
2.7
3.3
3.8
6.0 V < VSUP < 18 V
3.0
4.0
4.5
18 V < VSUP < 27 V
3.5
4.2
4.7
HS3 HIGH-SIDE OUTPUT PIN
Output Drain-to-Source ON Resistance
Output Current Limitation
Ω
RDS(ON)
OUT, E+, AND E- PINS AT CURRENT SENSE OPERATIONAL AMPLIFIER
With ± 1.0 mA Output Load Current
With ± 5.0 mA Output Load Current
Input Bias Current
V
VCC - 0.1
VCC - 0.3
L1 AND L2 INPUT PINS
Low-Voltage Detection Input Threshold Voltage
High-Voltage Detection Input Threshold Voltage
Input Hysteresis
VTHL
VTHH
- 0.2 V < VIN < 40 V
V
VHYS
5.5 V < VSUP < 27 V
Input Current
V
V
0.5
—
1.3
-10
—
10
μA
IIN
Notes
13. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI Register. Refer to description on page 26.
33689
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
0.0
—
0.9
3.75
—
5.25
Unit
RXD OUTPUT PIN (LIN PHYSICAL LAYER)
Low-Level Output Voltage
VOL
I OUT ≤ 1.5 mA
High-Level Output Voltage
V
VOH
I OUT ≤ 250 μA
V
TXD INPUT PIN (LIN PHYSICAL LAYER)
Low-Level Input Voltage
VIL
—
—
1.5
V
High-Level Input Voltage
VIH
3.5
—
—
V
Input Hysteresis
VINHYS
50
145
300
mV
Pullup Current Source
IPUTXD
1.0 V < VTXD < 3.5 V
μA
-100
—
- 20
LIN PHYSICAL LAYER, TRANSCEIVER
Transceiver Output Voltage
V
Dominant State, TXD LOW, External Bus Pullup 500 Ω
VLINDOM
—
—
1.4
Recessive State, TXD HIGH, I OUT = 1.0 μA
VLINREC
VSUP -1.0
—
—
Pullup Resistor to VSUP
RPU
In Normal Mode and in Sleep and Stop Modes When Not Disabled by
SPI
kΩ
20
30
47
—
1.3
—
50
75
150
mA
VS1 and VS2 Disconnected, VLIN = 18 V
—
1.0
10
μA
Recessive State, 8.0 V < VSUP < 18 V, 8.0 V < VLIN < 18 V
0.0
3.0
20
μA
GND Disconnected, VGND = VSUP , VLIN = -18 V
-1.0
—
1.0
mA
Pullup Current Source
In Sleep and Stop Modes When Pullup Disabled by SPI
Output Current Shutdown Threshold
Leakage Output Current to GND
μA
IPULIN
IOUTSD
IBUSLEAK
LIN PHYSICAL LAYER, RECEIVER
Receiver Input Threshold Voltage
VSUP
Dominant State, TXD HIGH, RXD LOW
VBUSDOM
0.0
—
Recessive State, TXD HIGH, RXD HIGH
VBUSREC
0.6
—
1.0
Center (VBUSDOM - VBUSREC) / 2
VBUSCNT
0.475
0.5
0.525
Hysteresis (VBUSDOM - VBUSREC)
VBUSHYS
—
—
0.175
VBUSWU
—
0.5
—
Bus Wake-Up Threshold
0.4
VSUP
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Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
fSPI
0.25
—
4.0
MHz
t PSCLK
250
—
N/A
ns
SCLK Clock High Time
t WSCLKH
125
—
N/A
ns
SCLK Clock Low Time
t WSCLKL
125
—
N/A
ns
Falling Edge of CS to Rising Edge of SCLK
t LEAD
100
—
N/A
ns
Falling Edge of SCLK to CS Rising Edge
t LAG
100
—
N/A
ns
MOSI to Falling Edge of SCLK (Data Setup Time)
t SI (SU)
40
—
N/A
ns
Falling Edge of SCLK to MOSI (Data Hold Time)
t SI (HOLD)
40
—
N/A
ns
SPI INTERFACE CHARACTERISTICS
SPI Operation Frequency
SCLK Clock Period
MISO Rise Time (14)
t RSO
ns
—
25
50
—
25
50
MISO Low Impedance (Enable)
t SO (EN)
0.0
—
50
MISO High Impedance (Disable)
t SO (DIS)
0.0
—
50
0.0
—
50
t DURRST
0.65
1.0
1.35
ms
ACC WDC
-15
—
15
%
—
10.558
—
—
99.748
—
107
160
215
CL = 220 pF
MISO Fall Time (14)
t FSO
CL = 220 pF
ns
ns
Time from Falling or Rising Edge of CS to: (14)
Time from Rising Edge of SCLK to MISO Data Valid (14)
t VALID
0.2 VDD ≤ MISO ≥ 0.8 VDD, CL = 100 pF
ns
RST OUTPUT PIN IN NORMAL AND STOP MODES
Reset Duration After VDD HIGH
WDC PIN
Watchdog Period Accuracy Using an External Resistor (Excluding Resistor
Tolerances) (15)
Watchdog Time Period (15)
10 kΩ External Resistor
100 kΩ External Resistor
No External Resistor, WDC Open, Normal Mode
t WDC
ms
Notes
14. Parameter guaranteed by design; however, it is not production tested.
15. Watchdog time period calculation formula: t WDC = 0.991 * R + 0.648 (R in kΩ and t WDC in ms).
33689
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Supply Voltage Rejection Ratio (16)
SVR
60
—
—
dB
Common Mode Rejection Ratio (16)
CMR
70
—
—
dB
Gain Bandwidth (16)
GBP
1.0
—
—
MHz
SR
0.5
—
—
V/μs
PHMO
40
—
—
deg.
OLG
—
85
—
dB
t WUF
8.0
20
38
μs
CURRENT SENSE OPERATIONAL AMPLIFIER
Output Slew Rate
Phase Margin
Open Loop Gain
(16)
L1 AND L2 INPUT PINS
Wake-Up Filter Time (16)
STATE MACHINE TIMING
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
μs
t STOP
and Stop Mode Activation (16)
1.4
—
5.0
No Watchdog Selected
6.0
—
30
Maximum Watchdog Period
12
—
50
Minimum Watchdog Period
Interrupt Low-Level Duration
t INT
7.0
10
13
μs
Internal Oscillator Frequency Accuracy (All Modes, for Information Only)
fOSC
- 35
—
35
%
Normal Request Mode Time-Out (Normal Request Mode)
t NRTOUT
97
150
205
ms
Delay Between SPI Command and HS1 or HS2 Turn On (17), (18)
t SHSON
Normal Mode, VSUP > 9.0 V, VHS ≥ 0.2 VVS2
Delay Between SPI Command and HS1 or HS2 Turn Off (17), (18)
—
20
μs
—
—
20
μs
tSHSON
Normal Mode, VSUP > 9.0 V, VHS ≥ 0.2 VVS2
Delay Between SPI Command and HS3 Turn Off (17), (19)
—
t SHSOFF
Normal Mode, VSUP > 9.0 V, VHS ≤ 0.8 VVS2
Delay Between SPI Command and HS3 Turn On (17), (19)
μs
—
—
20
μs
tSHSOFF
Normal Mode, VSUP > 9.0 V, VHS ≤ 0.8 VVS2
—
—
20
t SNR2N
7.0
15
30
Normal Request Mode, VDD ON and RST HIGH
t WUCS
15
40
80
First Accepted SPI Command
t WUSPI
90
—
N/A
t S1STSPI
30
—
N/A
μs
t 2CS
15
—
—
μs
Delay Between Normal Request and Normal Mode After a Watchdog Trigger
μs
Command (Normal Request Mode) (16)
μs
Delay Between CS Wake-Up (CS LOW to HIGH) in Stop Mode and:
Delay Between Interrupt Pulse in Stop Mode After Wake-Up and First
Accepted SPI Command
Minimum Time Between Rising and Falling Edge on the CS
Notes
16. Parameter guaranteed by design; however, it is not production tested.
17. When IN input is set to HIGH, delay starts at falling edge of clock cycle #8 of the SPI command and start of device activation/deactivation.
30 mA load on high-side switches. Excluding rise or fall time due to external load.
18. When IN is used to control the high-side switches, delays are measured between IN and HS1 or HS2 ON / OFF. 30 mA load on high-side
switches, excluding rise or fall time due to external load.
19. Delay between turn on or turn off command and HS ON or HS OFF, excluding rise or fall time due to external load.
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
LIN PHYSICAL LAYER: BUS DRIVER TIMING CHARACTERISTICS FOR NORMAL SLEW RATE
Typ
Max
μs
Propagation Delay TXD to LIN (21)
t DOMMIN
—
—
50
Dominant State Maximum Threshold (50% TXD to 28.4% VSUP)
t DOMMAX
—
—
50
Recessive State Minimum Threshold (50% TXD to 42.2% VSUP)
t RECMIN
—
—
50
Recessive State Maximum Threshold (50% TXD to 74.4% VSUP)
t RECMAX
—
—
50
t DOMMIN - t RECMAX
dt1s
-10.44
—
—
t DOMMAX - t RECMIN
dt2s
—
—
11
Dominant State Minimum Threshold (50% TXD to 58.1% VSUP)
μs
Propagation Delay Symmetry
LIN PHYSICAL LAYER: BUS DRIVER TIMING CHARACTERISTICS FOR SLOW SLEW RATE
(20)
μs
Propagation Delay TXD to LIN (22)
t DOMMIN
—
—
100
Dominant State Maximum Threshold (50% TXD to 25.1% VSUP)
t DOMMAX
—
—
100
Recessive State Minimum Threshold (50% TXD to 38.9% VSUP)
t RECMIN
—
—
100
Recessive State Maximum Threshold (50% TXD to 77.8% VSUP)
t RECMAX
—
—
100
Dominant State Minimum Threshold (50% TXD to 61.6% VSUP)
Unit
(20)
μs
Propagation Delay Symmetry
t DOMMIN - t RECMAX
dt1s
- 22
—
—
t DOMMAX - t RECMIN
dt2s
—
—
23
dv/dt Fast
—
13
—
V/μs
t OUTDLY
—
10
—
μs
LIN PHYSICAL LAYER: BUS DRIVER FAST SLEW RATE
LIN High Slew Rate (Programming Mode)
LIN PHYSICAL LAYER, TRANSCEIVER
Output Current Shutdown Delay (23)
Notes
20. 7.0 V < VSUP < 18 V, bus load C0 and R0 1.0 nF/1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. 50% of TXD signal to LIN signal threshold. See
Figure 5, page 16.
21. See Figure 7, page 17.
22. See Figure 8, page 17.
23. Parameter guaranteed by design; however, it is not production tested.
33689
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
—
3.0
6.0
Unit
LIN PHYSICAL LAYER: RECEIVER CHARACTERISTICS AND WAKE-UP TIMINGS
μs
Propagation Delay LIN to RXD (24)
Dominant State (LIN LOW to RXD LOW)
t RDOM
Recessive State (LIN HIGH to RXD HIGH)
t RREC
—
3.0
6.0
Symmetry (t RDOM - t RREC)
t RSYM
- 2.0
—
2.0
t PROPWL
30
70
90
t WU
—
30
—
t WU
—
20
—
Bus Wake-Up Deglitcher (Sleep and Stop Modes) (25)
μs
Bus Wake-Up Event Reported
From Sleep Mode
(26)
From Stop Mode (27)
μs
Notes
24. Measured between LIN signal threshold VINL or VINH and 50% of RXD signal.
25. See Figures 9 and 10, page 18.
26. t WU is typically 2 internal clock cycles after a LIN rising edge is detected. In Sleep Mode, the measurement is done without a capacitor
connected to the regulator. The delay is measured between the VSUP/2 rising edge of the LIN bus and when VDD reaches 3.0 V. The
VDD rise time is strongly dependent upon the decoupling capacitor at VDD pin. See Figure 9, page 18.
27.
t WU is typically 2 internal clock cycles after a LIN rising edge is detected. In Stop Mode, the delay is measured between the VSUP/2
rising edge of the LIN bus and the falling edge of the INT pin. See Figure 10, page 18.
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
VPWR
33689
VS1/VS2
TXD
R0
RXD
LIN
GND
TGND AGND
R0/C0 Combinations:
1.0 kΩ/1.0 nF
660 Ω/6.8 nF
500 Ω/10 nF
C0
Figure 5. Test Circuit for Timing Measurements
t PSCLK
CS
t WSCLKH
t LEAD
t LAG
SCLK
t WSCLKL
t SI(SU)
MOSI
Undefined
t SI(HOLD)
DI 0
Don’t Care
DI 7
t VALID
t SO(DIS)
t SO(EN)
MISO
Don’t Care
DO 0
DO 7
Note Incoming data at MOSI pin is sampled by the 33689 at SCLK falling edge. Outgoing data at MISO is set by the 33689
at SCLK rising edge (after tVALID delay time).
Figure 6. SPI Timing Characteristics
33689
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
Recessive State
t RECMAX
VLINREC
74.4% VSUP
58.1% VSUP
t DOMMIN
60% VSUP
40% VSUP
LIN
42.2% VSUP
28.4% VSUP
Dominant State
t DOMMAX
t RECMIN
RXD
t RDOM
tRREC
Figure 7. Timing Characteristics for Normal LIN Output Slew Rate
TXD
Recessive State
tRECMAX
VLINREC
77.8% VSUP
61.6% VSUP
t DOMMIN
60% VSUP
40% VSUP
LIN
38.9% VSUP
25.1% VSUP
Dominant State
t DOMMAX
tRECMIN
RXD
t RDOM
t RREC
Figure 8. Timing Characteristics for Slow LIN Output Slew Rate
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Recessive State
VLINREC
LIN
Recessive State
VLINREC
LIN
0.4 VSUP
Dominant Level
0.4 VSUP
Dominant State
VDD
INT
t PROPWL
t WU
Figure 9. LIN Bus Wake-Up Behavior, Sleep Mode
t PROPWL
t WU
Figure 10. LIN Bus Wake-Up Behavior, Stop Mode
33689
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
A System Basis Chip (SBC) is a monolithic IC combining
many functions found in standard microcontroller-based
systems; e.g., power management, communication interface,
system protection, and diagnostics.
The 33689 is a SPI-controlled SBC combining many
functions with a LIN transceiver for slave node applications.
The 33689 has a 5.0 V, 50 mA regulator with undervoltage
reset, output current limiting, overtemperature pre-warning,
and thermal shutdown. An externally selectable timing
Window Watchdog is also included.
The LIN transceiver has waveshaping that can be disabled
when high data rates are warranted. A single 50 mA and two
150 mA fully protected high-side switches with output
clamping are available for switching inductive or resistive
loads. The 150 mA switches are PWM capable.
Two high-voltage inputs can be used to monitor switches
or provide external wake-up. An internal current sense
operational amplifier is available for load current monitoring.
FUNCTIONAL PIN DESCRIPTION
LEVEL 1 AND LEVEL 2 INPUT PINS
(L1 AND L2)
These pins are used to sense external switches and to
wake up the 33689 from Sleep or Stop mode. During Normal
mode, the state of these pins can be read through the SPI
Register. (Refer to the section entitled SPI Interface and
Register Description on page 24 for information on the SPI
Register.)
HIGH-SIDE DRIVER OUTPUT PINS 1 AND 2 (HS1
AND HS2)
These two high-side switches are able to drive loads such
as relays or lamps. They are protected against overcurrent
and overtemperature and include internal clamp circuitry for
inductive load protection. Switch control is done through
selecting the correct bit in the SPI Register. HS1 and HS2
can be PWM-ed if required through the IN input pin. The
internal circuitry that drives both high-side switches is an
AND function between the SPI bit HS1 (or HS2) and the IN
input pin.
If no PWM control is required, the IN pin must be
connected to the VDD pin.
HIGH-SIDE DRIVER OUTPUT PIN 3 (HS3)
This high-side switch can be used to drive small lamps,
Hall sensors, or switch pullup resistors. Control is done
through the SPI Register only.
No direct PWM control is possible on this pin.
This high-side switch features current limit to protect it
against overcurrent and short circuit conditions. It is also
protected against overtemperature.
VOLTAGE SUPPLY PINS 1 AND 2
(VS1 AND VS2)
The 33689 is supplied from a battery line or other supply
source through the VS1 and VS2 pins. An external diode is
required to protect against negative transients and reverse
battery. The 33689 can operate from 4.5 V and under the
jump start condition at 27 V DC. Device functionality is
guaranteed down to 4.5 V at VS1 and VS2 pins. These pins
sustain standard automotive voltage conditions such as load
dump at 40 V.
LIN BUS PIN (LIN)
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems and is based
on the LIN bus specification.
VOLTAGE SOURCE PIN (VDD)
The VDD pin is the 5.0 V supply pin for the MCU and the
current sense operational amplifier.
CURRENT SENSE OPERATIONAL AMPLIFIER
PINS (E+, E- , VCC, AND OUT)
These are the pins of the single-supply current sense
operational amplifier.
• The E+ and the E- input pins are the non-inverting and
inverting inputs of the current sense operational amplifier,
respectively.
• The OUT pin is the output pin of the current sense
operational amplifier.
• The VCC pin is the + 5.0 V single-supply connection for the
current sense operational amplifier.
The current sense operational amplifier is enabled in
Normal mode only.
WATCHDOG CONFIGURATION PIN (WDC)
The WDC pin is the configuration pin for the internal
watchdog. A resistor is connected to this pin. The resistor
value defines the watchdog period. If the pin is left open, the
watchdog period is fixed to its default value (150 ms typical).
If no watchdog function is required, the WDC pin must be
connected to GND.
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Freescale Semiconductor
19
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
RESET OUTPUT PIN (RST)
The RST pin is the 5.0 V regulator and Watchdog reset
output pin.
PWM INPUT CONTROL PIN (IN)
The IN pin is the external PWM control pin for the HS1 and
HS2 high-side switches.
SERIAL DATA CLOCK PIN (SCLK)
The SCLK pin is the SPI clock input pin. MISO data
changes on the negative transition of the SCLK. MOSI is
sampled on the positive edge of the SCLK.
MASTER OUT SLAVE IN PIN (MOSI)
The MOSI pin receives SPI data from the MCU. This data
input is sampled on the positive edge of SCLK.
MASTER IN SLAVE OUT PIN (MISO)
The MISO pin sends data to an SPI-enabled MCU. Data
on this output pin changes on the negative edge of the SCLK.
When CS is HIGH, this pin enters the high-impedance state.
CHIP SELECT PIN (CS)
The CS pin is the chip select input pin for SPI use. When
this signal is high, SPI signals are ignored. Asserting this pin
LOW starts an SPI transaction. The transaction is completed
when this signal returns HIGH.
INTERRUPT OUTPUT PIN (INT)
The INT pin is used to report 33689 faults to the MCU.
Interrupt pulses are generated for:
•
•
•
•
Voltage regulator temperature pre-warning
HS1, HS2, or HS3 thermal shutdown
VS1 or VS2 overvoltage (20 V typical)
VS1 or VS2 undervoltage (6.0 V typical)
If an interrupt is generated, then when the next SPI read
operation is performed bit D7 in the SPI Register will be set
to logic [1] and bits D6 : D0 will report the interrupt source.
In cases of wake-up from the Stop mode, INT is set LOW
in order to signal to the MCU that a wake-up event from the
L1, L2, or LIN bus pin has occurred.
RECEIVER OUTPUT PIN (RXD)
The RXD pin is the receiver output of the LIN interface and
reports the state of the bus voltage (RXD LOW when LIN bus
is dominant, RXD HIGH when LIN bus is recessive).
TRANSMITTER INPUT PIN (TXD)
The TXD pin is the transmitter input of the LIN interface
and controls the state of the bus output (dominant when TXD
is LOW, recessive when TXD is HIGH).
GROUND PINS (GND, TGND, AND AGND)
The 33689 has three different types of ground pins.
• The GND pin is the electrical ground pin for the device.
• The AGND is the analog ground pin for the voltage
regulator and current sense operational amplifier.
• The four TGND pins are the thermal ground pins for the
device.
Important The GND, the AGND, and the four TGND pins
must be connected together to a ground external to the
33689.
33689
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
WINDOW WATCHDOG
The window watchdog can be configured using an external
resistor at WDC pin. The watchdog is cleared through
MODE1 and MODE2 bit in the SPI Register (refer to Table 2,
page 24; also refer to the section entitled Functional Pin
Description on page 19.
A watchdog clear is only allowed in the open window (see
Figure 1). If the watchdog is cleared in the closed window or
has not been cleared at the end of the open window, the
watchdog will generate a reset on the RST pin and reset the
whole device.
Note The watchdog clear in Normal request mode
(150 ms) (first watchdog clear) has no window.
Window Closed.
No Watchdog Clear Allowed
Window Open
for Watchdog Clear
the device. The output of the regulator is also connected to
the VDD pin to provide the 5.0 V to the microcontroller.
Current Limit (Overcurrent) Protection
The voltage regulator has current limit to protect the device
against overcurrent and short circuit conditions.
Overtemperature Protection
The voltage regulator also features overtemperature
protection that has an overtemperature warning (Interrupt VDDT) and an overtemperature shutdown.
Stop Mode
During Stop mode, the Stop mode regulator supplies a
regulated output voltage. The Stop mode regulator has a
limited output current capability.
Sleep Mode
t WDC * 50%
t WDC * 50%
Watchdog Period
t WDC
In Sleep mode, the voltage regulator external VDD is
turned off.
VDD VOLTAGE REGULATOR TEMPERATURE
PREWARNING
Figure 1. Window Watchdog Operation
Window Watchdog Configuration
If the WDC pin is left open, the default watchdog period is
selected (typ. 150 ms). If no watchdog function is required,
the WDC pin must be connected to GND.
The watchdog timer’s period is calculated using the
following formula:
t WDC = 0.991 * R +0.648 (with R in kΩ and t WDC in ms).
VDD VOLTAGE REGULATOR
The 33689 chip contains a low-power, low dropout voltage
regulator to provide internal power and external power for the
MCU. The on-chip regulator consist of two elements, the
main voltage regulator and the low-voltage reset circuit.
The VDD regulator accepts an unregulated input supply
and provides a regulated VDD supply to all digital sections of
VDD voltage regulator temperature prewarning (VDDT) is
generated if the voltage regulator temperature is above the
TPRE threshold. It will set the VDDT bit in the SPI Register
and an interrupt will be initiated. The VDDT bit remains set as
long as the error condition is present.
During Sleep and Stop modes the VDD voltage regulator
temperature prewarning circuitry is disabled.
HIGH-SIDE SWITCH THERMAL SHUTDOWN
The high-side switch thermal shutdown HSST is
generated if one of the high-side switches HS1 : HS3 is above
the HSST threshold. It will shutdown all high-side switches
and set the HSST flag in the SPI Register, and an interrupt
will be initiated. The HSST bit remains set as long as the error
condition is present. During Sleep and Stop modes the highside switch thermal shutdown circuitry is disabled.
33689
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Freescale Semiconductor
21
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
As described below and depicted in Figure 1 below and
Table 1 on page 23, the 33689 has three operational modes:
Normal, Sleep, and Stop. Operational modes are controlled
by MODE1 and MODE2 bits in the SPI Register (refer to
Logic Commands and Registers on page 24). In additional,
there are two transitional modes: Reset and Normal Request.
RESET MODE
At power up, the 33689 switches automatically to Reset
Mode for 1 ms if VDD goes high. If VDD stays low, after
150 ms the 33689 goes in Sleep Mode.
NORMAL REQUEST MODE
Before entering in Normal Request Mode, the 33689 stays
for 1 ms in Reset Mode. In this mode, the LIN bus can
transmit and receive information.
VDD LOW (150 ms) Expired & VSUV Bit = Logic [0]
VDD HIGH & Reset Counter (1.0 ms) Expired & Watchdog Not Selected
VDD HIGH & Reset Counter (1.0 ms)
Expired & Watchdog Selected
VDD LOW
Sleep Command
Stop
Command
Wake-Up & Watchdog Selected
Normal
VDD LOW OR (Watchdog
Fail & Watchdog Selected)
Wake-Up &
Watchdog Not
Selected
33689 Power-Up
Power
Down
VDD LOW OR
(Normal Request
Timeout Occurs
[150 ms] & Watchdog
Selected)
Watchdog
Trigger
Normal
Request
Reset
Stop
Wake-Up
Sleep
Legend
Watchdog Selected: External resistor between WDC pin and GND or WDC pin open.
Watchdog Not Selected: WDC pin connected to GND.
Watchdog Fail: Watchdog trigger occurs in closed window or no SPI Watchdog trigger command.
Stop Command: SPI stop command.
Sleep Command: SPI sleep request followed by SPI sleep command.
Wake-Up: L1 or L2 state change or LIN bus wake-up or CS rising edge.
Figure 1. 33689 Modes State Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
NORMAL MODE
Entering Sleep Mode
In Normal Mode, the 33689 has slew rate and timing
compatible with the LIN protocol specification. The LIN bus
can transmit and receive information. The VDD regulator is
ON and the watchdog function can be enabled.
First and second SPI commands (with bit D6 = 1, D7 = 1,
D5 = 0 or 1, D1 = 0, and D0 = 0) 11x00000 must be sent.
Entering Stop Mode
First and second SPI commands (with bit D6 = 1, D7 = 1,
D5 = 0 or 1, D1 = 0, and D0 = 1) 11x00001 must be sent.
SLEEP AND STOP MODE
To safely enter Sleep or Stop modes and to ensure that
these modes are not inadvertently entered due to noise
issues during SPI transmission, a dedicated sequence must
be sent twice: data with the bits controlling the LIN bus and
the device mode.
Sleep or Stop modes are entered after the second SPI
command. Register bit D5 must be set accordingly.
Table 1. Operational Modes and Associated Functions
Device Mode
Watchdog
Function
HS1, HS2, HS3
LIN Interface
Operational
Amplifier
LOW for 1.0 ms
typical, then
HIGH (if VDD
above threshold)
Disabled
OFF
Recessive only
Not active
N/A
HIGH.
Active LOW if
VDD
undervoltage
occurs and if
Normal Request
timeout (if
Watchdog
enabled)
150 ms timeout
if Watchdog
enabled
ON or OFF
Transmit and
receive
Not active
VDD: ON
N/A
HIGH.
Active LOW if
VDD
undervoltage
occurs or if
Watchdog fail (if
Watchdog
enabled)
Window
Watchdog if
enabled
ON or OFF
Transmit and
receive
Active
VDD: ON
(Limited current
capability)
LIN and state
change on
L1:L2 inputs
Normally HIGH.
Active LOW if
VDD
undervoltage
occurs
Disabled
OFF
Recessive state
with Wake
capability
Not active
VDD: OFF
(Set to 5.0 V
after Wake-Up
to enter Normal
Request)
LIN and state
change on
L1:L2 inputs
LOW.
Go to HIGH after
Wake-Up and
VDD within
specification
Disabled
OFF
Recessive state
with Wake
capability
Not active
VDD Voltage
Regulator
Wake-Up
Capabilities
VDD: ON
N/A
VDD: ON
Reset
Normal
Request
Normal
Stop
Sleep
RST Output
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Freescale Semiconductor
23
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE AND REGISTER DESCRIPTION
During an SPI data communication, the state of MISO
reports the state of the 33689 at time of a CS HIGH-to-LOW
transition. The status flags are latched at a CS HIGH-to-LOW
transition.
As shown in Figure 2, the SPI is an 8-bit SPI. All data is
sent as bytes. The MSB, D7, is sent first. The minimum time
between two rising edges on the CS pin is 15 μs.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
D7
D6
D5
D4
D3
D2
D1
D0
MISO
MOSI
Figure 2. Data Format Description
The following tables describe the SPI Register bits,
showing reset values and reset conditions.
Table 2. SPI Register Overview
Read / Write
Information
MSB
Bits
LSB
D7
D6
D5
D4
D3
D2
D1
D0
Write
LINSL2
LINSL1
LIN-PU
HS3
HS2
HS1
MODE2
MODE1
Read
INTSRC (1)
LINWU or
LINFAIL
VSOV
VSUV or
BATFAIL(2)
VDDT
HSST
L2
L1
Write Reset
Value
0
0
0
0
0
0
—
—
Write Reset
Condition
POR,
RESET
POR,
RESET
POR
POR,
RESET
POR,
RESET
POR,
RESET
—
—
Notes
1. D7 signals interrupt source. After interrupt occurs, if D7 is a logic [1] D6 : D0 indicate the interrupt source. If D7 is a logic [0] no interrupt
has occurred and D6 : D0 report real-time status.
2. The first SPI read after a 33689 reset returns the BATFAIL status flag bit D4.
SPI Register: Write Control Bits
LINSL2 and LINSL1 — LIN Baud Rate and Low-Power
Mode Pre-Selection Bits
These bits select the LIN slew rate and requested lowpower mode in accordance with Table 3. Reset clears the
LINSL2 : 1 bits.
Table 3. LIN Slew Rate Control and Device Low Power
Mode Pre-Selection Bits (D7 and D6)
LINSL2
LINSL1
Description
0
0
LIN slew rate normal
(baud rate up to 20 kbps)
0
1
LIN slew rate slow
(baud rate up to 10 kbps)
1
0
LIN slew rate fast (for program download,
baud rate up to 100 kbps)
1
1
Low power mode (Sleep or Stop mode)
request, no change in LIN slew rate
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
LIN-PU — LIN Pullup Enable Bit
This bit controls the LIN pullup resistor during Sleep and
Stop modes in accordance with Table 4. Reset clears the
LIN-PU bit.
Table 4. LIN Pullup Termination Control Bit (D5)
LIN-PU
Description
0
30 kΩ pullup connected in Sleep and Stop mode
1
30 kΩ pullup disconnected in Sleep and Stop mode
HS3: HS1 — High-Side H3 : HS1 Enable Bits
These bits enable the HS3 : HS1 bits in accordance with
Table 5. Reset clears the HSx bit.
Note If no PWM on HS1 and HS2 is required, the IN pin
must be connected to the VDD pin.
Table 5. High-Side Switches Control Bits (D4, D3, and D2)
HS3
Description
HS2
Description
HS1
Description
0
HS3 OFF
0
HS2 OFF
0
HS1 OFF
1
HS3 ON
1
HS2 ON (if IN = 1)
1
HS1 ON (if IN = 1)
MODE2 and MODE1 — Mode Section Bits
The MODE2 and MODE1 bits control the 33689 operating
modes in accordance with Table 6.
Table 6. Mode Control Bits (D1 and D0)
MODE2
MODE1
Description
0
0
Sleep mode (3)
0
1
Stop mode
1
0
Normal mode + Watchdog clear (4)
1
1
Normal mode
To safely enter Sleep or Stop mode and to ensure that
these modes are not affected by noise issue during SPI
transmission, the Sleep / Stop commands require two SPI
transmissions.
Sleep Mode Sequence The Sleep command, as shown in
Table 7, must be sent twice.
Table 7. Sleep Command Bits
LINSL2 LINSL1 LIN-PU
1
Notes
3. Special SPI command and sequence is implemented in
order to avoid going into Sleep or Stop mode with a single
8-bit SPI command. Refer to Tables 7 and 8.
4. When a logic [0] is written to MODE1 bit while MODE2 bit
is written as a logic [1]. After the SPI command is
completed, MODE1 bit is set to logic [1] and the 33689
stays in Normal mode. In order to set the 33689 in Sleep
mode, both MODE1 and MODE2 bits must be written in
the same 8-bit SPI command. The Watchdog clear on
Normal Request mode (150 ms) has no window.
1
x
HS3
HS2
HS1
0
0
0
MODE2 MODE1
0
0
x = Don’t care.
Stop Mode Sequence The Stop command, as shown in
Table 8, must be sent twice.
Table 8. Stop Command Bits
LINSL2 LINSL1 LIN-PU
1
1
x
HS3
HS2
HS1
0
0
0
MODE2 MODE1
0
1
x = Don’t care.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
SPI Register: Read Control Bits
INTSCR — Register Content Flags or Interrupt Source
LINWU / LINFAIL — LIN Bus Status Flag Bit
The INTSCR bit, as shown in Table 9, indicates if the
register contents reflect the flags or an interrupt / wake-up
source.
This bit indicates a LIN wake-up condition or a LIN
overcurrent/overtemperature in accordance with Table 10.
Table 10. LIN Bus Status (D6)
Table 9. Interrupt Status (D7)
INTSCR
Description
0
SPI word read reflects the flag state
1
SPI word read reflects the interrupt or wake-up
source
LINWU/
LINFAIL
Description
0
No LIN bus wake-up or failure
1
LIN bus wake-up occurred or LIN overcurrent /
overtemperature
VSOV — Overvoltage Flag Bit, VSUV / BATFAIL — Undervoltage Flag Bit, VDDT — VDD Voltage Regulator Status
Flag Bit, and HSST — High-Side Status Flag Bit
Table 11 indicates the register contents of the following
flags:
• VSOV flag is set on an overvoltage condition.
• VSUV/BATFAIL flag is set on an undervoltage condition.
• VDDT flag is set as pre-warning in case of an
overtemperature condition on the voltage regulator.
• HSST flag is set on overtemperature conditions on one of
the high-side outputs.
Table 11. Over- and Undervoltage, VDD Voltage Regulator, and High-Side Status Flag Bits (D5, D4, D3, and D2)
VSOV
Description
VSUV/
BATFAIL
Description
VDDT
Description
HSST
Description
0
VSUP below 19 V
0
VSUP above 6.0 V
0
No overtemperature
0
HS
No overtemperature
1
VSUP above 18 V
1
VSUP below 6.0 V
1
VDD overtemperature
pre-warning
1
HS1, HS2, or HS3
OFF
(overtemperature)
L2 and L1 — Wake-Up Inputs L2 and L1 Status Flag Bit
The L2 and L1 flags, as shown in Table 12, reflect the
status of the L2 and L1 input pins and indicate the wake-up
source.
Table 12. Switch Input Wake-Up and Real Time Status (D1 and D0)
L2
Description
L1
Description
0
L2 input LOW
0
L1 input LOW
1
L2 input HIGH or wake-up by L2
(first register read after wake-up)
1
L1 input HIGH or wake-up by L1
(first register read after wake-up)
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The 33689 can be configured in several applications. Figure 3 shows the 33689 in the typical master node application.
33689
VDD1
C3
C4
VDD
5.0 V/50 mA
RST
Reset
Control
WDC
R1
VBAT
D1
VS1
Voltage
Regulator
C1
C2
Window
Watchdog
VS2
IN
HS1
MOSI
MISO
SCLK
CS
SPI and
Mode
Control
HS2
Pre-Driver
INT
HS3
VDD1
VCC
MCU
EXT INPUT
E-
R2
R3
L2
C7
E+
C5
Current
Sense
Op Amp
R6
R7
L1
R4
D2
VS1
OUT
R5
TXD
LIN Physical Interface
RXD
LIN Bus
C6
AGND
Component Values
C1=47 μF
C2=C4=C5=100 nF
C3=10 μF
C6=220 pF
C7=4.7 nF
TGND
L1(1)
LIN
R8(1)
GND
R1=33 kΩ
R2 and R3 depend on the application
R4>5.0 kΩ
R5=1.0 kΩ
R6= 10 kΩ
R7=2.2 kΩ
R8=Varistor type TDK AVR-M1608C270MBAAB(1)
L1 = SMD Ferrite Bead-Type TDK MMZ2012Y202B(1)
Notes:
1. L1 and R8 are external components to improve EMC and ESD performances.
2. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit
drawings or tables. While freescale offers component recommendations in this configuration, it is the customer’s responsibility to
validate their application.
Figure 3. 33689 in Typical Master Node Application
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A
drawing number below.
EW SUFFIX (PB-FREE)
32-PIN SOICW
98ARH99137A
ISSUE B
33689
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS (CONTINUED)
PACKAGING DIMENSIONS (CONTINUED)
EW SUFFIX (PB-FREE)
32-PIN SOICW
98ARH99137A
ISSUE B
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
6.0
6/2006
•
•
•
•
•
Implemented Revision History page
Updated Outline Drawing to Revision “B”
Eliminated all pages (pages 30 to 47) referring to the MC33689DWB/R2 device
Removed MC33689DWB/R2 from the orderable parts information
Updated to the prevailing form and style
7.0
8/2006
•
Removed MC33689DEW/R2 and replaced with MCZ33689DEW/R2 in the Ordering Information
block
8.0
9/2012
•
•
•
•
Updated orderable part number from MC33689DEW to MC33689DPEW
Removed MCZ33689DPEW
Removed DWB suffix from drawing info
Updated Freescale form and style
33689
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
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application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters that
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© 2012 Freescale Semiconductor, Inc.
Document Number: MC33689
Rev. 8.0
9/2012
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