Data Sheet

UJA1023
LIN-I/O slave
Rev. 5 — 17 August 2010
Product data sheet
1. General description
The UJA1023 is a stand-alone Local Interconnect Network (LIN) I/O slave that replaces
basic components commonly used in electronic control units for input and output handling.
The UJA1023 contains a LIN 2.0 controller, an integrated LIN transceiver which is
LIN 2.0 / SAE J2602 compliant and LIN 1.3 compatible, a 30 kΩ termination resistor
necessary for LIN-slaves, and eight I/O ports which are configurable via the LIN bus.
An automatic bit rate synchronization circuit adapts to any (master) bit rate between
1 kbit/s and 20 kbit/s. For this, an oscillator is integrated.
The LIN protocol will be handled autonomously and both Node Address (NAD) and LIN
frame Identifier (ID) programming will be done by a master request and an optional slave
response message in combination with a daisy chain or plug coding function.
The eight bidirectional I/O pins are configurable via LIN bus messages and can have the
following functions:
• Input:
– Standard input pin
– Local wake-up
– Edge capturing on falling, rising or both edges
– Analog input pin
– Switch matrix (in combination with output pins)
• Output:
– Standard output pin as high-side driver, low-side driver or push-pull driver
– Cyclic sense mode for local wake-up
– Pulse Width Modulation (PWM) mode; for example, for back light illumination
– Switch matrix (in combination with input pins)
On entering a low-power mode it is possible to hold the last output state or to change over
to a user programmable output state. In case of a failure (e.g. LIN bus short to ground) the
output changes over to a user programmable limp home output state and the low-power
Limp home mode will be entered.
Due to the advanced low-power behavior the power consumption of the UJA1023 in
low-power mode is minimal.
UJA1023
NXP Semiconductors
LIN-I/O slave
2. Features and benefits
„ Automatic bit rate synchronization to any (master) bit rate between 1 kbit/s
and 20 kbit/s
„ Integrated LIN 2.0 / SAE J2602 transceiver (including 30 kΩ termination resistor)
„ Eight bidirectional I/O pins
„ 4 × 2, 4 × 3, or 4 × 4 switch matrix to support reading and supplying a maximum
number of 16 switches
„ Outputs configurable as high-side and/or low-side driver and as cyclic or PWM driver
„ 8-bit ADC
„ Advanced low-power behavior
„ On-chip oscillator
„ Node Address (NAD) configuration via daisy chain or plug coding
„ Inputs supporting local wake-up and edge capturing
„ Configurable Sleep mode
„ Limp home configuration in case of error conditions
„ Extremely low electromagnetic emission
„ High immunity against electromagnetic interference
„ Bus line protected in accordance with ISO 7637
„ Extended ambient temperature range (−40 °C to +125 °C)
3. Quick reference data
Table 1.
Quick reference data
Symbol Parameter
VBAT
UJA1023
Product data sheet
Conditions
supply voltage on pin BAT
Min
Typ
Max
Unit
all operating modes
[1]
5.5
-
27
V
[2]
-
45
65
μA
−27
-
+40
V
−40
-
+150
°C
−8
-
+8
kV
IBAT
supply current on pin BAT
LH sleep, Sleep and
Limp home mode;
VBAT = 8.1 V to 27 V
VLIN
voltage on pin LIN
DC value
Tvj
virtual junction temperature
VESD
electrostatic discharge voltage
human body model;
on pins LIN, BAT, C1, C2 and C3 C = 100 pF; R = 1.5 kΩ
[3]
[1]
Valid for the UJA1023T/2R04/C; for the UJA1023T/2R04, VBAT = 6.5 V to 27 V.
[2]
All outputs turned off, LIN recessive, Vth1 selected.
[3]
Junction temperature in accordance with IEC60747-1. An alternative definition of Tvj = Tamb + P × Rth(j-a),
where Rth(j-a) is a fixed value to be used for calculating Tvj. The rating for Tvj limits the allowable
combinations of power dissipation (P) and ambient temperature (Tamb).
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
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UJA1023
NXP Semiconductors
LIN-I/O slave
4. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
UJA1023T/2R04/C[1]
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
UJA1023T/2R04[1]
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
[1]
VBAT = 5.5 V to 27 V for the UJA1023T/2R04/C; VBAT = 6.5 V to 27 V for the UJA1023T/2R04 (see Table 32).
5. Block diagram
BAT
GND
3
VOLTAGE
REGULATOR
5
1
VIO
UJA1023
INH
TERMINATION
LIN
4
2
INH
ADC
LIN
TRANSCEIVER
AUTO
BIT RATE
DETECTION
LIN
CONTROLLER
I/O BLOCK
9 to 16
P0 to P7
OSCILLATOR
PWM
C1 to C3
6 to 8
CYCLIC
SENSE
CONFIGURATION
mdb488
Fig 1.
Block diagram
UJA1023
Product data sheet
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© NXP B.V. 2010. All rights reserved.
3 of 49
UJA1023
NXP Semiconductors
LIN-I/O slave
6. Pinning information
6.1 Pinning
VIO
1
16 P7
INH
2
15 P6
BAT
3
14 P5
LIN
4
13 P4
UJA1023T
GND
5
12 P3
C1
6
11 P2
C2
7
10 P1
C3
8
9
P0
001aab877
Fig 2.
Pin configuration
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type[1]
Description
VIO
1
I
reference input for level adaptation of the I/O pins P0 to P7
INH
2
O
inhibit output for controlling an external voltage regulator or internal
ADC
BAT
3
I
battery supply
LIN
4
I/O
LIN bus line
GND
5
I
ground
C1
6
I
configuration input 1 for LIN slave NAD assignment
C2
7
I
configuration input 2 for LIN slave NAD assignment
C3
8
I/O
configuration input / output 3 for LIN slave NAD assignment
P0
9
I/O
bidirectional I/O pin 0
P1
10
I/O
bidirectional I/O pin 1
P2
11
I/O
bidirectional I/O pin 2
P3
12
I/O
bidirectional I/O pin 3
P4
13
I/O
bidirectional I/O pin 4
P5
14
I/O
bidirectional I/O pin 5
P6
15
I/O
bidirectional I/O pin 6
P7
16
I/O
bidirectional I/O pin 7
[1]
I = input;
O = output;
I/O = input or output.
UJA1023
Product data sheet
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
4 of 49
UJA1023
NXP Semiconductors
LIN-I/O slave
7. Functional description
The UJA1023 combines all blocks necessary to work as a stand-alone LIN slave. Various
I/O functions typically used in a car are supported. For a more detailed description refer to
Section 7.2 to Section 7.6. The block diagram is shown in Figure 1.
7.1 Short description of the UJA1023
7.1.1 LIN controller
The LIN 2.0 controller monitors and evaluates the LIN messages in order to process the
LIN commands. It supervises and executes the NAD assignment, ID assignment and
I/O-configuration and controls the operating modes of the UJA1023.
The NAD configuration is done by a combination of a LIN master request frame and a
setting done by either a daisy chain or plug ID code.
7.1.2 LIN transceiver (including termination)
The LIN transceiver, which is LIN 2.0 / SAE J2602 compliant, is the interface between the
internal LIN controller and the physical LIN bus. The transmit data stream of the LIN
controller is converted into a bus signal with an optimized wave shape to minimize
electromagnetic emission. The required LIN slave termination of 30 kΩ is already
integrated. In case of LIN bus faults the UJA1023 switches to the low-power Limp home
mode.
7.1.3 Automatic bit rate detection
The automatic bit rate detection adapts to the LIN master’s bit rate. Any bit rate between
1 kbit/s and 20 kbit/s can be handled. This block checks whether the synchronization
break and synchronization field are valid. If not, the message will be rejected.
7.1.4 Oscillator
The on-chip oscillator provides the internal clock signal for some digital functions and is
the time reference for the automatic bit rate detection.
7.1.5 I/O block
The I/O block controls the configuration of the I/O pins. The LIN master configures the I/O
pin functionality by means of a master request frame and an optional slave response
frame.
Besides the standard level input and output behavior the following functions are also
handled by the UJA1023: local wake-up, cyclic input, edge capture, PWM output, switch
matrix I/O and AD conversion.
7.1.6 ADC
With three external components an 8-bit ADC function can be implemented. Each of the
eight bidirectional I/O pins can be used as input for the ADC, one at a time.
7.1.7 PWM
Each pin can be configured with a Pulse Width Modulation (PWM) function. The resolution
is 8-bit and the base frequency is approximately 2.7 kHz.
UJA1023
Product data sheet
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
5 of 49
UJA1023
NXP Semiconductors
LIN-I/O slave
7.1.8 Cyclic sense
To reduce current consumption, the cyclic sense function can be used to read a switch.
The switch will be supplied and read back periodically.
7.2 LIN controller
7.2.1 Configuration
In this data sheet basic knowledge of the “LIN diagnostic and configuration specification,
Rev. 2.0” is expected.
7.2.1.1
Message sequence
The UJA1023 conforms to the “LIN diagnostic and configuration specification, Rev. 2.0”
and is compatible with LIN 1.3.
The UJA1023 can be configured via the LIN command frames ‘Master Request’
(MasterReq) and ‘Slave Response’ (SlaveResp). Both frames consist of eight data bytes.
The MasterReq is used to send configuration data from the master to the slaves, whereas
the slave being addressed by the prior MasterReq will answer with the related data on
demand.
Depending on the usage of the MasterReq the meaning of the data bytes can be different.
Thus each LIN slave evaluates these data bytes.
Using MasterReq and SlaveResp for the UJA1023 configuration flow, as shown in
Figure 3, is a so-called ‘handshake’ concept. The slave echoes its received MasterReq
data in the SlaveResp, so the master can review slave configuration data. The use of the
SlaveResp is optional.
The configuration flow is not disturbed if LIN commands other than shown in Figure 3 are
sent to other LIN slave nodes. Thus the LIN master can transmit other LIN messages
while it (re)configures the UJA1023.
Remarks:
• The I/O configuration will be enabled during the first usage of the UJA1023 message
frames (see Section 7.2.5) of the PxResp or PxReq
• Notation Px is used in this document when referring to a function or property of any of
the I/O pins P0 to P7
• For correct I/O configuration, the configuration requests must be sent in sequential
order of first, second and third configuration data block
UJA1023
Product data sheet
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
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NXP Semiconductors
UJA1023
Product data sheet
Rev. 5 — 17 August 2010
All information provided in this document is subject to legal disclaimers.
assign NAD
(optional)
assign frame ID
slave I/O configuration
via data dump
enable new I/O
configuration
PxResp
SlaveResp
MasterReq
SlaveResp
MasterReq
SlaveResp
ID: 3C
ID: 3D
ID: 3C
ID: 3D
ID: 3C
ID: 3D
RxReq
mce653
UJA1023
Typical configuration flow
configured
LIN-I/O slave
7 of 49
© NXP B.V. 2010. All rights reserved.
Fig 3.
MasterReq
UJA1023
NXP Semiconductors
LIN-I/O slave
7.2.1.2
LIN slave node address assignment
The default slave Node Address (NAD) after power-on depends on the input levels of the
configuration pins C1, C2 and C3. These pins will be sampled directly after the power-on
event. The relation between the configuration pins and the NAD is shown in Table 4.
Table 4.
Default NAD after power-on
Configuration pins
Default NAD (hex)
C3
C2
C1
0
0
0
60
0
0
1
61
0
1
0
62
0
1
1
63
1
0
0
64
1
0
1
65
1
1
0
66
1
1
1
67
In case a different NAD is necessary the assign NAD command has to be used. The
assign NAD request is carried out if the Service Identifier (SID) in the third data byte of the
MasterReq is the assign NAD request and the fourth to seventh data bytes are the LIN
supplier codes of Philips (0x0011) and UJA1023 function ID (0x0000).
Data bytes of assign NAD request[1]
Table 5.
Data
byte
7
6
5
4
3
2
1
0
Default
value
(hex)
D0
d
d
d
d
d
d
d
d
08
D1
0
0
0
0
0
1
1
0
06
D2
1
0
1
1
0
0
0
0
B0
D3
0
0
0
1
0
0
0
1
11
D4
0
0
0
0
0
0
0
0
00
D5
0
0
0
0
0
0
0
0
00
D6
0
0
0
0
0
0
0
0
00
D7
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
[1]
UJA1023
Product data sheet
d = different values possible; see Table 6.
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© NXP B.V. 2010. All rights reserved.
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UJA1023
NXP Semiconductors
LIN-I/O slave
Table 6.
Bit description of assign NAD request
Byte
Bit
Symbol
Description
D0
7 to 0
C[3:1]
Initial NAD. This byte defines the initial NAD, refer to the
related items topics
0x08 to 0x0F (D0[0] = C1, D0[1] = C2 and
D0[2] = C3) defines Plug ID; D0[3] = 1 for Plug ID
configuration
0x20 = daisy chain on; enable daisy chain pin drivers and
receivers
0x21 = assign NAD via daisy chain
0x23 = daisy chain off; disable daisy chain pin drivers and
receivers
D1
7 to 0
PCI
Protocol control information.
D2
7 to 0
SID
Service identifier. As SlaveResp the RSID code will be 0xF0.
-
Supplier ID. Fixed code 0x0011 for Philips.
D3 and D4 7 to 0
D5 and D6 7 to 0
-
Function ID. For the UJA1023 this code is fixed as 0x0000.
D7
NAD[7:0]
Slave Node Address (NAD). NAD values are in the range 1 to
127, while 0 and 128 to 255 are reserved for other purposes.
7 to 0
The format of the positive response is shown in Table 7.
Positive response assign NAD request[1]
Table 7.
Data
byte
7
6
5
4
3
2
1
0
Default
value
(hex)
D0
d
d
d
d
d
d
d
d
08
D1
0
0
0
0
0
0
0
1
01
D2
1
1
1
1
0
0
0
0
F0
D3
1
1
1
1
1
1
1
1
FF
D4
1
1
1
1
1
1
1
1
FF
D5
1
1
1
1
1
1
1
1
FF
D6
1
1
1
1
1
1
1
1
FF
D7
1
1
1
1
1
1
1
1
FF
[1]
d = different values possible; see Table 6.
The NAD assignment can be done via Daisy Chain (DC), (see Section “Daisy chain NAD
assignment”) as well as via Plug ID (see Section “Plug ID NAD assignment”). The type of
NAD assignment can be distinguished on the value of the initial NAD, which is the first
data byte D0 of the MasterReq assign NAD request. For reliability reasons the
assignment mode decision is valid only if the combination of D0 to D6 (see Table 5) is
true. After power-on the UJA1023 message identifiers PxReq and PxResp (see
Section 7.2.5) are disabled. This is also true for NAD reassignment. In this case the
message identifiers PxReq, PxResp and I/O configuration are disabled.
UJA1023
Product data sheet
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
9 of 49
UJA1023
NXP Semiconductors
LIN-I/O slave
Daisy chain NAD assignment: Once the UJA1023 receives the assign NAD MasterReq
frame and the type of configuration is daisy chain, the following actions can take place,
depending on the initial NAD value:
• Initial NAD 0x20: Daisy chain on, the C1 to C3 pin drivers are enabled
• Initial NAD 0x21: The input level on the configuration pin C1 and the status flag of the
internal DC-switch is read. The UJA1023 will be configured if C1 is LOW and the
DC-switch is open (see slave 2 in Figure 4). The UJA1023 under daisy chain
configuration uses the data byte D7 as new NAD for its further LIN configuration
requests (e.g. Assign Frame ID). After the NAD assignment the DC-switch at pin C3 is
closed, which puts through the daisy chain signal to the next slave. The switch will be
opened again as soon as an Assign NAD request with initial NAD daisy chain off has
been received
• Initial NAD 0x23: Daisy chain off, the C1 to C3 pin drivers are disabled
After the NAD assignment, for example, the ‘assign frame ID’ can be used to assign
specific ID numbers.
The internal pull-up resistors at pin C1 to C3 are active during the assign NAD process
only. Thus it causes no permanent current (see also Section 7.4) and reduces power
consumption especially in the low-power modes.
Remark: There is no slave response to assign NAD requests using the initial NAD 0x20
and NAD 0x23.
UJA1023
Product data sheet
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
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IN CONFIGURATION
UJA1023
MASTER
Rev. 5 — 17 August 2010
All information provided in this document is subject to legal disclaimers.
ASSIGN NAD
INITIAL NAD = DAISY CHAIN
INITIAL NAD = DAISY CHAIN
INITIAL NAD = DAISY CHAIN
BAT
PLUG
BAT
LIN
BAT
DC FLAG
C1
BAT
&
C2
PLUG
C3
GND
BAT
LIN
BAT
DC FLAG
BAT
&
GND
n
ASSIGN NAD
BAT
LIN
UJA1023
2
ASSIGN NAD
DC FLAG
BAT
NOT CONFIGURED
UJA1023
1
NXP Semiconductors
UJA1023
Product data sheet
CONFIGURED
C1
&
C2
PLUG
C3
GND
BAT
LIN
C1
C2
C3
GND
PLUG
BAT
GND
mdb492
UJA1023
Daisy chain ID
LIN-I/O slave
11 of 49
© NXP B.V. 2010. All rights reserved.
Fig 4.
UJA1023
NXP Semiconductors
LIN-I/O slave
Plug ID NAD assignment: Here the UJA1023 can be addressed via the pins C1, C2, and
C3. Once the assign NAD MasterReq with the initial NAD ‘Plug ID configuration’ is
received, the UJA1023 compares the values of the configuration pins C3, C2, and C1 with
the values of the data bits D0[2:0]. If the values are equal and bits D0[7:4] are logic 0 and
D0[3] is logic 1, the value of D7 is used as new NAD for the UJA1023.
Next, for example, the ‘assign frame ID’ can be used to assign specific ID numbers.
The internal pull-up resistors at pin C1 to C3 are active during the assign NAD process
only. Thus it causes no permanent current (see also Section 7.4) and reduces power
consumption especially in the low-power modes.
UJA1023
Product data sheet
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
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UJA1023
1
ASSIGN NAD
Rev. 5 — 17 August 2010
All information provided in this document is subject to legal disclaimers.
D0.0
BAT
LIN
GND
PLUG
BAT
LIN
NAD
NAD
DATA BYTE 7
DATA BYTE 7
DATA BYTE 7
BAT
C1
INITIAL NAD = PLUG
NAD
D0.1
D0.2
D0.0
PLUG
D0.2
D0.0
COMPARATOR
BAT
C2
D0.1
BAT
C3
GND
BAT
LIN
BAT
C1
PLUG
D0.1
D0.2
COMPARATOR
BAT
C2
C1 = 0
C2 = 0
C3 = 0
ASSIGN NAD
INITIAL NAD = PLUG
COMPARATOR
BAT
8
C1 = 0
C2 = 1
C3 = 1
ASSIGN NAD
INITIAL NAD = PLUG
UJA1023
2
C1 = 1
C2 = 1
C3 = 1
NXP Semiconductors
UJA1023
Product data sheet
UJA1023
MASTER
BAT
C3
GND
BAT
LIN
BAT
C1
BAT
C2
C3
GND
PLUG
BAT
GND
mdb493
UJA1023
Plug ID
LIN-I/O slave
13 of 49
© NXP B.V. 2010. All rights reserved.
Fig 5.
UJA1023
NXP Semiconductors
LIN-I/O slave
7.2.1.3
Assign frame ID
By means of the assign frame ID command the LIN message identifier PxReq and
PxResp can be changed to the desired values.
Table 8.
Assign frame ID request bit allocation
Data
byte
7
6
5
4
3
2
1
0
Default
value (hex)
D0
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
D1
0
0
0
0
0
1
1
0
06
D2
1
0
1
1
0
0
0
1
B1
D3
0
0
0
1
0
0
0
1
11
D4
0
0
0
0
0
0
0
0
00
D5
0
0
0
0
0
0
0
0
00
D6
0
0
0
0
0
0
0
0
00
D7
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
protected ID
Table 9.
Assign frame ID request bit description
Byte
Bit
Symbol
Description
D0
7 to 0
NAD[7:0]
Slave Node Address (NAD). NAD values are in the range
from 1 to 127, while 0 and 128 to 255 are reserved for other
purposes. The slave node address is assigned with the
assign NAD command (see Table 5).
D1
7 to 0
PCI[7:0]
Protocol control information.
D2
7 to 0
SID[7:0]
Service identifier. As SlaveResp the RSID code will be 0xF1.
D3 and D4
7 to 0
-
Supplier ID. Fixed to 0x0011 for Philips.
D5 and D6
7 to 0
-
Message ID. Defines the assignment of the protected ID to
PxResp and PxReq
0x0000: PxReq = protected ID; PxResp = protected ID + 1
0x0001: PxReq = unchanged; PxResp = protected ID
0x0002: PxReq = protected ID; PxResp = unchanged
D7
7 to 0
ID[7:0]
Protected ID. Defines the protected ID.
The format of the positive response is shown in Table 10.
Table 10.
UJA1023
Product data sheet
Positive response assign frame ID
Data
byte
7
6
5
4
3
2
1
0
Default
value
(hex)
D0
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
D1
0
0
0
0
0
0
0
1
01
D2
1
1
1
1
0
0
0
1
F1
D3
1
1
1
1
1
1
1
1
FF
D4
1
1
1
1
1
1
1
1
FF
D5
1
1
1
1
1
1
1
1
FF
D6
1
1
1
1
1
1
1
1
FF
D7
1
1
1
1
1
1
1
1
FF
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LIN-I/O slave
7.2.1.4
Read by identifier
It is possible to read the supplier identifier, function identifier and the variant of the
UJA1023 by means of the read by identifier request. The format for this request is shown
in Table 11. The positive response is shown in Table 13, the negative response is shown
in Table 14.
Table 11.
Read by identifier (LIN product identification)
Data
byte
7
6
5
4
3
2
1
0
Default
value
(hex)
D0
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
D1
0
0
0
0
0
1
1
0
06
D2
1
0
1
1
0
0
1
0
B2
D3
0
0
0
0
0
0
0
0
00
D4
0
0
0
1
0
0
0
1
11
D5
0
0
0
0
0
0
0
0
00
D6
0
0
0
0
0
0
0
0
00
D7
0
0
0
0
0
0
0
0
00
Table 12.
Read by identifier bit description
Byte
Bit
Symbol
Description
D0
7 to 0
NAD[7:0]
Slave Node Address (NAD). NAD values are in the range
from 1 to 127, while 0 and 128 to 255 are reserved for other
purposes. The slave node address is assigned with the
assign NAD command (see Table 5).
D1
7 to 0
PCI[7:0]
Protocol control information.
D2
7 to 0
SID[7:0]
Service identifier. As SlaveResp the RSID code will be 0xF2
for a positive response and 0x7F for a negative response.
D3
7 to 1
-
Identifier. Only the LIN product identifier 0x00 is supported.
D4 and D5
7 to 0
-
Supplier ID. Fixed to 0x0011 for Philips.
D6 and D7
7 to 0
-
Function ID. For the UJA1023 this code is fixed to 0x0000.
Read by identifier positive response[1]
Table 13.
Data
byte
7
6
5
4
3
2
1
0
Default
value
(hex)
D0
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
D1
0
0
0
0
0
1
1
0
06
D2
1
1
1
1
0
0
1
0
F2
D3
0
0
0
1
0
0
0
1
11
D4
0
0
0
0
0
0
0
0
00
D5
0
0
0
0
0
0
0
0
00
D6
0
0
0
0
0
0
0
0
00
D7
d
d
d
d
d
d
d
d
variant
[1]
UJA1023
Product data sheet
d = different values possible; see Table 12.
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UJA1023
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LIN-I/O slave
Table 14.
7.2.1.5
Read by identifier negative response
Data
byte
7
6
5
4
3
2
1
0
Default
value
(hex)
D0
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
D1
0
0
0
0
0
0
1
1
03
D2
0
1
1
1
1
1
1
1
7F
D3
1
0
1
1
0
0
1
0
B2
D4
0
0
0
1
0
0
1
0
12
D5
1
1
1
1
1
1
1
1
FF
D6
1
1
1
1
1
1
1
1
FF
D7
1
1
1
1
1
1
1
1
FF
I/O configuration
The I/O configuration is done via the LIN configuration request ‘Data Dump’, where the
first data byte of the MasterReq contains the slave node address NAD. The I/O-pin
configuration process starts only, if the received slave node address matches the own
UJA1023 node address and if data byte D2 (SID) is 0xB4.
As with the other configuration commands, the master transmits the I/O-pin configuration
data via the MasterReq message. Due to the limited amount of data bytes within the LIN
configuration command ‘Data Dump’, the configuration and diagnosis is split-up into four
blocks. The configuration and diagnosis blocks are distinguished on bits 6 and 7 of data
byte D3. The master can review the new configuration data via the SlaveResp message.
Finally if the master considers the received configuration data of the LIN-I/O to be correct,
it can enable the slave I/O-configuration by using the UJA1023 message frames (see
Section 7.2.5) PxResp or PxReq.
It should be noted that for correct I/O configuration, the configuration requests must be
sent in sequential order of: first, second and third configuration data block.
Table 15.
UJA1023
Product data sheet
First I/O configuration data block bit allocation
Data
byte
7
6
5
4
3
2
1
0
Default
value
(hex)
D0
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
D1
0
0
0
0
0
1
1
0
06
D2
1
0
1
1
0
1
0
0
B4
D3
0
0
IM1
IM0
RxDL
ADCIN2 ADCIN1 ADCIN0 00
D4
HSE7
HSE6
HSE5
HSE4
HSE3
HSE2
HSE1
HSE0
00
D5
LSE7
LSE6
LSE5
LSE4
LSE3
LSE2
LSE1
LSE0
00
D6
OM0_7
OM0_6
OM0_5
OM0_4
OM0_3
OM0_2
OM0_1
OM0_0
00
D7
OM1_7
OM1_6
OM1_5
OM1_4
OM1_3
OM1_2
OM1_1
OM1_0
00
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
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UJA1023
NXP Semiconductors
LIN-I/O slave
Table 16.
First I/O configuration data block bit description
Byte
Bit
Symbol
Description
D0
7 to 0
NAD[7:0]
Slave node address (NAD). NAD values are in the range from
1 to 127, while 0 and 128 to 255 are reserved for other
purposes. The slave node address is assigned with the
assign NAD command (see Table 5).
D1
7 to 0
PCI[7:0]
Protocol control information.
D2
7 to 0
SID[7:0]
Service identifier. As SlaveResp the RSID value will be 0xF4.
D3
7 and 6
-
00 for first configuration data block.
5 and 4
IM[1:0]
Pin INH mode. Mode will be changed after PxReq or PxResp
00 = external regulator (control of external voltage
regulator)
01 = ADC
10 = reserved, if selected both bits will be logic 1
11 = switch open
3
RxDL
Receive data length. Message PxReq contains two data
bytes if RxDL = 0 and three data bytes if RxDL = 1.
2 to 0
ADCIN[2:0]
Analog source channel selection. The number of ADCIN[2:0]
determines which of the P7 to P0 input is used. For example
if ADCIN[2:0] = 101 then P5 will be the input. ADCIN[2:0] is
used only if ADC mode is selected (IM[1:0] = 01) and
RxDL = 0 (No analog input selection at PxReq).
D4
7 to 0
HSE[7:0]
High-side enable for I/O pin Px.
D5
7 to 0
LSE[7:0]
Low-side enable for I/O pin Px.
OM0_[7:0],
OM1_[7:0]
Output mode for I/O pin Px.
D6 and D7 7 to 0
UJA1023
Product data sheet
OM1_x
OM0_x
0
0
level
0
1
reserved
1
0
cyclic sense
1
1
PWM
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UJA1023
NXP Semiconductors
LIN-I/O slave
The second configuration data block (shown in Table 17) is selected only if D3.7 = 0 and
D3.6 = 1.
Table 17.
Second I/O configuration data block bit allocation
Data
byte
7
6
5
4
3
2
1
0
Default
value (hex)
D0
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
D1
0
0
0
0
0
1
1
0
06
D2
1
0
1
1
0
1
0
0
B4
D3
0
1
LSLP
TxDL
SMC
SMW
SM1
SM0
40
D4
CM0_7
CM0_6
CM0_5
CM0_4
CM0_3
CM0_2
CM0_1
CM0_0
00
D5
CM1_7
CM1_6
CM1_5
CM1_4
CM1_3
CM1_2
CM1_1
CM1_0
00
D6
TH2/TH1
TH2/TH1
TH2/TH1
TH2/TH1
TH2/TH1
TH2/TH1
TH2/TH1
TH2/TH1
00
D7
LWM7
LWM6
LWM5
LWM4
LWM3
LWM2
LWM1
LWM0
00
Table 18.
Second I/O configuration data block bit description
Byte
Bit
Symbol
Description
D0
7 to 0
NAD[7:0]
Slave node address (NAD). NAD values are in the range
from 1 to 127, while 0 and 128 to 255 are reserved for other
purposes. The slave node address is assigned with the
assign NAD command (see Table 5).
D1
7 to 0
PCI[7:0]
Protocol control information.
D2
7 to 0
SID[7:0]
Service identifier. As SlaveResp the RSID value will be
0xF4.
D3
7 and 6
-
01 for the second configuration data block.
5
LSLP
Limp home sleep mode. If LSLP = 1, the Limp home sleep
mode is enabled. In this case the Limp Home value (LH) is
automatically used as output value if the Sleep mode is
entered.
4
TxDL
Transmit data length. Message PxResp contains two data
bytes if TxDL = 0 and four data bytes if TxDL = 1.
3
SMC
Switch matrix capture. If SMC = 1, the Switch matrix
capture mode is enabled.
2
SMW
Switch matrix wake-up. If SMW = 1, the switch matrix
wakes up upon changed input level.
1 and 0
SM[1:0]
Switch matrix enable
00 = no switch matrix
01 = 4 × 2: P3 to P0 input and P5 and P4 strong pull
down
10 = 4 × 3: P3 to P0 input and P6 to P4 strong pull down
11 = 4 × 4: P3 to P0 input and P7 to P4 strong pull down
Unassigned pins can be used as I/O. It should be noted,
however, that for the unassigned pins, which are configured
in Capture mode, the captured edge value will not be
transferred.
UJA1023
Product data sheet
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
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UJA1023
NXP Semiconductors
LIN-I/O slave
Table 18.
Second I/O configuration data block bit description …continued
Byte
Bit
D4 and D5 7 to 0
Symbol
Description
CM0_[7:0],
CM1_[7:0]
Capture mode for I/O pin Px.
CM1_x
CM0_x
0
0
no capture
0
1
falling edge
1
0
rising edge
1
1
both edges
D6
7 to 0
TH2 and TH1
Threshold select. If logic 0 (= TH1), selects Vth1 as input
threshold. If logic 1 (= TH2) selects Vth2 as input threshold,
except in Cyclic sense mode, then Vth3 is selected.
D7
7 to 0
LWM_[7:0]
Local wake-up mask. If LWM_x = 1, the corresponding Px
pin is configured as local wake-up pin. LWM_x is ignored if
Px is configured as switch matrix.
Table 19 shows the third configuration data block, that is used to define the slope of the
transmitter, selection between classic or enhanced checksum model, limp home output
value and PWM initial value. It is selected only if D3.7 = 1 and D3.6 = 0.
Table 19.
Data
byte
6
5
4
3
2
1
0
Default
value
(hex)
D0
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
D1
0
0
0
0
0
1
0
0
04
D2
1
0
1
1
0
1
0
0
B4
D3[1]
1
0
r
r
r
r
LSC
ECC
80
D4
LH7
LH6
LH5
LH4
LH3
LH2
LH1
LH0
00
D5
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
00
D6
1
1
1
1
1
1
1
1
FF
D7
1
1
1
1
1
1
1
1
FF
[1]
r = reserved, must be ‘0’.
Table 20.
UJA1023
Product data sheet
Third I/O configuration data block bit allocation
7
Third I/O configuration data block bit description
Byte
Bit
Symbol
Description
D0
7 to 0
NAD[7:0]
Slave node address (NAD). NAD values are in the range from
1 to 127, while 0 and 128 to 255 are reserved for other
purposes. The slave node address is assigned with the assign
NAD command (see Table 5).
D1
7 to 0
PCI[7:0]
Protocol control information.
D2
7 to 0
SID[7:0]
Service identifier. As SlaveResp the RSID value will be 0xF4.
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LIN-I/O slave
Table 20.
Third I/O configuration data block bit description …continued
Byte
Bit
Symbol
Description
D3
7 and 6
-
10 for the third configuration data block.
5 to 2
-
Reserved. Must be 0.
1
LSC
LIN slope control
0 = up to 20 kbit/s (default)
1 = up to 10.4 kbit/s
0
ECC
Enhanced checksum control
0 = classic checksum (default)
1 = enhanced checksum
D4
7
LH[7:0]
Limp home value. Output value in Limp home and Limp home
sleep mode.
D5
7 to 0
PWM[7:0]
PWM initial value.
-
Not used.
D6 and D7 7 to 0
Table 21 shows the fourth data block, that is selected if D3.6 = 1 and D3.7 = 1. It is not
used for I/O-pin configuration but to provide the master with diagnosis data of the
UJA1023. It is a read-only data block. If the slave node address matches and the fourth
data block is selected, the UJA1023 transmits its diagnosis data via the SlaveResp
message.
Table 21.
Data
byte
6
5
4
3
2
1
0
Default
value
(hex)
D0
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
D1
0
0
0
0
0
0
1
0
02
D2
1
0
1
1
0
1
0
0
B4
D3
1
1
0
0
0
0
0
0
C0
D4
1
1
1
1
1
1
1
1
FF
D5
1
1
1
1
1
1
1
1
FF
D6
1
1
1
1
1
1
1
1
FF
D7
1
1
1
1
1
1
1
1
FF
Table 22.
Fourth I/O diagnostic data block request frame bit description
Byte
Bit
Symbol
Description
D0
7 to 0
NAD[7:0]
Slave node address (NAD). NAD values are in the range from
1 to 127, while 0 and 128 to 255 are reserved for other
purposes. The slave node address is assigned with the
assign NAD command (see Table 5).
D1
7 to 0
PCI[7:0]
Protocol control information.
D2
7 to 0
SID[7:0]
Service identifier.
D3
7 and 6
-
11 for the fourth configuration data block.
5 to 0
-
Not used.
7 to 0
-
Not used.
D4 to D7
UJA1023
Product data sheet
Fourth I/O diagnostic data block request frame bit allocation
7
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NXP Semiconductors
LIN-I/O slave
Table 23.
Fourth I/O diagnostic data block response frame bit allocation
Data
byte
7
6
5
4
3
2
1
0
Default
value
(hex)
D0
NAD7
NAD6
NAD5
NAD4
NAD3
NAD2
NAD1
NAD0
NAD
D1
0
0
0
0
0
1
0
0
04
D2
1
1
1
1
0
1
0
0
F4
D3
1
1
0
0
0
0
0
0
C0
D4
P
RxB
CS
TxB
u[1]
NVM
LHE
ERR
00
D5
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00
D6
1
1
1
1
1
1
1
1
FF
D7
1
1
1
1
1
1
1
1
FF
[1]
Undefined.
Table 24.
Fourth I/O diagnostic data block response frame bit description
Byte
Bit
Symbol
Description
D0
7 to 0
NAD[7:0]
Slave node address (NAD). NAD values are in the range
from 1 to 127, while 0 and 128 to 255 are reserved for other
purposes. The slave node address is assigned with the
assign NAD command (see Table 5).
D1
7 to 0
PCI[7:0]
Protocol control information.
D2
7 to 0
RSID[7:0]
Response service identifier.
D3
7 and 6
-
11 for the fourth configuration data block.
5 to 0
-
Not used.
7
P
Parity error. Set if identifier parity bits are erroneous.
6
RxB
Receive error. Set if start or stop bits are erroneous during
reception.
5
CS
Checksum error. Set if checksum is erroneous.
4
TxB
Transmit error. Set if start, data or stop bits are erroneous
during transmission.
3
undefined
-
2
NVM
No valid message. Set if there is bus activity, but no valid
message frame for longer than tto(idle).
1
LHE
Set if Limp home mode is entered.
0
ERR
Response error. Sets internal signal Response_Error if there
is an RxB, CS or TxB during a response frame.
7 to 0
PL[7:0]
PxOut latch value.
-
Not used.
D4[1]
D5
D6 and D7 7 to 0
[1]
UJA1023
Product data sheet
All diagnosis flags in byte D4 are reset after data access from master.
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Rev. 5 — 17 August 2010
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21 of 49
UJA1023
NXP Semiconductors
LIN-I/O slave
7.2.1.6
Configuration examples
Example 1, UJA1023 configuration with eight low-side outputs.
//
//Example 8 LSE and walking ‘1’ pattern
//C1, C2 and C3 are GND
//SB = SyncBreak; SF = SyncField
//
SB SF 3C 60 06 B1 11 00 00 00 04 D2 //
//
SB SF 7D 60 01 F1 FF FF FF FF FF AC //
SB SF 3C 60 06 B4 00 00 FF 00 00 E4 //
SB SF 7D 60 06 F4 00 00 FF 00 00 A4 //
SB SF 3C 60 06 B4 40 00 00 00 00 A4 //
//
SB SF 7D 60 06 F4 40 00 00 00 00 64 //
SB SF 3C 60 04 B4 80 55 10 FF FF 01 //
UJA1023
Product data sheet
SB
SB
SB
SB
SF
SF
SF
SF
7D
3C
7D
C4
60
60
60
01
04
06
06
80
F4 80 55 10 FF FF C0
B2 00 11 00 00 00 D5
F2 11 00 00 00 02 93
7E
SB
SB
SB
SB
SB
SB
SB
SF
SF
SF
SF
SF
SF
SF
C4
C4
C4
C4
C4
C4
C4
02
04
08
10
20
40
80
80
80
80
80
80
80
80
7D
7B
77
6F
5F
3F
FE
//
//
//
//
//
//
//
//
//
//
//
//
Assign frameID, default NAD used and
ID(PxReq) = 04,ID(PxResp) = 05
Positive response
Datadump1, 8 × LSE
Read back configuration sent
Datadump2, no capture and
threshold select (optional)
Read back configuration sent
Data dump3, LH value = 0x55, default
PWM = 0x10 (optional)
Read back configuration sent
Read by identifier request (optional)
Positive response
IO configuration enabled and low-side
switch P0 on
Low-sideswitch P1 on
Low-sideswitch P2 on
Low-sideswitch P3 on
Low-sideswitch P4 on
Low-sideswitch P5 on
Low-sideswitch P6 on
Low-sideswitch P7 on
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
22 of 49
UJA1023
NXP Semiconductors
LIN-I/O slave
Example 2, UJA1023 configuration with eight inputs and edge capture.
//
//Example 8 inputs with capture
//C1, C2 and C3 are GND
//SB = SyncBreak; SF = SyncField
//
SB SF 3C 60 06 B1 11 00 00 00 04 D2
SB SF 7D 60 06 F4 40 FF FF 00 FF 64
SB SF 3C 60 04 B4 80 55 10 FF FF 01
//
//
//
//
//
//
//
//
//
SB
SB
SB
SB
SB
SB
SB
SB
SB
//
//
//
//
//
//
//
//
// Input 0 still set
SB
SB
SB
SB
UJA1023
Product data sheet
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
7D
3C
7D
3C
7D
3C
7D
85
80
80
85
80
85
60
60
60
60
60
60
60
00
01
06
06
06
04
06
06
00
F1
B4
F4
B4
FF
00
00
40
FF
00
00
FF
FF
00
00
FF
FF
00
00
00
FF
00
00
FF
AC
E4
A4
A4
F4 80 55 10 FF FF C0
B2 00 11 00 00 00 D5
F2 11 00 00 00 02 93
FF
01 01 FD
01 00 FE
Assign frameID, default NAD used and
ID(PxReq) = 04,ID(PxResp) = 05
Positive response
Datadump1, all outputs disabled (optional)
Read back configuration sent
Datadump2, all both edge capture and
inputs as wake-up
Read back configuration sent
Data dump3, LH value = 0x55, default
PWM = 0x10 (optional)
Read back configuration sent
Read by identifier request (optional)
Positive response
IO configuration enabled and read inputs
Dummy message
Dummy message and input 0 changes
Input 0 set and edge detected
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Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
23 of 49
UJA1023
NXP Semiconductors
LIN-I/O slave
7.2.2 Operating modes
power-on
OR
undervoltage
Configuration
Active mode
HSE, LSE: 0x00
PxO: 0x00
INH: HIGH
LIN: active
failure
OR
sleep mode command
Standby
Active mode
HSE: as configured
LSE: as configured
PxO: limp home value
INH: as configured
LIN: active
"Assign NAD"
OR
default NAD used
NAD reconfiguration
HSE, LSE: 0×00
P×O: 0×00
read DIAGNOSE data
P×O
Normal
Active mode
HSE: as configured
LSE: as configured
PxO: output data
INH: as configured
LIN: active
oscillator
fail
failure
OR
sleep mode command
limp home value
Limp Home
Low-power mode
HSE: as configured
LSE: as configured
PxO: limp home value
INH: high impedance
LIN: off-line/failsilent
remote wake-up
P×O
remote wake-up
OR
local wake-up
OR local wake-up
limp home value
sleep mode command
AND
LSLP = 1
LH Sleep
Low-power mode
HSE: as configured
LSE: as configured
PxO: limp home value
INH: high impedance
LIN: off-line
Sleep
Low-power mode
HSE: as configured
LSE: as configured
PxO: output data
INH: high impedance
LIN: off-line
mdb494
HSE = High-Side Enable
Failure: bus idle time-out or bus dominant time-out
LSE = Low-Side Enable
Local: [(LWM = 1) AND (t > twake(local); after edge
capture) causes transmission of LIN wake-up request]
AND [reception of LIN header]
PxO = PxOut
LSLP = Limp-home sleep
LWM = Local Wake-up Mask
Fig 6.
(NAD assigned
OR default used)
AND
remote wake-up
failure
I/O
reconfiguration
sleep mode command
AND
LSLP = 0
(NAD not assigned
OR not used)
AND
remote wake-up
Remote: [(t > twake(bus); after falling edge) AND recessive
again] AND [reception of LIN header].
Overview of operating modes
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LIN-I/O slave
7.2.2.1
Configuration mode
The Configuration mode can be seen as initial state after power-on or undervoltage
detection. The UJA1023 configuration values are in the default settings. The I/O
pins P0 to P7 (Px) are set to high-impedance behavior and the INH is in its External
regulator mode, which outputs a HIGH-level in order to switch on an external voltage
regulator.
In Configuration mode the UJA1023 is not configured and it has no valid identifier and,
depending on the configuration pins, a default NAD. Thus, with the exception of the
MasterReq command, all LIN slave commands are disabled. Once the UJA1023 NAD is
assigned, via the assign NAD request, or the default NAD is used for the first time, the
Normal mode is entered. If a LIN bus failure is present (bus idle time-out or bus dominant
time-out) or the sleep command has been received, the UJA1023 enters its low-power
(Limp home) mode.
7.2.2.2
Normal mode
In Normal mode the UJA1023 receives and/or transmits input/output data as well as
configuration data.
A UJA1023 in Configuration mode enters the Normal mode only after its NAD assignment
or the first usage of the default NAD. After a NAD reconfiguration, all ports that are
configured in Output mode will be set to high-impedance.
Coming from Sleep mode or Limp home sleep mode the Normal mode can be entered via
local or remote wake-up. The output register of each I/O pin P0 to P7 (PxOut) keeps its
values of the Sleep mode or Limp home sleep mode. If the INH is in External regulator
mode, it outputs a HIGH-level to switch on an external voltage regulator.
For a mode transition from Standby mode to Normal mode the diagnostic data must be
read via a SlaveResp. With this request the master acknowledges the previous failure.
The PxOut registers keep their limp home values.
7.2.2.3
Sleep mode
The UJA1023 enters its Sleep mode when the ‘Sleep mode command’ has been received
and the limp home sleep bit LSLP is reset (LSLP = 0). In Sleep mode the UJA1023 keeps
the current status on its Px. The INH will switch to high-impedance state.
After a local wake-up event the UJA1023 sends a ‘wake-up signal’ to wake up the master.
In Sleep mode the PWM and ADC are reset. The first LIN message will be lost due to
waking up the UJA1023.
7.2.2.4
Limp home sleep mode
Some applications may need dedicated HIGH and/or LOW output levels during Sleep
mode in order to achieve the lowest power dissipation of the application. Therefore the
UJA1023 provides the Limp home sleep mode (LH sleep mode). By enabling the LSLP
bit, the LH sleep mode output behavior can be configured. The LH sleep mode is enabled
if the configuration bit LSLP (D3.5) is set (LSLP = 1, see Table 18).
After a local wake-up event the UJA1023 sends a ‘wake-up signal’ to wake up the master.
In the LH sleep mode the output registers (PxOut) of the UJA1023 are loaded with the
limp home value. After a wake-up event (local or remote wake-up) the PxOut keep their
limp home value.
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LIN-I/O slave
In LH sleep mode the PWM and ADC are reset. The first LIN message will be lost due to
waking up the UJA1023.
7.2.2.5
Limp home mode and Standby mode
Limp home mode and Standby mode differ in the output of pin INH if the INH is configured
in External regulator mode. Where in Limp home mode pin INH is high-impedance and in
Standby mode pin INH is HIGH. In contrast to the Standby mode the Limp home mode is
a low-power mode.
The limp home value specifies the PxOut values in case LIN bus communication fails. The
Px configuration push-pull, open-drain or high-impedance keeps unchanged in Limp
home mode.
The Limp home mode will be entered from Normal mode if the LIN bus is short-circuited to
ground for a time exceeding the bus dominant time-out (tto(dom)) or if the bus idle time-out
(tto(idle)) expires.
Coming from Limp home mode the Standby mode is entered after remote wake-up if the
UJA1023 is configured. In case the UJA1023 is not configured, it enters the Configuration
mode after remote wake-up.
In Standby and Configuration mode the UJA1023 enters the Limp home mode again if the
configuration fails or if the ‘Sleep mode command’ has been received.
7.2.3 I/O pin modes
7.2.3.1
Input
Inputs can always be read via a PxResp frame (see Section 7.2.5). The input threshold is
determined by the TH bits in the second I/O configuration block (see Table 17).
7.2.3.2
Level mode
In Level mode the PxOut register of the UJA1023 can be set or reset. Depending on the
Px configuration the PxOut value is output.
7.2.3.3
PWM mode
The PWM mode provides a PWM signal with 8-bit resolution to the I/O-stage. The base
frequency is typically 700 kHz divided by 256 (8-bit) and becomes approximately 2.7 kHz.
The mode is entered via both mode configuration bits OM0 and OM1. The PWM signal is
common for all assigned outputs.
In the low-power modes (Sleep mode, LH sleep mode and Limp home mode) the PWM
value is reset (PWM = 0x00) and the previous PWM value is lost.
7.2.3.4
Cyclic sense mode
The Cyclic sense mode is used to supply and read back external switches. In this mode
the Px pin is configured as a switched supply to reduce the power consumption. It is
primarily intended to supply wake-up switches.
A Px pin in Cyclic sense mode has to be configured with the High-Side Enable register
(HSE) in HIGH-state and the Low-Side Enable register (LSE) in LOW-state. The PxOut
flip-flop is being cyclically switched (see Figure 7).
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LIN-I/O slave
The Cyclic sense mode can be configured via the Output mode bits OM0 and OM1 in the
configuration data bytes (see Table 16). In case threshold TH2 is selected then threshold
TH3 will be used instead. This feature is used for diagnosis purposes to check the
presence of a switch with an integrated parallel resistor (typical value is 2800 Ω ± 1 %).
The switch can be detected by selecting first TH1 and then TH2.
All Px pins in Cyclic sense mode are sampled simultaneously. The Cyclic sense mode
timing is specified in Section 11. No wake-up will occur when the local wake-up mask is
set and Sleep mode is entered when the Px pin is LOW. A wake-up will be issued when in
Sleep mode and the Px input level changes.
ton
PxOut
Tcy
VPx
external
switch at Px
OPEN
CLOSE
tsample
capture
active
edge
capture
mdb495
Fig 7.
7.2.3.5
Cyclic sense mode
Switch matrix mode
Figure 8 shows an application example of a 4 × 4 switch matrix with the UJA1023. The
drive capability of the I/O-pins Px supports the use of a 4 × 4 switch matrix without extra
components. The I/O pins from P0 to P3 provide a weak but sufficient pull-up for switch
applications and the pins from P4 to P7 are used as strong pull-down in case a switch is
pushed.
The Switch matrix mode can be enabled for the I/O-pins Px via data byte D3 of the second
configuration data block (see Table 18).
The data bits SM0 and SM1 configure P0 to P3 as an input with a weak but sufficient
pull-up for switch applications and P4 to P7 as strong pull-down in order to detect an
activated switch (see Table 18).
In Normal mode when a valid sync break and sync field is received, automatically a matrix
scan starts:
• Immediately if the slave is not addressed
• When addressed, after the LIN message is handled
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LIN-I/O slave
This means that the scan matrix value is determined directly after the previous LIN
message.
In case two or more switches are closed simultaneously, extra diodes have to be added to
prevent the ‘short-circuit’ of neighbor switches.
For the switch matrix inputs a ‘quasi’ capture mode can be configured via the data bit
SMC (D3.3) of the second configuration block. If a matrix switch input value has been
changed the changed value is captured until the master reads the switch matrix value via
the UJA1023 command PxResp. Note that two readings are necessary for proper
initialization.
A switch matrix can be configured as local wake-up. If the data bit SMW (D3.2) of the
second configuration block is set to logic 1, a change of a matrix switch input value
causes a wake-up of the UJA1023. If in addition the Switch matrix capture mode is
enabled via SMC the switch matrix value of PxResp represents the local wake-up source
switch of the switch matrix.
Ron(HS)
1 kΩ
Vth1
P0
SM40
Ron(HS)
1 kΩ
Vth1
P1
SM41
Ron(HS)
1 kΩ
Vth1
P2
SM72
Ron(HS)
1 kΩ
Vth1
P3
SM73
P4
P5
Ron(LS)
50 Ω
Ron(LS)
50 Ω
P6
Ron(LS)
50 Ω
P7
Ron(LS)
50 Ω
mdb496
Fig 8.
7.2.3.6
Switch matrix principle
ADC mode
The principle of the bit stream ADC is shown in Figure 9. Only three external components
are needed per analog input, which should be dimensioned as: Ri = R1 = 100 kΩ;
C1 = 10 nF. All eight inputs can be used as analog input, one at a time. ADC values are
referenced to VVIO. A register/counter is used to count the ratio of HIGH and LOW phases
of the bit stream. This ratio represents the analog voltage VA. The upper counter is used
to define the measurement period, typically 1.5 ms.
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LIN-I/O slave
The inverted bit stream of the ADC comparator generates the quasi-analog output voltage
on pin INH, which can be used to control the analog voltage VA via a low-pass filter.
An analog-to-digital conversion will have following steps:
1. Select an input channel via PxReq, see Section 7.2.5. Not needed in case a fixed
ADC-input is selected (see Table 16 for RxDL = 0 and ADCIN[2:0]).
2. The internal multiplexer switches over to the selected input; note that some time is
needed to stabilize the loop, due to the RC network time constant.
3. In case a valid sync break and sync field is received, an analog-to-digital conversion
starts. The data is available in the next LIN message, implying the ADC value is
sampled during the previous LIN message.
To reduce current consumption, the 0.5VVIO reference voltage is turned off in the
low-power modes.
7.2.4 INH pin mode
The External regulator mode, IM0 = IM1 = 0 (see Table 16), can be used to control an
external voltage regulator. In Configuration mode, Normal mode and Standby mode the
INH outputs a HIGH level, and in the low-power modes (Sleep, LH sleep and Limp home)
the INH pin becomes high-impedance.
Switching between the INH modes ‘external regulator’ and ‘switch open’ the INH pin can
be used as high-side switch.
In ADC mode the INH pin is configured internally as follows: the high-side switch is put in
high-impedance state and a special symmetrical push-pull output is activated. Next, the
ADC mode enables an ADC control loop. The output level of the push-pull stage is
defined via the VVIO voltage.
7.2.5 LIN-I/O message frames
The UJA1023 uses one LIN command to receive data PxReq and one to transmit data
PxResp respectively. The IDs for PxReq and PxResp are configured by means of the
‘assign frame ID’ command as described in Section 7.2.1.3.
Please note that the I/O configuration will be enabled during the first usage of the PxResp
or PxReq.
The PxReq and PxResp data bytes are described in Table 25 to Table 28.
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LIN-I/O slave
oscillator
period
COUNTER
REGISTER/COUNTER
ADC
mode
ADC
VVIO
INH
Ri
100 kΩ
MUX
oscillator
up/down
0.5VVIO
Px
FF
R1
VA
TFILTER
100 kΩ
C1
10 nF
mdb497
Fig 9.
Analog-to-digital converter
Table 25.
Data
byte
7
6
5
4
3
2
1
0
Default
value
(hex)
D0
P7
P6
P5
P4
P3
P2
P1
P0
00
D1
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
00
D2[1]
-
-
-
-
-
ADCIN2 ADCIN1 ADCIN0 00
[1]
The UJA1023 expects to receive data byte D2 only if bit RxDL = 1 (bit 3 of byte D3 in the first I/O
configuration data block, see Table 15 and Table 16).
Table 26.
Product data sheet
PxReq frame bit description
Byte
Bit
Symbol
Description
D0
7 to 0
P[7:0]
Px output value. The Px output value is ignored if Px is
configured in cyclic sense or PWM mode.
D1
7 to 0
PWM[7:0]
PWM value.
D2[1]
7 to 3
-
Not used.
2 to 0
ADCIN[2:0]
ADC analog source channel selection. For example, 000
selects input 0, 001 selects input 1 and 111 selects input 7. The
ADC input source is observed only if the INH output is in ADC
mode.
[1]
UJA1023
PxReq frame bit allocation
The UJA1023 expects to receive data byte D2 only if bit RxDL = 1 (bit 3 of byte D3 in the first I/O
configuration data block, see Table 15 and Table 16).
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LIN-I/O slave
Table 27.
PxResp frame bit allocation
Data byte
7
6
5
4
3
2
1
0
D0
P7
P6
P5
P4
P3
P2
P1
P0
D1
EC7
EC6
EC5
EC4
EC3
EC2
EC1
EC0
SM53
SM52
SM51
SM50
SM43
SM42
SM41
SM40
PxL7
PxL6
PxL5
PxL4
PxL3
PxL2
PxL1
PxL0
SM73
SM72
SM71
SM70
SM63
SM62
SM61
SM60
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
D2
D3
Table 28.
PxResp frame bit allocation
Byte
Bit
Symbol
Description
D0
7 to 0
P[7:0]
Px input value.
Bytes D1 and D2 if switch matrix is not configured (default)[1]
D1
7 to 0
EC[7:0]
Edge capture value.
D2
7 to 0
PxL[7:0]
PxOut latch value.
Bytes D1 and D2 if switch matrix is configured[1]
D1
D2
Byte
D3
[1]
UJA1023
Product data sheet
7 to 0
SMxx
Switch matrix value 0. Refer to Figure 8.
7 to 0
SMxx
Switch matrix value 1.
D3[1]
7 to 0
PWM[7:0]
PWM value.
7 to 0
ADC[7:0]
ADC value. The ADC value is transmitted only if the INH output
is in ADC mode (IM0 = 1, IM1 = 0).
Data bytes D2 and D3 are transmitted only if bit TxDL = 1 (bit 4 of byte D3 in the second I/O configuration
data block, see Table 17 and Table 18).
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7.3 I/O block
7.3.1 I/O pins P0 to P7
The I/O-pin structure of the UJA1023 is shown in Figure 10.
VIO
PxOut
VIO
0
1
2
3 S0
FF
Y
Ron(HS)
S1
Px
0
1
2
3
low-side
enable
Y
S0
Ron(LS)
S1
FF
Vth3
high-side
enable
FF
Vth2
cyclic mode
input
threshold
FF
rise/fall/both
2
edge
capture
FF
TFILTER
Vth1
PxIn
to analog
multiplexer
mdb498
Fig 10. I/O-pin structure
The output is configurable as:
•
•
•
•
Push-pull
High-side switch
Low-side switch
High-impedance
The input can be configured:
•
•
•
•
UJA1023
Product data sheet
To capture on falling, rising or both edges
To provide an internal pull-up
With respect to the required threshold Vth1, Vth2 or Vth3
As analog multiplexer for the ADC
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LIN-I/O slave
Table 29.
I/O pin operation [1][2]
Operation
High-side
enable
Low-side
enable
PxOut
Input
threshold
Edge
capture
Power-on condition
(high-impedance)
0
0
0
0
none
High-impedance
0
0
X
X
X
Low-side open-state
0
1
0
X
X
Low-side close-state
0
1
1
X
X
High-side open-state (Cyclic 1
sense mode: off-state)
0
0
X
X
High-side close-state (Cyclic 1
sense mode: on-state)
0
1
X[3]
X
Push-pull HIGH-state
1
1
1
X
X
Push-pull LOW-state
1
1
0
X
X
Input with pull-up
1
0
1
X
X
Input at threshold Vth1
(typically 3 V)
X
X
X
0
X
Input at threshold Vth2
(typically 1.5 V)
X
X
X
1
X
Capture edge at falling and
rising edge
X
X
X
X
both
Capture edge at falling edge X
X
X
X
fall
Capture edge at rising edge
X
X
X
rise
X
[1]
X = don’t care.
[2]
The Ron values of the high-side and the low-side switches can be found in Section 10. The Ron(HS) value is
chosen to provide enough pull-up current for switches; thus no external pull-up resistor is needed. The
Ron(LS) of the low-side driver is much smaller than the Ron(HS) of the high-side driver, which enables the low
side driver to drive LEDs.
[3]
Refer to Table 17 where threshold TH3 is defined in Cyclic sense mode in case threshold TH2 is selected.
This feature is used for diagnosis purposes to check the presence of a switch with integrated parallel
resistor (a useful resistor value is 3000 Ω ± 1 %).
7.3.2 INH pin
The inhibit pin INH can be configured in three operation modes: ADC mode, Switch open
mode and External regulator mode (see Section 7.2.4 and Figure 11). After power-on the
INH is in External regulator mode (high-side switch is on).
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LIN-I/O slave
BAT
output
FF
&
Ron(INH1)
VIO
ADC mode
FF
&
Ron(INH2)
&
Ron(INH2)
INH
mdb499
Fig 11. INH structure
7.4 Configuration pins C1 to C3
The structure of the configuration pins C1 to C3 (Cx) is shown in Figure 12. Each pin has
a pull-up to the battery. The pull-up is switched on during node address configuration only.
In all other cases the Cx have high-impedance behavior.
In order to have a safety margin against ground shift the input threshold of the
configuration pins is about 0.5 × VBAT.
In addition the configuration pin C3 has a low-side driver to provide the output signal
during daisy chain ID configuration.
VBAT
configuration on/off
Cx
0.5VBAT
Cx input
Cx output
001aad492
Fig 12. Configuration pin structure
7.5 LIN transceiver
The integrated LIN transceiver of the UJA1023 is compliant with LIN 2.0 / SAE J2602 and
provides:
• Integrated 30 kΩ termination resistor
• Internal LIN-termination switch (RTLIN)
• Disabling of termination switch during a short-circuit from LIN to GND
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LIN-I/O slave
Figure 13 shows the states of the complete LIN transceiver including RTLIN for LIN
termination.
power-on
or undervoltage
Off-line
TX: off
RX: off
LPRX: on
RTLIN: 75 μA
tto(idle)
tto(dom)
or
sleep or LH sleep
remote wake-up
or
local wake-up
tto(rec)
tto(dom)
Active
Fail silent
TX: on
RX: on
LPRX: on
RTLIN: 30 kΩ
TX: off
RX: off
LPRX: on
RTLIN: off
local wake-up
mce652
TX = Transmitter.
RX = Receiver.
LPRX = Low-power receiver.
RTLIN = LIN termination.
Fig 13. LIN transceiver states
The first mode after power-on is the Off-line mode. The transmitter and receiver are both
switched off, but wake-up events will be recognized. Any LIN wake-up event will wake-up
the UJA1023.
Within Sleep mode any wake-up event is automatically forwarded to the LIN (protocol)
controller, the Normal mode will be entered and the LIN-transceiver automatically enters
the Active mode. It should be noted that the first message (wake-up message) will be lost
when no wake-up signal has been received before.
The differences between Active, Off-line and Fail silent mode are:
• In Off-line and Fail silent mode the transmitter is off, whereas in Active mode the
transmitter is enabled
• During active state with no short-circuit between LIN and GND the internal termination
switch RTLIN provides an internal 30 kΩ pull-up resistor to VBAT. In case the LIN wire
is shorted to GND for longer than tto(dom), the RTLIN switch switches off in order to
make sure that no current is discharging the battery unintentionally and Fail silent
mode will be entered
• After failure recovery (in fail silent) when the LIN bus is recessive again the Off-line
mode is entered and activates a weak termination of 75 μA
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• Entering Active mode out of Off-line mode results always in switching on the internal
30 kΩ pull-up resistor to battery
7.6 On-chip oscillator
The on-chip oscillator is the time reference for all timers in the LIN controller, auto bit rate
detector, ADC and LIN transceiver.
A too-low frequency of the on-chip oscillator or a not-running on-chip oscillator results
immediately in Limp home operating mode.
8. Limiting values
Table 30. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol Parameter
Conditions
Min
Max
Unit
V
VBAT
supply voltage on pin BAT
−0.3
+40
VVIO
supply voltage on pin VIO
−0.3
VBAT + 0.3 V
VLIN
voltage on pin LIN
DC value
−27
+40
VINH
voltage on pin INH
DC value
−0.3
VBAT + 0.3 V
VCx
voltage on pins C1 to C3
DC value
−27
+40
V
VPx
voltage on pins P0 to P7
DC value
−0.3
VVIO + 0.3
V
IPx
current on pins P0 to P7
DC value; VPx > VVIO + 0.3 V; VPx < −0.3 V
−15
+15
mA
Vtrt(LIN)
transient voltages on pin LIN
ISO 7637
−150
+100
V
Tvj
virtual junction temperature
−40
+150
°C
Tstg
storage temperature
−55
+150
°C
VESD
electrostatic discharge voltage
pins BAT, LIN, C1, C2 and C3 human body model; C = 100 pF; R = 1.5 kΩ
−8
+8
kV
corner pins
charged device model
−750
+750
V
other pins
human body model; C = 100 pF; R = 1.5 kΩ
−2
+2
kV
charged device model
−500
+500
V
[1]
[1]
V
Junction temperature in accordance with IEC60747-1. An alternative definition of Tvj = Tamb + P × Rth(j-a), where Rth(j-a) is a fixed value to
be used for calculating Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
9. Thermal characteristics
UJA1023
Product data sheet
Table 31.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
in free air
106
K/W
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NXP Semiconductors
LIN-I/O slave
10. Static characteristics
Table 32. Static characteristics
VBAT = 5.5 V to 27 V[1]; VVIO = 3 V to 27 V; Tvj = −40 °C to +150 °C; RL(LIN-BAT) = 500 Ω; all voltages are referenced to GND;
positive current flows into the IC; unless otherwise specified.[2]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
5.5
-
27
V
VBAT = 5.5 V to 8.1 V
[3]
-
75
100
μA
VBAT = 8.1 V to 27 V
[3]
-
45
65
μA
VBAT = 12 V
[4]
-
0.7
1.4
mA
VBAT = 27 V
[4]
-
1.0
2.0
mA
VBAT = 12 V
[4]
-
1.1
2.2
mA
VBAT = 27 V
[4]
-
1.7
3.4
mA
VBAT = 12 V
[4]
-
2.2
4.4
mA
VBAT = 27 V
[4]
-
3.6
7.5
mA
-
1040
1280
μA
4.45
-
5.0
V
3
-
VBAT + 0.3
V
Supply: pin BAT
VBAT
supply voltage on pin BAT
all operating modes
IBAT
supply current on pin BAT
LH sleep, Sleep and Limp
home mode
Normal mode;
LIN receiving recessive
Normal mode;
LIN receiving dominant
Normal mode;
LIN sending dominant
Additional current if all
high- and low-side
switches are activated
VBAT(pf)
[5]
VBAT power fail detection
voltage
I/O reference (Px operating range): pin VIO
VVIO
supply voltage on pin VIO
IVIO
supply current on pin VIO
LH sleep, Sleep and Limp
home mode; no load at Px
high-side switches
disabled
[6]
-
1.6
5.0
μA
high-side switches
enabled and active
[6]
-
230
280
μA
[6]
-
520
1000
μA
Normal mode; ADC
enabled; no load at Px and
INH; high-side switches
enabled
Configuration: pins C1, C2 and C3
VIH
HIGH-level input voltage
0.6 × VBAT
-
VBAT + 0.3
V
VIL
LOW-level input voltage
−0.3
-
0.4 × VBAT
V
⎪IL⎪
leakage current
configuration pins disabled
-
-
5
μA
Rpu
internal pull-up resistor
configuration pins enabled
5
11
25
kΩ
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Product data sheet
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Table 32. Static characteristics …continued
VBAT = 5.5 V to 27 V[1]; VVIO = 3 V to 27 V; Tvj = −40 °C to +150 °C; RL(LIN-BAT) = 500 Ω; all voltages are referenced to GND;
positive current flows into the IC; unless otherwise specified.[2]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL(C3)
LOW-level output voltage on
pin C3
external Rpu = 5 kΩ to
pin BAT; C3 enabled
-
-
0.25 × VBAT
V
external Rpu = 5 kΩ to
pin BAT; C3 enabled;
VBAT = 6.5 V to 27 V
-
-
0.2 × VBAT
V
C3 = VBAT; C3 enabled
-
-
50
mA
3.7
-
VVIO + 0.3
V
Isc(C3)
short-circuit current on
pin C3
I/O: pins P0 to P7
VIH(th1)
HIGH-level input voltage Vth1 VVIO ≥ 3.7 V
VIL(th1)
LOW-level input voltage Vth1
−0.3
-
+2.1
V
VIH(th2)
HIGH-level input voltage Vth2
VVIO ≥ 3.7 V
2.0
-
VVIO + 0.3
V
VIL(th2)
LOW-level input voltage Vth2
−0.3
-
+0.8
V
VIH(th3)
HIGH-level input voltage Vth3 VVIO ≥ 10 V
VVIO − 0.8
-
VVIO + 0.3
V
VIL(th3)
LOW-level input voltage Vth3
VVIO ≥ 10 V
−0.3
-
VVIO − 2.5
V
⎪IL⎪
leakage current
VI = VVIO or GND
-
-
10
μA
Ron(HS)
high-side on-state resistance VPx = VVIO − 1 V;
per switch
550
1200
3000
Ω
Isc(HS)
high-side short-circuit current VPx = 0 V
Ron(LS)
low-side on-state resistance
Isc(LS)
low-side short-circuit current
[7]
VPx = 1 V; per switch
VPx = VVIO
[7]
−3.1
−2.0
−0.8
mA
25
50
83
Ω
10
23
40
mA
Special function: pin INH
VBAT-INH
voltage drop
INH mode; IINH = −1 mA
-
1.2
1.8
V
⎪IL⎪
leakage current
VINH = 0 V
-
-
5
μA
Bus line: pin LIN
VO(dom)
LIN dominant output voltage
7.0 V < VBAT < 18 V
0
-
0.2 × VBAT
V
IL(H)
HIGH-level leakage current
7.0 V < VBAT < 18 V;
VLIN = VBAT
−10
-
+10
μA
IL(L)
LOW-level leakage current
Fail silent mode;
VLIN = 0 V; t > tto(dom)
−10
0
+10
μA
Ipu
LIN pull-up current
Off-line mode; VLIN = 0 V;
t < tto(dom)
−150
−60
−10
μA
Rpu(slave)
slave termination pull-up
Active mode
20
30
47
kΩ
-
0
-
μA
VLIN = 12 V; VBAT = 12 V
27
40
60
mA
VLIN = 18 V; VBAT = 18 V
40
60
86
mA
IL
leakage current
VBAT = 0 V
IO(sc)
short-circuit output current
LIN dominant; t < tto(dom)
[8]
Vth(dom)
receiver dominant state
voltage
Active mode
-
-
0.4 × VBAT
V
Vth(rec)
receiver recessive state
voltage
Active mode
0.6 × VBAT
-
-
V
Vcen(RX)
receiver center voltage
Active mode
0.475 × VBAT 0.5 × VBAT 0.525 × VBAT V
Vhys(RX)
receiver hysteresis voltage
Active mode
0.05 × VBAT
UJA1023
Product data sheet
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Rev. 5 — 17 August 2010
-
0.175 × VBAT V
© NXP B.V. 2010. All rights reserved.
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NXP Semiconductors
LIN-I/O slave
[1]
Valid for the UJA1023T/2R04/C; for the UJA1023T/2R04, VBAT = 6.5 V to 27 V.
[2]
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient
temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pre-testing
and final testing use correlated test conditions to cover the specified temperature and power supply voltage ranges.
[3]
All outputs turned off, LIN recessive, Vth1 selected.
[4]
All outputs turned off.
[5]
Configuration is lost when VBAT is below 5 V.
[6]
Vth1 on, Vth2 off, Vth3 off.
[7]
Outputs are not temperature protected.
[8]
Not tested in production.
11. Dynamic characteristics
Table 33. Dynamic characteristics
VBAT = 5.5 V to 27 V; VVIO = 3 V to 27 V; Tvj = −40 °C to +150 °C; RL(LIN-BAT) = 500 Ω; all voltages are referenced to GND;
unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[2]
-
200
-
μs
[2][3]
-
1.5
-
ms
Vth(rec)(max) = 0.744 × VBAT
Vth(dom)(max) = 0.581 × VBAT
tbit = 50 μs; VBAT = 7 V to 18 V
[4][5]
0.396
-
-
Vth(rec)(max) = 0.76 × VBAT
Vth(dom)(max) = 0.593 × VBAT
tbit = 50 μs; VBAT = 5.5 V to 7.0 V
[4][5]
0.396
-
-
Vth(rec)(min) = 0.422 × VBAT
Vth(dom)(min) = 0.284 × VBAT
tbit = 50 μs; VBAT = 7.6 V to 18 V
[4][6]
-
-
0.581
Vth(rec)(min) = 0.41 × VBAT
Vth(dom)(min) = 0.275 × VBAT
tbit = 50 μs; VBAT = 6.1 V to 7.6 V
[4][6]
-
-
0.581
Vth(rec)(max) = 0.778 × VBAT
Vth(dom)(max) = 0.616 × VBAT
tbit = 96 μs; VBAT = 7 V to 18 V
[4][5]
0.417
-
-
Vth(rec)(max) = 0.797 × VBAT
Vth(dom)(max) = 0.630 × VBAT
tbit = 96 μs; VBAT = 5.5 V to 7 V
[4][5]
0.417
-
-
Vth(rec)(min) = 0.389 × VBAT
Vth(dom)(min) = 0.251 × VBAT
tbit = 96 μs; VBAT = 7.6 V to 18 V
[4][6]
-
-
0.590
Vth(rec)(min) = 0.378 × VBAT
Vth(dom)(min) = 0.242 × VBAT
tbit = 96 μs; VBAT = 6.1 V to 7.6 V
[4][6]
-
-
0.590
[7]
-
-
6
I/O processing
tprocess
tconv(ADC)
PxReq to output
conversion time ADC
LIN transceiver; see Figure
δ1
δ2
δ3
δ4
tPHL(RX),
tPLH(RX)
after valid LIN message
14[4]
duty cycle 1
duty cycle 2
duty cycle 3
duty cycle 4
propagation delay of
receiver
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Product data sheet
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μs
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LIN-I/O slave
Table 33. Dynamic characteristics …continued
VBAT = 5.5 V to 27 V; VVIO = 3 V to 27 V; Tvj = −40 °C to +150 °C; RL(LIN-BAT) = 500 Ω; all voltages are referenced to GND;
unless otherwise specified.[1]
Symbol
tP(RX)(sym)
Parameter
Conditions
symmetry of receiver
propagation delay rising
edge with respect to falling
edge
Min
Typ
Max
Unit
[7]
−2
-
+2
μs
LIN protocol controller
tto(idle)
bus idle time-out
[2]
4.1
-
18.0
s
tto(dom)
bus dominant time-out
[2]
32
-
270
ms
bus recessive time-out
[2]
15
-
65
μs
twake(bus)
network wake-up signal
time
after local wake-up, sent by slave
[2]
0.25
-
5
ms
twake(local)
bus wake-up dominant
time
Sleep mode, sent by master
[2]
30
100
150
μs
[4]
-
10 × tbit
-
μs
-
-
2
%
tto(rec)
Automatic bit rate detection
tdet(syncbrk)
sync break detection
threshold
ftol(sync)
total tolerance slave
synchronized
complete message
Cyclic function; see Figure 7
Tcy
ton(PxOut)
tsample(PxIn)
cycle period
[2]
-
16
-
ms
PxOut pin turned on
[2]
-
350
-
μs
PxIn sample time
[2]
-
262
-
μs
VVIO = 6.5 V to 12 V;
VBAT = 6.5 V to 12 V
[8]
-
-
4
LSB
VVIO = 3 V to 27 V;
VBAT = 6.5 V to 27 V
[8]
-
-
6
LSB
ADC function
EADC
[1]
total ADC error
R = 100 kΩ; C = 10 nF
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient
temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pre-testing
and final testing use correlated test conditions to cover the specified temperature and power supply voltage ranges.
[2]
Guaranteed by design.
[3]
Analog-to-digital conversion starts when valid sync break and sync field is received.
[4]
tbit = selected bit time 50 μs or 96 μs (20 kbit/s or 10.4 kbit/s), depends on LSC bit; bus load conditions are (C parallel to R): Cbus = 1 nF
and Rbus = 1 kΩ, Cbus = 6.8 nF and Rbus = 660 Ω or Cbus = 10 nF and Rbus = 500 Ω.
[5]
t bus ( rec ) ( min )
δ 1, δ 3 = -----------------------------2 × t bit
[6]
t bus ( rec ) ( max )
δ 2, δ 4 = ------------------------------2 × t bit
[7]
RXD is an internal signal.
[8]
Not tested.
UJA1023
Product data sheet
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NXP Semiconductors
LIN-I/O slave
tbit
tbit
tbit
VTXDL
tbus(dom)(max)
tbus(rec)(min)
VBAT
Vth(rec)(max)
Vth(dom)(max)
LIN BUS
signal
Vth(rec)(min)
Vth(dom)(min)
tbus(dom)(min)
receiving
node 1
thresholds of
receiving node 2
tbus(rec)(max)
VRXDL1
tp(rx1)f
receiving
node 2
thresholds of
receiving node 1
tp(rx1)r
VRXDL2
tp(rx2)r
tp(rx2)f
001aae375
Fig 14. Timing diagram LIN transceiver
UJA1023
Product data sheet
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NXP Semiconductors
LIN-I/O slave
12. Application information
LIN MASTER NODE ECU
V1
VDD
BAT42
BAT14
SPI
INTERFACE
RTLIN
RSTN
RSTN
INTN
INTN
RXDL
RXD
TXDL
FAIL-SAFE SBC
TXD
CBAT
RMASTER
SPI
INTERFACE
LIN
CLIN
GND
MICROCONTROLLER
UJA106x
VBAT
LIN bus
LIN SLAVE NODE ECU
INH
SWITCH BACKGROUND ILLUMINATION
P7
VIO
P6
BAT
CBAT
4 × 3 SWITCH MATRIX
P5
P4
LIN
CLIN
GND
P3
C1
P2
C2
P1
C3
P0
LIN I/O SLAVE
UJA1023
001aad687
Fig 15. Application Diagram
13. Test information
Immunity against automotive transients (malfunction and damage) in accordance with LIN
EMC Test Specification / Version 1.0; August 1, 2004.
13.1 Quality information
This product has been qualified to the appropriate Automotive Electronics Council (AEC)
standard Q100 or Q101 and is suitable for use in automotive applications.
UJA1023
Product data sheet
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UJA1023
NXP Semiconductors
LIN-I/O slave
14. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 16. Package outline SOT109-1 (SO16)
UJA1023
Product data sheet
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15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 17) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 34 and 35
Table 34.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 35.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 17.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 17. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Revision history
Table 36.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
UJA1023 v.5
20100817
Product data sheet
-
UJA1023 v.4
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
VBAT (min) value changed to 5.5 V (Table 1, Table 32 and Table 33).
Table 32 “Static characteristics”: updated:
– condition/value added for VOL(C3)
– table note 1 added
•
Table 33 “Dynamic characteristics”: updated:
– δ1, δ2, δ3 and δ4: conditions changed (LSC = 0 deleted) and conditions/values added
•
Table 2 “Ordering information” updated to indicate that two versions are now available:
– UJA1023T/2R04/C with VBAT = 5.5 V to 27 V
– UJA1023T/2R04 with VBAT = 6.5 V to 27 V
UJA1023 v.4
20060705
Product data sheet
-
UJA1023 v.3
UJA1023 v.3
20060209
Preliminary data sheet
-
UJA1023 v.2
UJA1023 v.2
(9397 750 12022)
20050203
Objective specification
-
-
UJA1023
Product data sheet
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NXP Semiconductors
LIN-I/O slave
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
UJA1023
Product data sheet
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
47 of 49
UJA1023
NXP Semiconductors
LIN-I/O slave
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
UJA1023
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 17 August 2010
© NXP B.V. 2010. All rights reserved.
48 of 49
UJA1023
NXP Semiconductors
LIN-I/O slave
19. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.1.4
7.2.1.5
7.2.1.6
7.2.2
7.2.2.1
7.2.2.2
7.2.2.3
7.2.2.4
7.2.2.5
7.2.3
7.2.3.1
7.2.3.2
7.2.3.3
7.2.3.4
7.2.3.5
7.2.3.6
7.2.4
7.2.5
7.3
7.3.1
7.3.2
7.4
7.5
7.6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Short description of the UJA1023 . . . . . . . . . . . 5
LIN controller . . . . . . . . . . . . . . . . . . . . . . . . . . 5
LIN transceiver (including termination) . . . . . . . 5
Automatic bit rate detection . . . . . . . . . . . . . . . 5
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I/O block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Cyclic sense . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
LIN controller . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Message sequence . . . . . . . . . . . . . . . . . . . . . 6
LIN slave node address assignment . . . . . . . . 8
Assign frame ID . . . . . . . . . . . . . . . . . . . . . . . 14
Read by identifier . . . . . . . . . . . . . . . . . . . . . . 15
I/O configuration . . . . . . . . . . . . . . . . . . . . . . . 16
Configuration examples . . . . . . . . . . . . . . . . . 22
Operating modes . . . . . . . . . . . . . . . . . . . . . . 24
Configuration mode . . . . . . . . . . . . . . . . . . . . 25
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 25
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Limp home sleep mode . . . . . . . . . . . . . . . . . 25
Limp home mode and Standby mode . . . . . . . 26
I/O pin modes . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Level mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Cyclic sense mode . . . . . . . . . . . . . . . . . . . . . 26
Switch matrix mode . . . . . . . . . . . . . . . . . . . . 27
ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
INH pin mode . . . . . . . . . . . . . . . . . . . . . . . . . 29
LIN-I/O message frames . . . . . . . . . . . . . . . . 29
I/O block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I/O pins P0 to P7 . . . . . . . . . . . . . . . . . . . . . . 32
INH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Configuration pins C1 to C3 . . . . . . . . . . . . . . 34
LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 34
On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 36
8
9
10
11
12
13
13.1
14
15
15.1
15.2
15.3
15.4
16
17
17.1
17.2
17.3
17.4
18
19
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Quality information . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
36
37
39
42
42
42
43
44
44
44
44
45
46
47
47
47
47
48
48
49
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 17 August 2010
Document identifier: UJA1023
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