UCS2112 USB Dual-Port Power Switch and Current Monitor Features Description • Dual-Port Power Switches: - 2.9V to 5.5V source voltage range - 3.0A continuous current per VBUS port with 40 m On resistance per switch - Independent port power switch enable pins - DUAL fault ALERT# active drain output pins - Constant Current or Trip mode current limiting behaviors - Undervoltage and overvoltage lockout - Back-drive, back-voltage protection - Auto-recovery fault handling with low test current - BOOST# logic output to increase DC-DC converter output under large load conditions - A_DET# open-drain outputs for device attach detection per port • SMBus 2.0/I2C™ Mode Features: - Eight programmable current limits assignable to each power switch - Other SMBus addresses available upon request - Block read and block write • Self-contained current monitoring (no external sense resistor required) • Fully programmable per-port charge rationing and behaviors • Per-port BC1.2 VBUS Discharge Function • Wide Operating Temperature Range: - -40°C to +105°C • UL recognized and EN/IEC 60950-1 (CB) certified. The UCS2112 is a dual USB port power switch configuration which can provide 3.0A continuous current (3.4A maximum) per VBUS port with precision overcurrent limiting (OCL), port power switch enables, auto-recovery fault handling, undervoltage and overvoltage lockout, back-drive protection and back-voltage protection, and dynamic thermal management. The UCS2112 is well suited for both stand-alone and applications having SMBus/I2C communications. For applications with SMBus, the UCS2112 provides per-port current monitoring and eight programmable current limits per switch, ranging from 0.53A to 3.0A continuous current (3.4A maximum). Per-port charge rationing is also provided ranging from 3.8 mAh to 246.3 Ah. In Stand-alone mode, the UCS2112 provides eight current limits for both switches, ranging from 0.53A + 0.53A to 3A + 3A total continuous current (see Table 1-1). Both power switches include an independent VBUS discharge function and constant current mode current limiting for BC1.2 applications. The UCS2112 is available in a 4x4 mm 20-pin QFN package. Package Type ALERT#1 GND SMDATA SMCLK ALERT#2 UCS2112 4x4 QFN* 20 19 18 17 16 15 PWR_EN2 PWR_EN1 1 A_DET#1 2 14 A_DET#2 EP 21 BOOST# 3 13 COMM_ILIM 7 8 9 10 VS 6 VS 11 VBUS2 VDD VBUS1 5 VS 12 VBUS2 VS VBUS1 4 * Includes Exposed Thermal Pad (EP); see Table 3-1. 2015 Microchip Technology Inc. DS20005424B-page 1 UCS2112 Block Diagram VBUS VS Power Switch 1 UVLO, OVLO VS VBUS Power Switch 2 VBUS discharge PWR_EN1 ALERT#1 BOOST# VDD A_DET#1 Interface Logic Temp Charger Control, Measurement, OCL PWR_EN2 ALERT#2 A_DET#2 COMM_ILIM SMCLK GND DS20005424B-page 2 SMDATA 2015 Microchip Technology Inc. UCS2112 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Voltage on VDD, VS, and VBUS pins ...................................................................................................................-0.3 to 6V Pull-Up Voltage (VPULLUP) ..................................................................................................................... -0.3 to VDD + 0.3 Port Power Switch Current ..................................................................................................................... Internally limited Voltage on any Other Pin to Ground ...................................................................................................-0.3 to VDD + 0.3V Current on any Other Pin ..................................................................................................................................... ±10 mA Package Power Dissipation ........................................................................................................................ See Table 1-1 Operating Ambient Temperature Range .................................................................................................-40°C to +105°C Storage Temperature Range ..................................................................................................................-55°C to +150°C † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: POWER DISSIPATION SUMMARY De-Rating Factor TA < +25°C TA = +70°C TA = +85°C Above +25°C Power Rating Power Rating Power Rating Package JC JA High K (Note) 20-pin QFN 4x4 mm 6 °C/W 41 °C/W 24.4 mW/°C 2193 mW 1095 mW 729 mW Low K (Note) 20-pin QFN 4x4 mm 6 °C/W 60 °C/W 16.67 mW/°C 1498 mW 748 mW 498 mW Board Note: A High K board uses a thermal via design with the thermal landing soldered to the PCB ground plane with 0.3 mm (12 mil) diameter vias in a 3x3 matrix (9 total) at 0.5 mm (20 mil) pitch. The board is multi-layer with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom. A Low K board is a two layer board without thermal via design with 2-ounce copper traces on the top and bottom. TABLE 1-2: ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C. Characteristic Symbol Min. Typ. Max. Unit Conditions VDD 4.5 5 5.5 V Supply Current in Active (IDD_ACT + IS1_ACT + IS2_ACT) IACTIVE — 850 — µA Average current IBUS = 0 mA Supply Current in Sleep (IDD_SLEEP + IS1_SLEEP + IS2_SLEEP) ISLEEP — 6 20 µA Average current VPULLUP VDD IDETECT — 200 — µA Average current No portable device attached (Note 1) VDD Low Threshold VDD_TH — 4 — V VDD voltage increasing VDD Low Hysteresis VDD_TH_HYST — 500 — mV VDD voltage decreasing Power and Interrupts - DC Supply Voltage Supply Current in Detect (IDD_DET + IS1_DET + IS2_DET) Power-on Reset Note 1: 2: 3: 4: This parameter is characterized, not 100% tested. This parameter is ensured by design and not 100% tested. The current measurement full scale range maximum value is 3.4A. However, the UCS2112 cannot report values above ILIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A). This parameter is characterized, not 100% production tested. 2015 Microchip Technology Inc. DS20005424B-page 3 UCS2112 TABLE 1-2: ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C. Characteristic Symbol Min. Typ. Max. Unit Conditions I/O Pins - SMCLK, SMDATA, PWR_EN, ALERT#, A_DET#, BOOST# - DC Parameters Output Low Voltage VOL — — 0.4 V ISINK_IO = 8 mA SMDATA, ALERT#, A_DET#, BOOST# Input High Voltage VIH 2.0 — — V PWR_EN, SMDATA, SMCLK Input Low Voltage VIL — — 0.8 V PWR_EN, SMDATA, SMCLK Leakage Current ILEAK — — ±5 µA Powered or unpowered VPULLUP VDD TA < 85°C (Note 1) ALERT# Pin Blanking Time tBLANK — 25 — ms Blanking time, coming out of reset ALERT# Pin Interrupt Masking Time tMASK — 5 — ms BOOST# Pin Minimum Assertion Time tBOOST_MAT — 1 — s BOOST# Pin Assertion Current IBOOST — 1.9 — A Input Capacitance CIN — 5 — pF Clock Frequency fSMB 10 — 400 kHz tSP — — 50 ns tBUF 1.3 — — µs tSU:STA 0.6 — — µs Start Hold Time tHD:STA 0.6 — — µs Stop Setup Time tSU:STO 0.6 — — µs Data Hold Time tHD:DAT 0 — — µs When transmitting to the master Data Hold Time tHD:DAT 0.3 — — µs When receiving from the master Data Setup Time tSU:DAT 0.6 — — µs Clock Low Period tLOW 1.3 — — µs Clock High Period tHIGH 0.6 — — µs Clock / Data Fall Time tFALL — — 300 ns Min = 20+0.1CLOAD ns (Note 1) Clock / Data Rise Time tRISE — — 300 ns Min = 20+0.1CLOAD ns (Note 1) Per bus line (Note 1) Interrupt Pins - AC Parameters SMBus/I2C™ Timing Spike Suppression Bus Free Time Stop to Start Start Setup Time Capacitive Load Timeout Idle Reset Note 1: 2: 3: 4: CLOAD — — 400 pF tTIMEOUT 25 — 35 ms Disabled by default (Note 1) tIDLE_RESET 350 — — µs Disabled by default (Note 1) This parameter is characterized, not 100% tested. This parameter is ensured by design and not 100% tested. The current measurement full scale range maximum value is 3.4A. However, the UCS2112 cannot report values above ILIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A). This parameter is characterized, not 100% production tested. DS20005424B-page 4 2015 Microchip Technology Inc. UCS2112 TABLE 1-2: ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C. Characteristic Symbol Min. Typ. Max. Unit Conditions Port Power Switch Port Power Switch - DC Parameter VS_OV — 6 — V Note 2 VS Low Threshold Overvoltage Lockout VS_UVLO — 2.5 — V Note 2 VS Low Hysteresis VS_UVLO_HYST — 100 — mV Note 2 On Resistance RON_PSW — 40 — m 4.75V < VS < 5.25V VS Leakage Current ILEAK_VS — — 5 µA Sleep state into VS pin on one channel (Note 1) Back-voltage Protection Threshold VBV_TH — 150 — mV VBUS > VS VS > VS_UVLO IBD_1 — 0 3 µA VDD < VDD_TH, Leakage current from VBUS pins to the VDD and the VS pins (Note 1) IBD_2 — 0 2 µA VDD > VDD_TH, Leakage current from VBUS pins to the VDD (in Detect State) or the VS pins (in Active State) (Note 1) ILIM1 — 530 — mA ILIM Resistor = 0 or 47 k (530 mA setting) ILIM2 — 960 — mA ILIM Resistor = 10 k or 56 k (960 mA setting) (Note 4) ILIM3 — 1070 — mA ILIM Resistor = 12 k or 68 k (1070 mA setting) (Note 4) ILIM4 — 1280 — mA ILIM Resistor = 15 k or 82 k (1280 mA setting) (Note 4) ILIM5 — 1600 — mA ILIM Resistor = 18 k or 100 k (1600 mA setting) (Note 4) ILIM6 — 2130 — mA ILIM Resistor = 22 k or 120 k (2130 mA setting) (Note 4) ILIM7 — 2670 — mA ILIM Resistor = 27 k or 150 k (2670 mA setting) (Note 4) ILIM8 3000 3200 3400 mA ILIM Resistor = 33 k or VDD (3200 mA setting) tPIN_WAKE — 3 — ms SMBus Wake Time tSMB_WAKE — 4 — ms Idle Sleep Time tIDLE_SLEEP — 200 — ms TREG — 110 — °C Die Temperature at which current limit will be reduced TREG_HYST — 10 — °C Hysteresis for tREG functionality. Temperature must drop by this value before ILIM value restored to normal operation Back-drive Current Selectable Current Limits Pin Wake Time Thermal Regulation Limit Thermal Regulation Hysteresis Note 1: 2: 3: 4: This parameter is characterized, not 100% tested. This parameter is ensured by design and not 100% tested. The current measurement full scale range maximum value is 3.4A. However, the UCS2112 cannot report values above ILIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A). This parameter is characterized, not 100% production tested. 2015 Microchip Technology Inc. DS20005424B-page 5 UCS2112 TABLE 1-2: ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C. Characteristic Symbol Min. Typ. Max. Unit Thermal Shutdown Threshold TTSD — 135 — °C Die Temperature at which port power switch will turn off Thermal Shutdown Hysteresis TTSD_HYST — 35 — °C After shutdown due to TTSD being reached, die temperature drop required before port power switch can be turned on again Auto-recovery Test Current ITEST — 190 — mA Portable device attached, VBUS= 0 V, Die temp < TTSD Auto-recovery Test Voltage VTEST — 750 — mV Portable device attached, VBUS = 0 V before application, Die temp < TTSD Programmable, 250 - 1000 mV, default listed RDISCHARGE — 100 — Discharge Impedance Conditions Port Power Switch - AC Parameters Turn-On Delay tON_PSW — 200 — ms Depends on the VBUS Discharge setting. Programmable 100-400 ms, default listed Turn-Off Time tOFF_PSW_INA — 0.75 — ms PWR_EN inactive toggle to switch off time CBUS = 120 µF Turn-Off Time tOFF_PSW_ERR — 1 — ms Over-current Error, VBUS Min Error, or Discharge Error to switch off CBUS = 120 µF Turn-Off Time tOFF_PSW_ERR1 — 100 — ns TSD or Back-drive Error to switch off CBUS = 120 µF tR_BUS — 1.1 — ms Measured from 10% to 90% of VBUS, CLOAD = 220 µF ILIM = 1.0A Soft Turn-On Rate IBUS/t — 100 — mA/µs Temperature Update Time tDC_TEMP — 200 — ms Short-Circuit Response Time tSHORT_LIM — 1.5 — µs Time from detection of short to current limit applied. No CBUS applied Short-Circuit Detection Time tSHORT — 6 — ms Time from detection of short to port power switch disconnect and ALERT# pin assertion. tUL — 7 — ms From PWR_EN edge transition from inactive to active to begin error recovery VBUS Output Rise Time Latched Mode Cycle Time Note 1: 2: 3: 4: This parameter is characterized, not 100% tested. This parameter is ensured by design and not 100% tested. The current measurement full scale range maximum value is 3.4A. However, the UCS2112 cannot report values above ILIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A). This parameter is characterized, not 100% production tested. DS20005424B-page 6 2015 Microchip Technology Inc. UCS2112 TABLE 1-2: ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C. Characteristic Auto-recovery Mode Cycle Time Auto-recovery Delay Discharge Time Symbol Min. Typ. Max. Unit Conditions tCYCLE — 25 — ms Time delay before error condition check Programmable 15-50 ms, default listed tTST — 20 — ms Portable device attached, VBUS must be > VTEST after this time Programmable 10-25 ms, default listed tDISCHARGE — 200 — ms Amount of time discharge resistor applied Programmable 100-400 ms, default listed Port Power Switch Operation With Trip Mode Current Limiting Region 2 Current Keep-out IBUS_R2MIN_1 — — 0.1 A Note 2 Minimum VBUS Allowed at Output VBUS_MIN_1 2.0 — — V Note 2 Port Power Switch Operation With Constant Current Limiting (Variable Slope) Region 2 Current Keep-out IBUS_R2MIN — — 2.13 A Note 2 Minimum VBUS Allowed at Output VBUS_MIN 2.0 — — V Note 2 Current Measurement - DC Current Measurement Range Reported Current Measurement Resolution IBUS_M 0 — 3400 mA Range (Note 2 and Note 3) IBUS_M — 13.3 — mA 1 LSB — ±2 — % — ±2 — LSB Current Measurement Accuracy 200 mA < IBUS < ILIM IBUS < 200 mA Current Measurement - AC Sampling Rate Conversion Time both channels — — 1.1 — ms Note 2 tCONV — 2.2 — ms All registers updated in digital (Note 2) Charge Rationing - DC Accumulated Current Measurement Accuracy — — ±4.5 — % Charge Rationing - AC Current Measurement Update Time Note 1: 2: 3: 4: tPCYCLE — 1 — s This parameter is characterized, not 100% tested. This parameter is ensured by design and not 100% tested. The current measurement full scale range maximum value is 3.4A. However, the UCS2112 cannot report values above ILIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A). This parameter is characterized, not 100% production tested. 2015 Microchip Technology Inc. DS20005424B-page 7 UCS2112 TABLE 1-2: ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C. Characteristic Symbol Min. Typ. Max. Unit Conditions Attach / Removal Detection VBUS Bypass - DC On Resistance RON_BYP — 45 — Ω Leakage Current ILEAK_BYP — — 3 µA Switch off TA < +85°C (Note 1) Current Limit IDET_CHG/ IBUS_BYP — 700 — µA VDD = 5V and VBUS> 4.75V tDET_CHARGE — 800 — ms CBUS = 500 µF maximum VBUS Charge Time for Attachment Attach/Removal Detection - DC Attach Detection Threshold Primary Removal Detection Threshold IDET_QUAL — 800 — µA Programmable 200-1000 µA, default listed IREM_QUAL_ACT — 700 — µA Programmable 100-900 µA, default listed. Active power state IREM_QUAL_DET — 800 — µA Programmable, default listed. Detect power state Time from Attach to A_DET# assert. Attach/Removal Detection - AC Attach Detection Time tDET_QUAL — 100 — ms Removal Detection Time tREM_QUAL — 1000 — ms Note 1: 2: 3: 4: This parameter is characterized, not 100% tested. This parameter is ensured by design and not 100% tested. The current measurement full scale range maximum value is 3.4A. However, the UCS2112 cannot report values above ILIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A). This parameter is characterized, not 100% production tested. T LOW T HD:STA T HIGH T SU:STO T FALL SMCLK T RISE T HD:STA T SU:DAT T HD:DAT T SU:STA SMDATA TBUF S P FIGURE 1-1: TABLE 1-3: S S - Start Condition P - Stop Condition P SMSBus Timing. TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Operating Temperature Range TA -40 — +105 °C Storage Temperature Range TA -55 — +150 °C Conditions Temperature Ranges Thermal Package Resistances - see Table 1-1 DS20005424B-page 8 2015 Microchip Technology Inc. UCS2112 1.1 ESD and Transient Performance TABLE 1-4: ESD RATINGS ESD Specification Rating or Value Human Body Model (JEDEC JESD22-A114) - All pins 8 kV Charged Device Model (JEDEC JESD22-C101) - All pins 500V 1.1.1 HUMAN BODY MODEL (HBM) PERFORMANCE HBM testing verifies the ability to withstand ESD strikes like those that occur during handling and manufacturing and is done without power applied to the IC. To pass the test, the device must have no change in operation or performance due to the event. 1.1.2 CHARGED DEVICE MODEL (CDM) PERFORMANCE CDM testing verifies the ability to withstand ESD strikes like those that occur during handling and assembly with pick and place style machinery and is done without power applied to the IC. To pass the test, the device must have no change in operation or performance due to the event. 2015 Microchip Technology Inc. DS20005424B-page 9 UCS2112 NOTES: DS20005424B-page 10 2015 Microchip Technology Inc. UCS2112 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C. 6 VS = VDD = 5V ILIM = 3A min (3.4A max), short applied at 2 ms 5 6 6 5 5 4 4 VBUS 3 2 2 1 1 VBUS 0 5 Time (ms) -1 FIGURE 2-4: Short Applied After VDD ALERT# 4 6 45 5 40 4 3 3 2 2 1 1 IBUS 0 0 -1 -1 0 100 200 300 400 6 300 400 500 VBUS Discharge Behavior. 35 30 25 20 15 10 5 -40 -15 10 35 60 85 110 Temperature (°C) Power-Up Into a Short. VS = VDD = 5V ILIM = 2.13A (typical), short applied at 10 µs 5 200 0 500 Time (ms) FIGURE 2-2: 100 Time (ms) 6 5 0 10 On Resistance (mΩ) FIGURE 2-1: Power-Up. 2 0 -1 0 3 1 0 -1 Voltage (V) Voltage (V) 3 Current (A) Voltage (V) IBUS Current (A) ALERT# 4 FIGURE 2-5: Power Switch On Resistance vs. Temperature. 28 24 4 20 3 16 2 12 1 8 Current (A) Voltage (V) VBUS 4 0 IBUS -1 0 -4 -2 0 20 40 Time (µs) FIGURE 2-3: Response. Internal Power Switch Short 2015 Microchip Technology Inc. DS20005424B-page 11 UCS2112 6.10 6.08 6.06 6.04 6.02 6.00 5.98 5.96 5.94 5.92 5.90 0% Current Limit Accuracy %) VS Threshold Voltage (V) Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C. VDD = 5V -40 -15 10 35 60 85 VS = VDD = 5V ILIM = 3.0A min. (3.2A typ., 3.4A max.) -2% Note: The percentage is relative to the maximum specification (3.4A) -4% -6% -8% -10% -12% 110 -40 -15 Temperature (°C) 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 VS Overvoltage Threshold FIGURE 2-9: vs. Temperature. 60 85 110 Trip Current Limit Operation 4 3 Threshold Hysteresis 2 1 0 -1 -2 -3 -4 -40 -15 10 35 60 85 -5 110 0.0 0.5 1.0 Temperature (°C) FIGURE 2-7: vs. Temperature. VS Undervoltage Threshold FIGURE 2-10: Accuracy. Supply Current (ȝA) 5.0 VBUS1 4.0 VBUS2 3.0 2.0 VS = VDD = 5V; ATT_DET enabled; PWR_EN disabled for one chanel and enabled for the other channel. 1.0 0.0 0 500 1000 1500 2000 2500 Current (µA) FIGURE 2-8: DS20005424B-page 12 1.5 2.0 2.5 3.0 Current (A) 6.0 Voltage (V) 35 5 VDD = 5V Accuracy (%) VS Threshold Voltage (V) FIGURE 2-6: vs. Temperature. 10 Temperature (°C) Detect State VBUS vs. IBUS. 1000 900 800 700 600 500 400 300 200 100 0 IBUS Measurement IDD + IS1 + IS2 IDD IS1 + IS2 -40 -15 10 35 60 85 110 Temperature (°C) FIGURE 2-11: Active State Current vs. Temperature (both channels on, PWR_EN1 = PWR_EN2 = 1). 2015 Microchip Technology Inc. UCS2112 Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C. 700 60% IDD + IS1 + IS2 50% 500 IDD Samples (%) 400 300 IS1 + IS2 200 100 40% 30% 20% 10% FIGURE 2-12: Active State Current vs. Temperature (only one channel on, PWR_EN1 = 1, PWR_EN2 = 0). FIGURE 2-15: Distribution. 300 ILIM1 Trip Current 60% 250 50% IDD + IS1 + IS2 40% 200 Samples (%) IDD 150 100 50 IS1 + IS2 Detect State Current vs. FIGURE 2-16: Distribution(1). 14 60% 12 50% Samples (%) 10 IDD + IS1 + IS2 8 6 1.01 1 0.99 0.98 VBUS Current (A) Temperature (°C) FIGURE 2-13: Temperature. 0.97 110 0.96 85 0.95 60 0.94 35 0.93 10 10% 0.91 -15 20% 0% 0 -40 30% 0.92 IDD 4 ILIM2 Trip Current 40% 30% 20% 10% IS1 + IS2 Sleep State Current vs. 1.12 VBUS Current (A) Temperature (°C) FIGURE 2-14: Temperature. 1.11 110 1.1 85 1.09 60 1.08 35 1.07 10 1.06 -15 1.04 -40 1.03 0% 0 1.02 2 1.05 Supply Current (ȝA) 0.555 VBUS Current (A) Temperature (°C) Supply Current (ȝA) 0.55 110 0.54 85 0.545 60 0.535 35 0.53 10 0.525 -15 0.52 -40 0.515 0 0.51 0% 0.505 Supply Current (ȝA) 600 FIGURE 2-17: Distribution(1). ILIM3 Trip Current Note 1: The histogram aspect is caused by a mixture of two normal distributions, corresponding to the two VBUS channels. 2015 Microchip Technology Inc. DS20005424B-page 13 UCS2112 60% 50% 50% 40% 40% 40% 40% 2.745 2.72 3.32 3.28 3.24 3.2 3.16 3 1.675 1.66 1.645 1.63 0% 1.615 0% 1.6 10% 1.585 10% 3.12 20% 3.08 20% ILIM7 Trip Current 30% 3.04 30% 1.57 2.795 50% 1.555 3.4 50% Samples (%) 60% 1.54 2.77 FIGURE 2-21: Distribution. ILIM4 Trip Current VBUS Current (A) VBUS Current (A) FIGURE 2-19: Distribution(1). 2.695 VBUS Current (A) 60% 1.525 Samples (%) FIGURE 2-18: Distribution(1). 3.36 VBUS Current (A) 2.67 2.545 1.33 1.32 1.31 1.3 1.29 1.28 1.27 0% 1.26 0% 1.25 10% 1.24 10% 2.645 20% 2.62 20% 30% 2.595 30% 2.57 Samples (%) 60% 1.23 Samples (%) Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C. FIGURE 2-22: Distribution. ILIM5 Trip Current ILIM8 Trip Current 60% Samples (%) 50% 40% 30% 20% 10% 2.23 2.21 2.19 2.17 2.15 2.13 2.11 2.09 2.07 2.05 2.03 0% VBUS Current (A) FIGURE 2-20: Distribution. ILIM6 Trip Current Note 1: The histogram aspect is caused by a mixture of two normal distributions, corresponding to the two VBUS channels. DS20005424B-page 14 2015 Microchip Technology Inc. PIN DESCRIPTION Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE UCS2112 4x4 QFN Symbol 1 PWR_EN1 2 Function Pin Type Connection Type if Pin Not Used Port power switch enable #1 DI Connect to ground or VDD (depending on the polarity decoded via COMM_ILIM pin) A_DET#1 Open-drain output for Attach Detection on VBUS1 (requires pullup resistor) OD Connect to ground 3 BOOST# Logic output for DC-DC converter voltage increase (requires pull-up resistor) OD Connect to ground 4, 5 VBUS1 Port power switch #1 output (requires both pins tied together) High Power, AIO Leave open 6, 7 VS Voltage input to port power switch VBUS1 (requires both pins tied together) High Power, AIO Connect to ground 2015 Microchip Technology Inc. 8 VDD 9, 10 VS Voltage input to port power switch VBUS2 (requires both pins tied together) High Power, AIO Connect to ground 11, 12 VBUS2 Port power switch #2 output (requires both pins tied together) High Power, AIO Leave open 13 COMM_ILIM Enables SMBus or Stand-Alone mode at power-up. Hardware strap for maximum current limit AIO N/A 14 A_DET#2 Open-drain output for Attach Detection on VBUS2 (requires Pull Up) OD Connect to ground 15 PWR_EN2 Port power switch enable #2 DI Connect to ground or VDD (depending on the polarity decoded via COMM_ILIM pin) 16 ALERT#2 Output fault ALERT for VBUS2 (requires pull-up resistor) OD Connect to ground 17 SMCLK SMCLK - SMBus clock input (requires pull-up resistor) DI Connect to VPULLUP(or to ground in Stand-alone mode) 18 SMDATA SMDATA - SMBus data input/output (requires pull-up resistor) DIOD Connect to VPULLUP (or to ground in Stand-alone mode) 19 GND Ground Power N/A 20 ALERT#1 21 EP Common supply voltage Power N/A Output fault ALERT for VBUS1 (requires pull-up resistor) OD Connect to ground Exposed thermal pad. Must be connected to electrical ground. EP N/A UCS2112 DS20005424B-page 15 3.0 UCS2112 TABLE 3-2: PIN TYPES Pin Type Power Description This pin is used to supply power or ground to the device. Hi-Power This pin is a high-current pin. AIO Analog Input/Output - this pin is used as an I/O for analog signals. DI Digital Input - this pin is used as a digital input. DIOD Open-Drain Digital Input/Output - this pin is bidirectional. It is open-drain and requires a pull-up resistor. OD Open-Drain Digital Output - used as a digital output. It is open-drain and requires a pull-up resistor. EP Exposed thermal pad DS20005424B-page 16 2015 Microchip Technology Inc. UCS2112 4.0 TERMS AND ABBREVIATIONS Note: The PWR_EN1 and PWR_EN2 pins each have configuration bits (“<pin name>_S” in General Configuration 1 register (Address 11h) and General Configuration 2 register (Address 12h)) that may be used to perform the same function as the external pin state. These bits are accessed via the SMBus/I2C™ and are OR’d with the respective pin. This OR’d combination of pin state and register bit is referenced as the <pin name> control. TABLE 4-1: TERMS AND ABBREVIATIONS Term/Abbreviation Attach Detection Description An Attach Detection event occurs when the current drawn by a portable device is greater than IDET_QUAL for longer than tDET_QUAL. Attachment The physical insertion of a portable device into a USB port that UCS2112 is controlling. CC Constant Current CDM Charged Device Model. JEDEC model for characterizing susceptibility of a device to damage from ESD. Current Limiting Mode Determines the action that is performed when the IBUS current reaches the ILIM threshold. Trip opens the port power switch. Constant Current (variable slope) allows VBUS to be dropped by the portable device. Disconnection USB-IF term which refers to the loss of active USB communications between a USB host and a USB device. Dynamic Thermal Management The UCS2112 automatically adjusts port power switch limits and modes to lower internal power dissipation when the thermal regulation temperature value is approached. HBM Human Body Model IBUS_R2MIN Current limiter mode boundary ILIM The IBUS current threshold used in current limiting. In Trip mode, when ILIM is reached, the port power switch is opened. In Constant Current mode, when the current exceeds ILIM, operation continues at a reduced voltage and increased current; if VBUS voltage drops below VBUS_MIN, the port power switch is opened. OCL Overcurrent limit POR Power-on Reset Portable Device USB device attached to the USB port. Removal Detection A Removal Detection event occurs when the current load on the VBUS pin drops to less than IREM_QUAL for longer than tREM_QUAL. Removal The physical removal of a portable device from a USB port that the UCS2112 is controlling. Stand-Alone Mode Indicates that the communications protocol is not active and all communications between the UCS2112 and a controller are done via the external pins only (PWR_EN1 and PWR_EN2 as inputs, and ALERT1#, ALERT2#, A_DET1# and A_DET2# as outputs). 2015 Microchip Technology Inc. DS20005424B-page 17 UCS2112 NOTES: DS20005424B-page 18 2015 Microchip Technology Inc. UCS2112 5.0 GENERAL DESCRIPTION The UCS2112 is a dual-port power switch. Two USB power ports are supported with current limits up to 3.0A continuous current (3.4A maximum) each. Selectable and programmable current limiting configurations are also available to the application. A typical block diagram is shown in Figure 5-1. D+ DVBUS VB SMDATT SMCLK USB Port 1 Connector S SMDAT SSMCLK D+ DPD_ALERT1 2 PORT HUB VBUS1 ALERT1 A_DET1 PWR_EN1 UCS2112 VBUS2 ALERT2 A_DET2 PWR_EN2 D+ DPD_ALERT2 FIGURE 5-1: VBUS V D+ D- USB Port 2 Connector Typical USB Application. 2015 Microchip Technology Inc. DS20005424B-page 19 UCS2112 5.1 UCS2112 Power States Power states are indicators of the device’s current consumption in the System and the functionality of the Digital Logic. Table 5-1 details the UCS2112 power states. TABLE 5-1: POWER STATES DESCRIPTION State Description Off This power state is entered when the voltage at the VDD pin voltage is < VDD_TH. In this state, the device is considered “off”. The UCS2112 will not retain its digital states and register contents nor respond to SMBus/I2C™ communications. The port power switch and bypass switch will be off. See Section 5.1.1 “Off State Operation”. Sleep This is the lowest power state available. While in this state, the UCS2112 will retain digital functionality and wake to respond to SMBus/I2C communications. See Section 5.1.2 “Sleep State Operation”. Detect The Detect power state should not be confused with the actual Attach / Removal Detection feature. Detect Power State is both channels awaiting attachment. This is a lower-current power state. In this state, the device is actively looking for a portable device to be attached. While in this state, the UCS2112 will retain the configuration and charge rationing data, but it will not monitor the bus current. SMBus/I2C communications will be fully functional. See Section 5.1.3 “Detect State Operation”. Error This power state is entered when a fault condition exists. Error power state is one or both channels in Fault Handling. This state is updated as Priority One. The Interrupt Status Registers for each channel will update the fault detected per channel. Only the channel that has detected a Fault will be affected since the other channel can remain active if no fault is detected. See Section 5.1.5 “Error State Operation”. Active Active power State is one, or both channels active and sourcing current to the VBUS Port. This state is updated as Priority Two. None of the channels have detected Fault. This power state provides full functionality. While in this state, operations include activation of the port power switch, current limiting, and charge rationing. See Section 5.1.4 “Active State Operation”. Table 5-2 shows the settings for the various power states, except Off and Error. If VDD < VDD_TH, the UCS2112 is in the Off state. TABLE 5-2: POWER STATES CONTROL SETTINGS Power PWR_EN1 PWR_EN2 ATT_DET State Portable Device Attached Behavior Sleep disabled disabled N/A N/A • All switches disabled. • VBUS will be near ground potential. • The UCS2112 wakes to respond to SMBus communications. Detect enabled disabled enabled No • Automatic transition to Active state when conditions met for VBUS1(see Section 5.1.3.1 “Automatic Transition from Detect to Active”). • VBUS2 pins have very low current delivery capability. disabled enabled enabled No • Automatic transition to Active state when conditions met for VBUS2 (see Section 5.1.3.1 “Automatic Transition from Detect to Active”). • VBUS1 pins have very low current delivery capability. enabled enabled enabled No • Automatic transition to Active state when conditions met for both VBUS1 and VBUS2 (see Section 5.1.3.1 “Automatic Transition from Detect to Active”). DS20005424B-page 20 2015 Microchip Technology Inc. UCS2112 TABLE 5-2: POWER STATES CONTROL SETTINGS (CONTINUED) Power PWR_EN1 PWR_EN2 ATT_DET State Active 5.1.1 Portable Device Attached enabled disabled N/A Yes • Port power switch is on during A_DET1=1 for VBUS1. VBUS2 pins have very low current delivery capability. disabled enabled N/A Yes • Port power switch is on during A_DET2=1 for VBUS2. • VBUS1 pins have very low current delivery capability. enabled enabled N/A Yes • Port power switch is on during A_DET1=A_DET2=1 for VBUS1 and VBUS2. enabled disabled disabled N/A • Forced ACTIVE Power State: Port power switch is on at all times for VBUS1. • VBUS2 pins have very low current delivery capability. disabled enabled disabled N/A • Forced ACTIVE Power State: Port power switch is on at all times for VBUS2. • VBUS1 pins have very low current delivery capability. enabled enabled disabled N/A • Forced ACTIVE Power State: Port power switch is on at all times for VBUS1 and VBUS2. OFF STATE OPERATION The device will be in the Off state if VDD is less than VDD_TH. When the UCS2112 is in the Off state, it will do nothing and all circuitry will be disabled. Digital register values are not stored and the device will not respond to SMBus commands. 5.1.2 Behavior SLEEP STATE OPERATION The PWR_EN1 and PWR_EN2 pins may be used to cause the UCS2112 to enter/exit Sleep. These pins are AND’ed for Sleep mode. The first data byte read from the UCS2112 when it is in the Sleep state will wake it; however, the data to be read will return all 0’s and should be considered invalid. This is a “dummy” read byte meant to wake the UCS2112. Subsequent read or write bytes will be accepted normally. After the dummy read, the UCS2112 will be in a higher-power state (see Figure 5-2). After communication has not occurred for tIDLE_SLEEP, the UCS2112 will return to Sleep. When the UCS2112 is in the Sleep state, the device will be in its lowest-power state. The bypass switch and the port power switch will be disabled. The Attach and Removal Detection feature will be disabled. VBUS1 and VBUS2 will be near ground potential. The ALERT#1 and ALERT#2 pins will not be asserted. If asserted prior to entering the Sleep state, the ALERT# pin will be released. SMBus activity is limited to single byte read or write. SMBus Read Dummy read returns invalid data and places device in temporary Read returns valid data Active state S 0101_1110 A 0001_0000 A S 0101_1111 A invalid dataN P Power State FIGURE 5-2: S 0101_1110 A 0001_0000 A S 0101_1111 A valid data N P tSMB_WAKE temporary Active state (not all functionality available) Sleep tIDLE_SLEEP Sleep Wake from Sleep using SMBus Read. 2015 Microchip Technology Inc. DS20005424B-page 21 UCS2112 5.1.3 DETECT STATE OPERATION When the UCS2112 is in the Detect state, the port power switch will be disabled. The VBUS output will be connected to the VDD voltage by a secondary bypass switch. There are two methods for transitioning from the Detect state to the Active state: automatic and host-controlled. 5.1.3.1 Automatic Transition from Detect to Active For the Detect state, enable PWR_EN1 and/or PWR_EN2, and supply VDD ≥ VDD_TH. When a portable device is attached and an Attach Detection event occurs, the UCS2112 will automatically transition to the Active state. 5.1.3.2 State Change from Detect to Active When conditions cause the UCS2112 to transition from the Detect state to the Active state, the following occurs: • The Attach Detection feature will be disabled; the Removal Detection feature remains enabled. • The bypass switch will be turned off. • The discharge switch will be turned on briefly for tDISCHARGE. • The port power switch will be turned on. 5.1.4 ACTIVE STATE OPERATION Every time the UCS2112 enters the Active state, the port power switches are closed. The UCS2112 cannot be in the Active state (and therefore, the port power switch cannot be turned on) if any of the following conditions exist: • An overcurrent condition has been detected. • An undervoltage condition on either VBUS pin has been detected (see Section 5.3.4 “Undervoltage Lockout on VS”). • A back-drive condition has been detected (see Section 5.3.2 “Back-voltage Detection”). • A discharge error has been detected. • An overvoltage condition on the VS pin. The UCS2112 will enter the Error state from the Detect state when a back-drive condition has been detected on either port, or when the maximum allowable internal die temperature has been exceeded. The UCS2112 will enter the Error state from the Sleep state when a back-drive condition has been detected. When the UCS2112 enters the Error state, the port power switch and the VBUS bypass switch will be disabled while the ALERT# pin is asserted (by default). They will remain off while in this power state. The UCS2112 will leave this state as determined by the fault handling selection. With the Auto-recovery fault handler, after the tCYCLE time period, the UCS2112 will check that all of the error conditions have been removed. If all of the error conditions have been removed, the UCS2112 will return to the Active state or Detect state, as applicable. If the device is in the Error state and a Removal Detection event occurs, it will check the error conditions and then return to the power state defined. 5.2 Communication The UCS2112 will enter the Error state from the Active state when any of the following events are detected: The UCS2112 can operate in SMBus mode (see Section 8.0 “System Management Bus Protocol”) or Stand-alone mode. The resistor connected to the COMM_ILIM pin determines the operating mode and the hardware-set ILIM setting, as shown in Table 5-3. Unless connected to GND or VDD, the resistors in Table 5-3 are external pull-down resistors. • The maximum allowable internal die temperature (TTSD) has been exceeded. The SMBus address is specified in Section 8.2 “SMBus Address and RD/WR Bit”. • VS < VS_UVLO • PWR_EN1 and PWR_EN2 are disabled. 5.1.5 ERROR STATE OPERATION TABLE 5-3: COMMUNICATION DECODE COMM_ILIM Pulldown Resistor (±1%) PWR_EN1 and PWR_EN2 Polarity ILIM (A) Total ILIM (A) (Note 1) Communication Mode GND Active-High 0.53 0.53+0.53 SMBUS 10 k Active-High 0.96 0.96+0.96 SMBUS 12 k Active-High 1.07 1.07+1.07 SMBUS 15 k Active-High 1.28 1.28+1.28 SMBUS 18 k Active-High 1.6 1.6+1.6 SMBUS 22 k Active-High 2.13 2.13+2.13 SMBUS DS20005424B-page 22 2015 Microchip Technology Inc. UCS2112 TABLE 5-3: COMMUNICATION DECODE (CONTINUED) COMM_ILIM Pulldown Resistor (±1%) PWR_EN1 and PWR_EN2 Polarity ILIM (A) Total ILIM (A) (Note 1) Communication Mode 27 k Active-High 2.67 2.67+2.67 SMBUS 33 k Active-High 3.2 3.2+3.2 SMBUS 47 k Active-Low 0.53 0.53+0.53 Stand-Alone 56 k Active-Low 0.96 0.96+0.96 Stand-Alone 68 k Active-Low 1.07 1.07+1.07 Stand-Alone 82 k Active-Low 1.28 1.28+1.28 Stand-Alone 100 k Active-Low 1.6 1.6+1.6 Stand-Alone 120 k Active-Low 2.13 2.13+2.13 Stand-Alone 150 k Active-Low 2.67 2.67+2.67 Stand-Alone VDD Active-Low 3.2 3.2+3.2 Stand-Alone Note 1: 5.3 5.3.1 The total maximum current depends on power dissipation characteristics of the design (see Table 1-1) Supply Voltages VDD SUPPLY VOLTAGE The UCS2112 requires 4.5V to 5.5V present on the VDD pin for core device functionality. Core device functionality consists of maintaining register states, wake-up upon SMBus/I2C query and Attach Detection. 5.3.2 BACK-VOLTAGE DETECTION The back drive detector is functional in all power states (Sleep, Detect, and Active). When in Sleep, the UCS2112 will enter the Error state from Sleep if a Back Drive condition was detected. Whenever the following condition is true for either port, the port power switch will be disabled, the VBUS bypass switch will be disabled and a back-voltage event will be flagged. This will cause the UCS2112 to enter the Error power state (see Section 5.1.5 “Error State Operation”). Note: The VBUS voltage exceeds the VS and/or the VDD pin voltage by VBV_TH and the port power switch is closed. The port power switch will be opened immediately. If the condition lasts for longer than tMASK, then the UCS2112 will enter the Error state. Otherwise, the port power switch will be turned on as soon as the condition is removed. 2015 Microchip Technology Inc. 5.3.3 BACK-DRIVE CURRENT PROTECTION If a portable device is attached that is self-powered, it may drive the VBUS port to its power supply voltage level; however, the UCS2112 is designed such that leakage current from the VBUS pins to the VDD and/or the VS pin shall not exceed IBD_1 (if the VDD and/or VS voltage is zero) or IBD_2 (if the VDD and/or VS voltage exceeds VDD_TH). 5.3.4 UNDERVOLTAGE LOCKOUT ON VS The UCS2112 requires a minimum voltage (VS_UVLO) be present on the VS pin for Active power state. 5.3.5 OVERVOLTAGE DETECTION AND LOCKOUT ON VS/VDD The UCS2112 port power switch will be disabled if the voltage on the VS pin exceeds a voltage (VS_OV) for longer than the specified time (tMASK). This will cause the device to enter the Error state. 5.3.6 PWR_EN1 AND PWR_EN2 INPUT The PWR_EN control affects the power state and enables the port power switch to be turned on if conditions are met (see Table 5-2). The port power switch cannot be closed if PWR_EN is disabled. However, if PWR_EN is enabled, the port power switch is not necessarily closed (see Section 5.1.4 “Active State Operation”). In SMBus mode, the PWR_EN1 and PWR_EN2 pins states will be ignored by the UCS2112 if the PIN_IGN configuration bit is set; otherwise, the PWR_EN1S and PWR_EN2S configuration bits are checked along with the pins. DS20005424B-page 23 UCS2112 BOOST# OUTPUT PIN If R 1 R 3 SMDATA/LOW_ILM SMCLK/LOAD_SHARE ALERT#2 18 17 16 R 1 + R 2 + R 3 V FB 5V OUT = -------------------------------------------------------R3 R2 + R 3 R 1 V FB V = -------------------------------------------------------OUT R3 R4 5V OUT R 1 R 1 V FB V OUT = -------------------- – ------ -----------------------R4 R3 V FB GND The UCS2112 has two independent ALERT# out pins. ALERT#1 is tied to the status of the VBUS1 pin. ALERT#2 is tied to the status of the VBUS2 pin. The ALERT# pin is an active-low open-drain interrupt to the host controller. The ALERT# pin is asserted when an error occurs. The ALERT# pin can also be asserted when the LOW_CUR (portable device is pulling less current and may be finished charging) or TREG (thermal regulation temperature exceeded) bits are set and linked. As well, when charge rationing is enabled, the ALERT# pin is asserted by default when the current rationing threshold is reached (as determined by RATION_BEH<1:0>). The ALERT# pin is released when all error conditions that may assert the ALERT# pin (such as an error condition, charge rationing, and TREG and LOW_CUR if linked) have been removed or reset as necessary. 19 The UCS2112 provides a BOOST# output pin to compensate for voltage drops during high loads. The BOOST# pin is an active-low, open-drain output that would be connected to a resistor in the DC-DC Converter’s feedback error voltage loop (see Figure 5-3). The BOOST# pin is asserted when VBUS Current > IBOOST. IBOOST typical value is 1.9A. The BOOST# is OR’ed for both VBUS1 and VBUS2 ports. When the BOOST# pin is asserted, it will remain in this state for at least tBOOST_MAT (minimum assertion time). ALERT#1 AND ALERT#2 OUTPUT PINS ALERT#1 5.4.1 5.4.2 Discrete Output Pins 20 5.4 5V OUT R 1 VOUT --------------------------------R 4 5.0VOUT PWR_EN1 1 15 PWR_EN2 A_DET#1 2 14 A_DET#2 13 COMM_ILIM R1 R4 DC-DC Converter Block R2 VFB FeedBack BOOST# UCS2112 20-QFN 4x4 mm 3 VBUS1 4 12 VBUS2 VBUS1 5 11 VBUS2 5.5 5.5.1 9 8 7 10 VS VS GND FLAG Boost# Pin Usage. Discrete Input Pins COMM_ILIM INPUT The COMM_ILIM input determines the communications mode, as shown in Table 7-1. This is also the hardware strap for MAX Current Limit. 5.5.2 VDD VS FIGURE 5-3: VS 6 R3 GND 5.5.3 SMDATA When used in Stand-Alone, this pin should be tied to ground. When the UCS2112 is configured for SMBus communications, the SMDATA is the data input/output. SMCLK When operated in Stand-Alone mode, this pin should be tied to ground. When the UCS2112 is configured for SMBus communications, the SMCLK is the clock input. DS20005424B-page 24 2015 Microchip Technology Inc. UCS2112 6.1.3 6.0 DETECT STATE 6.1 Device Attach / Removal Detection The UCS2112 can detect the attachment and removal of a portable device on the VBUS1 or VBUS2 ports. Note: 6.1.1 By default, device attach / removal detection feature is disabled. It can be enabled by clearing ATT_DISABLE bit 6 from Register 9-9 VBUS BYPASS SWITCH The UCS2112 contains circuitry to provide VBUS current as shown in Figure 6-1. In the Detect state, VDD is the voltage source; in the Active state, VS is the voltage source. The bypass switch and the port power switch are never both on at the same time. REMOVAL DETECTION The Removal Detection feature will be active in the Active and Detect power states. This feature monitors the current load on the VBUS1 and VBUS2 pins. If this load drops to less than IREM_QUAL_DET for longer than tREM_QUAL, a Removal Detection event is flagged. When a Removal Detection event is flagged, the following will be done: 1. 2. 3. 4. Disable the port power switch and the bypass switch. Set the REM status register bit. Enable an internal discharging device that will discharge the VBUS line within tDISCHARGE. Once the VBUS pin has been discharged, the device will return to the Detect state regardless of the PWR_EN control state. Bypass Switch VDD VS VBUS Port Power Switch VS FIGURE 6-1: VBUS Bypass Switch. While the VBUS bypass switch is active, the current available to a portable device will be limited to IBUS_BYP and the Attach Detection feature will be active. 6.1.2 ATTACH DETECTION The primary Attach Detection feature is only active in the Detect power state. When active, this feature constantly monitors the current load on the VBUS1 or VBUS2 pins. If the current drawn by a portable device is greater than IDET_QUAL for longer than tDET_QUAL, an Attach Detection event occurs. This will cause the A_DET# status bits to be set. Until the port power switch is enabled, the current available to a portable device will be limited to that used to detect device attachment (IDET_QUAL). Once an Attach Detection event occurs, the UCS2112 will wait for the PWR_EN control to be enabled (if not already). When PWR_EN is enabled and VS is above the threshold, the UCS2112 will activate the VBUS port power switch and operate in Active state. 2015 Microchip Technology Inc. DS20005424B-page 25 UCS2112 NOTES: DS20005424B-page 26 2015 Microchip Technology Inc. UCS2112 7.0 USB PORT POWER SWITCH To assure compliance to various charging specifications, the UCS2112 contains a USB port power switch that supports two current-limiting modes: Trip and Constant current (variable slope). The current limit (ILIM) is pin selectable (and may be updated via the register set). The switch also includes soft start circuitry and a separate short circuit current limit. TABLE 7-1: COMM_ILIM PWR_EN1 Pulldown and Resistor PWR_EN2 (±1%) Polarity The port power switch is on in the Active state (except when VBUS is discharging). Note: 7.1 7.1.1 If a load that draws between 2 mA and 7 mA is connected to the port power switch, a voltage ripple between 40-90 mVPP is observed at the VBUS output. This behavior is normal and it does not affect the charging process when a portable device is connected. Current Limiting CURRENT LIMIT SETTING The UCS2112 hardware set current limit, ILIM, can be one of eight values. This resistor value is read once upon UCS2112 power-up. The current limit can be changed via the SMBus/I2C after power-up; however, the programmed current limit cannot exceed the hardware set current limit. Unless connected to VDD, the resistors in Table 7-1 are pull-down resistors. At power-up, the communication mode (Stand-alone or SMBus/I2C) and hardware current limit (ILIM) are determined via the pull-down resistor (or pull-up resistor if connected to VDD) on the COMM_ILIM pin, as shown in Table 7-1. 7.1.2 SHORT CIRCUIT OUTPUT CURRENT LIMITING Short circuit current limiting occurs when the output current is above the selectable current limit (ILIMx). This event will be detected and the current will immediately be limited (within tSHORT_LIM time). If the condition remains, the port power switch will flag an Error condition and enter the Error state. 7.1.3 SOFT START When the PWR_EN control changes states to enable the port power switch, or an Attach Detection event occurs in the Detect power state and the PWR_EN control is already enabled, the UCS2112 invokes a soft start routine for the duration of the VBUS rise time (tR_BUS). This soft start routine will limit current flow from VS into VBUS while it is active. This circuitry will prevent current spikes due to a step in the portable device current draw. In the case when a portable device is attached while the PWR_EN pin is already enabled, if the bus current exceeds ILIM, the UCS2112 current limiter will respond within a specified time (tSHORT_LIM) and will operate normally at this point. The CBUS capacitor will deliver the extra current, if any, as required by the load change. 2015 Microchip Technology Inc. ILIM DECODE ILIM (A) Total ILIM (A) (Note 1) GND Active-High 0.53 0.53+0.53 10 kΩ Active-High 0.96 0.96+096 12 kΩ Active-High 1.07 1.07+1.07 15 kΩ Active-High 1.28 1.28+1.28 18 kΩ Active-High 1.6 1.6+1.6 22 kΩ Active-High 2.13 2.13+2.13 27 kΩ Active-High 2.67 2.67+2.67 33 kΩ Active-High 3.2 3.2+3.2 47 kΩ Active-Low 0.53 0.53+0.53 56 kΩ Active-Low 0.96 0.96+0.96 68 kΩ Active-Low 1.07 1.07+1.07 82 kΩ Active-Low 1.28 1.28+1.28 100 kΩ Active-Low 1.6 1.6+1.6 120 kΩ Active-Low 2.13 2.13+2.13 150 kΩ Active-Low 2.67 2.67+2.67 VDD Active-Low 3.2 3.2+3.2 Note 1: 7.1.4 The total maximum current depends on power dissipation characteristics of the design (see Table 1-1). CURRENT LIMITING MODES The UCS2112 current limiting has two modes: trip and constant current (variable slope). Either mode functions at all times when the port power switch is closed. When operating in the Detect power state, the current capacity at VBUS is limited to IBUS_BYP as described in Section 6.1.1 “VBUS Bypass Switch”. 7.1.4.1 Trip Mode When using trip current limiting, the UCS2112 USB port power switch functions as a low resistance switch and rapidly turns off if the current limit is exceeded. While operating using trip current limiting, the VBUS output voltage will be held relatively constant (equal to the VS voltage minus the RON x IBUS current) for all current values up to the ILIM. If the current drawn by a portable device exceeds ILIM, the following occurs: 1. 2. 3. The port power switch will be turned off (Trip action). The UCS2112 will enter the Error state and assert the ALERT# pin. The fault handling circuitry will then determine subsequent actions. DS20005424B-page 27 UCS2112 Figure 7-1 shows operation of current limits in trip mode with the shaded area representing the USB 2.0 specified VBUS range. Dashed lines indicate the port power switch output will go to zero (e.g., trip) when ILIM is exceeded. Note that operation at all possible values of ILIM are shown in Figure 7-1 for illustrative purposes only; in actual operation only one ILIM can be active at any time. ILIM (Amps) Operating 0.53 Current 5.25 0.96 1.07 1.28 1.6 2.13 2.67 3.2 5 Figure 7-3 shows operation of current limits while using CC mode. Unlike trip mode, once IBUS current exceeds ILIM, operation continues at a reduced voltage and increased current. Note that the shaded area representing the USB 2.0 specified VBUS range is now restricted to an upper current limit of IBUS_R2MIN. Note that the UCS2112 will heat up along each load line as voltage decreases. If the internal temperature exceeds the TREG or TTSD thresholds, the port power switch will open. Also note that when the VBUS voltage is brought low enough (below VBUS_MIN), the port power switch will open. 4.75 = ILIM’s ILIM (Amps) 0.53 Trip action (ILIM = 0.53 A) 4 0.96 1.28 1.6 2.13 3.2 IBUS_R2MIN 5 Trip action (ILIM = 3.2 A) VBUS (Volts) 2.67 5.25 4.75 = ILIM’s 3 4 Constant resistance IBUS operation line 4 (ILIM = 1.6 A) Constant resistance IBUS operation line 1 (ILIM = 0.53 A) VBUS (Volts) 2 Power Switch Voltage and Current Output go to Zero when ILIM is Exceeded 1 3 2 0 0.96 1.07 1.28 0.53 0 1.6 2.13 2.67 1 3.2 CC Mode - Power switch current increases as voltage decreases when ILIM is exceeded following constant resistance lines IBUS (Amps) FIGURE 7-1: 7.1.4.2 Current Limiting in Trip Mode. Constant Current Limiting (Variable Slope) Constant current limiting is used when the current drawn is greater than ILIM (and ILIM < 1.6A). In CC mode, the port power switch allows the attached portable device to reduce VBUS output voltage to less than the input VS voltage while maintaining current delivery. The V/I slope depends on the user set ILIM value. This slope is held constant for a given ILIM value. This mode is specifically provided for devices that rely on resistive means to reduce VBUS voltage for direct battery charging or to allow portable devices a means to “test” charger capacity. See Figure 7-2. IBUS VS VBUS << VS Power Switch ILIM Control Loop RSense Temp 5 V DC Battery Charger IC VBAT GND UCS 2112 FIGURE 7-2: Portable Device Constant Current Example. 0 0.53 0 0.96 1.28 1.6 2.13 2.67 3.2 IBUS (Amps) FIGURE 7-3: 7.2 Current Limiting in CC Mode. USB Port Power Profiles The UCS2112 combines the qualities of traditional USB port power switches with USB port power profiles set forth in the USB-IF BC1.2 specification. USB port power profiles consist of distinct voltage-current operation regions defined by “keep-out” and “operation” regions. While operating in the CC mode of operation, the UCS2112 provides voltage-current output operating profiles that are specified by two keep-out regions. If the current reaches the IBUS_R2MIN setting for longer than tMASK, the UCS2112 enters the Error state and an Overcurrent event is flagged. If the VBUS voltage ever goes below the no operation lower-voltage keep-out (VBUS_MIN) value for longer than tMASK, the port power switch is disabled and a keep-out violation is flagged (by setting the MIN_KEEP_OUT status bit). This will cause the device to enter the Error state. Figure 7-4 illustrates the relationship between these USB port power profile parameters. DS20005424B-page 28 2015 Microchip Technology Inc. UCS2112 7.2.1 OPERATION WITHIN A USB PORT POWER PROFILE An attached device may be constrained to operate within the boundaries of a USB port power profile by setting the value of ILIM less than the USB port power profile IBUS_R2MIN value. In this case, the port power switch will be in Trip mode up until ILIM is exceeded. At which point, the switch will transition into CC mode. If the attached device reduces the output voltage to less than VBUS_MIN, the switch will trip and terminate charging. 7.2.2 OPERATION OUTSIDE OF A USB PORT POWER PROFILE An attached device may be allowed to operate outside of the boundaries of a USB port power profile by setting the value of ILIM greater than the USB port power profile IBUS_R2MIN value. This is the default operation for all portable devices. In this case, the USB port power switch will operate in Trip mode until the bus current reaches the ILIM value. Once the ILIM value has been exceeded, the port power switch will open and terminate charging. Figure 7-5 illustrates an example of current limiting in this configuration. ILIM (Amps) 0.53 0.96 1.28 1.6 2.13 2.67 3.2 5.25 5 ILIM (Amps) 0.53 0.96 1.28 1.6 2.13 2.67 3.2 5.25 4.75 ILIM = 1.6A 5 4.75 ILIM = 2.67 A 4 IBUS_R2MIN = 1.6A Port Power Profile Operating Region 4 Port Power Profile Operating Region VBUS (Volts) 3 IBUS_R2MIN = 1. A VBUS (Volts) 3 2 VBUS_MIN = 2.0 V 2 VBUS_MIN = 2.0 V 1 (Trip) 1 (Trip) 0 0.53 0 0.96 1.28 1.6 2.13 2.67 3.2 IBUS (Amps) FIGURE 7-4: Note: ILIM < IBUS_R2MIN Example. The CC mode of operation is possible only up to 1.6A. As long as the value of ILIM is less than the fixed port power profile IBUS_R2MIN value, CC mode is possible. Otherwise, the USB port power switch will operate in trip mode operation. 2015 Microchip Technology Inc. 0 0 0.53 0.96 1.28 1.6 2.13 2.67 3.2 IBUS (Amps) FIGURE 7-5: ILIM > IBUS_R2MIN Example. DS20005424B-page 29 UCS2112 7.3 Thermal Management and Voltage Protection 7.3.1.2 Thermal Shutdown The UCS2112 utilizes two-stage internal thermal management. The first stage is Dynamic Thermal Management, and the second stage is Fixed Thermal Shutdown. The second stage of thermal management consists of a hardware implemented thermal shutdown corresponding to the maximum allowable internal die temperature (TTSD). If the internal temperature exceeds this value, the port power switches (both ports) will immediately be turned off until the temperature is below TTSD - TTSD_HYST. 7.3.1.1 7.4 7.3.1 THERMAL MANAGEMENT Dynamic Thermal Management For the first stage (active in both current-limiting modes), referred to as Dynamic Thermal Management, the UCS2112 automatically adjusts port power switch limits and modes to lower power dissipation when the thermal regulation temperature value is approached, as described in the following paragraphs. If the internal temperature exceeds the TREG value, the port power switch is opened, the current limit (ILIM) will be lowered by one step and a timer is started (tDC_TEMP). When this timer expires, the port power switch is closed and the internal temperature will be checked again. If it remains above the TREG threshold, the UCS2112 will repeat this cycle (open port power switch and reduce the ILIM setting by one step) until ILIM reaches its minimum value. If the UCS2112 is operating using Constant Current Limiting (variable slope) and the ILIM setting has been reduced to its minimum set point and the temperature is still above TREG, the UCS2112 will switch to operating using trip current limiting. This will be done by reducing the IBUS_R2MIN setting to 100 mA and restoring the ILIM setting to the value immediately below the programmed setting (e.g., if the programmed ILIM is 2.13A, the value will be set to 1.6A). If the temperature continues to remain above TREG, the UCS2112 will continue this cycle (open the port power switch and reduce the ILIM setting by one step). If the UCS2112 internal temperature drops below TREG - TREG_HYST, the UCS2112 will take action based on the following: 1. If the Current Limit mode changed from CC mode to Trip mode, then a timer is started. When this timer expires, the UCS2112 will reset the port power switch operation to its original configuration, allowing it to operate using Constant Current Limiting (variable slope). 2. If the Current Limit mode did not change from CC mode to Trip mode, or was already operating in Trip mode, the UCS2112 will reset the port power switch operation to its original configuration. If the UCS2112 is operating using Trip Current Limiting and the ILIM setting has been reduced to its minimum set point and the temperature is above TREG, the port power switch will be closed and the current limit will be held at its minimum setting until the temperature drops below TREG - TREG_HYST. DS20005424B-page 30 VBUS Discharge The UCS2112 will discharge VBUS through an internal 100 resistor when at least one of the following conditions occurs: • The PWR_EN control is disabled (triggered on the inactive edge of the PWR_EN control). • A portable device Removal Detection event is flagged if the Attach/Removal Detect feature is enabled (by default it is disabled). • The VS voltage drops below a specified threshold (VS_UVLO) that causes the port power switch to be disabled. • When commanded into the Sleep power state. • Upon recovery from the Error state. • When commanded via the SMBus in the Active state. • Any time the port power switch is activated after the VBUS bypass switch has been on (i.e., whenever VBUS voltage transitions from being driven from VDD to being driven from VS, such as going from Detect to Active power state) if the Attach/Removal Detect feature is enabled (by default it is disabled). • Any time the VBUS bypass switch is activated after the port power switch has been on (i.e., going from Active to Detect power state) if the Attach/Removal Detect feature is enabled (by default it is disabled). When the VBUS discharge circuitry is activated at the end of the tDISCHARGE time, the UCS2112 will confirm that VBUS was discharged. If the VBUS voltage is not below the V TEST level, a discharge error will be flagged (by setting the DISCH_ERR(1/2) status bit) and the UCS2112 will enter the Error state. 2015 Microchip Technology Inc. UCS2112 7.5 Charge Rationing Interactions When charge rationing is active, regardless of the specified behavior, the UCS2112 will function normally until the charge rationing threshold is reached. Note that charge rationing is only active when the UCS2112 is in the Active state, and it does not automatically reset when a Removal or Attach Detection event occurs. This allows charging of sequential portable devices while charge is being rationed, which means that the accumulated power given to several portable devices will still be held to the stated rationing limit. TABLE 7-2: Changing the charge rationing behavior will have no effect on the charge rationing data registers. If the behavior is changed prior to reaching the charge rationing threshold, this change will occur and be transparent to the user. When the charge rationing threshold is reached, the UCS2112 will take action as shown in Table 7-2. If the behavior is changed after the charge rationing threshold has been reached, the UCS2112 will immediately adopt the newly programmed behavior, clearing the ALERT# pin and restoring switch operation respectively (see Table 7-4). CHARGE RATIONING BEHAVIOR RATION_BEH (1 or 2) <1:0> Behavior Actions taken Notes 1 0 0 0 Report 0 1 Report and Disconnect (default) 1. 2. ALERT# pin asserted. Port power switch disconnected. All bus monitoring is still active. Toggling the PWR_EN control will cause the device to change power states as defined by the registers; however, the port power switch will remain off until the rationing circuitry is reset. Furthermore, the bypass switch will not be turned on if enabled via the Attach Detection. 1 0 Disconnect and Go to Sleep 1. Port power switch disconnected. Device will enter the Sleep state. All VBUS and VS monitoring will be stopped. Toggling the PWR_EN control will have no effect on the power state until the rationing circuitry is reset. 1 Ignore 1 TABLE 7-3: ALERT# pin asserted. 2. Take no further action. CHARGE RATIONING RESET BEHAVIOR Behavior Reset Actions Report 1. 2. 3. Reset the Total Accumulated Charge registers. Clear the RATION status bit. Release the ALERT# pin. Report and Disconnect 1. 2. 3. 4. Reset the Total Accumulated Charge registers. Clear the RATION status bit. Release the ALERT# pin. Check the PWR_EN controls and enter the indicated power state if the controls changed. Disconnect and Go to Sleep 1. 2. 3. Reset the Total Accumulated Charge registers. Clear the RATION status bit. Check the PWR_EN controls and enter the indicated power state if the controls changed. Ignore 1. 2. Reset the Total Accumulated Charge registers. Clear the RATION status bit. 2015 Microchip Technology Inc. DS20005424B-page 31 UCS2112 TABLE 7-4: EFFECTS OF CHANGING RATIONING BEHAVIOR AFTER THRESHOLD REACHED Previous Behavior New Behavior Ignore Report Actions Taken Assert ALERT# pin. Report and Disconnect 1. 2. Assert ALERT# pin. Open port power switch. See the Report and Disconnect (default) in Table 7-2. Disconnect and Go to Sleep 1. 2. Open port power switch. Enter the Sleep state. See the Disconnect and Go to Sleep in Table 7-2. Report Ignore Report and Disconnect Release ALERT# pin. Open port power switch. See the Report and Disconnect (default) in Table 7-2. Disconnect and Go to Sleep 1. 2. 3. Release the ALERT# pin. Open the port power switch. Enter the Sleep state. See the Disconnect and Go to Sleep in Table 7-2. Ignore 1. 2. Release the ALERT# pin. Check the PWR_EN controls and enter the indicated power state if the controls changed. Report Check the PWR_EN controls and enter the indicated power state if the controls changed. Report and Disconnect Disconnect and Go to Sleep Disconnect and go to Sleep 1. 2. Release the ALERT# pin. Enter the Sleep state. See the Disconnect and Go to Sleep in Table 7-2. Ignore Check the PWR_EN controls and enter the indicated power state if the controls changed. Report 1. 2. Assert the ALERT# pin. Check the PWR_EN controls and enter the indicated power state if the controls changed. Report and Disconnect 1. 2. Assert the ALERT# pin. Check the PWR_EN controls to determine the power state then enter that state except that the port power switch and bypass switch will not be closed. If the RATION_EN control is set to ‘0’ prior to reaching the charge rationing threshold, rationing will be disabled and the Total Accumulated Charge registers will be cleared. If the RATION_EN control is set to ‘0’ after the charge rationing threshold has been reached, the following additional steps occur: 1. 2. 3. RATION status bit will be cleared. The ALERT# pin will be released if asserted by the rationing circuitry and no other conditions are present. The PWR_EN controls are checked to determine the power state. Setting the RATION_RST control to ‘1’ will automatically reset the Total Accumulated Charge registers to 00_00h. If this is done prior to reaching the charge rationing threshold, the data will continue to be accumulated restarting from 00_00h. If this is done after the charge rationing threshold is reached, the UCS2112 will take action as shown in Table 7-3. DS20005424B-page 32 2015 Microchip Technology Inc. UCS2112 7.6 7.6.1 Fault Handling Mechanism The UCS2112 has two modes for handling faults: When the LATCH_SET bit is low, Auto-Recovery Fault Handling is used. When an error condition is detected, the UCS2112 will immediately enter the Error state and assert the ALERT# pin. Independently from the host controller, the UCS2112 will wait a preset time (tCYCLE), check error conditions (tTST), and restore Active operation if the error condition(s) no longer exist. If all other conditions that may cause the ALERT# pin to be asserted have been removed, the ALERT# pin will be released. Short-Circuit Auto-Recovery example in Figure 7-6. • Latch (latch-upon-fault) • Auto-recovery (automatically attempt to restore the Active power state after a fault occurs). If the SMBus is actively utilized, Auto-Recovery Fault Handling is the default error handler as determined by the LATCH_SET bit. Faults include overcurrent, overvoltage (on VS), undervoltage (on VBUS), back-voltage (VBUS to VS or VBUS to VDD), discharge error, and maximum allowable internal die temperature (TTSD) exceeded. Faults do not include keep-out violations except VBUS_MIN. tCYCLE VBUS AUTO-RECOVERY FAULT HANDLING tTST tCYCLE tTST VTEST tDISCHARGE SHORT applied. IBUS ITEST Short Detected. VBUS discharged. Enter Error state. FIGURE 7-6: 7.6.2 Wait tCYCLE. Check short condition. Short still present. Return to Error State. ITEST Wait tCYCLE. Check short condition. Short removed. Return to normal operation. Error Recovery. LATCHED FAULT HANDLING When the LATCH_SET bit is high, latch fault handling is used. When an error condition is detected, the UCS2112 will enter the Error power state and assert the ALERT# (1 or 2) pin. Upon command from the host controller (by toggling the PWR_EN (1, or 2) pin control from enabled to disabled or by clearing the ERR bit via SMBus), the UCS2112 will check error conditions once and restore Active operation if error conditions no longer exist. If an error condition still exists, the host controller is required to issue the command again to check error conditions. If the ALERT# pin is asserted and the interrupt status registers (addresses 03h or 04h) are not read, the corresponding ALERT# pin remains asserted until the corresponding PWR_EN pin is toggled. If the ALERT# pin is asserted and the interrupt status registers are read, the ALERT# pin will de-assert, but the UCS will remain in error state until the ERR bit is cleared via SMBus or the PWR_EN pin is toggled. 2015 Microchip Technology Inc. DS20005424B-page 33 UCS2112 8.0 SYSTEM MANAGEMENT BUS PROTOCOL In SMBus mode, the UCS2112 communicates with a host controller, such as an Microchip PIC® microcontroller or hub, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 1-1. Stretching of the SMCLK signal is supported; however, the UCS2112 will not stretch the clock signal. 8.1 SMBus Start Bit 8.6 SMBus Time-out The UCS2112 includes an SMBus time-out feature. If the clock is held at logic ‘0’ for tTIMEOUT, the device can time out and reset the SMBus interface. The SMBus interface can also reset if both the clock and data lines are held at a logic ‘1’ for tIDLE_RESET. Communication is restored with a start condition. The time-out function defaults to disabled. It can be enabled by clearing the DIS_TO bit in the General Configuration 3 register (see Register 9-9). 8.7 SMBus and I2C Compliance The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state. The major difference between SMBus and I2C devices is highlighted here. For complete compliance information, refer to the SMBus 2.0 specification and Application Note 14.0. 8.2 • UCS2112 supports I2C fast mode at 400 kHz. This covers the SMBus maximum time of 100 kHz. • The minimum frequency for SMBus communications is 10 kHz. • The client protocol will reset if the clock is held low longer than 30 ms. This time out functionality is disabled by default in the UCS2112 and can be enabled by clearing the DIS_TO bit. I2C does not have a time out. • Except when operating in Sleep, the client protocol will reset if both the clock and the data line are logic ‘1’ for longer than 200 µs (idle condition). This function is disabled by default in the UCS2112 and can be enabled by clearing the DIS_TO bit. I2C does not have an idle condition. • I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). • I2C devices support block read and write differently. I2C protocol allows for unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read/write is transmitted. The UCS2112 supports I2C formatting only. SMBus Address and RD/WR Bit The SMBus Address Byte consists of the 7-bit client address followed by the RD/WR indicator bit. If this RD/WR bit is a logic ‘0’, the SMBus Host is writing data to the client device. If this RD/WR bit is a logic ‘1’, the SMBus Host is reading data from the client device. The UCS2112 with the order code UCS2112-1-V/G4 has the SMBus address 57h - 1010_111(r/w). Customers should contact their distributor, representatives or field application engineer (FAE) for additional SMBus addresses. Local sales offices are also available to help customers. A list of sales offices and locations is included in the back of this document. 8.3 SMBus Data Bytes All SMBus Data bytes are sent most significant bit first and composed of 8 bits of information. 8.4 SMBus ACK and NACK Bits The SMBus client will acknowledge all data bytes that it receives. This is done by the client device pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write protocols. The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK (acknowledge) each data byte that it receives except the last data byte. 8.5 SMBus Stop Bit The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the UCS2112 detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its client interface and prepare to receive further communications. DS20005424B-page 34 8.8 SMBus Protocols The UCS2112 is SMBus 2.0-compatible and supports Send Byte, Read Byte, Block Read, Receive Byte as valid protocols as shown below. The UCS2112 also supports the I2C block read and block write protocols. The device supports Write Byte, Read Byte, and Block Read/Block Write. All of the below protocols use the convention in Table 8-1. TABLE 8-1: SMBUS PROTOCOL Data Sent to Device Data Sent to the Host Data sent Data sent 2015 Microchip Technology Inc. UCS2112 8.9 SMBus Write Byte The Write Byte is used to write one byte of data to a specific register as shown in Table 8-2. TABLE 8-2: WRITE BYTE PROTOCOL START Slave Address WR ACK Reg. Addr. ACK Register Data ACK STOP 1→0 YYYY_YYY 0 0 XXh 0 XXh 0 0→1 8.10 SMBus Read Byte The Read Byte protocol is used to read one byte of data from the registers as shown in Table 8-3. TABLE 8-3: READ BYTE PROTOCOL START Slave Address WR ACK Register Address ACK 1→0 YYYY_YYY 0 0 XXh 0 START Slave Address RD ACK Register Data NACK STOP 1 →0 YYYY_YYY 1 0 XXh 1 0→1 8.11 Block Write The Block Write is used to write multiple data bytes to a group of contiguous registers, as shown in Table 8-4. It is an extension of the Write Byte Protocol. The Block Write and Block Read protocols require that the address pointer be automatically incremented. For a write command, the address pointer will be automatically incremented when the ACK is sent to the host. There are no over or under bound limit checking and the address pointer will wrap around from FFh to 00h if necessary Note: TABLE 8-4: START 1→0 8.12 BLOCK WRITE PROTOCOL Slave Address YYYY_YYY WR 0 ACK Repeat N Times Register Address ACK XXh 0 0 STOP Register Data ACK XXh 0 0→1 Block Read The Block Read is used to read multiple data bytes from a group of contiguous registers, as shown in Table 8-5. It is an extension of the Read Byte Protocol. TABLE 8-5: BLOCK READ PROTOCOL START Slave Address WR ACK Register Address ACK 1→0 YYYY_YYY 0 0 XXh 0 START Slave Address RD ACK Repeat N Times 1→0 YYYY_YYY 2015 Microchip Technology Inc. 1 0 Register Data NACK Register Data ACK XXh 0 XXh 1 STOP 0→1 DS20005424B-page 35 UCS2112 8.13 SMBus Send Byte The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 8-6. TABLE 8-6: SEND BYTE PROTOCOL START Slave Address WR ACK Register Address ACK STOP 1→0 YYYY_YYY 0 0 XXh 0 0→1 8.14 SMBus Receive Byte The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 8-7. TABLE 8-7: RECEIVE BYTE PROTOCOL START Slave Address RD ACK Register Data NACK STOP 1→0 YYYY_YYY 1 0 XXh 1 0→1 8.14.1 STAND-ALONE OPERATING MODE Stand-alone mode allows the UCS2112 to operate communications. without active SMBus/I2C Stand-alone mode can be enabled by connecting a pull-down resistor greater or equal to 47 k on the COMM_ILIM pin as shown in Table 5-3.The SMCLK pin should be tied to ground in this mode. DS20005424B-page 36 2015 Microchip Technology Inc. UCS2112 9.0 REGISTER DESCRIPTION The registers shown in Table 9-1 are accessible through the SMBus or I2C. An entry of ‘—’ indicates that the bit is not used. Writing to these bits will have no effect and reading these bits will return ‘0’. Writing to a reserved bit may cause unexpected results and reading from a reserved bit will return either ‘1’ or ‘0’ as indicated in the bit description. While in the Sleep state, the UCS2112 will retain configuration and charge rationing data as indicated in the text. If a register does not indicate that data will be retained in the Sleep power state, this information will be lost when the UCS2112 enters the Sleep power state. TABLE 9-1: REGISTER SET IN HEXADECIMAL ORDER Register Address Register Name R/W Default Value Page No. 00h Port 1 Current Measurement R Stores the current measurement for port 1 00h 38 01h Port 2 Current Measurement 02h Load Share VBUS Port Status R Stores the current measurement for port 2 00h 38 R Indicates Load ShareVBUS Port and general status 00h 39 03h Interrupt Status1 See Text Indicates why ALERT# pin asserted for port 1 00h 40 04h Interrupt Status2 See Text Indicates why ALERT# pin asserted for port 2 00h 42 Function 0Fh General Status1 R/R-C Indicates General Status for port 1 00h 43 10h General Status2 R/R-C Indicates General Status for port 2 00h 44 11h General Configuration1 R/W Controls basic functionality for port 1 06h 45 12h General Configuration2 R/W Controls basic functionality for port 2 02h 46 13h General Configuration3 R/W Controls other functionality 60h 47 14h Current Limit R/W Controls/Displays MAX Current Limit per port 00h 48 15h Auto-recovery Configuration R/W Controls the Auto-recovery functionality 2Ah 49 16h Port 1 Total Accumulated Charge High Byte R Stores the total accumulated charge delivered high byte, Port 1 00h 50 17h Port 1 Total Accumulated Charge Middle High Byte R Stores the total accumulated charge delivered middle high byte, Port 1 00h 50 18h Port 1 Total Accumulated Charge Middle Low Byte R Stores the total accumulated charge delivered middle low byte, Port 1 00h 50 19h Port 1 Total Accumulated Charge Low Byte R Stores the total accumulated charge delivered low byte, Port 1 00h 50 1Ah Port 2 Total Accumulated Charge High Byte R Stores the total accumulated charge delivered high byte, Port 2 00h 51 1Bh Port 2 Total Accumulated Charge Middle High Byte R Stores the total accumulated charge delivered middle high byte, Port 2 00h 51 1Ch Port 2 Total Accumulated Charge Middle Low Byte R Stores the total accumulated charge delivered middle low byte, Port 2 00h 51 1Dh Port 2 Total Accumulated Charge Low Byte R Stores the total accumulated charge delivered low byte, Port 2 00h 51 1Eh Port 1 Charge Rationing Threshold High Byte R/W Sets the maximum allowed charge that will be delivered to Port 1 FFh 52 1Fh Port 1 Charge Rationing Threshold Low Byte R/W Sets the maximum allowed charge that will be delivered to Port 1 FFh 52 2015 Microchip Technology Inc. DS20005424B-page 37 UCS2112 TABLE 9-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address Register Name R/W Function Default Value Page No. 20h Port 2 Charge Rationing Threshold High Byte R/W Sets the maximum allowed charge that will be delivered to Port 2 FFh 52 21h Port 2 Charge Rationing Threshold Low Byte R/W Sets the maximum allowed charge that will be delivered to Port 2 FFh 52 22h Ration Configuration R/W Controls Charge Ration Functionality 11h 53 23h Port 1 Current Limit Behavior R/W Controls the Current Limiting Behavior (CC Mode Region 2) for Port 1 96h 54 24h Port 2 Current Limit Behavior R/W Controls the Current Limiting Behavior (CC Mode Region 2) for Port 2 96h 54 FDh Product ID E0hE1h 55 R Stores a fixed value that identifies each product FEh Manufacturer ID R Stores a fixed value that identifies Microchip 5Dh 55 FFh Revision R Stores a fixed value that represents the revision number 81h 55 9.1 Current Measurement Register The Current Measurement register stores the measured current value delivered to the portable device (IBUS). This value is updated continuously while the device is in the Active power state. REGISTER 9-1: R-0 PORTS 1 AND 2 CURRENT MEASUREMENT REGISTERS (ADDRESSES 00H, 01H) R-0 R-0 R-0 R-0 R-0 R-0 R-0 CM(x)<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7:0 Note 1: 2: x = Bit is unknown CM(x)<7:0>: Port X Current Measurement, where x=1 or 2 (address 00h for Port 1 and address 01h for Port 2). The bit weights are in mA,1 LSB = 13.3 mA (maximum value is 255 LSB corresponding to 3.4A). This data will be cleared when the device enters the Sleep or Detect states. This data will also be cleared whenever the port power switch is turned off (or any time that VBUS is discharged). DS20005424B-page 38 2015 Microchip Technology Inc. UCS2112 9.2 Status Registers The Status registers store bits that indicate error conditions as well as Attach Detection and Removal Detection. REGISTER 9-2: R-0 ALERT2_PIN VBUS PORT STATUS REGISTER (ADDRESS 02H) R-0 ALERT1_PIN R-0 CC_MODE2 R-0 U-0 U-0 R-0 R-0 CC_MODE1 — — ADET2_PIN ADET1_PIN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALERT2_PIN: Reflects the status of the ALERT#2 pin. This bit is set and cleared as the ALERT#2 pin changes states. 1 = ALERT#2 Pin asserted (logic low) 0 = ALERT#2 Pin not asserted bit 6 ALERT1_PIN: Reflects the status of the ALERT#1 pin. This bit is set and cleared as the ALERT#1 pin changes states. 1 = ALERT#1 Pin asserted (logic low) 0 = ALERT#1 Pin not asserted bit 5 CC_MODE2: Port2 Constant Current Mode State 1 = Port 2 in Constant Current mode 0 = Port 2 operating normally bit 4 CC_MODE1: Port1 Constant Current Mode State 1 = Port 1 in Constant Current mode 0 = Port 1 operating normally bit 3-2 Unimplemented bit 1 ADET2:_PIN Reflects the status of the A_DET#2 pin. When set, indicates that the A_DET#2 pin is asserted low. This bit is set and cleared as the A_DET#2 pin changes states. 1 = A_DET#2 pin is asserted (logic low) 0 = A_DET#2 pin is not asserted bit 0 ADET1_PIN: Reflects the status of the A_DET#1 pin. When set, indicates that the A_DET#1 pin is asserted low. This bit is set and cleared as the A_DET#1 pin changes states. 1 = A_DET#1 pin is asserted (logic low) 0 = A_DET#1 pin is not asserted 2015 Microchip Technology Inc. DS20005424B-page 39 UCS2112 REGISTER 9-3: INTERRUPT STATUS 1 REGISTER (ADDRESS 03H) R/W-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 ERR1 DISCH_ERR1 RESET KEEP_OUT1 TSD OV_VOLT BACK_V1 OV_LIM1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ERR1: Error Port 1 - Indicates that an error was detected on the VBUS1 pin and the device has entered the Error state. Writing this bit to ‘0’ will clear the Error state and allows the device to be returned to the Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been removed, the UCS2112 returns to the Active state. This bit is set automatically by the UCS2112 when the Error state is entered. If any other bit is set in the Interrupt Status register (03h), the device will not leave the Error state. This bit is cleared automatically by the UCS2112 if the Auto-recovery fault handling functionality is active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN1 control is disabled (Note 1). 1 = Port 1 in Error State. 0 = Port 1 in Active State (no errors detected). bit 6 DISCH_ERR1: Discharge Error Port 1 - indicates the device was unable to discharge Port1. This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state. 1 = UCS2112 was unable to Discharge VBUS1. 0 = No VBUS1 discharge error. bit 5 RESET: Indicates that the UCS2112 has just been reset and should be re-programmed. This bit will be set at power-up. This bit is cleared when read or when the PWR_EN control is toggled. The ALERT# pins are not asserted when this bit is set. This data is retained in the Sleep state. 1 = UCS2112 has just been reset. 0 = Reset did not occur. bit 4 KEEP_OUT1: Port 1 Minimum Keep-out region - Indicates that the V-I output on the VBUS1 pin has dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state. 1 = VBUS1 < VBUS_MIN 0 = VBUS1 > VBUS_MIN bit 3 TSD: Thermal Shutdown - Indicates that the internal temperature has exceeded TTSD threshold and the device has entered the Error state. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1and ALERT#2 pins to be asserted and the device to enter the Error state. 1 = Thermal Shutdown Temperature reached. 0 = Internal temperature < TTSD bit 2 OV_VOLT: VS Overvoltage Indicates that the VS voltage has exceeded the VS_OV threshold, and the device has entered the Error state. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 and ALERT#2 pins to be asserted and the device to enter the Error state. 1 = VS > VS_OV 0 = VS < VS_OV DS20005424B-page 40 2015 Microchip Technology Inc. UCS2112 REGISTER 9-3: INTERRUPT STATUS 1 REGISTER (ADDRESS 03H) (CONTINUED) bit 1 BACK_V1: Back-Bias Voltage Port 1 - Indicates that the VBUS1 voltage has exceeded the VS or VDD voltages by more than 150 mV. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state. 1 = VBUS1 > VS, or VBUS1 > VDD by more than 150 mV. 0 = VBUS1 voltage has not exceeded the VS and VDD voltages by more than 150 mV. bit 0 OV_LIM1: Over Current Limit Port 1 -Indicates that the IBUS current has exceeded both the ILIM threshold and the IBUS_R2MIN threshold settings for VBUS1. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state. 1 = Current Limit for Port 1 exceeded 0 = Current Limit for Port 1 not exceeded Note 1: Note that the ERR1 bit does not necessarily reflect the ALERT#1 pin status. The ALERT#1 pin may be cleared or asserted without the ERR1 bit changing states. 2015 Microchip Technology Inc. DS20005424B-page 41 UCS2112 REGISTER 9-4: INTERRUPT STATUS 2 REGISTER (ADDRESS 04H) R/W-0 R/C-0 R-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 ERR2 DISCH_ERR2 VS_LOW KEEP_OUT2 TREG — BACK_V2 OV_LIM2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ERR2: Error Port 2 - Indicates that an error was detected on the VBUS1 pin and the device has entered the Error state. Writing this bit to a ‘0’ will clear the Error state and allows the device to be returned to the Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been removed, the UCS2112 returns to the Active state. This bit is set automatically by the UCS2112 when the Error state is entered. If any other bit is set in the Interrupt Status register (04h), the device will not leave the Error state. This bit is cleared automatically by the UCS2112 if the auto-recovery fault handling functionality is active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN2 control is disabled (Note 1). 1 = Port 2 in Error State. 0 = Port 2 in Active State (no errors detected). bit 6 DISCH_ERR2: Discharge Error Port 2 - indicates the device was unable to discharge Port2. This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state. 1 = Device was unable to Discharge VBUS2. 0 = No VBUS2 discharge error. bit 5 VS_LOW: Indicates that the VS voltage has fallen below the VS_UVLO threshold and both VBUS1 and VBUS2 port power switches are held off. This bit is cleared automatically when the VS voltage is above the VS_UVLO threshold. 1 = VS voltage has fallen below the VS_UVLO. 0 = VS voltage is above VS_UVLO. bit 4 KEEP_OUT2: Port 2 Minimum Keep-out region - Indicates that the V-I output on the VBUS2 pin has dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state. 1 = VBUS2 < VBUS_MIN 0 = VBUS2 > VBUS_MIN bit 3 TREG: Thermal Regulation - Indicates that the internal temperature has exceeded TREG and that the current limit has been reduced. This bit is cleared when read and will not cause the ALERT#1 and ALERT#2 pins to be asserted unless the ALERT_LINK bit is set. 1 = Internal temperature > TREG 0 = Internal temperature < TREG bit 2 Unimplemented: Read as '0' bit 1 BACK_V2: Back-Bias Voltage Port 2 - Indicates that the VBUS2 voltage has exceeded the VS or VDD voltages by more than 150 mV. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state. 1 = VBUS2 > VS, or VBUS2 > VDD by more than 150 mV. 0 = VBUS2 voltage has not exceeded the VS and VDD voltages by more than 150 mV. bit 0 OV_LIM2: Overcurrent Limit Port 2 - Indicates that the IBUS current has exceeded both the ILIM threshold and the IBUS_R2MIN threshold settings for VBUS2. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state. 1 = Current Limit for Port 2 exceeded 0 = Current Limit for Port 2 not exceeded. Note 1: Note that the ERR2 bit does not necessarily reflect the ALERT#2 pin status. The ALERT#2 pin may be cleared or asserted without the ERR2 bit changing states. DS20005424B-page 42 2015 Microchip Technology Inc. UCS2112 REGISTER 9-5: GENERAL STATUS 1 REGISTER (ADDRESS 0FH) R/C-0 U-x U-x RATION1 — — R-0 R-0 R/C-0 CC_MODE1 PWR_EN1_CON LOW_CUR1 R/C-0 R-0 REM1 ADET1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RATION1: Indicates the state of Port 1 Rationing. This bit is cleared when read, or cleared automatically when the RATION_RST1 bit is set or the RATION_EN1 bit is cleared. 1 = Port 1 has delivered the programmed mAh of current 0 = Port 1 has not delivered the programmed mAh of current bit 6-5 Unimplemented bit 4 CC_MODE1: Indicates whether Port 1 has entered CC mode. 1 = Port 1 is in CC mode 0 = Port 1 not in CC mode bit 3 PWR_EN1_CON: Reflects the PWR_EN control state. This bit is set and cleared automatically with the logic expression (PWR_EN1 pin OR PWR_EN1S). 1 = Port 1 Power Enable is set 0 = Port 1 Power Enable is clear bit 2 LOW_CUR1: Indicates if the portable device charge current is below the 13.3 mA threshold on the VBUS1 and may be finished charging. This bit is cleared when read and will cause the ALERT#1 pin to be asserted if the ALERT_LINK1 bit is set. 1 = Port 1 charging current less than threshold 0 = Port 1 charging current above threshold bit 1 REM1: Removal Detection Port1 - Indicates if a Removal Detection event has occurred and there is no longer a portable device present on the VBUS1 pin. This bit is cleared when read and will not cause the ALERT#1 pin to be asserted. 1 = Removal Detection occurred 0 = No Removal Detection bit 0 ADET1: Attach Detection Port1 - Indicates that an Attach Detection event has occurred on the VBUS1 pins and there is a new portable device present. Asserts the A_DET#1 pin. This bit is set and cleared as the A_DET#1 pin changes. 1 = Attach Detection event has occurred. A_DET#1 pin asserted 0 = No Attach Detection event 2015 Microchip Technology Inc. DS20005424B-page 43 UCS2112 REGISTER 9-6: GENERAL STATUS 2 REGISTER (ADDRESS 10H) R/C-0 U-x U-x RATION2 — — R-0 R-0 R/C-0 CC_MODE2 PWR_EN2_CON LOW_CUR2 R/C-0 R-0 REM2 ADET2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RATION2: Indicates the state of Port 2 Rationing. This bit is cleared when read, or cleared automatically when the RATION_RST2 bit is set or the RATION_EN2 bit is cleared. 1 = Port 2 has delivered the programmed mAh of current 0 = Port 2 has not delivered the programmed mAh of current bit 6-5 Unimplemented bit 4 CC_MODE2: Indicates whether Port 2 has entered CC mode. 1 = Port 2 is in CC mode 0 = Port 2 not in CC mode bit 3 PWR_EN2_CON: Reflects the PWR_EN control state. This bit is set and cleared automatically with the logic expression (PWR_EN2 pin OR. PWR_EN2S). 1 = Port 2 Power Enable is set 0 = Port 2 Power Enable is clear bit 2 LOW_CUR2: Indicates if the portable device charge current is below the 13.3 mA threshold on the VBUS2 and may be finished charging. This bit is cleared when read and will cause the ALERT#2 pin to be asserted if the ALERT_LINK2 bit is set. 1 = Port 2 charging current less than threshold 0 = Port 2 charging current above threshold bit 1 REM2: Removal Detection Port2 - Indicates if a Removal Detection event has occurred and there is no longer a portable device present on the VBUS1 pin. This bit is cleared when read and will not cause the ALERT#2 pin to be asserted. 1 = Removal Detection occurred 0 = No Removal Detection bit 0 ADET2: Attach Detection Port2 - indicates that an Attach Detection event has occurred on the VBUS2 pins and there is a new portable device present. Asserts the A_DET#2 pin. This bit is set and cleared as the A_DET#2 pin changes. 1 = Attach Detection event has occurred. A_DET#2 pin asserted 0 = No Attach Detection event DS20005424B-page 44 2015 Microchip Technology Inc. UCS2112 9.3 Configuration Registers The Configuration registers control basic device functionality. The contents of these registers are retained in Sleep. REGISTER 9-7: GENERAL CONFIGURATION 1 REGISTER (ADDRESS 11H) R/W-0 R/W-0 R/W-0 R/W-0 ALERT1_MASK ALERT1_LINK DSCHG1 PWR_EN1S R/W-0 R/W-1 DISCHG_TIME<1:0> R/W-1 R/W-0 ATT_TH1<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALERT1_MASK: Mask errors for all interrupts in Register 9-3 except OV_LIM1 and TSD. 1 = The ALERT#1 pin will only assert if a OV_LIM1 or TSD is detected. 0 = The ALERT#1 pin will be asserted if an error condition or indicator event is detected. bit 6 ALERT1_LINK: Links the ALERT#1 pin to be asserted when the LOW_CUR1 bit is set. 1 = The ALERT#1 pin will be asserted if the LOW_CUR1 indicator bit is set. 0 = The ALERT#1 pin will not be asserted if the LOW_CUR1 indicator bit is set. bit 5 DSCHG1: Forces the VBUS1 to be reset and discharged when the UCS2112 is in the Active state. Writing this bit to a logic ‘1’ will cause the port power switch to be opened and the discharge circuitry to activate and discharge VBUS. Actual discharge time is controlled by DISCHG_TIME<1:0>. This bit is self-clearing. 1 = VBUS1 discharge initiated. 0 = Port 1 not in discharge bit 4 PWR_EN1S: Power Enable Port 1 override - This bit is OR’ed with the PWR_EN1 pin. Thus, if the polarity is set to active-high, either the PWR_EN1 pin or this bit must be ‘1’ to enable the port power switch. bit 3-2 DISCHG_TIME<1:0>: Discharge time Port 1 - sets tDISCHARGE. The discharge time value is the same for both ports. 00 = 100 ms 01 = 200 ms 10 = 300 ms 11 = 400 ms bit 1-0 ATT_TH1<1:0>: Attach Detection Threshold Port 1 - determines the current draw needed to determine an Attach event has occurred. Also controls the Removal Detection current level (Note 1). 00 = 200 µA Attach/100 µA Removal 01 = 400 µA Attach/300 µA Removal 10 = 800 µA Attach/700 µA Removal 11 = 1000 µA Attach/900 µA Removal Note 1: The removal threshold is different when operating in the Active power state versus when operating in the Detect power state. 2015 Microchip Technology Inc. DS20005424B-page 45 UCS2112 REGISTER 9-8: GENERAL CONFIGURATION 2 REGISTER (ADDRESS 12H) R/W-0 R/W-0 ALERT2_MASK ALERT2_LINK R/W-0 R/W-0 U-0 U-0 DSCHG2 PWR_EN2S — — R/W-1 R/W-0 ATT_TH2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALERT2_MASK: Mask errors for all interrupts in Register 9-4 except OV_LIM2 and TSD. 1 = The ALERT#2 pin will only assert if a OV_LIM2 or TSD is detected. 0 = The ALERT#2 pin will be asserted if an error condition or indicator event is detected. bit 6 ALERT2_LINK: Links the ALERT#2 pin to be asserted when the LOW_CUR2 or TREG bits are set. 1 = The ALERT#2 pin will be asserted if the LOW_CUR2 or TREG indicator bit is set. 0 = The ALERT#2 pin will not be asserted if the LOW_CUR2 or TREG indicator bit is set. bit 5 DSCHG2: Forces the VBUS2 to be reset and discharged when the UCS2112 is in the Active state. Writing this bit to a logic ‘1' will cause the port power switch to be opened and the discharge circuitry to activate to discharge VBUS. Actual discharge time is controlled by DISCHG_TIME<1:0>. This bit is self-clearing. 1 = VBUS2 discharge initiated. 0 = Port 2 not in discharge bit 4 PWR_EN2S: Power Enable Port 2 override - This bit is OR’ed with the PWR_EN2 pin. Thus, if the polarity is set to active-high, either the PWR_EN2 pin or this bit must be ‘1’ to enable the port power switch. bit 3-2 Unimplemented bit 1-0 ATT_TH2<1:0>: Attach Detection Threshold Port 2 - determines the current draw needed to determine an Attach event has occurred. Also controls the Removal Detection current level (Note 1). 00 = 200 µA Attach/100 µA Removal 01 = 400 µA Attach/300 µA Removal 10 = 800 µA Attach/700 µA Removal 11 = 1000 µA Attach/900 µA Removal Note 1: The removal threshold is different when operating in the Active power state versus when operating in the Detect power state. DS20005424B-page 46 2015 Microchip Technology Inc. UCS2112 REGISTER 9-9: GENERAL CONFIGURATION 3 REGISTER (ADDRESS 13H) R/W-0 R/W-1 R/W-1 PIN_IGN ATT_DIS DIS_TO R-0 R-0 PWR_STATE<1:0> R/W-0 U-0 U-0 BOOST — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PIN_IGN: Ignores the PWR_EN1 and PWR_EN2 pin states when determining the power state. This bit is retained in Sleep. 1 = PWR_EN1 and PWR_EN2 pin states are ignored. 0 = Power state is determined by the OR'd combination of the PWR_EN1 and PWR_EN2 pins states and the corresponding PWR_EN1S and PWR_EN2S bit states. bit 6 ATT_DIS: Attach Detect Disable - Disables the Attach and Removal Detection feature and affects the power state (see Table 5-2). Setting this bit to 1 forces Active state provided the PWR_EN 1/2 control is enabled. 1 = Attach/Removal Detection disabled. 0 = Attach/Removal Detection enabled. bit 5 DIS_TO: Disable Time Out - Disables the SMBus time out feature. 1 = Time out disabled 0 = Time out enabled bit 4-3 PWR_STATE<1:0>: Current Power State - These bits indicate the current Power State. See Note 1 00 =SLEEP 01 =DETECT 10 =ACTIVE 11 =ERROR bit 2 BOOST: Indicates that the IBUS current is higher than IBOOST on VBUS1 or VBUS2 (bit is OR’ed). 1 = IBUS has exceeded IBOOST on either or both ports 0 = IBUS is less than IBOOST on either port individually bit 1-0 Note 1: Unimplemented Accessing the SMBus/I2C™ causes the UCS2112 to leave the Sleep state. As a result, the PWR_STATE<1:0> bits will never read as 00b. 2015 Microchip Technology Inc. DS20005424B-page 47 UCS2112 9.4 Current Limit Register The Current Limit register controls the ILIM used by the port power switch. The default setting is based on the resistor on the COMM_ILIM pin and this value cannot be changed to be higher than hardware set value. The contents of this register are retained in Sleep. REGISTER 9-10: CURRENT LIMIT REGISTER (ADDRESS 14H) U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 ILIM_PORT2<2:0> R/W-0 R/W-0 ILIM_PORT1<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’' bit 5-3 ILIM_PORT2<2:0>: Sets the ILIM value for port 2. 000 = 0.53A 001 = 0.96A 010 = 1.07A 011 = 1.28A 100 = 1.6A 101 = 2.13A 110 =2.67A 111 =3.2A bit 2-0 ILIM_SW<2:0>: Sets the ILIM value for port 1. 000 = 0.53A 001 = 0.96A 010 = 1.07A 011 = 1.28A 100 = 1.6A 101 = 2.13A 110 = 2.67A 111 = 3.2A DS20005424B-page 48 x = Bit is unknown 2015 Microchip Technology Inc. UCS2112 9.5 Auto-Recovery Register The contents of this register are retained in Sleep. The Auto-Recovery Configuration register sets the parameters used when the Auto-recovery fault handling algorithm is invoked. Once the Auto-recovery fault handling algorithm has checked the overtemperature and back-drive conditions, it will set the ILIM value to ITEST and then turn on the port power switch and start the tTST timer. If, after the timer has expired, the VBUS voltage is less than VTEST, then it is assumed that a short-circuit condition is present and the Error state is restarted for Auto Recovery. REGISTER 9-11: R/W-0 AUTO RECOVERY CONFIGURATION REGISTER (ADDRESS 15H) R/W-0 LATCHS R/W-1 TCYCLE<2:0> R/W-0 R/W-1 R/W-0 TTST<1:0> R/W-1 R/W-0 VTST_SW<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 LATCHS: Latch Set - Controls the fault-handling routine that is used in the case that an error is detected. 1 = Error state will be latched. In order for the UCS2112 to return to normal Active state, the ERR bit must be cleared by the user. 0 = The UCS2112 will automatically retry when an error condition is detected. bit 6-4 TCYCLE<2:0>: Defines the delay (tCYCLE) after the Error state is entered before the Auto-recovery fault handling algorithm is started as shown below. 000 = 15 ms 001 = 20 ms 010 = 25 ms 011 = 30 ms 100 = 35 ms 101 = 40 ms 110 = 45 ms 111 = 50 ms bit 3-2 TTST<1:0>: Retry Duration timer - Sets the tTST as shown below. 00 = 10 ms 01 = 15 ms 10 = 20 ms 11 = 25 ms bit 1-0 VTST_SW: Short-circuit Voltage Threshold VTEST voltage threshold that must be crossed during retries to declare the short removed. 00 = 250 mV 01 = 500 mV 10 = 750 mV 11 = 1000 mV 2015 Microchip Technology Inc. DS20005424B-page 49 UCS2112 9.6 Total Accumulated Charge Registers The Total Accumulated Charge registers store the total accumulated charge delivered from the VS source to a portable device. The bit weighting of the registers is given in mA-hrs. The register value is reset to 00_00h only when the RATION_RST bit is set or if the RATION_EN bit is cleared. This value will be retained when the device transitions out of the Active state and resumes accumulation if the device returns to the Active state and charge rationing is still enabled. These registers are updated every one (1) second while the UCS2112 is in the Active power state. Every time the value is updated, it is compared against the target value in the Charge Rationing Threshold registers. This data is retained in the Sleep state. REGISTER 9-12: R-0 R-0 PORT1 TOTAL ACCUMULATED CHARGE REGISTERS (ADDRESS 16H, 17H, 18H, 19H) R-0 R-0 R-0 R-0 R-0 R-0 TAC1<25:18> bit 31 bit 24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TAC1<17:10> bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TAC1<9:2> bit 15 bit 8 R-0 R-0 TAC1<1:0> U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-6 TAC1<25:0>: Total Accumulated Charge Port 1 - Each LSB of this 26-bit value equals 0.00367 mAh. bit 5-0 Unimplemented: Read as ‘0’' DS20005424B-page 50 2015 Microchip Technology Inc. UCS2112 REGISTER 9-13: R-0 PORT2 TOTAL ACCUMULATED CHARGE REGISTERS (ADDRESS 1AH,1BH,1CH,1DH) R-0 R-0 R-0 R-0 R-0 R-0 R-0 TAC2<25:18> bit 31 bit 24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TAC2<17:10> bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TAC2<9:2> bit 15 bit 8 R-0 R-0 TAC2<1:0> U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-6 TAC2<25:0>: Total Accumulated Charge Port 2 - Each LSB of this 26-bit value equals 0.00367 mAh. bit 5-0 Unimplemented: Read as ‘0’' 2015 Microchip Technology Inc. DS20005424B-page 51 UCS2112 9.7 Charge Rationing Threshold Registers The Charge Rationing Threshold registers set the maximum allowed charge that will be delivered to a portable device. Every time the Total Accumulated Charge registers are updated, the value is checked against this limit. If the value meets or exceeds this limit, the RATION(1/2) bit is set and action taken according to the RATION_BEH1<1:0> and RATION_BEH2<1:0> bits. REGISTER 9-14: R/W-1 PORT 1 CHARGE RATIONING THRESHOLD REGISTERS (ADDRESS 1EH,1FH) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CT1<15:8> bit 15 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CT1<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 CT1<15:0>: Charge Rationing Threshold Port 1 - Each LSB of this 16-bit value equals 3.76 mAh. REGISTER 9-15: R/W-1 x = Bit is unknown PORT 2 CHARGE RATIONING THRESHOLD REGISTERS (ADDRESS 20H, 21H) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CT2<15:8> bit 15 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CT2<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown CT2: Charge Rationing Threshold Port 2 - Each LSB of this 16-bit value equals 3.76 mAh. DS20005424B-page 52 2015 Microchip Technology Inc. UCS2112 REGISTER 9-16: RATION CONFIGURATION REGISTER (ADDRESS 22H) R/W-0 R/W-0 RTN_EN2 RTN_RST2 R/W-0 R/W-1 RTN_BEH2<1:0> R/W-0 R/W-0 RTN_EN1 RTN_RST1 R/W-0 R/W-1 RTN_BEH1<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RTN_EN2: Charge Ration Enable Port 2 - Enables Charge Rationing for Port 2. 1 = Charge Rationing enabled 0 = Charge Rationing disabled. The Total Accumulated Charge registers for port 2 will be cleared to 00_00h and current data will no longer be accumulated. If the Total Accumulated Charge registers have already reached the Charge Rationing Threshold, the applied response will be removed as if the charge rationing had been reset. This will also clear the RATION2 status bit (if set). bit 6 RTN_RST2: Port 2 Ration Reset - Resets the charge rationing functionality for port 2. 1 = Total Accumulated Charge registers are reset to 00_00h. In addition, when this bit is set, the RATION2 status bit will be cleared and, if there are no other errors or active indicators, the ALERT#2 pin will be released. 0 = Normal operation. This bit must be cleared to enable charge rationing. bit 5-4 RTN_BEH2<1:0>: Ration Behavior Control bits - Controls how the UCS2112 responds when the Ration Threshold has been exceeded (as shown in Table 7-2). 00 = Report 01 = Report and Disconnect 10 = Disconnect and SLEEP 11 = Ignore bit 3 RTN_EN1: Charge Ration Enable Port 1 - Enables Charge Rationing for Port 1. 1 = Charge Rationing enabled 0 = Charge Rationing disabled. The Total Accumulated Charge registers for port 1 will be cleared to 00_00h and current data will no longer be accumulated. If the Total Accumulated Charge registers have already reached the Charge Rationing Threshold, the applied response will be removed as if the charge rationing had been reset. This will also clear the RATION1 status bit (if set). bit 2 RTN_RST1: Port 1 Ration Reset - Resets the charge rationing functionality for port 1. 1 = Total Accumulated Charge registers are reset to 00_00h. In addition, when this bit is set, the RATION1 status bit will be cleared and, if there are no other errors or active indicators, the ALERT#1 pin will be released. 0 = Normal operation. This bit must be cleared to enable charge rationing. bit 1-0 RTN_BEH1<1:0>: Ration Behavior Control bits - Controls how the UCS2112 responds when the Ration Threshold has been exceeded (as shown in Table 7-2). 00 = Report 01 = Report and Disconnect 10 = Disconnect and SLEEP 11 = Ignore 2015 Microchip Technology Inc. DS20005424B-page 53 UCS2112 9.8 Current Limit Behavior Registers The Current Limit Behavior register stores the values used by the applied current limiting mode (trip or CC). The contents of this register are not retained in Sleep. REGISTER 9-17: R/W-1 PORT 1 CURRENT LIMIT BEHAVIOR REGISTER (ADDRESS 23H) R/W-0 U-0 SEL_VBUS1_MIN<1:0> R/W-1 — R/W-0 R/W-1 SEL_R2_IMIN1<2:0> R/W-1 R/W-0 Reserved Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 SEL_VBUS1_MIN<1:0>: Define the VBUS_MIN voltage for port 1 as follows: 00 = 1.50V 01 =1.75V 10 =2.0V 11 =2.25V bit 5 Unimplemented bit 4-2 SEL_R2_IMIN1<2:0>: Defines the IBUS_R2MIN current. 000 =100 mA 001 =530 mA 010 =960 mA 011 =1280 mA 100 =1600 mA 101 =2130 mA bit 1-0 Reserved: Do not change. REGISTER 9-18: R/W-1 PORT 2 CURRENT LIMIT BEHAVIOR REGISTER (ADDRESS 24H) R/W-0 U-0 SEL_VBUS2_MIN<1:0> — R/W-1 R/W-0 R/W-1 SEL_R2_IMIN2_MIN<2:0> R/W-1 R/W-0 Reserved Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 SEL_VBUS2_MIN<1:0>: Define the VBUS_MIN voltage for port 2 as follows: 00 = 1.50V 01 =1.75V 10 =2.0V 11 =2.25V bit 5 Unimplemented bit 4-2 SEL_R2_IMIN2_MIN<2:0>: Defines the IBUS_R2MIN current. 000 =100 mA 001 =530 mA 010 =960 mA 011 =1280 mA 100 =1600 mA 101 =2130 mA bit 1-0 Reserved: Do not change. DS20005424B-page 54 2015 Microchip Technology Inc. UCS2112 9.9 Product ID Register The Product ID register stores a unique 8-bit value that identifies the UCS device family. REGISTER 9-19: R-1 PRODUCT ID REGISTER (ADDRESS FDH) R-1 R-1 R-0 R-0 R-0 R-0 R-1 PID<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 9.10 x = Bit is unknown PID<7:0>: Product ID for the UCS2112. Manufacture ID Register The Manufacturer ID register stores a unique 8-bit value that identifies Microchip Technology Inc. REGISTER 9-20: R-0 MANUFACTURER ID REGISTER (ADDRESS FEH) R-1 R-0 R-1 R-1 R-1 R-0 R-1 MID<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 9.11 x = Bit is unknown MID<7:0>: Manufacturer ID for Microchip. Revision Register The Revision register stores an 8-bit value that represents the part revision. REGISTER 9-21: R-1 REVISION REGISTER (ADDRESS FFH) R-0 R-0 R-0 R-0 R-0 R-0 R-1 REV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown REV<7:0>: Part Revision. 2015 Microchip Technology Inc. DS20005424B-page 55 UCS2112 NOTES: DS20005424B-page 56 2015 Microchip Technology Inc. UCS2112 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 4x4 mm QFN, 20-lead PIN 1 Example PIN 1 UCS e3 2112-1 446256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2015 Microchip Technology Inc. DS20005424B-page 57 UCS2112 DS20005424B-page 58 2015 Microchip Technology Inc. Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging UCS2112 APPENDIX A: REVISION HISTORY Revision B (October 2015) • Updated Features to indicate EN/IEC 60950-1 (CB) certification. Revision A (August 2015) • Original release of this document. 2015 Microchip Technology Inc. DS20005424B-page 59 UCS2112 NOTES: DS20005424B-page 60 2015 Microchip Technology Inc. UCS2112 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [T ](1) Device Tape and Reel –X –X /XX Version Temperature Range Package Device: UCS2112: Version 1 = SMBus address 57h Temperature Range: V = -40°C to +105°C (Various) Package: G4 = Plastic Quad Flat No Lead Package - 4x4 mm Body with 0.40 mm Contact Length, Saw Singulated, QFN, 20-lead 2015 Microchip Technology Inc. Examples: a) UCS2112-1-V/G4: Various Temperature, 20-pin 4x4 QFN package. b) UCS2112T-1-V/G4: Tape and Reel, Various Temperature, 20-pin 4x4 QFN Package. USB Dual-Port Power Switch and Current Monitor Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS20005424B-page 61 UCS2112 NOTES: DS20005424B-page 62 2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-902-1 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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