Data Sheet

TJA1100
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Rev. 2 — 26 April 2016
Product data sheet
1. General description
The TJA1100 is an OPEN Alliance BroadR-Reach compliant Ethernet PHY optimized for
automotive use cases. The device provides 100 Mbit/s transmit and receive capability
over a single Unshielded Twisted Pair (UTP) cable, supporting a cable length of up to at
least 15 m. Optimized for automotive use cases such as IP camera links, driver
assistance systems and back-bone networks, the TJA1100 has been designed to
minimize power consumption and system costs, while still providing the robustness
required for automotive use cases.
2. Features and benefits
2.1 Optimized for automotive use cases















Transmitter optimized for capacitive coupling to unshielded twisted-pair cable
Enhanced integrated PAM-3 pulse shaping for low RF emissions
Adaptive receive equalizer optimized for automotive cable length of up to at least 15 m
Reduced power consumption through configurable transmitter pulse amplitude
adapted to cable length
Dedicated PHY enable/disable input pin to minimize power consumption
Low-power Sleep mode with local wake-up support
Robust remote wake-up via the bus lines
Gap-free supply undervoltage detection with fail-silent behavior
EMC-optimized output driver strength for Media Independent Interface (MII) and
Reduced MII (RMII)
Diagnosis of cabling errors (shorts and opens)
Small HVQFN-36 package for PCB space-constrained applications
MDI pins protected against ESD to 6kV HBM and 6kV IEC61000-4-2
MDI pins protected against transients in automotive environment
Automotive-grade temperature range from 40 C to +125 C
Automotive product qualification in accordance with AEC-Q100
2.2 Miscellaneous






MII as well as RMII standard compliant interface
Reverse MII mode for back-to-back connection of two PHYs
3V3 single supply operation with on-chip 1.8 V LDO regulators
On-chip termination resistors for balanced UTP cable
Jumbo frame support up to 16 kB
Internal, external and remote loopback mode for diagnosis
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
 Bus pins short-circuit proof to battery voltage and ground (including common mode
choke, 100 nF coupling capacitors)
 LED control output for link diagnosis
3. Ordering information
Table 1.
Ordering information
Type number
Package
TJA1100
HVQFN36 plastic thermal enhanced very thin quad flat package; no leads; 36 terminals; SOT1092-2
body 6  6  0.85 mm
Name
TJA1100
Product data sheet
Description
Version
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
4. Block diagram
A block diagram of the TJA1100 is shown in Figure 1. The BroadR-Reach section
contains the functional blocks specified in the BroadR-Reach standard that make up the
Physical Coding Sublayer (PCS) and the Physical Medium Attachment (PMA) layer for
both the transmit and receive signal paths. The MII/RMII interface (including the Serial
Management Interface (SMI)) conforms to IEEE802.3 clause 22.
Additional blocks are defined for mode control, register configuration, interrupt control,
system configuration, reset control, LED control, local wake-up and configuration control.
A number of power supply related functional blocks are defined: Very Low Power (VLP)
supply in Sleep mode, Reset circuit, supply monitoring and a 1.8 V regulator for the digital
core. Pin strapping allows a number of default PHY settings (e.g. Master or Slave
configuration) to be hardware-configured at power-up.
The clock signals needed for the operation of the PHY are generated in the PLL block,
derived from an external crystal or an oscillator input signal.
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Block diagram
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
5. Pinning information
5.1 Pinning
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TJA1100
Product data sheet
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The pin configuration of the TJA1100 is shown in Figure 2. The following standard
interfaces are provided by the TJA1100: MII/RMII (including SMI) and MDI. Since
BroadR-Reach allows for full-duplex bidirectional communication, the standard MII signals
COL and CRS are not needed.
DDD
Pin configuration
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Rev. 2 — 26 April 2016
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
5.2 Pin description
Table 2.
Pin Type[1] Description
MDC
1
I
SMI clock input (weak pull-down)
INT_N
2
O
interrupt output (active-LOW, open-drain output)
RST_N
3
I
reset input (active-LOW)
VDDA(1V8)
4
P
1.8 V analog supply voltage (internally generated)
XO
5
AO
crystal feedback - used in MII/RMII mode with 25 MHz crystal
XI
6
AI
crystal input - used in MII/RMII mode with 25 MHz crystal
VDDA(3V3)
7
P
3.3 V analog supply voltage
LED
8
AO
LED open-drain output (when enabled: LED_ENABLE = 1)
WAKE
8
AI
local WAKE input (when LED output disabled: LED_ENABLE = 0)
VBAT
9
P
battery supply voltage
INH
10
AO
inhibit output for voltage regulator control (VBAT-related, active-HIGH)
VDDA(TX)
11
P
3.3 V analog supply voltage for the transmitter
TRX_P
12
AIO
+ terminal for transmit/receive signal
TRX_M
13
AIO
 terminal for transmit/receive signal
VDDD(3V3)
14
P
3.3 V digital supply voltage
GND[2]
15
G
ground reference
VDDD(1V8)
16
P
1.8 V digital supply voltage (internally generated)
RXER
17
O
MII/RMII receive error output
CONFIG3
17
I
pin strapping configuration input 3
RXDV
18
O
MII/RMII receive data valid output
CONFIG2
18
I
pin strapping configuration input 2
CRSDV
18
O
RMII mode: carrier sense/receive data valid output
VDD(IO)
19
P
3.3 V I/O supply voltage
GND[2]
20
G
ground reference
RXD3
21
O
MII mode: receive data output, bit 3 of RXD[3:0] nibble
CONFIG1
21
I
pin strapping configuration input 1
RXD2
22
O
MII mode: receive data output, bit 2 of RXD[3:0] nibble
CONFIG0
22
I
pin strapping configuration input 0
RXD1
23
O
MII mode: receive data output, bit 1 of RXD[3:0] nibble
RMII mode: receive data output, bit 1 of RXD[1:0] nibble
PHYAD1
23
I
pin strapping configuration input for bit 1 of the PHY address used for
the SMI address/Cipher scrambler
RXD0
24
O
MII mode: receive data output, bit 0 of RXD[3:0] nibble
RMII mode: receive data output, bit 0 of RXD[1:0] nibble
PHYAD0
24
I
pin strapping configuration input for bit 0 of the PHY address used for
the SMI address/Cipher scrambler
RXC
25
O
MII mode: 25 MHz receive clock output
I
MII reverse mode: 25 MHz receive clock input
I
RMII mode: 50 MHz oscillator clock input
O
RMII mode: 50 MHz interface reference clock
REF_CLK
TJA1100
Product data sheet
Pin description
Symbol
25
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Rev. 2 — 26 April 2016
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 2.
TJA1100
Product data sheet
Pin description …continued
Symbol
Pin Type[1] Description
GND[2]
26
G
ground reference
VDD(IO)
27
P
3.3 V I/O supply voltage
TXC
28
IO
MII mode: 25 MHz transmit clock output
MII reverse mode: 25 MHz transmit clock input
TXEN
29
I
MII/RMII mode: transmit enable input (active-HIGH, weak pull-down)
TXD3
30
I
MII mode: transmit data input, bit 3 of TXD[3:0] nibble
TXD2
31
I
MII mode: transmit data input, bit 2 of TXD[3:0] nibble
TXD1
32
I
MII mode: transmit data input, bit 1 of TXD[3:0] nibble
RMII mode: transmit data input, bit 1 of TXD[1:0] nibble
TXD0
33
I
MII mode: transmit data input, bit 0 of TXD[3:0] nibble
RMII mode: transmit data input, bit 0 of TXD[1:0] nibble
TXER
34
I
MII/RMII: transmit error input (weak pull-down)
EN
35
I
PHY enable input (active-HIGH)
MDIO
36
IO
SMI data I/O (weak pull-up)
[1]
AIO: analog input/output; AO: analog output; AI: analog input; I: digital input (VDD(IO) related);
O: digital output (VDD(IO) related); IO: digital input/output (VDD(IO) related); P: power supply; G: ground.
[2]
The HVQFN36 package die supply ground is connected to the GND pins and the exposed center pad. The
GND pins must be soldered to board ground. For enhanced thermal and electrical performance, it is
recommended to connect the exposed center pad to board ground as well.
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Rev. 2 — 26 April 2016
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
6. Functional description
6.1 System configuration
As an OPEN Alliance BroadR-Reach compliant Ethernet PHY, the TJA1100 provides
100 Mbit/s transmit and receive capability over a single unshielded twisted-pair cable,
supporting a cable length of up to at least 15 m with a bit error rate less than or equal to
1E10. It is optimized for capacitive signal coupling to the twisted-pair lines. To comply
with automotive EMC requirements, a common-mode choke (CMC) is typically inserted
into the signal path.
The TJA1100 is designed to provide a cost-optimized system solution for automotive
Ethernet links. Communication with the Media Access Control (MAC) unit can be realized
via the MII or the RMII.
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A system diagram showing capacitive coupling
6.2 MII and RMII
The TJA1100 contains MII and RMII interfaces to the MAC controller.
6.2.1 MII
6.2.1.1
Signaling and encoding
The connections between the PHY and the MAC are shown in more detail in Figure 4.
Data is exchanged via 4-bit wide data nibbles on TXD[3:0] and RXD[3:0]. Transmit and
receive data is synchronized with the transmit (TXC) and receive (RXC) clocks. Both clock
signals are provided by the PHY and are typically derived from an external crystal running
at a nominal frequency of 25 MHz (100 ppm). Normal data transmission is initiated with a
HIGH level on TXEN, while a HIGH level on RXDV indicates normal data reception.
MII encoding is described in Table 3 and Table 4.
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
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Table 3.
MII signaling
MII encoding of TXD[3:0], TXEN and TXER
TXEN
TXER
TXD[3:0]
Indication
0
0
0000 through 1111
normal interframe
0
1
0000 through 1111
reserved
1
0
0000 through 1111
normal data transmission
1
1
0000 through 1111
transmit error propagation
Table 4.
MII encoding of RXD[3:0], RXDV and RXER
RXDV
RXER
RXD[3:0]
Indication
0
0
0000 through 1111
normal interframe
0
1
0000
normal interframe
0
1
0001 through 1101
reserved
0
1
1110
false carrier indication
0
1
1111
reserved
1
0
0000 through 1111
normal data transmission
1
1
0000 through 1111
data reception with errors
Since BroadR-Reach provides full-duplex communication, the standard signals COL and
CRS are not needed.
6.2.2 RMII
6.2.2.1
Signaling and encoding
In the case of RMII, data is exchanged via 2-bit wide data nibbles on TXD[1:0] and
RXD[1:0], as illustrated in Figure 5. To achieve the same data rate as MII, the interface is
clocked at a nominal frequency of 50 MHz. A single clock signal, REF_CLK, is provided
for both transmit and received data. This clock signal is provided by the PHY and is
typically derived from an external 25 MHz (100 ppm) crystal (see Figure 5). Alternatively,
a 50 MHz clock signal (50 ppm) generated by an external oscillator can be connected to
pin REFCLK_IN (see Figure 6).
RMII encoding is described in Table 5 and Table 6.
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
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RMII signaling using an external crystal
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Table 5.
Product data sheet
RMII signaling using an externally generated reference clock
RMII encoding of TXD[1:0], TXEN
TXEN
TXD[1:0]
Indication
0
00 through 11
normal interframe
1
00 through 11
normal data transmission
Table 6.
TJA1100
DDD
RMII encoding of RXD[1:0], CRSDV and RXER
CRSDV
RXER
RXD[1:0]
Indication
0
0
00 through 11
normal interframe
0
1
00
normal interframe
0
1
01 through 11
reserved
1
0
00 through 11
normal data transmission
1
1
00 through 11
data reception with errors
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Rev. 2 — 26 April 2016
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
6.2.3 Reverse MII
In Reverse MII mode, two PHYs are connected back-to-back via the MII interface to
realize a repeater function on the physical layer (see Figure 7). The MII signals are
cross-connected: RX output signals from each PHY are connected to the TX inputs on the
other PHY. For the PHY connected in Reverse MII mode, the TXC and RXC clock signals
become inputs.
Since the MII interface is a standardized solution, two PHYs can be used to implement
two different physical layers to realize, for example, a conversion from Fast Ethernet to
BroadR-Reach and vice versa. Another use case for such a repeater could be to double
the link length up to 30 m.
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Fig 7.
Fast Ethernet to BroadR-Reach media converter with TJA1100 Reverse MII
6.3 System controller
6.3.1 Operating modes
6.3.1.1
Power-off mode
TJA1100 remains in Power-off mode as long as the voltage on pin VBAT is below the
power-on reset threshold. The analog blocks are disabled and the digital blocks are in a
passive reset state in this mode.
6.3.1.2
Standby mode
At power-on, when the voltage on pin VBAT rises above the under-voltage recovery
threshold (Vuvr(VBAT)), the TJA1100 enters Standby mode, switching on the INH control
output. This control signal may be used to activate the supply to the microcontroller in the
ECU. Once the 3.3 V supply voltage is available, the internal 1.8 V regulators are
activated and the PHY is configured according to the pin-strapping implemented on the
CONFIGn and PHYADn pins. No SMI access takes place during the power-on settling
time (ts(pon)).
From an operating point of view, Standby mode corresponds to the IEEE 802.3
Power-down mode, where the transmit and receive functions (in the PHY) are disabled.
Standby mode also acts as a fail-silent mode. The TJA1100 switches to Standby mode
when an under-voltage condition is detected on VDDA(3V3), VDDA(1V8), VDDD(1V8) or VDD(IO).
TJA1100
Product data sheet
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
6.3.1.3
Normal mode
To establish a communication link, the TJA1100 must be switched to Normal mode, either
autonomously (AUTO_OP = 1; see Table 18) or via an SMI command (AUTO_OP = 0).
When the PHY is configured for autonomous operation, the TJA1100 will automatically
enter Normal mode and activate the link on power-on.
When the PHY is host-controlled, the internal PLL starts running when the TJA1100
enters Normal mode and the transmit and receive functions (both PCS and PMA) are
enabled. After a period of stabilization, tinit(PHY), the TJA1100 is ready to set up a link.
Once the LINK_CONTROL bit is set to 'ENABLE', the PHY configured as Master initiates
the training sequence by transmitting idle pulses. The link is established when bit
LINK_UP in the Communication Status register is set.
6.3.1.4
Disable mode
Whenever the Ethernet interface is not in use or must be disabled for fail-safe reasons,
the PHY can be switched off by pulling pin EN LOW. The PHY is switched off completely
in Disable mode, minimizing power consumption. The configuration register settings are
maintained. To exit Disable mode, pin EN must be forced HIGH to activate the PHY.
6.3.1.5
Sleep mode
If the network management in a node decides to withdraw from the network because the
functions of the node are no longer needed, it may power down the entire ECU via PHY
Sleep mode. In Sleep mode, the transmit and receive functions are switched off and no
signal is driven onto the twisted-pair lines. Transmit requests from the MII interface are
ignored and the MII output pins are in a high-ohmic state. The SMI is also deactivated to
minimize power consumption.
By releasing the INH output, the ECU is allowed to switch off its main power supply unit.
Typically, the entire ECU is powered-down. The TJA1100 is kept partly alive by the
permanent battery supply and can still react to activity on the Ethernet lines. Once valid
Ethernet idle pulses are detected on the lines, the TJA1100 wakes up, switching on the
main power unit via the INH control signal. As soon as the supply voltages are stable
within their operating ranges, the TJA1100 can be switched to Normal mode via an SMI
command and the communication link to the partner can be re-established. Sleep mode
can be entered from Normal mode via the intermediate Sleep Request mode as well as
from Standby mode, as shown in Figure 8. Note that the configuration register settings are
maintained in Sleep mode.
6.3.1.6
Sleep Request mode
Sleep Request mode is an intermediate state used to introduce a transition to Sleep
mode. In Sleep Request mode, the PHY transmits reserved Sleep code-groups (also
called LPS code-groups) to inform the link partner about the request to enter Sleep mode.
The LPS code-groups are separated by 32 idle symbols. An LPS code-group consists of
the vector sequence (0,0), (0,0), (1,1), (1,1). The PHY sleep request timer starts when
the TJA1100 enters Sleep Request mode. This timer determines how long the PHY
remains in Sleep Request mode. When the timer expires (after tto(req)sleep), the PHY
switches to Sleep mode and INH is switched off. The PHY does not expect to receive
Ethernet frames in Sleep Request mode. If any Ethernet frames are received at MDI or
MII in Sleep Request mode, the PHY returns to Normal mode, the DATA_DET_WU flag in
the General status register is set and a WAKEUP interrupt is generated.
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 7 presents an overview of the status of TJA1100 functional blocks in each operating
mode.
Table 7.
Status of functional blocks in TJA1100 operating modes
Functional block
MII
6.3.1.7
Normal
Standby[1]
Sleep Request Sleep
Disable
on
high-ohmic[2]
on
high-ohmic
high-ohmic
PMA/PCS-TX
on
off
on
off
off
PMA/PCS-RX
on
off
on
off
off
SMI
on
on
on
off
off
Activity detection
off
on
off
on
off
Crystal oscillator
on
off
on
off
off
LDO_1V8
on
on
on
off
off
RST_N input
on
on
on
off
on
EN input
on
on
on
off
on
on/off[3]
on/off[3]
off
WAKE input
off
on/off[3]
INT_N output
on
on
on
high-ohmic
high-ohmic
LED output
on/off[3]
off
on/off[3]
off
off
INH output
on
on
on
off
on/off[4]
Temp detection
on
on
on
off
off
[1]
Outputs RXD[3:0], RXER and RXDV are LOW in Standby mode; the other MII pins are configured as inputs
via internal 100 k pull-down resistors.
[2]
Pins configured as outputs will be LOW in Standby mode.
[3]
The WAKE input is active in Standby, Sleep Request and Sleep modes if LED_ENABLE = 0; the LED
output is active in Normal and Sleep Request modes if LED_ENABLE = 1.
[4]
The behavior of the INH output in Disable mode is configurable.
Reset mode
The TJA1100 switches to Reset mode from any mode except Power-off when pin RST_N
is held LOW for at least the maximum reset detection time (tdet(rst)(max)), provided the
voltage on VDD(IO) is above the undervoltage threshold.
When RST_N goes HIGH again, or an undervoltage is detected on VDD(IO), the TJA1100,
switches to Standby mode. All register bits are reset to their default values in Reset mode.
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
6.3.2 Transitions between operating modes
One of the key features of the TJA1100 is the possibility to put a link and its associated
nodes into Sleep mode, while ensuring that the node can be woken up by activity on the
Ethernet wires. A node can be switched to Sleep mode when link operation is not needed,
minimizing power consumption. Configuration bits LPS_ACTIVE and SLEEP_CONFIRM
determine when a link can be switched to Sleep mode.
Figure 8 shows the TJA1100 mode transition diagram with LPS_ACTIVE = FALSE, while
Figure 9 illustrates mode transitions with LPS_ACTIVE = TRUE. For a detailed
description of the Sleep transition process, see the TJA1100 Application Hints [Ref. 2].
The following events, listed in order of priority, trigger mode transitions:
•
•
•
•
•
•
TJA1100
Product data sheet
Power on/off
Undervoltage on VDD(IO) or VDDD(1V8)
RST_N input
EN input
Overtemperature or Undervoltage on VDDA(3V3), VDDA(1V8) or VDDD(1V8)
SMI command and wake-up (local or remote)
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© NXP Semiconductors N.V. 2016. All rights reserved.
13 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
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** INH can be configured to be on or off
Fig 8.
Operating mode transitions with LPS_ACTIVE = FALSE
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
14 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
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** INH can be configured to be on or off
Fig 9.
Operating mode transitions with LPS_ACTIVE = TRUE
6.4 Wake-up request
A link that is in Sleep mode must be woken up before the link can be re-established. The
node requesting the link can issue a wake request by sending idle symbols onto the link.
The link partner detects the idle activity and wakes up.
TJA1100
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TJA1100
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
A link wake-up request is issued by setting bit WAKE_REQUEST in the Extended Control
register to 1 while the TJA1100 is in Normal mode with link control disabled
(LINK_CONTROL = 0). The wake request phase lasts at least 5 ms to ensure a reliable
wake-up. The TJA1100 aborts the wake request and stops sending idle symbols if bit
WAKE_REQUEST is reset or link control is enabled.
To support a global wake-up scheme, it must be possible to propagate a wake-up request
throughout the network, even if a link is already active. If the link is already active (bit
LINK_UP = 1) when WAKE_REQUEST is set, dedicated wake-up request (WUR)
code-groups are sent during the interframe gap following each frame transmission. A
WUR code-group consists of the vector sequence (0,0),(0,0),(-1,1),(-1,1). Decoding of
WUR code-groups at the link partner triggers a WUR_RECEIVED interrupt (if enabled).
6.5 Wake-up
When the TJA1100 detects a wake-up event, a WAKEUP interrupt is generated and the
wake-up source is indicated in the General status register (status bits LOCAL_WU,
REMOTE_WU and DATA_DET_WU; see Table 24). The wake-up source status bits are
reset when the TJA1100 enters Sleep Request or Sleep mode. The TJA1100
distinguishes three wake-up sources:
6.5.1 Remote wake-up
In Standby and Sleep modes, any Ethernet activity on the MDI (idle pulses or Ethernet
frames) triggers a remote wake-up.
6.5.2 Local wake-up
In Standby, Sleep Request and Sleep modes, a falling edge on pin WAKE (provided
configuration bit LED_ENABLE = 0) triggers a local wake-up.
6.5.3 Wake-up by data detection
In Sleep Request mode, any Ethernet frame detected at the MDI or MII triggers wake-up
by data detection.
6.6 Autonomous operation
If the PHY is configured for autonomous operation (either via pin strapping, see
Section 6.11, or via bit AUTO_OP in Configuration register 1, see Table 18), the TJA1100
can operate and establish a link without further interaction with a host controller. On
power-on or wake-up from Sleep mode, the TJA1100 goes directly to Normal mode once
all supply voltages are available and the link-up process starts automatically. AUTO_OP
must be reset when link or mode control are configured by the Host.
6.7 Autonomous power-down
If autonomous power-down is enabled via Configuration register 1 (AUTO_PWD = 1), the
TJA1100 goes to Sleep Request mode automatically if no Ethernet frames have been
received at the MDI and MII for the time-out time, tto(pd)autn.
TJA1100
Product data sheet
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TJA1100
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
6.8 Transmitter amplitude
Power can be saved by adapting the amplitude of the transmitter output to the specific
needs of a link. For example, a short link of up to 2 m does not need to operate on the
same transmitter amplitude as a link of 15 m to achieve the same signal-to-noise ratio.
The nominal transmitter output amplitude can be selected via bit TX_AMPLITUDE (see
Table 18). The default value of 1000 mV can support a link of up to 15 m, while the lower
values of 500 mV and 750 mV may be sufficient for shorter links of up to 2 m. The
compliance, interoperability and EMC tests are performed at the default amplitude.
6.9 Test modes
Five test modes are supported, in accordance with the BroadR-Reach specification
(Ref. 1). The test modes can be individually selected via an SMI command in Normal
mode while link control is disabled. The EN pin is used as a clock output in test modes
that need a reference clock. The normal EN function is disabled in test modes.
6.9.1 Test mode 1
Test mode 1 is for testing the transmitter droop. In Test mode 1, the PHY transmits ‘+1’
symbols for 600 ns followed by ‘1’ symbols for a further 600 ns. This sequence is
repeated continuously.
6.9.2 Test mode 2
Test mode 2 is for testing the transmitter timing jitter in Master configuration. In test
mode 2, the PHY transmits the data symbol sequence {+1, -1} repeatedly. The
transmission of the symbols is synchronized with the local external oscillator.
6.9.3 Test mode 3
Test mode 3 is for testing the transmitter timing jitter in Slave configuration. In test mode 3,
the PHY transmits the data symbol sequence {+1, -1} repeatedly. The transmission of the
symbols is synchronized with the recovered receiver clock.
6.9.4 Test mode 4
Test mode 4 is for testing the transmitter distortion. In test mode 4, the PHY transmits the
sequence of symbols generated by the scrambler polynomial gs1 = 1 + x9 + x11.
The bit sequence x0n, x1n is derived from the scrambler according to the following
equations:
x0n = Scrn  0 
x1n = Scrn  1  XOR Scrn  4 
This stream of 3-bit nibbles is mapped to a stream of ternary symbols according to
Table 8.
Table 8.
TJA1100
Product data sheet
Symbol mapping in test mode 4
x1n
x0n
PAM-3 transmit symbol
0
0
0
0
1
+1
1
0
0
1
1
1
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
6.9.5 Test mode 5
Test mode 5 is for testing the transmit PSD mask. In test mode 5, the PHY transmits a
random sequence of PAM-3 symbols.
6.10 Error diagnosis
6.10.1 Undervoltage detection
Like state-of-the-art CAN and FlexRay transceivers, the TJA1100 monitors the status of
the supply voltages continuously. Once a supply voltage drops below the specified
minimum operating voltage, the TJA1100 enters the fail-silent Standby mode and
communication is halted. A UV_ERR interrupt is generated and the source of the
undervoltage (VDDA(1V8), VDDD(1V8) or VDDA(3V3)) is indicated in the External status register
(Table 25). The under-voltage detection/recovery range is positioned immediately next to
the operating range, without a gap. Since parameters are specified down to the min. value
of the under-voltage detection threshold, it is guaranteed that the behavior of the TJA1100
is fully specified and defined for all possible voltage condition on the supply pins.
6.10.2 Cabling errors
The TJA1100 is able to detect open and short circuits in the twisted-pair bus lines. It may
make sense to run the diagnostic before establishing the Ethernet link. When bit
CABLE_TEST in the Extended Control register (Table 17) is set to 1, test pulses are
transmitted onto the transmission medium with a repetition rate of 666.6 kHz. The
TJA1100 evaluates the reflected signals and uses impedance mismatch data along the
channel to determine the quality of the link. The results of the cable test are available in
the External status register (Table 25) within tto(cbl_tst).
This TDR-based measurement is limited to the detection of open and short circuits in and
between the cable wires. Shorts between a single wire and the battery voltage or ground
are not necessarily detected. However, they will lead to a significant reduction in the SNR.
The TJA1100 must be in Normal mode to trigger the cable test. Since with BroadR-Reach
the termination is always integrated into the PHY, a missing node at the other side of the
cable always leads to the detection of an open error.
6.10.3 Link stability
The signal-to-noise ratio is the parameter used to estimate link stability. The PMA Receive
function monitors the signal-to-noise ratio continuously. Once the signal-to-noise ratio falls
below a configurable threshold (SNR_FAILLIMIT), the link status is set to FAIL and
communication is interrupted. The TJA1100 allows for adjusting the sensitivity of the PMA
Receive function by configuring this threshold. The microcontroller can always check the
current value of the signal-to-noise ratio via the SMI, allowing it to track a possible
degradation in link stability.
6.10.4 Link-fail counter
High losses and/or a noisy channel may cause the link to shut down when reception is no
longer reliable. In such cases, a LINK_STATUS_FAIL interrupt is generated by the PHY.
Retraining of the link begins automatically provided link control is enabled
(LINK_CONTROL = 1).
TJA1100
Product data sheet
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TJA1100
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
LOC_RCVR_COUNTER and REM_RCVR_COUNTER in the Link-fail counter register
(Table 26) are incremented after every link fail event. Both counters are reset when this
register is read.
6.10.5 Jabber detection
The Jabber detection function prevents the PHY being locked in the DATA state of the
PCS Receive state diagram when the End-of-Stream Delimiters, ESD1 and ESD2, are not
detected. The maximum time the PHY can reside in the DATA state is limited to tto(PCS-RX)
(rcv_max_timer in the BroadR-Reach specification; Ref. 1). After this time, the PCS-RX
state machine is reset and a transition to PHY Idle state is triggered.
6.10.6 Interleave detection
An OPEN Alliance BroadR-Reach PHY can send two different interleave sequences of
ternary symbols, (TAn, TBn) or (TBn, TAn). The receiver in the TJA1100 is able to
de-interleave both sequences. The order of the ternary symbols detected by the receiver
is indicated by the INTERLEAVE_DETECT bit in the External status register (Table 25).
6.10.7 Loopback modes
In accordance with the BroadR-Reach specification (Ref. 1), the TJA1100 provides three
loopback modes: Internal, External and Remote loopback.
6.10.7.1
Internal loopback
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In Internal loopback mode, the PCS Receive function gets the ternary symbols An and Bn
directly from the PCS Transmit function as shown in Figure 10. This action allows the
MAC to compare packets sent through the MII transmit function with packets received
from the MII receive function and, therefore, to validate the functionality of the
BroadR-Reach PCS function.
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Fig 10. Internal loopback
TJA1100
Product data sheet
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TJA1100
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
6.10.7.2
External loopback
In external loopback mode, the PMA Receive function receives signals directly from the
PMA Transmit function as shown in Figure 11. The cable link must be removed for this
test. Removing the cable link allows the MAC to compare packets sent through the MII
transmit function with packets received from the MII receive function and, therefore, to
validate the functionality of the BroadR-Reach PCS and PMA functions.
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Fig 11. External loopback
6.10.7.3
Remote loopback
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In Remote loopback mode, the packet received by the link partner at the MDI is passed
through the PMA Receive and PCS Receive functions and forwarded to the PCS Transmit
functions, which in turn sends it back to the link partner from where it came. The PCS
receive data is made available at the MII. Remote loopback allows the MAC to compare
the packets sent to the MDI with the packets received back from the MDI and thus to
validate the functionality of the physical channel, including both BroadR-Reach PHYs. To
run the PHY in a loopback mode, the LOOPBACK control bit in the Basic control register
should be set before enabling link control.
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Fig 12. Remote loopback
TJA1100
Product data sheet
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
6.11 Auto-configuration of the PHY during power-up via pin strapping
The logic levels on inputs PHYAD0, PHYAD1 and CONFIG0 to CONFIG3 determine the
default configuration of the PHY at power-up or after a hardware reset. Pin strapping
occurs during the power-on settling time (ts(pon)), once all voltages (including 1V8) are
available.
Pin strapping at pins 23 (PHYAD1) and 24 (PHYAD0) determine bits 1 and 0, respectively,
of the PHY address used for the SMI address/Cipher scrambler. The PHY address cannot
be changed once the PHY has been configured. Besides the address configured via pin
strapping, the TJA1100 can always be accessed via address 0.
Table 9.
Hardware configuration via CONFIG0 to CONFIG3 pin strapping during power-up
Pin
CONFIG0 (pin 22)
CONFIG1 (pin 21)
CONFIG3/CONFIG2
(pin 17/pin 18)
Value
Description
HIGH
PHY configured as Master
LOW
PHY configured as Slave
HIGH
Autonomous operation
LOW
Managed operation
LOW LOW
Normal MII mode
LOW HIGH
RMII mode (external 50 MHz oscillator)
HIGH LOW
RMII mode (25 MHz crystal)
HIGH HIGH
Reverse MII mode
6.12 SMI registers
6.12.1 SMI register mapping
Table 10.
TJA1100
Product data sheet
SMI register mapping
Register index (dec)
Register name
Group
0
Basic control register
Basic
1
Basic status register
Basic
2
PHY identification register 1
Extended
3
PHY identification register 2
Extended
15
Extended status register
Extended
17
Extended control register
NXP specific
18
Configuration register 1
NXP specific
19
Configuration register 2
NXP specific
20
Symbol error counter register
NXP specific
21
Interrupt source register
NXP specific
22
Interrupt enable register
NXP specific
23
Communication status register
NXP specific
24
General status register
NXP specific
25
External status register
NXP specific
26
Link-fail counter register
NXP specific
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 11.
Table 12.
Register notation
Notation
Description
R/W
Read/write
R
Read only
LH
Latched HIGH
LL
Latched LOW
SC
Self-clearing
CR
Cleared on reset
Basic control register (Register 0)
Bit
Symbol
Access
Value
15
RESET
R/W
SC
0[1]
normal operation
1
PHY reset
14
LOOPBACK
software reset control:
R/W
loopback control:
0[1]
13
SPEED_SELECT (LSB)
R/W
12
AUTONEG_EN
R/W
SC
11
POWER_DOWN
R/W
10
ISOLATE
Description
normal operation
1
loopback mode
[2]
speed select (LSB):
0
10 Mbit/s if SPEED_SELECT (MSB) = 0
1000 Mbit/s if SPEED_SELECT (MSB) = 1
1[1]
100 Mbit/s if SPEED_SELECT (MSB) = 0
reserved if SPEED_SELECT (MSB) = 1
0[1]
Auto negotiation not supported; always 0; a write access is
ignored.
Standby power down enable:
0[1]
normal operation (clearing this bit automatically triggers a
transition to Normal mode; control bits POWER_MODE must
be set to 0011 to select Normal mode, see Table 17)
1
power down and switch to Standby mode (provided
ISOLATE = 0; ignored if ISOLATE = 1 and CONTROL_ERR
interrupt generated)
R/W
PHY isolation:
0[1]
normal operation
1
isolate PHY from MII/RMII (provided POWER_DOWN = 0;
ignored if POWER_DOWN = 1 and CONTROL_ERR interrupt
generated)
9
RE_AUTONEG
R/W
SC
0[1]
Auto negotiation not supported; always 0; a write access is
ignored.
8
DUPLEX_MODE
R/W
1[1]
only full duplex supported; always 1; a write access is ignored.
COL signal test not supported; always 0; a write access is
ignored.
speed select (MSB):
7
COLLISION_TEST
R/W
0[1]
6
SPEED_SELECT (MSB)
R/W
[2]
TJA1100
Product data sheet
0[1]
10 Mbit/s if SPEED_SELECT (LSB) = 0
100 Mbit/s if SPEED_SELECT (LSB) = 1
1
1000 Mbit/s if SPEED_SELECT (LSB) = 0
reserved if SPEED_SELECT (LSB) = 1
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 12.
Basic control register (Register 0) …continued
Bit
Symbol
Access
5
UNIDIRECT_EN
R/W
4:0
reserved
R/W
Value
Description
unidirectional enable when bit 12 = 0 and bit 8 = 1:
0[1]
enable transmit from MII only when the PHY has determined
that a valid link has been established
1
enable transmit from MII regardless of whether the PHY has
determined that a valid link has been established
00000[1]
write as 00000; ignore on read
[1]
Default value.
[2]
Speed Select: 00: 10 Mbit/s; 01: 100 Mbit/s; 10: 1000 Mbit/s; 11: reserved; a write access value other than 01 is ignored.
TJA1100
Product data sheet
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 13.
Bit
Basic status register (Register 1)
Symbol
Access
Value
Description
0[1]
PHY not able to perform 100BASE-T4
1
PHY able to perform 100BASE-T4
0[1]
PHY not able to perform 100BASE-X full duplex
1
PHY able to perform 100BASE-X full duplex
PHY not able to perform 100BASE-X half duplex
15
100BASE-T4
R
14
100BASE-X_FD
R
13
100BASE-X_HD
R
0[1]
1
PHY able to perform 100BASE-X half duplex
12
10Mbps_FD
R
0[1]
PHY not able to perform 10 Mbit/s full duplex
1
PHY able to perform 10 Mbit/s full duplex
0[1]
PHY not able to perform 10 Mbit/s half duplex
1
PHY able to perform 10 Mbit/s half duplex
0[1]
PHY not able to perform 100BASE-T2 full duplex
1
PHY able to perform 100BASE-T2 full duplex
0[1]
PHY not able to perform 100BASE-T2 half duplex
1
PHY able to perform 100BASE-T2 half duplex
0
no extended status information in register 15h
1[1]
extended status information in register 15h
0
PHY able to transmit from MII only when the PHY has
determined that a valid link has been established
1[1]
PHY able to transmit from MII regardless of whether the
PHY has determined that a valid link has been established
0
PHY will not accept management frames with preamble
suppressed
1[1]
PHY will accept management frames with preamble
suppressed
0
Autonegotiation process not completed
1[1]
Autonegotiation process completed
11
10Mbps_HD
R
10
100BASE-T2_FD
R
9
100BASE-T2_HD
R
8
EXTENDED_STATUS
R
7
UNIDIRECT_ ABILITY
6
MF_PREAMBLE_SUPPRESSION
5
AUTONEG_COMPLETE
4
REMOTE_FAULT
R
R
R
R
LH
0[1][2]
no remote fault condition detected
1
remote fault condition detected
0[1]
PHY not able to perform Autonegotiation
3
AUTONEG_ABILITY
R
1
PHY able to perform Autonegotiation
2
LINK_STATUS
R
LL
0[1][2]
link is down
1
link is up
no jabber condition detected
1
JABBER_DETECT
R
LH
0[1][2]
1
jabber condition detected
0
EXTENDED_CAPABILITY
R
0
basic register set capabilities only
1[1]
extended register capabilities
[1]
Default value.
[2]
Reset to default value when link control is disabled (LINK_CONTROL = 0).
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 14.
Bit
PHY identifier register 1 (Register 2)
Symbol
15:0
PHY_ID
Access
Value
Description
R
0180h[1]
bits 3 to 18 of the Organizationally Unique IDentifier (OUI)[2]
[1]
Default value.
[2]
OUI = 00.60.37h (note that bits 1 and 2 of OUI are always 0).
Table 15.
Bit
PHY identifier register 2 (Register 3)
Symbol
Access
Value
Description
bits 19 to 24 of the OUI[2]
15:10
PHY_ID
R
110111[1]
9:4
TYPE_NO
R
000100[1]
six-bit manufacturer’s type number
R
1000[1]
four-bit manufacturer’s revision number
3:0
REVISION_NO
[1]
Default value.
[2]
OUI = 00.60.37h (note that bits 1 and 2 of OUI are always 0).
Table 16.
Bit
Extended status register (Register 15)
Symbol
Access Value
15
1000BASE-X_FD
R
14
1000BASE-X_HD
R
13
1000BASE-T_FD
R
12
1000BASE-T_HD
R
Description
0[1]
PHY not able to perform 1000BASE-X full duplex
1
PHY able to perform 1000BASE-X full duplex
0[1]
PHY not able to perform 1000BASE-X half duplex
1
PHY able to perform 1000BASE-X half duplex
0[1]
PHY not able to perform 1000BASE-T full duplex
1
PHY able to perform 1000BASE-T full duplex
0[1]
PHY not able to perform 1000BASE-T half duplex
1
PHY able to perform 1000BASE-T half duplex
11:8 reserved
R
0000[1]
7
R
0
PHY not able to 1-pair BroadR-Reach 100 Mbit/s
1[1]
PHY able to 1-pair BroadR-Reach 100 Mbit/s
0[1]
PHY not able to RTPGE
1
PHY able to RTPGE
000000[1]
always 000000; ignore on read
100BASE-BroadR-REACH
6
1000BASE-RTPGE
5:0
[1]
reserved
R
R
Default value.
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Product data sheet
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 17.
Bit
15
14:11
10
9
Extended control register (Register 17)
Symbol
LINK_CONTROL
POWER_MODE
SLAVE_JITTER_TEST
TRAINING_RESTART
Access
Value
Description
R/W
[1]
link control enable:
R/W
0
link control disabled
1
link control enabled
[2]
operating mode select:
0000[3]
no change
0011
Normal mode
1100
Standby mode
1011
Sleep Request mode
R/W
R/W
SC
enable/disable Slave jitter test
0[3]
disable Slave jitter test
1
enable Slave jitter test
Autonegotiation process restart:
0[3]
1
8:6
5
TEST_MODE
CABLE_TEST
forces a restart of the training phase
R/W
R/W
SC
test mode selection:
000[3]
no test mode
001
BroadR-Reach test mode 1
010
BroadR-Reach test mode 2
011
BroadR-Reach test mode 3
100
BroadR-Reach test mode 4
101
BroadR-Reach test mode 5
110
scrambler and descrambler bypassed
111
reserved
TDR-based cable test:
0[3]
1
4:3
2
LOOPBACK_MODE
CONFIG_EN
loopback mode select:
00[3]
internal loopback
01
external loopback
10
external loopback
11
remote loopback
R/W
configuration register access:
1
0
CONFIG_INH
WAKE_REQUEST[4]
TJA1100
Product data sheet
stops TDR-based cable test
forces TDR-based cable test
R/W
0[3]
1
halts the training phase
configuration register access disabled
configuration register access enabled
R/W
INH configuration:
0
INH switched off in Disable mode
1[3]
INH switched on in Disable mode
R/W
wake-up request configuration:
0[3]
no wake-up signal to be transmitted
1
transmit idle symbols as bus wake-up request
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
[1]
Default value is 0 when AUTO_OP = 0; default value is 1 when AUTO_OP = 1.
[2]
Any other value generates a CONTROL_ERR interrupt.
[3]
Default value.
[4]
Link control must be disabled (LINK_CONTROL = 0) before WAKE_REQUEST is set.
Table 18.
Bit
15
14
Configuration register 1 (Register 18)
Symbol
MASTER_SLAVE
AUTO_OP
Access
Value
Description
R/W
[1]
PHY Master/Slave configuration:
R/W
0
PHY configured as Slave
1
PHY configured as Master
[1]
0
1
13
LINK_LENGTH
R/W
12
reserved
R/W
11:10
TX_AMPLITUDE
R/W
9:8
MII_MODE
R/W
6
MII_DRIVER
SLEEP_CONFIRM
< 15 m
1
> 15 m
x
3
LED_ENABLE
00
500 mV
01
750 mV
10[2]
1000 mV
11
1250 mV
[1]
TJA1100
Product data sheet
MII mode:
MII mode enabled
01
RMII mode enabled (50 MHz input at REFCLK_IN)
10
RMII mode enabled (25 MHz XTAL)
11
Reverse MII mode
R/W
MII output driver strength:
0[2]
standard
1
reduced
R/W
sleep confirmation setting:
R/W
R/W
ignore on read
nominal transmit amplitude:
1
LED_MODE
autonomous operation
0[2]
0[2]
5:4
managed operation
cable length:
00
7
managed/autonomous operation:
no confirmation needed from another PHY before going to sleep
confirmation needed from another PHY before going to sleep
LED mode:
00
link up (LED on when link OK: LINK_UP = 1)
01[2]
frame reception (LED on when BRreceive = true)
10
symbol error
11
CRS signal
[3]
LED enable:
0[2]
LED output disabled; WAKE input enabled
1
LED output enabled; WAKE input disabled
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 18.
Configuration register 1 (Register 18) …continued
Bit
Symbol
Access
2
CONFIG_WAKE
R/W
1
AUTO_PWD
0
LPS_ACTIVE
Value
Description
local wake configuration:
0[2]
absolute input threshold
1
ratiometric input threshold (VDD(IO))
R/W
autonomous power down:
0[2]
autonomous power-down disabled
1
autonomous power-down enabled
R/W
LPS code group reception:
0
automatic transition from Normal to Sleep Request when LPS
code group received disabled
1[2]
automatic transition from Normal to Sleep Request when LPS
code group received enabled
[1]
Default value determined by pin strapping (see Section 6.11).
[2]
Default value.
[3]
The WAKE input is enabled in Sleep, Sleep Request and Standby modes if LED_ENABLE = 0.
Table 19.
Bit
Configuration register 2 (Register 19)
Symbol
Access
Value
Description
[1]
PHY address used for the SMI address and for initializing the
Cipher scrambler key; PHYAD[1:0] is predetermined by the
hardware configuration straps on pins 23 and 24; PHYAD[4:2] set
to 001
15:11
PHYAD[4:0]
R
10:9
SNR_AVERAGING
R/W
signal-to-noise ratio averaging:
00
SNR averaged 32 symbols
01[2]
SNR averaged 64 symbols
10
SNR averaged 128 symbols
11
8:6
SNR_WLIMIT
TJA1100
Product data sheet
SNR averaged 256 symbols
R/W
signal-to-noise ratio warning limit:
000
no warning limit
001[2]
class A SNR warning limit
010
class B SNR warning limit
011
class C SNR warning limit
100
class D SNR warning limit
101
class E SNR warning limit
110
class F SNR warning limit
111
class G SNR warning limit
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 19.
Configuration register 2 (Register 19) …continued
Bit
Symbol
Access
5:3
SNR_FAILLIMIT
R/W
2
JUMBO_ENABLE
Value
000[2]
no fail limit
001
class A SNR fail limit
010
class B SNR fail limit
011
class C SNR fail limit
100
class D SNR fail limit
101
class E SNR fail limit
110
class F SNR fail limit
111
class G SNR fail limit
R/W
Jumbo packet support:
0
1[2]
1:0
SLEEP_REQUEST_TO R/W
Default value determined by pin strapping.
[2]
Default value.
Bit
[1]
packets up to 16 kB supported
00
0.4 ms
01[2]
1 ms
10
4 ms
11
16 ms
Symbol error counter register 2 (Register 20)
Symbol
15:0
packets up to 4 kB supported
sleep request time-out:
[1]
Table 20.
Description
signal-to-noise ratio fail limit:
Access
SYM_ERR_CNT R
Value
Description
0000h[1]
The symbol error counter is incremented when an invalid code
symbol is received (including idle symbols). The counter is
incremented only once per packet, even when the received packet
contains more than one symbol error. This counter increments up to
216. When the counter overflows, the value FFFFh is retained. The
counter is reset when the register is read.
Default value. Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 21.
Bit
Interrupt status register (Register 21)
Symbol
Access
Value
Description
power-on not detected
15
PWON
R
LH
0[1]
1
power-on detected
14
WAKEUP
R
LH
0[1]
no local or remote wake-up detected
1
local or remote wake-up detected
no dedicated wake-up request detected
13
WUR_RECEIVED
R
LH
0[1]
1
dedicated wake-up request detected
12
LPS_RECEIVED
R
LH
0[1]
no LPS code groups received
1
LPS code groups received
no PHY initialization error detected
11
PHY_INIT_FAIL
R
LH
0[1]
1
PHY initialization error detected
10
LINK_STATUS_FAIL
R
LH
0[1][2]
link status not changed
1
link status bit LINK_UP changed from ‘link OK’ to ‘link fail’
link status not changed
9
LINK_STATUS_UP
R
LH
0[1][2]
1
link status bit LINK_UP changed from ‘link fail’ to ‘link OK’
8
SYM_ERR
R
LH
0[1][2]
no symbol error detected
1
symbol error detected
no training phase failure detected
7
TRAINING_FAILED
R
LH
0[1]
1
training phase failure detected
6
SNR_WARNING
R
LH
0[1][2]
SNR value above warning limit
1
SNR value below warning limit and bit LINK_UP set
no SMI control error detected
5
CONTROL_ERR
R
LH
0[1]
1
SMI control error detected
4
TXEN_CLAMPED
R
LH
0[1]
no TXEN clamping detected
1
TXEN clamping detected
R
LH
0[1]
no undervoltage detected
1
undervoltage detected on VDD(IO), VDDA(1V8), VDDD(1V8) or
VDDA(3V3)
R
LH
0[1]
no undervoltage recovery detected
1
undervoltage recovery detected
R
LH
0[1]
no overtemperature error detected
1
overtemperature error detected
R
LH
0[1]
no transition from Sleep Request back to Normal as a result of
the Sleep Request timer expiring
1
transition from Sleep Request back to Normal as a result of the
Sleep Request timer expiring
3
UV_ERR
2
UV_RECOVERY
1
TEMP_ERR
0
SLEEP_ABORT
[1]
Default value.
[2]
Interrupts LINK_STATUS_FAIL, LINK_STATUS_UP, SYM_ERR and SNR_WARNING are cleared on entering Sleep Request mode, on
entering Standby mode due to an undervoltage and when an undervoltage is detected in Standby mode.
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
30 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 22.
Interrupt enable register (Register 22)
Bit
Symbol
Access
Value
Description
15
PWON_EN
R/W
0
PWON interrupt disabled
1[1]
PWON interrupt enabled
0[1]
WAKEUP interrupt disabled
1
WAKEUP interrupt enabled
0[1]
WUR_RECEIVED interrupt disabled
14
WAKEUP_EN
R/W
13
WUR_RECEIVED_EN
R/W
12
LPS_RECEIVED_EN
R/W
11
PHY_INIT_FAIL_EN
R/W
10
LINK_STATUS_FAIL_EN
R/W
9
LINK_STATUS_UP_EN
R/W
8
SYM_ERR_EN
R/W
1
WUR_RECEIVED interrupt enabled
0[1]
LPS_RECEIVED interrupt disabled
1
LPS_RECEIVED interrupt enabled
0[1]
PHY_INIT_FAIL interrupt disabled
1
PHY_INIT_FAIL interrupt enabled
0[1]
LINK_STATUS_FAIL interrupt disabled
1
LINK_STATUS_FAIL interrupt enabled
0[1]
LINK_STATUS_UP interrupt disabled
1
LINK_STATUS_UP interrupt enabled
0[1]
SYM_ERR interrupt disabled
1
SYM_ERR interrupt enabled
TRAINING_FAILED interrupt disabled
7
TRAINING_FAILED_EN
R/W
0[1]
1
TRAINING_FAILED interrupt enabled
6
SNR_WARNING_EN
R/W
0[1]
SNR_WARNING interrupt disabled
1
SNR_WARNING interrupt enabled
0[1]
CONTROL_ERR interrupt disabled
5
CONTROL_ERR_EN
R/W
4
TXEN_CLAMPED_EN
R/W
1
CONTROL_ERR interrupt enabled
0[1]
TXEN_CLAMPED interrupt disabled
1
TXEN_CLAMPED interrupt enabled
UV_ERR interrupt disabled
3
UV_ERR_EN
R/W
0[1]
1
UV_ERR interrupt enabled
2
UV_RECOVERY_EN
R/W
0[1]
UV_RECOVERY interrupt disabled
1
UV_RECOVERY interrupt enabled
0[1]
TEMP_ERR interrupt disabled
1
TEMP_ERR_EN
R/W
0
SLEEP_ABORT_EN
R/W
[1]
1
TEMP_ERR interrupt enabled
0[1]
SLEEP_ABORT interrupt disabled
1
SLEEP_ABORT interrupt enabled
Default value.
TJA1100
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 23.
Bit
Communication status register (Register 23)
Symbol
Access
Value
Description
0[1][2]
link failure
1
link OK
00[1][2]
transmitter disabled
01
transmitter in SEND_N mode
10
transmitter in SEND_I mode
11
transmitter in SEND_Z mode
0[1][2]
local receiver not OK
1
local receiver OK
0[1][2]
remote receiver not OK
15
LINK_UP
R
14:13
TX_MODE
R
12
LOC_RCVR_STATUS
R
LL
11
REM_RCVR_STATUS
R
LL
1
remote receiver OK
10
SCR_LOCKED
R
0[1][2]
descrambler unlocked
1
descrambler locked
0[1][2]
no SSD error detected
1
SSD error detected
9
SSD_ERR
R
LH
8
ESD_ERR
R
LH
0[1][2]
no ESD error detected
1
ESD error detected
R
000[1][2]
worse than class A (unstable link)
001
class A (unstable link)
010
class B (unstable link)
011
class C (unstable link)
100
class D (poor link; potential bit error)
7:5
SNR
101
class E (good link)
110
class F (very good link)
111
class G (very good link; class G is the highest level)
0[1][2]
no receive error detected
1
receive error detected since register last read
4
RECEIVE_ERR
R
LH
3
TRANSMIT_ERR
R
LH
0[1][2]
no transmit error detected
1
transmit error detected since register last read
R
000[1]
PHY Idle
001
PHY Initializing
010
PHY Configured
011
PHY Offline
100
PHY Active
2:0
PHY_STATE
101
PHY Isolate
110
PHY Cable test
111
PHY Test mode
[1]
Default value.
[2]
Reset to default value when link control is disabled (LINK_CONTROL = 0).
TJA1100
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Rev. 2 — 26 April 2016
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 24.
Bit
General status register (Register 24)
Symbol
Access
Value
Description
0[1]
all interrupts cleared
15
INT_STATUS
R
1
unmasked interrupt pending
14
PLL_LOCKED
R
LL
0[1]
PLL unstable and not locked
1
PLL stable and locked
no local wake-up detected
13
LOCAL_WU
R
LH
0[1]
1
local wake-up detected
12
REMOTE_WU
R
LH
0[1]
no remote wake-up detected
1
remote wake-up detected
R
LH
0[1]
no BroadR-Reach data detected at MDI or MII in Sleep
Request mode
1
BroadR-Reach data detected at MDI (pcs_rx_dv = TRUE; see
Ref. 1) or MII (TXEN = 1) in Sleep Request mode
11
DATA_DET_WU
10
EN_STATUS
R
LH
0[1]
EN HIGH
1
EN switched LOW since register last read
9
RESET_STATUS
R
0[1]
no hardware reset detected
1
hardware reset detected since register last read
R
0
always 0; ignore on read
number of link fails since register last read.
always 000; ignore on read
8
reserved
7:3
LINKFAIL_CNT
R
00000[1][2]
2:0
reserved
R
000
[1]
Default value.
[2]
Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 25.
Bit
External status register (Register 25)
Symbol
Access
Value
Description
15
reserved
R
0
always 0; ignore on read
14
UV_VDDA_3V3
R
LH
0[1]
no undervoltage detected on pin VDDA(3V3)
1
undervoltage detected on pin VDDA(3V3)
no undervoltage detected on pin VDDD(1V8)
13
UV_VDDD_1V8
R
LH
0[1]
1
undervoltage detected on pin VDDD(1V8)
12
UV_VDDA_1V8
R
LH
0[1]
no undervoltage detected on pin VDDA(1V8)
1
undervoltage detected on pin VDDA(1V8)
0[1]
no undervoltage detected on pin VDD(IO)
1
undervoltage detected on pin VDD(IO)
0[1]
temperature below high level
1
temperature above high level
temperature below warning level
11
UV_VDDIO
R
LH
10
TEMP_HIGH
R
LH
9
TEMP_WARN
R
LH
0[1]
1
temperature above warning level
8
SHORT_DETECT
R
LH
0[1][2]
no short circuit detected
1
short circuit detected since register last read
R
LH
0[1][2]
no open circuit detected
1
open circuit detected since register last read
7
OPEN_DETECT
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 25.
External status register (Register 25) …continued
Bit
Symbol
Access
Value
Description
6
reserved
R
0
always 0; ignore on read
5
INTERLEAVE_DETECT R
0[1]
interleave order of detected ternary symbols: TAn, TBn [2]
1
interleave order of detected ternary symbols: TBn, TAn
00000
always all 0s; ignore on read
4:0
reserved
R
[1]
Default value.
[2]
Bit NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 26.
Bit
Link fail counter register (Register 26)
Symbol
Access
Value
Description
The counter is incremented when local receiver is
NOT_OK; when the counter overflows, the value FFh is
retained. The counter is reset when the register is read.
The counter is incremented when remote receiver is
NOT_OK; when the counter overflows, the value FFh is
retained. The counter is reset when the register is read.
15:8
LOC_RCVR_CNT
R
00h[1][2]
7:0
REM_RCVR_CNT
R
00h[1][2]
[1]
Default value.
[2]
Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
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Rev. 2 — 26 April 2016
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OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
7. Limiting values
Table 27. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symb Parameter
ol
Conditions
Vx
DC value
voltage on pin x
Min
Max
Unit
on pin VBAT
0.3
+40
V
on pin INH
0.3
VBAT + 0.3
V
on pins WAKE, LED
36
+42
V
on pins VDDA(TX), VDDD(3V3), VDD(IO),
TRX_P, TRX_M
0.3
+4.6
V
VBAT < 3.1 V; 9 hours at an equivalent
junction temperature of 150 C;
activation energy of 0.78 eV
0.3
+3.6
V
VBAT  3.1 V
0.3
+4.6
V
on pins MDC, MDIO, RST_N, INT_N, EN
and MII digital input and output pins
0.3
min(VDD(IO) + V
0.3, +4.6)
on pins VDDA(1V8), VDDD(1V8), XI, XO
0.3
+2.5
V
-
250
A
-
250
A
on pin VDDA(3V3)
current on pin EN
IEN
IRST_N current on pin RST_N
IINH
current on pin INH
no time limit
2
-
mA
ILED
current on pin LED
no time limit; LED_ENABLE = 1
-
10
mA
transient voltage
Vtrt
VESD
electrostatic discharge voltage
on pins WAKE, VBAT, TRX_P, TRX_M
[1]
pulse 1
100 -
V
pulse 2a
-
V
pulse 3a
150 -
V
pulse 3b
-
100
V
75
IEC 61000-4-2; 150 pF, 330 
on pins TRX_P, TRX_M to GND
[2][3]
6.0
+6.0
kV
on pins WAKE, LED to GND
[2][4]
6.0
+6.0
kV
on pin VBAT to GND
[2][5]
6.0
+6.0
kV
on pins TRX_P, TRX_M to GND
[6]
6.0
+6.0
kV
on pins WAKE, LED to GND
[7]
6.0
+6.0
kV
on pin VBAT to GND
[8]
6.0
+6.0
kV
on any other pin
[6]
2.0
+2.0
kV
Human Body Model (HBM); 100 pF, 1.5 k
Charged Device Model (CDM); 1 
on any pin
[9]
500 +500
V
Tamb
ambient temperature
40
+125
C
Tstg
storage temperature
55
+150
C
[1]
According to ISO7637, class C; verified by an external test house.
[2]
Verified by external test house; test result must be equal to or better than 6 kV.
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
35 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
[3]
Tested with a common mode choke and 100 nF coupling capacitors.
[4]
Tested with 10 nF capacitor to GND and 10 k in series between the capacitor and the WAKE/LED pin.
[5]
Tested with 100 nF from VBAT to GND.
[6]
According to AEC-Q100-002.
[7]
According to AEC-Q100-002 with 10 nF capacitor to GND and 10 k in series between the capacitor and the WAKE/LED pin.
[8]
According to AEC-Q100-002 with 100 nF from VBAT to GND.
[9]
According to AEC-Q100-011.
8. Thermal characteristics
Table 28.
Thermal characteristics
Symbol
Parameter
Rth(j-a)
thermal resistance from junction to ambient
Rth(j-c)
thermal resistance from junction to case
[1]
[1]
Conditions
Typ
Unit
in free air
31
K/W
in free air
8
K/W
TJA1100 mounted on a JEDEC 2s2p board with 25 vias between layer 1 and layer 2; via diameter: 0.5 mm, wall thickness: 18 m.
9. Static characteristics
Table 29. Static characteristics
Tvj = 40 C to +150 C; VDDIO = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VBAT
battery supply voltage
operating range
3.1
-
36
V
IBAT
battery supply current
all modes except Sleep;
VBAT < 36 V; IINH = 0 A
-
-
1.2
mA
Sleep mode; Tvj  85 C;
7.2 V < VBAT < 30 V
-
30
70
A
VBAT < 40 V; IINH = 0 A
-
-
5
mA
Supply
Vuvd(VBAT)
undervoltage detection voltage on
pin VBAT
2.8
-
-
V
Vuvr(VBAT)
undervoltage recovery voltage on
pin VBAT
-
-
3.1
V
Vuvhys(VBAT)
undervoltage hysteresis voltage
on pin VBAT
15
100
-
mV
VDDA(3V3)
analog supply voltage (3.3 V)
operating range
3.1
3.3
3.5
V
IDDA(3V3)
analog supply current (3.3 V)
Normal/Sleep Request modes
-
21
27
mA
Standby mode
-
110
250
A
Disable/Reset modes
-
4
20
A
VDDA(TX)
transmitter analog supply voltage
operating range
3.1
3.3
3.5
V
IDDA(TX)
transmitter analog supply current
Normal/Sleep Request modes;
amplitude transmitter = 1 V
-
60
75
mA
Standby/Disable/Reset modes
-
0
50
A
operating range
3.1
3.3
3.5
V
VDDD(3V3)
digital supply voltage (3.3 V)
TJA1100
Product data sheet
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Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
36 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 29. Static characteristics …continued
Tvj = 40 C to +150 C; VDDIO = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDDD(3V3)
digital supply current (3.3 V)
Normal/Sleep Request modes
-
53
65
mA
Standby mode; Tvj = 25 C;
-
150
700
A
Standby mode; Tvj = 125 C;
-
0.4
6
mA
Disable/Reset modes
-
0
10
A
Vuvd(VDDA3V3)
undervoltage detection voltage on
pin VDDA(3V3)
2.9
-
-
V
Vuvr(VDDA3V3)
undervoltage recovery voltage on
pin VDDA(3V3)
-
-
3.1
V
50
80
-
mV
3.1
3.3
3.5
V
-
-
9
mA
-
-
20
A
-
35
70
A
Vuvhys(VDDA3V3) undervoltage hysteresis voltage
on pin VDDA(3V3)
VDD(IO)
IDD(IO)
input/output supply voltage
input/output supply current
operating range
Normal/Sleep Request modes;
Cload on MII pins = 15 pF
[1]
Standby/Disable modes;
no currents in pull-up resistors on
digital inputs
Reset mode; no currents in
pull-up resistors on digital inputs
[1]
Vuvd(VDDIO)
undervoltage detection voltage on
pin VDD(IO)
2.9
-
-
V
Vuvr(VDDIO)
undervoltage recovery voltage on
pin VDD(IO)
-
-
3.1
V
Vuvhys(VDDIO)
undervoltage hysteresis voltage
on pin VDD(IO)
50
80
-
mV
P
power dissipation
-
475
660
mW
2
-
-
V
Normal/Sleep Request modes
SMI interface: pins MDC and MDIO
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
Ci
input capacitance
-
-
0.8
V
pin MDC
[1]
-
-
8
pF
pin MDIO
[1]
-
-
10
pF
VOH
HIGH-level output voltage
pin MDIO; IOH = 4 mA
VDDIO  0.4
-
V
VOL
LOW-level output voltage
pin MDIO; IOL = 4 mA
-
-
0.4
V
IIH
HIGH-level input current
VIH = VDD(IO)
-
-
20
A
IIL
LOW-level input current
pin MDC; VIL = 0 V
20
-
-
A
pin MDIO; 0 V  Vi  VDD(IO)
3800
-
20
A
Rpd
pull-down resistance
on pin MDC
262.5
500
-
k
Rpu
pull-up resistance
on pin MDIO
70
100
130
k
2
-
-
V
-
-
0.8
V
-
-
8
pF
(R)MII interface: pins TXER, TXEN, TXDx, TXC, RXDx, RXDV, RXER, RXC
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
Ci
[1]
input capacitance
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
37 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 29. Static characteristics …continued
Tvj = 40 C to +150 C; VDDIO = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
VOH
HIGH-level output voltage
IOH = 4 mA
VOL
LOW-level output voltage
IIH
Typ
Max
Unit
VDDIO  0.4
-
V
IOL = 4 mA
-
-
0.4
V
HIGH-level input current
VIH = VDD(IO)
-
-
200
A
IIL
LOW-level input current
VIL = 0 V
20
-
-
A
Rpd
pull-down resistance
on pins TXER, TXEN, TXDx
70
100
130
k
on pin TXC; reverse MII mode
70
100
130
k
2
-
-
V
pins RST_N, EN
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
-
-
0.8
V
Vhys(i)
input hysteresis voltage
0.36
0.5
-
V
Ci
input capacitance
-
-
8
pF
IIH
HIGH-level input current
-
-
20
A
[1]
at pin RST_N; VIH = VDD(IO)
IIL
LOW-level input current
at pin EN; VIL = 0 V
20
-
-
A
Rpd
pull-down resistance
on pin EN
70
100
130
k
Rpu
pull-up resistance
on pin RST_N
70
100
130
k
pins RXD[3:0], RXER and RXDV during pin strapping
VIH
HIGH-level input voltage
2
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
CONFIG_WAKE = 0 (see
Table 18)
2.8
-
4.1
V
CONFIG_WAKE = 1
0.44 
VDD(IO)
-
0.64  V
VDD(IO)
CONFIG_WAKE = 0
2.4
-
3.75
CONFIG_WAKE = 1
0.38 
VDD(IO)
-
0.55  V
VDD(IO)
CONFIG_WAKE = 0
0.25
-
0.8
CONFIG_WAKE = 1
0.025  VDD(IO)
0.2 
V
VDD(IO)
LED driver off
5
-
+5
A
LED driver on; ILED = 0.8 mA
-
-
1.4
V
LED driver on; ILED = 3 mA
-
-
2
V
20
mA
pin WAKE (LED_ENABLE = 0)
VIH
VIL
Vhys(i)
Ii
HIGH-level input voltage
LOW-level input voltage
input hysteresis voltage
input current
V
V
pin LED (LED_ENABLE = 1)
VOL
LOW-level output voltage
IO(sc)
short-circuit output current
VLED = 40 V
LOW-level output voltage
IOL = 2 mA
-
-
0.4
V
HIGH-level output voltage
all modes except Sleep,
Power-off; IINH = 1 mA
VBAT 
1
-
VBAT
V
pin INT_N
VOL
pin INH
VOH
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
38 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 29. Static characteristics …continued
Tvj = 40 C to +150 C; VDDIO = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOL
LOW-level output current
all modes except Sleep,
Power-off; VINH = 0 V
15
7
2
mA
IL
leakage current
Sleep, Power-off modes
5
-
+5
A
input capacitance
pin XI
[1]
-
3.5
-
pF
pin XO
[1]
-
2
-
pF
13.3
25
47
mA/V
pins XI, Xo
Ci
gm(DC)
DC transconductance
Normal, Sleep Request modes;
MII_MODE = 00, 01 or 11
Transmitter test results
Vdroop/VM
droop voltage to peak voltage ratio OPEN Alliance BroadR-Reach
test mode 1; with respect to initial
peak value
[1]
45
-
+45
%
Vdist(M)
peak distortion voltage
OPEN Alliance BroadR-Reach
test mode 4
[1]
-
-
15
mV
PSDM
power spectral density mask
OPEN Alliance BroadR-Reach
test mode 5
f = 1 MHz
[1]
30.9
-
23.3
dBm
f = 20 MHz
[1]
35.8
-
24.8
dBm
f = 40 MHz
[1]
49.2
-
28.5
dBm
f = 57 MHz to 200 MHz
[1]
-
-
36.5
dBm
TX_AMPLITUDE = 00 (see
Table 18); RL(dif) = 100 
-
500
-
mV
TX_AMPLITUDE = 01;
RL(dif) = 100 
-
750
-
mV
TX_AMPLITUDE = 10;
RL(dif) = 100 
-
1000
-
mV
TX_AMPLITUDE = 11;
RL(dif) = 100 
-
1250
-
mV
47.5
50
52.5

30
67
85

47.5
50
52.5

30
67
85

Transmitter output amplitude
VoM(TX)
Rterm(TRX_P)
Rterm(TRX_M)
transmitter peak output voltage
termination resistance on pin
TRX_P
Normal, Sleep Request modes
termination resistance on pin
TRX_M
Normal, Sleep Request modes
Standby, Sleep, Disable modes
Standby, Sleep, Disable modes
[1]
[1]
Temperature protection
Tj(sd)
shutdown junction temperature
180
-
200
C
Tj(sd)rel
release shutdown junction
temperature
147
-
167
C
Tj(warn)
warning junction temperature
155
-
175
C
Tj(warn)rel
release warning junction
temperature
147
-
167
C
Tj(warn)hys
warning junction temperature
hysteresis
2
8
-
C
[1]
Guaranteed by design.
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
39 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
10. Dynamic characteristics
Table 30. Dynamic characteristics
Tvj = 40 C to +150 C; VDDIO = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
MII transmit
Parameter
timing[1];
Conditions
Min
Typ
Max
Unit
see Figure 13
Tclk(TXC)
TXC clock period
-
40
-
ns
TXC
TXC duty cycle
35
-
65
%
tWH(TXC)
TXC pulse width HIGH
14
20
-
ns
tWL(TXC)
TXC pulse width LOW
14
20
-
ns
tsu(TXD)
TXD set-up time
to rising edge on TXC
10
-
-
ns
tsu(TXEN)
TXEN set-up time
to rising edge on TXC
10
-
-
ns
tsu(TXER)
TXER set-up time
to rising edge on TXC; transmit coding
error
10
-
-
ns
th(TXD)
TXD hold time
from rising edge on TXC
0
-
-
ns
th(TXEN)
TXEN hold time
from rising edge on TXC
0
-
-
ns
th(TXER)
TXER hold time
from rising edge on TXC; transmit
coding error
0
-
-
ns
MII receive timing[1]; Figure 14
Tclk(RXC)
RXC clock period
-
40
-
ns
RXC
RXC duty cycle
35
-
65
%
tWH(RXC)
RXC pulse width HIGH
14
20
-
ns
tWL(RXC)
RXC pulse width LOW
14
20
-
ns
td(RXC-RXD)
delay time from RXC to RXD from rising edge on RXC
15
-
25
ns
td(RXC-RXDV)
delay time from RXC to
RXDV
from rising edge on RXC
15
-
25
ns
td(RXC-RXER)
delay time from RXC to
RXER
from rising edge on RXC
15
-
25
ns
RMII transmit and receive timing[1]; see Figure 15 and Figure 16
Tclk(REF_CLK)
REF_CLK clock period
-
20
-
ns
REF_CLK
REF_CLK duty cycle
35
-
65
%
tWH(REF_CLK)
REF_CLK pulse width HIGH
7
10
-
ns
tWL(REF_CLK)
REF_CLK pulse width LOW
7
10
-
ns
tsu(TXD)
TXD set-up time
to rising edge on REF_CLK
4
-
-
ns
tsu(TXEN)
TXEN set-up time
to rising edge on REF_CLK
4
-
-
ns
th(TXD)
TXD hold time
from rising edge on REF_CLK
2
-
-
ns
th(TXEN)
TXEN hold time
from rising edge on REF_CLK
2
-
-
ns
td(REF_CLK-RXD)
delay time from REF_CLK to from rising edge on REF_CLK
RXD
4
-
13
ns
td(REF_CLK-RXER)
delay time from REF_CLK to from rising edge on REF_CLK
RXER
4
-
13
ns
td(REF_CLK-CRSDV) delay time from REF_CLK to from rising edge on REF_CLK
CRSDV
4
-
13
ns
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
40 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 30. Dynamic characteristics …continued
Tvj = 40 C to +150 C; VDDIO = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
(R)MII interface
Parameter
Conditions
Min
Typ
Max
Unit
MII output pins; CL = 15 pF;
MII mode; MII_DRIVER = 0;
1.3
-
5
ns
MII output pins; reduced EMC;
MII mode; MII_DRIVER = 1;
CL = 15 pF
2.5
-
10
ns
RMII output pins; CL = 15 pF;
RMII mode; MII_DRIVER = 0
0.7
-
2.5
ns
RMII output pins; reduced EMC;
RMII mode; RMII_DRIVER = 1;
CL = 15 pF
1.3
-
5
ns
MII output pins; CL = 15 pF;
MII mode; MII_DRIVER = 0
1.3
-
5
ns
MII output pins; reduced EMC;
MII mode; MII_DRIVER = 1;
CL = 15 pF
2.5
-
10
ns
RMII output pins; CL = 15 pF;
RMII mode; MII_DRIVER = 0
0.7
-
2.5
ns
RMII output pins; reduced EMC;
RMII mode; MII_DRIVER = 1;
CL = 15 pF
1.3
-
5
ns
timing[1]
tf
tr
fall time
from 2 V to 0.8 V
rise time
from 0.8 V to 2 V
SMI timing[1]; see Figure 17
Tclk(MDC)
MDC clock period
400
-
-
ns
tWH(MDC)
MDC pulse width HIGH
160
-
-
ns
tWL(MDC)
MDC pulse width LOW
160
-
-
ns
tsu(MDIO)
MDIO set-up time
to rising edge on MDC
10
-
-
ns
th(MDIO)
MDIO hold time
from rising edge on MDC
10
-
-
ns
td(MDC-MDIO)
delay time from MDC to
MDIO
from rising edge on MDC; read from
PHY
0
-
300
ns
10
-
40
s
JUMBO_ENABLE = 0
-
1.1
-
ms
JUMBO_ENABLE = 1
-
2.2
-
ms
Normal mode; CABLE_TEST = 1
-
100
-
s
WAKE timing; pin WAKE
tdet(wake)
tto(PCS-RX)[2]
wake-up detection time
PCS-RX time-out time
Normal and Sleep Request modes
Cable test timing
tto(cbl_tst)
cable test time-out time
LED timing[1]; pin LED
ton(LED)
turn-on time on pin LED
RL = 1 k; CL = 100 pF
-
-
10
s
toff(LED)
turn-off time on pin LED
RL = 1 k; CL = 100 pF
-
-
10
s
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
41 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
Table 30. Dynamic characteristics …continued
Tvj = 40 C to +150 C; VDDIO = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
timing[1];
INH
Parameter
Conditions
Min
Typ
Max
Unit
pin INH
ton(INH)
turn-on time on pin INH
RL = 100 k; CL = 50 pF;
Vth(INH) = 2 V
0
2
50
s
toff(INH)
turn-off time on pin INH
RL = 100 k; CL = 50 pF;
Vth(INH) = 2 V
5
50
65
s
tdet(rst)
reset detection time
on pin RSTN;
Vuvd(VDDIO) < VDD(IO)  3.5 V
5
-
20
s
tdet(EN)
detection time on pin EN
Vuvd(VDDIO) < VDD(IO)  3.5 V
5
-
20
s
-
-
50
ps
-
-
150
ps
pins RST_N, EN
Transmitter test results
tjit(RMS)
RMS jitter time
Master mode
Slave mode (with link);
SLAVE_JITTER_TEST = 1
[1]
[3]
Undervoltage detection
tdet(uv)(VBAT)
undervoltage detection time
on pin VBAT
VBAT = 2.7 V
[1]
0
-
30
s
tdet(uv)VDDA(3V3)
undervoltage detection time
on pin VDDA(3V3)
VDDA(3V3) = 2.8 V
[1]
2
-
30
s
trec(uv)VDDA(3V3)
undervoltage recovery time
on pin VDDA(3V3)
VDDA(3V3) = 3.2 V
[1]
2
-
30
s
tdet(uv)VDD(IO)
undervoltage detection time
on pin VDD(IO)
VDD(IO) = 2.8 V
[1]
2
-
30
s
trec(uv)VDD(IO)
undervoltage recovery time
on pin VDD(IO)
VDD(IO) = 3.2 V
[1]
2
-
30
s
tto(uvd)
undervoltage detection
time-out time
Normal, Standby, Sleep Request and
Disable modes
300
670
ms
General timing parameters
ts(pon)
power-on settling time
from power-on to Standby mode
-
-
2
ms
tinit(PHY)
PHY initialization time
from Standby mode to Normal mode
-
-
2
ms
tto(req)sleep
sleep request time-out time
SLEEP_REQUEST_TO = 00
360
-
500
s
SLEEP_REQUEST_TO = 01
900
-
1150
s
SLEEP_REQUEST_TO = 10
3.6
-
4.4
ms
SLEEP_REQUEST_TO = 11
14.4
-
17.6
ms
tdet(wake)
wake-up detection time
on bus pins TRX_P and TRX_M
-
-
0.7
ms
tto(pd)autn
autonomous power-down
time-out time
Normal mode; AUTO_PWD = 1
1
-
2
s
tPD
propagation delay
from MII/RMII to MDI; Normal mode
[1]
-
-
240
ns
from MDI to MII/RMII; Normal mode
[1]
tdetCL(TXEN)
TXEN clamp detection time
[1]
Guaranteed by design.
[2]
rcv_max_timer in the BroadR-Reach specification; Ref. 1.
[3]
Measured at the EN pin, representing the transmit clock (TX_CLK).
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
-
-
780
ns
1.9
-
2.1
ms
© NXP Semiconductors N.V. 2016. All rights reserved.
42 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
7FON7;&
7;&
W:+7;&
W:/7;&
9
9
WVX7;(1
7;(1
WK7;(1
9
9
WVX7;'
7;'>@
WVX7;'
WK7;'
9
9
WVX7;(5 WK7;(5
7;(5
9
9
DDD
Fig 13. MII transmit timing diagram
W:+5;&
7FON5;&
5;&
W:/5;&
9
9
WG5;&5;'9
5;'9
9
9
WG5;&5;'
5;'>@
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WG5;&5;'
9
9
WG5;&5;(5
5;(5
WG5;&5;'
WG5;&5;(5
9
9
DDD
Fig 14. MII receive timing diagram
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
43 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
W:+5()B&/. W:/5()B&/.
7FON5()B&/.
5()B&/.
9
9
WK7;(1
WVX7;(1
7;(1
9
9
WVX7;'
7;'>@
WK7;'
WVX7;'
WK7;'
9
9
DDD
Fig 15. RMII transmit timing diagram
7FON5()B&/.
5()B&/.
9
9
&56'9
WG5()B&/.&56'9
WG5()B&/.&56'9
WG5()B&/.5;(5
WG5()B&/.5;(5
WG5()B&/.5;'
WG5()B&/.5;'
9
9
5;(5
9
9
5;'>@
9
9
DDD
Fig 16. RMII receive timing diagram
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
44 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
W:+0'&
7FON0'&
0'&
9
9
WG0'&0',2
0',2
'DWDRXW
W:/0'&
WG0'&0',2
9
9
WVX0',2 WK0',2
0',2
'DWDLQ
9
9
DDD
Fig 17. SMI timing diagram
11. Package information
The TJA1100 comes in the HVQFN-36 package as shown in Figure 18. Measuring just
36 mm2 with a pitch of 0.5 mm, it is particularly suitable for use in PCB space-constrained
applications, such as an integrated IP camera module. The package features wettable
sides/flanks to allow for optical inspection of the soldering process. The exposed die pad
shown in the package diagram should be connected to ground.
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
45 of 52
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NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
12. Package outline
+94)1SODVWLFWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV
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627
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5HIHUHQFHV
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Fig 18. Package outline SOT1092-2 (HVQFN36)
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
46 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
47 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 31 and 32
Table 31.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 32.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
48 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. References
[1]
OPEN Alliance BroadR-Reach Physical Layer Transceiver Specification for
Automotive Applications, V3.2, 24 June 2014
[2]
TJA1100 Application Hints
15. Revision history
Table 33.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TJA1100 v.2
20160426
Product data sheet
-
TJA1100 v.1
Modifications:
TJA1100 v.1
TJA1100
Product data sheet
• Figure 2 amended
• Table 2: pin 1: MDC pin description changed; pin 25: added functionality to RXC pin
• Section 6.10.1, Section 6.10.4: text revised
• Section 6.10.6 deleted
• Section 6.11: moved (was Section 6.10.8.4)
• Table 18: bits 13 and 12 revised
• Table 19: bit description for SNR_WLIMIT and SNR_FAILLIMIT changed
• Table 21: references to Table note 2 added
• Table 25: bit 6 is reserved
• Table 29: parameter P (power dissipation) moved to Supply section
20160104
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
-
© NXP Semiconductors N.V. 2016. All rights reserved.
49 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TJA1100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
50 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
51 of 52
TJA1100
NXP Semiconductors
OPEN Alliance BroadR-Reach PHY for Automotive Ethernet
18. Contents
1
2
2.1
2.2
3
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.2.1.1
6.2.2
6.2.2.1
6.2.3
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.1.6
6.3.1.7
6.3.2
6.4
6.5
6.5.1
6.5.2
6.5.3
6.6
6.7
6.8
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
6.10
6.10.1
6.10.2
6.10.3
6.10.4
6.10.5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Optimized for automotive use cases. . . . . . . . . 1
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 7
System configuration . . . . . . . . . . . . . . . . . . . . 7
MII and RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signaling and encoding . . . . . . . . . . . . . . . . . . 7
RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signaling and encoding . . . . . . . . . . . . . . . . . . 8
Reverse MII . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System controller . . . . . . . . . . . . . . . . . . . . . . 10
Operating modes . . . . . . . . . . . . . . . . . . . . . . 10
Power-off mode . . . . . . . . . . . . . . . . . . . . . . . 10
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disable mode . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sleep Request mode . . . . . . . . . . . . . . . . . . . 11
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transitions between operating modes . . . . . . 13
Wake-up request . . . . . . . . . . . . . . . . . . . . . . 15
Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 16
Local wake-up . . . . . . . . . . . . . . . . . . . . . . . . 16
Wake-up by data detection . . . . . . . . . . . . . . . 16
Autonomous operation . . . . . . . . . . . . . . . . . . 16
Autonomous power-down . . . . . . . . . . . . . . . . 16
Transmitter amplitude . . . . . . . . . . . . . . . . . . . 17
Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Test mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Test mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Test mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Test mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Test mode 5 . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Error diagnosis . . . . . . . . . . . . . . . . . . . . . . . . 18
Undervoltage detection. . . . . . . . . . . . . . . . . . 18
Cabling errors . . . . . . . . . . . . . . . . . . . . . . . . . 18
Link stability . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Link-fail counter . . . . . . . . . . . . . . . . . . . . . . . 18
Jabber detection . . . . . . . . . . . . . . . . . . . . . . . 19
6.10.6
6.10.7
6.10.7.1
6.10.7.2
6.10.7.3
6.11
6.12
6.12.1
7
8
9
10
11
12
13
13.1
13.2
13.3
13.4
14
15
16
16.1
16.2
16.3
16.4
17
18
Interleave detection . . . . . . . . . . . . . . . . . . . .
Loopback modes . . . . . . . . . . . . . . . . . . . . . .
Internal loopback . . . . . . . . . . . . . . . . . . . . . .
External loopback . . . . . . . . . . . . . . . . . . . . .
Remote loopback . . . . . . . . . . . . . . . . . . . . . .
Auto-configuration of the PHY during
power-up via pin strapping. . . . . . . . . . . . . . .
SMI registers . . . . . . . . . . . . . . . . . . . . . . . . .
SMI register mapping. . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Package information. . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
19
20
20
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Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 26 April 2016
Document identifier: TJA1100
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