EVB-USB3340 USB Transceiver Evaluation Board User Manual Copyright © 2010 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. 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SMSC USB3340 EVB USER MANUAL Revision 1.1 (12-14-10) EVB-USB3340 USB Transceiver Evaluation Board User Manual 1 Introduction This user manual is for the USB3340 USB Transceiver Evaluation Board (EVB) for use with USB3340 products with the integrated USB switch. The USB3340 features a ULPI interface to support systems with USB Host, Device, or On-the-Go (OTG) capability. The integrated switch can be used to multiplex a Full Speed USB signal or audio signals over the HS USB DP/DM pins. 2 Overview The USB3340 EVB is a Daughter Card designed to plug into a user's test system using a T&MT connector. The card attaches to a USB link layer to create a USB Host, Device, or On-the-Go (OTG) system. The board edge connector meets the UTMI+ Low Pin Interface (ULPI) Standard requirements for the T&MT connector. A link to the ULPI Working Group Page is available at www.smsc.com or may be obtained from your local FAE. The USB3340 EVB includes USB3340 packaged silicon and all external components required for the USB transceiver function. This manual describes PCB assembly PCB-7220AZ. 2.1 Supplying VBUS Voltage In Host or OTG operation, the USB3340 EVB must provide 5 Volts on VBUS at the USB connector. The USB3340 EVB includes a switch that can drive VBUS using the 5 Volt supply that comes from pin 28 of the T&MT connector. The VBUS switch is controlled by the CPEN signal from the USB3340. The USB controller dictates the state of CPEN by programming the ULPI register in the USB3340. The 5 Volt switch is backdrive protected when in the off state. The switch does not provide protection from reverse currents when it is on. See Section 2.10 and Section 2.11 for more information on configuring the USB3340 EVB for OTG and Host operation. 2.2 ULPI I/O Voltage The USB3340 supports variable ULPI I/O voltage signaling. The ULPI I/O voltage is supplied in one of two ways. By default, the EVB is shipped with VDDIO supplied by the on-board LDO. Resistor R18 is used to set VDDIO, the digital logic high voltage. To change the value of VDDIO, calculate a new value for R18 (ohms) as follows. R18 = (VDDIO/1.225-1) x 169000 VDDIO must be in the range of 1.8 Volts - 3.3 Volts nominal. VDDIO can also be supplied to the USB3340 from the T&MT connector instead of using the LDO. To do this, the LDO (U10) must be removed. The VDDIO voltage level that has been configured on the USB3340 EVB must be the same as the ULPI I/O voltage level that the link is using. Revision 1.1 (12-14-10) 2 USER MANUAL SMSC USB3340 EVB EVB-USB3340 USB Transceiver Evaluation Board User Manual 2.3 Edge Connector for Digital I/O The T&MT edge connector is compliant to the ULPI specification. Part numbers and manufacturers for this connector and it’s mate are given in Table 2.1. Table 2.1 Edge Connector on the USB3340 EVB PART NUMBER DESCRIPTION MANUFACTURER 2-557101-5 100 pin edge connector on USB3340 EVB AMP 2-557-101-5 Mating connector to the USB3340 EVB AMP 1-1734037-0 Alternate 100 pin edge connector for USB3340 EVB TYCO 1-1734099-0 Alternate mating connector to the USB3340 EVB TYCO 2.4 REFCLK Frequency Selection The USB3340 EVB offers a user selectable reference clock frequency. R25 - R30 are used to configure the REFCLK[2:0] signals which will select the reference clock frequency desired on the USB3340 EVB. Ensure that the frequency of the reference clock or reference crystal being used matches the desired operation frequency configured based on Table 2.2 below. By default, the USB3340 EVB is configured for 26MHz REFCLK operation. Table 2.2 Reference Frequency Selection Resistor Configurations R25 R26 R27 R28 R29 R30 REFCLK FREQUENCY INSTALL EMPTY INSTALL EMPTY EMPTY INSTALL 26.0 MHz (Default) EMPTY INSTALL INSTALL EMPTY EMPTY INSTALL 12.0 MHz EMPTY INSTALL EMPTY INSTALL EMPTY INSTALL 52.0 MHz INSTALL EMPTY INSTALL EMPTY INSTALL EMPTY 24.0 MHz INSTALL EMPTY EMPTY INSTALL INSTALL EMPTY 19.2 MHz EMPTY INSTALL INSTALL EMPTY INSTALL EMPTY 27.0 MHz EMPTY INSTALL EMPTY INSTALL INSTALL EMPTY 38.4 MHz INSTALL EMPTY EMPTY INSTALL EMPTY INSTALL 13.0 MHz 2.5 USB Connector A standard Mini-AB connector is provided to attach a USB cable or connector. Provision is made on the PCB to accept a Micro-AB connector. See the bill of materials in Section 6 for connector part numbers. Do not substitute a different part number for the Mini-AB receptacle or a short circuit of the USB signals may result at the micro-AB connector PCB footprint. 2.6 VBUS Present Detection The USB controller must detect VBUS when a USB cable is attached in device mode or when the USB controller turns on VBUS in host or OTG mode. The USB connector VBUS signal is connected to the VBUS pin of the USB3340. The USB3340 includes all of the comparators required to detect VBUS and report the state of VBUS to the USB controller via the ULPI bus. SMSC USB3340 EVB 3 USER MANUAL Revision 1.1 (12-14-10) EVB-USB3340 USB Transceiver Evaluation Board User Manual 2.7 ULPI Signal Test Points Probe points at location J2, provide access to all ULPI signals. Install the Tektronix logic analyzer probe retention kit at J2 to probe these signals. Ordering information for the retention kit is provided in the bill of materials. 2.8 Other Signal Test Points There are five other test points located on the board for easy access. TP1 connects to the 5V supply coming from the T&MT connector. TP2 connects to the 3.3V VDD supply coming from the T&MT connector. TP3 connects to Ground. TP4 and TP5 connect to the Speaker Left and Speaker Right pins respectively. 2.9 Speaker Left and Speaker Right signals The Speaker Left and Speaker Right pins can accept audio signals ranging from 0V to 3.3V. If the audio signal coming into the test points goes below 0V, biasing circuitry is required. Install R11, R14, R15, and R16 with 10k resistors to add a DC bias to the audio signal. This will ensure the best signal quality when routing through the USB3340. 2.10 Converting the EVB to an OTG System “Out of the box”, the USB3340 EVB is delivered as a USB Device system. To convert it to be a USB OTG development board, the following modifications must be made: 1. Install R13 (zero ohm resistor). This connects the VBUS 5V switch to the VBUS signal. 2. Remove R23. This is the RVBUS value required for a USB Device. 3. Install R10 (1.0K, 1W resistor). This is the RVBUS value required for a USB OTG Device. Since the USB3340 is designed to accommodate up to 30V on VBUS, R10 is rated at 1W to accommodate this entire voltage range. Refer to the USB3340 datasheet for more information on sizing this resistor. 2.11 Converting the EVB to a Host System “Out of the box”, the USB3340 EVB is delivered as a USB Device System. To convert it to be a USB Host development board, the following modifications must be made: 1. Install R13 (zero ohm resistor). This connects the VBUS 5V switch to the VBUS signal. 2. Install C24 (120uF capacitor). This increases the value of CVBUS to be USB 2.0 Host compliant. 2.12 Converting the EVB to Support ULPI Clock Input Mode “Out of the box”, the USB3340 EVB uses a crystal (Y1) as the clock reference, and is configured for ULPI Clock Output Mode where CLKOUT sources a 60MHz clock. To convert the EVB to support ULPI Clock Input Mode, the following changes must be made: 1. Install R12 (zero ohm resistor). This shorts CLKOUT to VDD18. 2. Install R3 (zero ohm resistor). This shorts REFCLK to the System Clock pin on the T&MT connector. 3. Confirm that R4 is not populated. 4. Remove the following components to remove the crystal circuit: Y1, R17, C22, C23 Refer to the USB3340 datasheet for more information on ULPI Clock Input Mode. Revision 1.1 (12-14-10) 4 USER MANUAL SMSC USB3340 EVB EVB-USB3340 USB Transceiver Evaluation Board User Manual 2.13 T&MT Pin Description The T&MT signal names, pin number and function are described in Table 43 and Table 44 of the ULPI Specification rev 1.1. The USB3340 EVB fully implements a ULPI compliant interface to the T&MT connector, including support for ULPI Clock Input Mode. This EVB supports a 1.8-3.3V ULPI I/O voltages. All signals are described in Table 2.3. Table 2.3 T&MT Connector Pin Definitions PIN NAME 86, 36, 85, 34, 83, 33, 82, 31 DATA[7:0] 96 DESCRIPTION DIRECTION ULPI Data Bus IN/OUT STP ULPI STP Signal INPUT TO EVB 70 DIR ULPI DIR Signal OUTPUT FROM EVB 71 NXT ULPI NXT Signal OUTPUT FROM EVB 90 CLKOUT ULPI Clock Signal OUTPUT FROM EVB 55 VBUS_FAULT_N Driven low by the VBUS switch (U2) in the event of a switch fault condition. OUTPUT 15 SPKR_L In USB Audio mode, SPKR_L is connected to the DP pin via an analog switch in the USB3340. IN/OUT 45 SPKR_RM In USB Audio mode, SPKR_RM is connected to the DP pin via an analog switch in the USB3340. IN/OUT 17 RESET Asserting RESET will place the USB3340 in a low power state. Upon exiting this state (RESET=0), all ULPI registers will contain power-on reset values. INPUT 47 VBUS_IN This pin is not connected NO CONNECT 28 VBUS_OUT +5V from the T&MT connector INPUT TO EVB 8, 16, 57, 69 VDD +3.3V from the T&MT connector INPUT TO EVB 52 SYSTEM_CLOCK Optional clock input to EVB. The EVB is built with the USB3340 REFCLK provided by a crystal. See Section 2.12 for more information on configuring the USB3340 EVB for ULPI Clock Input mode. NO CONNECT (input to EVB if R3 is installed) 100 PSU_SHD_N This pin is driven low indicating that +3.3V must be sourced from the link through the T&MT connector pins 8, 16, 57, 69 and +5.0V must be sourced from the link through the T&MT connector pin 28. OUTPUT FROM EVB 49 DC_PSNT_N This pin is driven low indicating a daughter card is present. OUTPUT FROM EVB Refer to Schematic for Connector Pin Assignment SMSC USB3340 EVB 5 USER MANUAL Revision 1.1 (12-14-10) EVB-USB3340 USB Transceiver Evaluation Board User Manual 3 Getting Started The block diagram in Figure 3.1 gives a simplified view of the USB3340 EVB. The USB3340 EVB is ready for device operation. To modify the board for OTG or Host applications, refer to Section 2.10 or Section 2.11, respectively. It is required to provide +5V to T&MT connector pin 28 and +3.3V on T&MT pins 8,16,57,69 to power the USB3340 EVB. The USB3340 EVB is built with a USB Mini-AB receptacle. Do not substitute a Mini-AB receptacle different from the one specified in the bill of materials, or a short circuit may occur on the USB signals at the Micro-AB connector PCB footprint. Install C20=150uF if host operation is desired VBUS Switch ONA 2.2uF FAULTAn 150uF EXT_VBUS_DET VARIABLE VDDIO REG CPEN +5V J1 100-pin T&MT RESET ULPI Signals VBAT VBUS VDDIO USB3340 DM DM DP DP VDD3p3 RESETB ULPI Bus ID ID GND 1.0uF REFSEL[2:0] XI XO PCB can accept Micro-AB Or Mini-AB receptacle VDD1p8 1.8V LDO USER REFCLK CONFIG VDD3.3 Figure 3.1 Block Diagram of USB3340 EVB When the USB3340 EVB is powered on, check the following things to be certain the board is functioning normally: RESET should be de-asserted (logic low at the T&MT connector and RESETB at the USB3340 should be logic high = VDD18). If RESETB=0, the USB3340 will be in a low power state. The voltage at R2 (RBIAS) should be 0.8V DC. If this voltage is not present, the USB3340 is in a low power state. There should be a digital 60 MHz square wave signal at T&MT connector pin 90. The amplitude should be approximately VDDIO. This is the CLKOUT signal of the USB3340. Revision 1.1 (12-14-10) 6 USER MANUAL SMSC USB3340 EVB EVB-USB3340 USB Transceiver Evaluation Board User Manual The voltage at C3 should be approximately 3.3V. This is the USB3340 internal 3.3V voltage regulator output. The voltage at C4 should be 1.8V. This is the 1.8V regulator output. 4 Protecting VBUS from Non-Compliant VBUS Voltages The USB3340 is fully tolerant to VBUS voltages up to 30V. An external resistor on the VBUS line (RVBUS) is required for the integrated overvoltage protection circuit in the USB3340. RVBUS is either R10 or R23 on the USB3340 EVB. For peripheral and host applications, RVBUS is 10K (install R23, remove R10). For OTG applications, RVBUS is 1K (install R10, remove R23). SMSC USB3340 EVB 7 USER MANUAL Revision 1.1 (12-14-10) A B C D ZERO 1/4W R32 TEST_POINT TP1 49 100 52 28 47 1 26 3 29 5 6 56 7 58 11 61 12 63 50 78 DNP R6 10.0k 1/16W 2 1 OUT VCC 26.0 MHz GND EN X1 R5 10.0k 1/16W 3 4 5 C10 0.1uF 10V +3.3V C9 0.1uF 10V AMP_UTMI+_ULPI DC_PSNT_N PSU_SHD_N System_Clock VBUS_out VBUS_in GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 Reserved1 Reserved2 Reserved3 Reserved4 Reserved5 Reserved6 Reserved7 Reserved8 Reserved9 Reserved10 Reserved11 Reserved12 Reserved13 Reserved14 Reserved15 Reserved16 Reserved17 Reserved18 Reserved19 Reserved20 Reserved21 Reserved22 Reserved23 Reserved24 Reserved25 Reserved26 Reserved27 Reserved28 Reserved29 Reserved30 Reserved31 Reserved32 Reserved33 Reserved34 Oscillator Support +5.0V CPEN VBUS_FAULT_N 60 75 66 72 74 22 19 20 18 67 25 23 98 48 55 97 59 10 79 37 88 41 91 42 93 44 94 99 30 89 64 77 14 40 J1 R8 10.0k 1/16W R7 27k 1/16W 1 2 U6 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VIO VIO VIO VDD VDD VDD VDD Reset Clk DIR NXT STP SPKR_MIC SPKR_L DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 2 4 9 13 21 24 27 32 35 39 43 46 51 53 54 62 65 68 73 76 80 84 92 95 81 87 38 2 U8 C13 0.1uF 10V REFSEL0 1/16 W ZERO 1/16W +5.0V 3 2 1 FB Vout TPS77001DVBT /EN GND Vin R18 = 78.7K R18 = 107K R18 = 178K R18 = 243K R18 = 287K C14 1.0uF 16V U10 R9 169k 1 1/16W R18 78.7k 1/16W 6.3V 6.3V REFSEL0 DATA4 DATA3 DATA2 DATA1 DATA0 NXT CLKOUT VDDIO DNP R11 10.0k 1/16W +3.3V REFSEL2 REFSEL1 VDDIO = 1.8 V VDDIO = 2.0 V VDDIO = 2.5 V VDDIO = 3.0 V VDDIO = 3.3 V 4 5 VDDIO Regulator C17 10uF C18 10uF 8 7 6 5 4 3 2 1 C12 10uF 6.3V ZERO 1/16W TEST_POINT SPKR_RM TP5 SPKR_L TEST_POINT TP4 27 R33 U1 DNP 4 RESETB DNP R12 ZERO 1/16W VDDIO R16 10.0k 1/16W REFCLK 74LVC1G04 4 VDDIO DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 R3 DNP VDDIO +3.3V 1 C8 0.1uF 10V R4 DNP 74LVC1G04 4 VDDIO RESET 17 8 16 57 69 CLKOUT DIR 90 NXT 71 STP 70 96 45 15 31 82 33 83 34 85 36 86 T&MT Connector This portion of the schematic shows components needed for PHY to operate in a HS peripheral application. DATA5 9 5 3 32 VDDIO 31 DIR 30 29 C4 1.0uF 6.3V RESETB REFCLK 3 USB33XX QFN32 VDD18_2 REFSEL1 DNP 3 R15 10.0k 1/16W DNP R14 10.0k 1/16W +3.3V 11 DATA6 10 STP NC 12 25 XO CPEN33 DP DM VDD33 VBAT VBUS ID RBIAS XO 28 VDD18_1 DATA7 13 26 REFCLK 27 RESETB REFSEL2 14 SPK_L 15 SPK_R +5.0V 16 FLAG 33 4 17 18 19 20 21 22 23 24 R35 10.0 CPEN C3 1.0uF 6.3V +5.0V C11 0.1uF 10V 1/16W 5 2 3 4 1 OUTA GND OUTB MAX1823B ONB FAULTB INA IN INB ONA FAULTA U2 10 6 9 8 7 DNP C22 22pF R1 100k 1/10W +3.3V 20k 1/10W R23 1.0k 1W R10 C21 0.1uF 10V 3 4 C23 22pF 2.2uF C1 50V 50V DNP DNP 2 R30 ZERO 1/16W DNP R29 ZERO 1/16W REFSEL0 REFSEL1 REFSEL2 13.0 MHz 19.2 MHz 26.0 MHz 24.0 MHz 110 111 + DNP C24 120uF DNP R13 ZERO 1/16W R13 DNP VBUS_FAULT_N Peripheral Zero Ohm Host / OTG 6 7 8 9 10 11 1 2 3 4 5 Date: Size C Title C16 0.1uF 10V VBUS DM DP ID USBGND P1 DNP VBUS DM DP ID USBGND RESETB CPEN VBUS_FAULT_N CLKOUT A7 A8 A1 A2 B2 B3 A4 A5 B5 B6 B8 B9 A10 A11 B11 B12 A13 A14 B14 B15 A16 A17 B17 B18 A19 A20 A22 A23 B23 B24 A25 A26 B26 B27 B21 B20 DNP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 CK2+ CK2-- CK1+ CK1-- J2 Thursday, April 01, 2010 Document Number SCH-7220AZ-A00 1 PCB7220: USB3340 Evaluation Board STP DATA1 DATA0 DATA3 DATA2 DATA5 DATA4 DATA7 DATA6 DIR NXT P2 VBUS DD+ ID GND SHIELD1 SHIELD2 SHIELD3 SHIELD4 USB mini AB SMD 1 2 3 4 5 6 7 8 9 ULPI Testpoints USB MICRO-AB SHLD1 SHLD2 SHLD3 SHLD4 SHLD5 SHLD6 VBUS DD+ ID GND +3.3V 27.0 MHz 101 12.0 MHz 100 38.4 MHz 001 011 52.0 MHz 000 010 REFSEL[2:0] REFCLK Source 1 For OTG applications, R10 1K resistor should be installed. For peripheral/host applications, R23 20K resistor should be installed. R28 ZERO 1/16W R27 ZERO 1/16W R26 ZERO 1/16W R25 ZERO 1/16W VDDIO Schematic shows 26.0 MHz Configuration. REFCLK[2:0] = 110 For host applications 120 uF to ground is required on VBUS to comply with the USB2.0 specification. C2 0.1uF 10V R2 8.06k GND VDDIO 26 MHz GND VBUS Switch 1/16W R17 1M 1/10W 2 1 Y1 Crystal Support 2 TEK_6960_CONN DM Sheet 1 of 1 3930 East Ray Road Suite 200 Phoenix, Arizona 85044 480-759-0200 Rev D TEST_POINT TP3 TEST_POINT TP2 B1 A27 B25 A12 A24 B22 A9 A21 B19 GND GND GND GND GND GND GND GND GND USB3340 32-pin Evaluation Board 5 3 USER MANUAL 8 GND GND GND GND GND GND GND GND GND Revision 1.1 (12-14-10) B4 B7 B10 B13 A15 A3 B16 A18 A6 5 A B C D EVB-USB3340 USB Transceiver Evaluation Board User Manual 5 USB3340 EVB Schematic Figure 5.1 USB3340 EVB Schematic SMSC USB3340 EVB SMSC USB3340 EVB 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 14 2 3 4 5 6 7 8 9 10 11 12 13 DNP 8 2 3 1 2 0 C24 0 0 J2 1 0 P1 1 1 R3 R4 R12 3 R13 R26 R28 R6 R11 R14 3 R15 R16 1 1 0 R10 1 1 1 1 1 1 5 1 1 2 1 1 1 Item # Quantity 1 1 USER MANUAL 9 R17 R18 R23 R32 R33 R35 TP1 TP2 TP3 U1 U2 U6 U8 U10 X1 Y1 R5 R8 R7 R9 R25 R27 R30 R1 R2 P2 J1 Part Reference C1 C2 C8 C9 C10 C11 C13 C16 C3 C4 C12 C17 C18 C14 C22 C23 RESISTOR 10.0K OHM 1/16W 1% 0402 SMD RESISTOR 27.0K OHM 1/16W 1% 0402 SMD RESISTOR 169K OHM 1/16W 1% 0402 SMD RESISTOR 1.0K OHM 1W 5% 2512 SMD RESISTOR 1MEG OHM 1/10W 5% 0603 RESISTOR 78.7K OHM 1/16W 1% 0402 SMD RESISTOR 20K OHM 1/10W 0.1% 0603 SMD RESISTOR ZERO OHM 1/4W 5% 1206 RESISTOR 27.0 OHM 1/16W 1% 0402 SMD RESISTOR 10.0 OHM 1/16W 1% 0402 SMD TEST POINT USB33XX QFN32 IC SW DUAL USB AUTORESET 10-UMAX MAX1823 INVERTER SINGLE LVC SOT23-5 SN74LVC1G04 IC ADJ 50MA LDO REG SOT-23-5 OSCILLATOR PROG 3.3V +-50PPM SMD CRYSTAL 26.000 MHZ 10PF SMD RESISTOR ZERO OHM 1/16W 5% 0402 SMD CAPACITOR CERAMIC 0.1UF 10V X5R 0402 CAPACITOR CERAMIC 1.0UF 6.3V 20% X5R 040 CAPACITOR CERAMIC 10UF 6.3VDC 20% X5R 08 CAPACITOR CERAMIC 1.0UF 16VDC 10% X5R 06 CAPACITOR CERAMIC 22PF 5% 50V NP0 0402 CAPACITOR AUMINUM ELEC 120UF 10V AMP_T&MT_UTMI+_ULPI COMBO TEK_6960_CONN_DM CONNECTOR RECEPT USB MINI AB 5POS RT ANG CONNECTOR RECEPT MICRO USB TYPE AB SMT RESISTOR 100K OHM 1/10W 5% 0402 SMD RESISTOR 8.06K OHM 1/16W 1% 0402 SMD Description CAPACITOR CERAMIC 2.2UF 50V Y5V 0805 Manuf YAGEO PANASONIC MURATA ERIE PANASONIC PANASONIC AVX United Chemi-Con TYCO TEKTRONIX MOLEX TYCO PANASONIC PANASONIC TDK VISHAY-DALE YAGEO VISHAY-DALE VISHAY-DALE YAGEO VISHAY-DALE PANASONIC YAGEO VISHAY-DALE PANASONIC KEYSTONE SMSC MAX1823BEUB+-ND MAXIM 296-11599-1-ND TI 296-2762-1-ND TI AP3S3EC-ND ABRACON 535-9624-1-ND ABRACON 541-10.0KLCT-ND 311-27.0KLRCT-ND 311-169KLRCT-ND 541-1.0KXCT-ND 311-1.0MGRCT-ND 541-78.7KLCT-ND P20KYCT-ND 311-0.0ERCT-ND 541-27.0LCT-ND P10.0LCT-ND 5015KCT-ND 311-0.0JRCT-ND WM17122CT-ND A97799CT-ND P100KJCT-ND P8.06KLCT-ND PCC2146CT-ND 490-1319-1-ND PCC2225CT-ND PCC2224CT-ND 478-1074-1-ND 565-3066-1-ND A33470-ND Digikey_Number 445-3464-1-ND CRCW040210K0FKED RC0402FR-0727KL CRCW0402169KFKED CRCW25121K00JNEG RC0603JR-071ML CRCW040278K7FKED ERA-3YEB203V RC1206JR-070RL CRCW040227R0FKED ERJ-2RKF10R0X 5015 USB33XX MAX1823BEUB SN74LVC1G04DBVR TPS77001DBVT AP3S-26.0MHz ABM10-26.000MHZ-7A15-T RC0402JR-070RL ECJ-0EB1A104K GRM155R60J105ME19D ECJ-2FB0J106M ECJ-1VB1C105K 04025A220JAT2A APXA100ARA121MH70G 1-1734037-0 P6960DM 56579-0576 1981584-1 ERJ-2GEJ104X ERJ-2RKF8061X Manuf_PN C2012Y5V1H225Z Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes RoHS Yes EVB-USB3340 USB Transceiver Evaluation Board User Manual 6 USB3340 EVB Bill of Materials Figure 6.1 USB3340 EVB Bill of Materials Revision 1.1 (12-14-10) EVB-USB3340 USB Transceiver Evaluation Board User Manual 7 User Manual Revision History Table 7.1 Customer Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY Rev. 1.1 (12-14-10) R9 on Schematic and BOM Rev. 1.0 (05-01-10) Initial Release Revision 1.1 (12-14-10) 10 CORRECTION Changed from 10k to 169k USER MANUAL SMSC USB3340 EVB