C2000 Digital Power Supply One-Day Workshop Student Guide (pdf file)

TI
C28x™ Digital Power Supply Workshop
Workshop Guide and Lab Manual
C28xdps
Revision 1.1
May 2008
Technical Training
Organization
Workshop Topics
Important Notice
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Copyright © 2008 Texas Instruments Incorporated
Revision History
January 2008 – Revision 1.0
May 2008 – Revision 1.1
Mailing Address
Texas Instruments
Training Technical Organization
7839 Churchill Way
M/S 3984
Dallas, Texas 75251-1903
2
C28x Digital Power Supply Workshop
Workshop Topics
Workshop Topics
Workshop Topics.........................................................................................................................................3
Workshop Outline .......................................................................................................................................4
1 – Introduction to Digital Power Supply Design.......................................................................................5
What is a Digital Power Supply?............................................................................................................5
Why use Digital Control Techniques?....................................................................................................6
Peripherals used for Digital Power Supply Design...............................................................................10
Development Tools and Software ........................................................................................................12
Lab1: Exploring the Development Environment.......................................................................................16
2 – Driving the Power Stage with PWM Waveforms ................................................................................24
Open-Loop System Block Diagram......................................................................................................24
Generating PWM using the ePWM Module.........................................................................................25
Power Stage Topologies and Software Library Support.......................................................................28
Lab2: PWM Generation / Open-Loop Control .........................................................................................32
3 – Controlling the Power Stage with Feedback.......................................................................................42
Closed-Loop System Block Diagram ...................................................................................................42
ADC Module Block Diagram...............................................................................................................43
Digital Control of Power Converter .....................................................................................................43
High-Resolution PWM Benefits...........................................................................................................46
Soft Start – Starting the Loop ...............................................................................................................47
Lab3: Closed-Loop Control ......................................................................................................................48
4 – Tuning the Loop for Good Transient Response ..................................................................................57
Digital Power Supply Control Theory ..................................................................................................57
Intuitive Loop Tuning – “Visually without Math” ...............................................................................59
Active Load Feature of the Power EVM ..............................................................................................63
Lab4: Tuning the Loop..............................................................................................................................64
Multi-Loop Control ..............................................................................................................................71
5 – Summary and Conclusion ...................................................................................................................73
Review of Workshop Topics and Exercises .........................................................................................73
TI Digital Power Products ....................................................................................................................74
C2000 Digital Signal Controller Family...............................................................................................75
UCD9xxx Digital Power Controller Family .........................................................................................80
Where to Find More Information .........................................................................................................81
C28x Digital Power Supply Workshop
3
Workshop Outline
Workshop Outline
Workshop Outline
1.
Introduction to Digital Power
Supply Design
Š
2.
Driving the Power Stage with PWM
Waveforms
Š
3.
4
Lab: Closed-Loop Control
Tuning the Loop for Good Transient
Response
Š
5.
Lab: PWM Generation / Open-Loop Control
Controlling the Power Stage with
Feedback
Š
4.
Lab: Exploring the Development Environment
Lab: Tuning the Loop
Summary and Conclusion
C28x Digital Power Supply Workshop
1 – Introduction to Digital Power Supply Design
1 – Introduction to Digital Power Supply Design
Introduction to Digital Power Supply Design
‹
‹
‹
‹
What is a Digital Power Supply?
Why use Digital Control
Techniques?
Peripherals used for Digital Power
Supply Design
Development Tools and Software
What is a Digital Power Supply?
What is Digital Power?
Generic Power System Block Diagram
Vin
Controller
(Compensator)
PWM
Switches
(FETs)
LC
Network
Vout
The controller block is what differentiates between a digital
power system and a conventional analog power system
C28x Digital Power Supply Workshop
5
1 – Introduction to Digital Power Supply Design
Why use Digital Control Techniques?
Why Digital Control Techniques?
Controller
Power Elec.
PWM
Analog
or
Digital ??
Sensor(s)
Analog Controller
+
Digital Controller
‹
High bandwidth
High resolution
‹ Easy to understand / use
‹ Historically lower cost
‹
‹
‹
‹
Component drift and aging / unstable
Component tolerances
‹ Hardwired / not flexible
‹ Limited to classical control theory only
‹ Large parts count for complex systems
‹
‹
‹
Insensitive to environment (temp, drift,…)
S/w programmable / flexible solution
Precise / predictable behavior
‹ Advanced control possible (non-linear, multi-variable)
‹ Can perform multiple loops and “other” functions
‹
Bandwidth limitations (sampling loop)
PWM frequency and resolution limits
‹ Numerical problems (quantization, rounding,…)
‹ AD / DA boundary (resolution, speed, cost)
‹ CPU performance limitations
‹ Bias supplies, interface requirements
Benefits of Digital Control
V
Filter
Bridge
I
Inrush/
Hot-plug
Control
V
PFC
DC/DC
VI
8
4
5
1
V
V
I
Multi-mode
Multi-mode
Power control
control
Power
Interface
Circuit
Monitor
MCU
MCU
(MCU)
(MCU?)
Output
Traditional Analog
Power Supply
DC/DC
DC/DC
Current/Load
Current/Load
Converter
Converter
Sharing
Sharing
Control
Control
Control
Control
PFC Control
I
Supervisory
Supervisory
Housekeeping
Housekeeping
Circuits
Circuits
„
Multiple chips for
control
„
Micro-controller for
supervisory
„
Dedicated design
To Host
Aux P/S
Eliminate Components
Filter
Bridge
V
PFC
DC/DC
V
Output
Reduce Manufacturing Cost
Better Performance Across Corners
One Design, Multiple Supplies
Failure Prediction
Aux P/S
Digital controller enables multi-threaded applications
6
One Device, Multiple DC Outputs
Variable DC Output
C28x Digital Power Supply Workshop
1 – Introduction to Digital Power Supply Design
Analog Control System
R
+
Σ
-
“Analog Computation”
Differential equations
e
C
P
(controller)
(plant)
Y
C
C2
C1
R
Energy
Storage
Elements
R
R2
R
R1
C ( s) =
L
d 3 y (t )
d 2 y (t )
dy(t )
+ k2
+ k1
+k 0 y (t ) = f (t )
3
dt
dt 2
dt
R2 ⎛ 1 + R1C1s ⎞
⎜
⎟
R1 ⎜⎝ 1 + R2C2 s ⎟⎠
Differential equations
1st, 2nd, 3rd,…order
Need to find:
R1, R2, C1, C2
Laplace Transform
Digital Control System
R
+
Σ
-
E
Cd
U
(controller)
D-A
P
ZOH
(plant)
Y
A-D
S&H
Difference equation
C
U(n) = a2 ⋅U(n − 2) + a1 ⋅U(n −1) +
R
b2 ⋅ E(n − 2) + b1 ⋅ E(n −1) + b0 ⋅ E(n)
L
whereK E(n) = R(n) − Y (n)
Need to find:
a1, a2, b0, b1, b2
d 3 y (t )
d 2 y (t )
dy(t )
+ k2
+ k1
+k 0 y (t ) = f (t )
3
dt
dt 2
dt
Differential equations
1st, 2nd, 3rd,…order
OR
C28x Digital Power Supply Workshop
Energy
Storage
Elements
Laplace Transform
Z Transform
7
1 – Introduction to Digital Power Supply Design
Time Sampled Systems
Digital Processor
-
A-D
+
Control
Law
Σ
D-A
Ref
y(t)
y(n)
sample
period
T
t
Continuous
time signal
u(n)
u(t)
t
t
t
Discrete
time signal
Processor Bandwidth
y(n)
TSAMPLE
t
Processor
Control Code
Sam ple Freq (=PW M)
(kHz )
100
300
500
700
1000
1500
2000
8
Control Code
Control
Sa mple Period
(ns )
10000
3333
2000
1429
1000
667
500
C28x Digital Power Supply Workshop
1 – Introduction to Digital Power Supply Design
Time Division Multiplexing (TDM)
y(n)
TSAMPLE
t
Processor 1
Control Code (C1)
Processor 2 Control Code (C2)
Processor 3
Single CPU
Control Code (C3)
C1
C2
C3
Control Code
Control Code
Control
Control Code
C1
C2
Control
Control
C3
C1
C2
C3
Digitally Controlled Power Supply
DAC
DSC
(PWM)
ADC
0110101100
1011011101
0010100111
C28x Digital Power Supply Workshop
“Plant”
“High fidelity”
Translation boundary
9
1 – Introduction to Digital Power Supply Design
System Mapping
PFC – 3ph Interleaved
F280xx
DSP
Ch1
Ch2
ADC
32 bit core
60~100
MHz
VO UT
Vin
12 bit
(80nS)
Ch16
1A
ePWM1
1B
Phase-Shifted Full Bridge
2A
ePWM2
2B
3A
ePWM3
V OUT
VIN
3B
8A
ePWM8
8B
Peripherals used for Digital Power Supply Design
TMS320F280x
High Performance DSP (C28x
Code security
ƒ
64Kw Flash
+ 1Kw OTP
18Kw
RAM
4Kw
Boot
ROM
ƒ
ePWM
eCAP
Memory Bus
TM
100 MIPs C28x 32-bit DSP
32x32-bit
Multiplier
32-bit
Timers (3)
Real-Time
JTAG
R‚M‚W
Atomic
ALU
Peripheral Bus
Interrupt Management
eQEP
12-bit ADC
Watchdog
ƒ
Core)
100MIPS performance
Single cycle 32 x32-bit MAC (or dual 16 x16 MAC)
Very Fast Interrupt Response
Single cycle read-modified-write
Memory Sub-System
Fast program execution out of both RAM and
Flash memory
ƒ 85 MIPS with Flash Acceleration Technology
ƒ 100 MIPS out of RAM for time-critical code
Control Peripherals
CAN 2.0 B
I2C
SCI
32-bit
Register
File
ƒ
TM
SPI
Up to 6 ePWM, 4 eCAP, and 2 eQEP
Ultra-Fast 12-bit ADC
ƒ 6.25 MSPS throughput
ƒ Dual sample&holds enable simultaneous sampling
ƒ Auto Sequencer, up to 16 conversions w/o CPU
Communications Ports
GPIO
Multiple standard communication ports provide
simple interfaces to other components
Datasheet available at: http://www-s.ti.com/sc/ds/tms320f2808.pdf
10
C28x Digital Power Supply Workshop
1 – Introduction to Digital Power Supply Design
Efficient 32-bit Processor Capability
C28xTM DSP Core
Interrupt Management
C28x
TM
ƒ Single-cycle 32-bit multiplier makes
computationally intensive control
algorithms more efficient
ƒ Three 32-bit timers support multiple
control loops / time bases
ƒ Single cycle read-modified-write in any
memory location and 32-bit registers
improve control algorithm efficiency
ƒ Real-time JTAG debug shortens
development cycle
ƒ Fast & flexible interrupt management
significantly reduce interrupt latency
32-bit DSP
32x32 bit
Multiplier
R‚M‚W
Atomic
ALU
32-bit
Timers (3)
32-bit
Register
File
Real-Time
JTAG
# Instructions vs PWM
PWM freq. PWM per. Processor MIPS
(kHz)
(μs)
100
150
50
20.0
2000
3000
100
10.0
1000
1500
200
5.0
500
750
250
4.0
400
600
300
3.3
333
500
500
2.0
200
300
750
1.3
133
200
1000
1.0
100
150
TPWM
PWM
CPU
Control Code spare Control Code spare
Control
MIPS = Million Instruction Per Second
ePWM “DAC” Capability
ePWM
Counter
Compare
Action
Qualifier
Time-Base
Control Peripherals
Event
Trig.
& Int.
Trip
Zone
Dead
Band
PWM
Chop
EPWMxA
EPWMxB
PWM effective resolution (CPU=100MHz)
PWM
(kHz)
50
100
150
250
500
750
1000
Standard PWM
bits
%
11.0
0.05
10.0
0.10
9.4
0.15
8.6
0.25
7.6
0.50
7.1
0.75
6.6
1.00
C28x Digital Power Supply Workshop
HR-PWM
bits
%
17.0
0.0007
16.0
0.0015
15.4
0.0022
14.7
0.0037
13.7
0.0075
13.1
0.0112
12.7
0.0150
ePWM
ƒ Number of channels scalable
and resources allocated per
channel
ƒ Two independent PWM outputs
per module
ƒ Dedicated time-base timer
ƒ Two independent compare
registers
ƒ Multi-event driven waveform
ƒ Trip zones and event interrupts
ƒ F2808 offers 6 modules
ƒ Provides ePWM DAC capability
for DPS
ƒ Switching can be programmed
as Asymmetric or Symmetric
PWM
ƒ High-Resolution PWM mode
11
1 – Introduction to Digital Power Supply Design
12-bit ADC Capability
ADC
SYSCLK
Prescaler
8 ADC
Inputs
Analog
MUX
8 ADC
Inputs
Analog
MUX
S/H
A
12-bit
ADC
Module
S/H
B
Start of
Conversion
Result
Registers
16 words
Control Peripherals
Fast & Flexible
12-bit 16-Channel ADC
ƒ 12.5 MSPS throughput
ƒ Dual sample/hold enable
simultaneous sampling or
sequencing sampling modes
Auto Sequencer
ƒ Analog input: 0V to 3V
ADC Utilization:
# Channels (“Loops”) vs. PWM frequency
MSPS = 3
PWM
# Channels
(kHz)
125
24
250
12
500
6
750
4
1000
3
MSPS = 6.25
PWM
# Channels
(kHz)
125
50
250
25
500
13
750
8
1000
6
ƒ 16 channel, multiplexed inputs
ƒ Auto Sequencer supports up to 16
conversions without CPU
intervention
ƒ Sequencer can be operated as two
independent 8-state sequencers or
as one large 16-state sequencer
ƒ Sixteen result registers (individually
addressable) to store conversion
values
Development Tools and Software
Code Composer Studio
Menus or Icons
Help
CPU
Window
Project Manager:
¾Source & object files
¾File dependencies
¾Compiler, Assembler &
Linker build options
Full C/C++ & Assembly
Debugging:
¾C & ASM Source
¾Mixed mode
¾Disassembly (patch)
¾Set Break Points
¾Set Probe Points
Editor:
¾Structure
Expansion
Status
Window
12
Watch Window
Graph
Window
Memory Window
C28x Digital Power Supply Workshop
1 – Introduction to Digital Power Supply Design
Software Library Approach
CNTL
2P2Z
CNTL
3P3Z
Ref
Ref
Uout
FB
Control 2-pole / 2-zero
Buck
Single
DRV
E
P
W
M
Duty
H
W
HR
Buck
Single
DRV
Uout
FB
Control 3-pole / 3-zero
EPWMnA
Duty
Buck Single Output
IIR-FILT
2P2Z
IIR-FILT
3P3Z
f
In
MPIL
DRV
f
Out
In
2nd order IIR filter
E
P
W
M
Out
PFC
2PHIL
DRV
EPWM1A
EPWM1B
EPWM2A
Duty
Adj
H
W
SGenHP1
Freq
F req
Gain
Out
HHB
DRV
Gain
Offset
Out
Duty
Offset
Sine Wave generator
High precision Sine Gen
IBM
FB
DRV
E
P
W
M
H
W
EPWMnA
In
EPWMnB
D elLL
D elRL
Half H-Bridge
INV
SQ R
PSFB
DRV
Out
Delay
E
P
W
M
Phase
Slope
Inverse Square function
E
P
W
M
EPWMnA
H
W
EPWMnB
E
P
W
M
H
W
EPWMnA
EPWMnB
EPWM(n+1)A
EPWM(n+1)B
IBM method Full Bridge
SSartSEQ
In
EPWMnA
Power Factor 2-phase
Interleaved
Multi-Phase Interleaved
SinGen1
H
W
High Resolution Buck
EPWM2B
Duty
3rd order IIR filter
E
P
W
M
Out
Llegdb
T arget
Rlegdb
Soft Start and Sequencing
H
W
EPWMnA
ADC
DRV
EPWMnB
EPWM(n+1)A
Rslt
EPWM(n+1)B
A
D
C
Ch0
Ch1
Ch3
Ch4
H
W
Analog-Digital Converter driver
Phase Shifted Full Bridge
Modular Software Architecture
“Signal Net” based module connectivity
Net1
In 1A
Net2
In 1B
f1
O ut1
Net6
f2
Net3
In 2A
In 3A
Net7
In4A
In4B
Out4
Net8
f5
In5A
Out5
Net9
O ut3
Initialization time
// pointer & Net declarations
Int *In1A, *In1B, *Out1, *In2A,...
Int Net1, Net2, Net3, Net4,...
// “connect” the modules
In1A=&Net1; In1B=&Net2; In2A=&Net3; In3A=&Net4; // inputs
Out4=&Net8; Out5=&Net9;
// outputs
Out1=&Net5; In4A=&Net5;
// Net5
Out2=&Net6; In4B=&Net6;
// Net6
Out3=&Net7; In4C=&Net7; In5A=&Net7;
// Net7
C28x Digital Power Supply Workshop
f4
In4C
O ut2
f3
Net4
Net5
Run time - ISR
; Execute the code
f1
f2
f3
f4
f5
13
1 – Introduction to Digital Power Supply Design
Peripheral Drivers
CPU dependency only:
• Math / algorithms
• Per-Unit math (0-100%)
• Independent of Hardware
BUCK
DRV
CNTL
2P2Z
Vref
Ref
(Q15)
Out
Fdbk
Duty
ADC
SEQ1
DRV
Vout
Rslt0
(Q15)
E
P
W
M
H
W
In
(Q15)
A
D
C
H
W
// pointer & Net declarations
int *CNTL_Ref1, *CNTL_Fdbk1, *CNTL_Out1;
int *BUCK_In1, *ADC_Rslt1;
int Vref, Duty, Vout;
Depends on:
• PWM frequency
• System clock frequency
EPWM1A
ADC_A0
ADC_A1
ADC_A2
ADC_A3
Depends on:
• # ADC bits (10 / 12 ?)
• Unipolar, Bipolar ?
• Offset ?
// “connect” the modules
CNTL_Ref1 = &Vref;
CNTL_Out1 = &Duty; BUCK_In1 = &Duty;
CNTL_Fdbk1 = &Vout; ADC_Rslt1 = &Vout;
Dual Buck Example
BG
ISR
Start / Stop trigger
Voltag e
Contro ller
S-start / SEQ
V ref1
CNTL
2P2Z
Ref
FB
Uout
DutyCmd 1
BUCK
DRV
E
P
W
M
Duty
H
W
Single Power Stage
Vin
EPWM1A
Vout1
DRV
B uck
400 kHz
400 kHz
ADC
DRV
Vout1
rslt0
A
D
C
H
W
Ch0
400 kHz
Voltag e
Contro ller
S-start / SEQ
V ref2
CNTL
2P2Z
Ref
Uout
DutyCmd 2
FB
BUCK
DRV
E
P
W
M
Duty
H
W
Single Power Stage
Vin
EPWM2A
Vo ut2
DRV
B uck
400 kHz
400 kHz
ADC
DRV
Vout2
rslt0
A
D
C
H
W
Ch1
400 kHz
14
C28x Digital Power Supply Workshop
1 – Introduction to Digital Power Supply Design
Software Block Execution
BG
ISR
(400 kHz)
SStartSeq
Context Save
Comms
ADC_DRV (1)
CNTL_2P2Z(1)
Loop-1
BUCK_DRV (1)
ISR body
ADC_DRV (2)
CNTL_2P2Z(2)
Loop-2
Other....
BUCK_DRV (2)
Context
Restore
C28x Digital Power Supply Workshop
15
Lab1: Exploring the Development Environment
Lab1: Exploring the Development Environment
¾ Objective
The objective of this lab exercise is to demonstrate the topics discussed in this module and
become familiar with the operation of Code Composer Studio (CCS). Steps required to build and
run a project will be explored. The project will generate various PWM waveforms which will be
viewed using the CCS graphical capabilities. The slider feature in CCS will be used to adjust the
duty, phase, and dead-band values of the waveforms. Additionally, the Digital Power software
framework, associated files, and library modules will be used.
Lab1: Exploring the Development Environment
‹
‹
‹
Navigate CCS features
Understand DPS library structure
Generate and visualize PWM waveforms
ƒ
ƒ
ƒ
ƒ
ƒ
TI PowerTrain
PTD08A010W
10A module
SW1
Phase Links
Current meas.
Temp meas
Over Current Prot.
Over Current Flag
No Heat-sink needed
Active
Load LEDs
Volt
Meter
controlCard 2808
¾ Project Overview
The PWMexplore project makes use of the “C-background/ASM-ISR” framework. This
framework will be used throughout all the lab exercises in this workshop. It uses C-code as the
main supporting program for the application, and is responsible for all system management tasks,
decision making, intelligence, and host interaction. The assembly code is strictly limited to the
ISR, which runs all the critical control code and typically this includes ADC reading, control
calculations, and PWM updates.
The key framework C files used in this project are:
PWMexplore-Main.c – this file is used to initialize, run, and manage the application. This is
the “brains” behind the application.
PWMexplore-DevInit.c – this file is responsible for a one time initialization and
configuration of the F280x device, and includes functions such as setting up the clocks, PLL,
GPIO, etc.
16
C28x Digital Power Supply Workshop
Lab1: Exploring the Development Environment
The ISR consists of a single file:
PWMexplore-ISR.asm – this file contains all time critical “control type” code. This file has
an initialization section (one time execute) and a run-time section which executes (typically) at
the same rate as the PWM timebase used to trigger it.
The Power Library functions (modules) are “called” from this framework. Library modules may
have both a C and an assembly component. In this lab exercise, six library modules (all PWM
waveform generators or drivers) are used. The C and corresponding assembly module names are:
C configure function
ASM initialization macro
ASM run-time macro
BuckSingle_CNF()
BuckSingle_DRV_INIT n
BuckSingle_DRV
BuckDual_CNF()
BuckDual_DRV_INIT n
BuckDual_DRV
MPhIL_CNF()
MPhIL_DRV_INIT n, N
MPhIL_DRV
FullBridgePS_CNF()
FullBridgePS_DRV_INIT n
FullBridgePS_DRV
n
n
n, N
n
FullBridgeIBM_CNF() FullBridgeIBM_DRV_INIT n
FullBridgeIBM_DRV n
PFC2PhIL_CNF()
PFC2PhIL_DRV_INIT n
PFC2PhIL_DRV_INIT n
These blocks can also be represented graphically. This helps visualize the system software flow
and function input/output. The PWM driver modules used in Lab1 are:
C28x Digital Power Supply Workshop
17
Lab1: Exploring the Development Environment
¾ Lab Exercise Overview
The software in Lab1 has been configured so the user can quickly evaluate the 6 PWM driver
modules by viewing the output waveforms and interactively adjusting the duty, phase, and
deadband values. The graphing feature of CCS is used to visualize the waveform. The ADC
peripheral is configured to provide a “scope” capture function. The PWM outputs on the buck
EVM are directly connected to ADC inputs via zero ohm resistors. Collected data samples are
stored in four separate memory buffers, hence a simple 4-channel scope is realized. CCS can link
each memory buffer to a graph window and display the captured data. With the real-time feature
enabled, this data can be captured at high speed and streamed back via JTAG (at a slower rate) to
update the graph windows periodically (~200 ms update rate).
Since the PWM waveforms being sampled are essentially “square waves” (high speed edges) they
have been scaled down in frequency to approximately 10 kHz. This allows the ADC sampling to
better capture and display the edge transitions in the graph window during datalogging. As Lab1
is more for visual demonstration purposes, the high speed ISR code subroutine _ISR_Run has
been allocated to datalogging. The PWM driver macros are running at a much slower update rate
from subroutine _ISR_Pseudo, which is conveniently called directly from C. The PWM driver
macro instantiation convention however is still the same as in the more typical case where
_ISR_Run is used to execute all PWM updates and loop control. This will be the convention
used in Labs 2, 3 and 4 where an actual 2-channel buck stage will be controlled with high speed
PWM outputs.
The following diagram shows an example of how the Full Bridge Phase Shifted PWM module is
evaluated in this lab. This setup is essentially the same for all 6 cases, except the PWM driver
macro module is swapped and the appropriate sliders used to adjust the relevant timing are
selected.
18
C28x Digital Power Supply Workshop
Lab1: Exploring the Development Environment
¾ Procedure
Start CCS and Open a Project
1. Move the switch SW1 to the “on” position to power the 2-channel buck EVM board.
2. Double click on the Code Composer Studio icon on the desktop. Maximize Code
Composer Studio to fill your screen. Code Composer Studio has a Connect/Disconnect
feature which allows the target to be dynamically connected and disconnected. This will
reset the JTAG link and also enable “hot swapping” a target board. Connect to the target.
Click: Debug Æ Connect
The menu bar (at the top) lists File ... Help. Note the horizontal tool bar below the menu
bar and the vertical tool bar on the left-hand side. The window on the left is the project
window and the large right hand window is your workspace.
3. A project contains all the files and build options needed to develop an executable output
file (.out) which can be run on the DSP hardware. A project named Lab1.pjt has
been created for this lab exercise. Open the project by clicking:
Project Æ Open…
and look in C:\C28x_DPS\LABS\LAB1. This project (.pjt file) will invoke all the
necessary tools (compiler, assembler, linker) to build the project. It will also create a
folder that will hold immediate output files.
4. In the project window on the left, click the plus sign (+) to the left of Project. Now,
click on the plus sign next to Lab1.pjt. Click on the plus sign next to Source to see
the current source file list.
5. A GEL file can be used to create a custom GEL menu and automate steps in CCS. A
GEL file which will setup sliders has been created for this lab exercise. The slider will be
used to adjust the duty, phase, and dead-band values of the waveforms. Load the
PWMexplore.gel file by clicking:
File Æ Load Gel…
and look in C:\C28x_DPS\LABS\LAB1.
Device Initialization, Main, and ISR Files
Note: DO NOT make any changes to the source files – ONLY INSPECT
6. Open and inspect PWMexplore-DevInit.c by double clicking on the filename in the
project window. Notice that system clock, peripheral clock prescale, and peripheral
clock enables have been setup. Next, notice that the shared GPIO pins have been
configured.
C28x Digital Power Supply Workshop
19
Lab1: Exploring the Development Environment
7. Open and inspect PWMexplore-Main.c. Notice the background for(;;) loop and
the case statements. This is where each of the PWM configuration functions are called
for the 6 cases previously described. The case statement provides a convenient way to
showcase each PWM driver quickly and interactively for demonstration purposes.
8. Open and inspect PWMexplore-ISR.asm. Notice the _ISR_Init and
_ISR_Pseudo sections. This is where the PWM driver macro instantiation is done for
initialization and runtime, respectively. Optionally, you can close the inspected files.
Build and Load the Project
9. The top four buttons on the horizontal toolbar control code generation. Hover your
mouse over each button as you read the following descriptions:
Button
1
2
3
4
Name
Description
Compile File
Incremental Build
Rebuild All
Stop Build
Compile, assemble the current open file
Compile, assemble only changed files, then link
Compile, assemble all files, then link
Stop code generation
10. Code Composer Studio can automatically load the output file after a successful build. On
the menu bar click: Option Æ Customize… and select the
“Program/Project/CIO” tab, check “Load Program After Build”.
Also, Code Composer Studio can automatically connect to the target when started. Select
the “Debug Properties” tab, check “Connect to the target at
startup”, then click OK.
11. Click the “Rebuild All” button and watch the tools run in the build window. The
output file should automatically load.
12. Under Debug on the menu bar click “Reset CPU”, “Restart”, and then “Go
Main”. You should now be at the start of Main().
Debug Environment Windows
It is standard debug practice to watch local and global variables while debugging code. There
are various methods for doing this in Code Composer Studio, such as memory windows and
watch windows. Additionally, Code Composer Studio has the ability to make time (and
frequency) domain plots. This allows us to view waveforms using graph windows. We will
use two of them here: watch windows and graph windows.
13. Open the watch window to view the variables used in the project.
Click: View Æ Watch Window on the menu bar.
Click the “Watch 1" tab at the bottom of the watch window. In the empty box in the
"Name" column, type the symbol name “ConfigOption” and press enter on
keyboard. Next add the following other symbol names: “Duty1”, “Duty2”,
20
C28x Digital Power Supply Workshop
Lab1: Exploring the Development Environment
“Phase”, “DbLeft”, and “DbRight”. The watch window should look something
like:
14. Open and setup two dual time graph windows to plot the four data log buffers A, B, C
and D (ADC result registers). Click: View Æ Graph Æ Time/Frequency… and
set the following values:
Select OK to save the graph options.
Saving the Workspace Environment
The workspace contains all of the elements that make up the current Code Composer Studio
working environment. These elements include the project, project settings, configuration settings,
and windows such as watch window and graphs. A workspace can be saved in a workspace file
(*.wks) and reloaded at a later time. This is very useful for a subsequent Code Composer Studio
session, or if a problem occurs and the tools need to be reset.
15. Save the current workspace by naming it Lab1.wks and clicking:
File Æ Workspace Æ Save Workspace As…
C28x Digital Power Supply Workshop
21
Lab1: Exploring the Development Environment
and saving in C:\C28x_DPS\LABS\LAB1.
When needed, a workspace can be loaded by clicking:
File Æ Workspace Æ Load Workspace…
and looking in the saved location.
Using Real-time Emulation
Real-time emulation is a special emulation feature that allows the windows within Code
Composer Studio to be updated at up to a 10 Hz rate while the DSP is running. This not only
allows graphs and watch windows to update, but also allows the user to change values in
watch or memory windows, and have those changes affect the DSP behavior. This is very
useful when tuning control law parameters on-the-fly, for example.
16. Enable real-time mode by selecting:
Debug Æ Real-time Mode
17. A message box may appear. If so, select YES to enable debug events. This will set bit 1
(DGBM bit) of status register 1 (ST1) to a “0”. The DGBM is the debug enable mask bit.
When the DGBM bit is set to “0”, memory and register values can be passed to the host
processor for updating the debugger windows.
18. The graph windows should be open. In real-time mode, we would like to have our
window continuously refresh. Click:
View Æ Real-time Refresh Options…
and check “Global Continuous Refresh”. Use the default refresh rate of 100
ms and select OK. Alternately, we could have right clicked on each window individually
and selected “Continuous Refresh”.
Note: “Global Continuous Refresh” causes all open windows to refresh at the
refresh rate. This can be problematic when a large number of windows are open, as
bandwidth over the emulation link is limited. Updating too many windows can cause the
refresh frequency to bog down. In that case, either close some windows, or disable
global refresh and selectively enable “Continuous Refresh” for individual
windows of interest instead.
Run the Code – PWMexplore
19. Run the code by using the <F5> key, or using the Run button on the vertical toolbar, or
using Debug Æ Run on the menu bar. The top graph window should display two
PWM waveforms generated by the two BuckSingle macros.
20. In the watch window, the variable ConfigOption should be set to 1. This option or
case selects the BuckSingle macro (actually there are two of them) as the active waveform generator. Change the option to 2, and examine the waveforms for the BuckDual.
22
C28x Digital Power Supply Workshop
Lab1: Exploring the Development Environment
Next, try the other options. Below is a list of the active PWM driver macro for each selected ConfigOption:
1
2
3
4
5
6
BuckSingle
BuckDual
MPhIL
FullBridgePS
FullBridgeIBM
PFC2PhIL
(uses 2 single buck modules)
(Multi-Phase Interleaved)
(Phase-shifted full bridge)
(IBM method Full bridge)
(2 phase Interleaved PFC)
21. Select the BuckSingle again (ConfigOption = 1). Open sliders D1Slider,
D2Slider and TrigSlider by using GEL Æ PWM explore Sliders Æ and move
the sliders into the workspace area. The D1Slider and D2slider control the duty cycle of
each BuckSingle. The TrigSlider works by moving a trigger point similar to a trigger on
an oscilloscope, and permits the waveform to be viewed more conveniently. Note, when
adjusting the sliders the actual value in the watch window also changes. The value can
be changed by directly editing the watch window, but the slider position will not be updated.
22. Next, select FullBridgePS (ConfigOption = 4). Open sliders PhaseSlider,
DbLSlider, and DbRSlider (GEL Æ PWM explore slidersÆ). The PhaseSlider
controls the phase relationship between the left and right legs of the full bridge. The
DbLslider and DbRSlider control the deadband of left leg and right leg, respectively.
23. Fully halting the DSP when in real-time mode is a two-step process. First, halt the processor by using Shift <F5>, or using the Halt button on the vertical toolbar, or by using
Debug Æ Halt. Then click Debug Æ Real-time Mode and uncheck the
“Real-time mode” to take the DSP out of real-time mode.
24. If time permits, evaluate the other PWM macro drivers. The D1Slider is used to adjust
duty in ConfigOptions 3, 5, and 6. The LLdelSlider (left-leg delay) and LRdelSlider
(right-leg delay) is used to adjust the delay between bottom falling edge to top rising edge
for left and right full bridge legs, respectively in ConfigOption 5.
25. Close Code Composer Studio and turn off the power (SW1) to the 2-channel buck EVM.
End of Exercise
C28x Digital Power Supply Workshop
23
2 – Driving the Power Stage with PWM Waveforms
2 – Driving the Power Stage with PWM Waveforms
Driving the Power Stage with PWM Waveforms
‹
‹
‹
Open-Loop System Block Diagram
Generating PWM using the ePWM
Module
Power Stage Topologies and
Software Library Support
Open-Loop System Block Diagram
Simple Open-Loop Diagram
HR
BUCK
DRV
Watch Window
Duty1
Duty1
Single Power Stage
E
P
W
M
In
H
W
ADC
1CH
DRV
A
D
C
Vin1
EPWMnA
DRV
Vout1
Buck
Duty2
Duty3
Duty1
slider
24
Vfdbk
Vout1
Rslt
H
W
Ch0
C28x Digital Power Supply Workshop
2 – Driving the Power Stage with PWM Waveforms
Generating PWM using the ePWM Module
Scaleable PWM Peripherals
Each peripheral module has the same structure
xSYNCI
SYNCI
EPWM1INTn
EPWM1
Module
EPWM1SOC
EPWM1AO
‰ Resources allocated on a per channel basis
EPWM1BO
‰ Each channel (module) supports 2
independent PWM outputs (A&B)
SYNCO
xSYNCO
‰ # Channels easily scaleable – software reuse
‰ Time-base synch feature for all channels
SYNCI
EPWM2INTn
PIE
EPWM2
Module
EPWM2SOC
EPWM2AO
GPIO
Mux
EPWM2BO
‰ 6 modules (12 PWM outputs) on F2808
‰ Key features:
SYNCO
‰Phase & edge control
‰New counting modes
SYNCI
EPWM6INTn
EPWM6
Module
EPWM6SOC
EPWM6AO
‰Independent deadband
EPWM6BO
‰Flexible trip-zones
TZ1n to TZ6n
‰High frequency chopper mode
SYNCO
SOC
xSOC
ADC
VBus32
to ECAP1 module (sync in)
ePWM Module Block Diagram
T im e -B a s e (T B )
T B PR D S h ad o w (16)
C TR = Z E R O
T B P R D A c ti v e (1 6 )
CT R=CMP B
S yn c
In / O u t
S e le ct
M ux
D i sa b le d
S0
E PW M xS Y N C O
S1
C T R = PR D
T B CT L[ S Y N C O S E L ]
16
E P W M x S YN C I
C o u n ter
UP / D W N
(1 6 b i t)
TBC NT
A c t iv e (1 6 )
T B CT L [S W F S Y N C]
(so ft w a re f orce d sy nc)
T B C T L [ CN T L D E ]
C TR =ZE R O
C T R _ D ir
16
T B PH S A c ti v e ( 1 6 )
Ph a se
C o n tr o l
C T R = PR D
E P W M x IN T n
CT R=Z E RO
CT R=CMPA
C o u n ter C o m p a r e (C C )
CT R=CMPB
E v en t
T rig g e r &
In t e rr u p t
(E T )
EP W M xS O C A
EP W M xS O C B
C T R _ D ir
16
C TR =C M P A
A c tio n
Q ua l i fie r
(A Q )
16
16
E P W M xA O
E PWM A
C M P A A c ti ve ( 1 6 )
C M P A S h ad o w (16)
D ead
Ban d
(D B )
PW M
Choppe r
(P C )
T rip
Z on e
( TZ )
CT R=CMP B
E P W M xB O
E PWM B
16
C M P B A c ti ve ( 1 6 )
C M P B S h ad o w (16)
C28x Digital Power Supply Workshop
E PW M xT Z I N T n
T Z 1n to T Z 6 n
C TR =ZE R O
25
2 – Driving the Power Stage with PWM Waveforms
Module Sync and Phase Control
TBCTR
FFFFh
Master Module
Ext Sync In
(optional)
Master
600
TBPRD
Phase Reg
En
600
SyncIn
Φ = 0ο
EPWM1A
CNT=Zero
CNT=CMPB
EPWM1B
X
1
0000
CTR=Zero
(SycnOut)
SyncOut
time
TBCTR
Φ2
FFFFh
Phase = 120o
Slave Module
Slave
Φ=Ξ
600
SyncIn
En
ο
EPWM2A
X
200
TBPHS
CNT=Zero
CNT=CMPB
2
600
TBPRD
Phase Reg
EPWM2B
200
0000
SyncOut
SyncIn
time
Action Qualifier Module (AQ)
Key Features
‰
‰
‰
‰
‰
‰
TBCTR = Period
Multi event driven waveform generator
Events drive outputs A and B independently.
Full control on waveform polarity
Full transparency on waveform construction
S/W forcing events supported
All events can generate interrupts & ADC SOC
EPWMA
Action
Qualifier
Module
(AQ)
TBCT R = Zero
TBCTR = Co mpare A
TBCTR = Co mpare B
EPWMB
SW force
TBCTR Directio n
Events
Zero
Actions
Nothi ng
Clear Lo
Set Hi
Z
Z
Z
(ZRO)
TBCTR
(Up)
equals:
CMPA
CA
CA
CA
(CAu)
CMPB
Period
CA
T
CB
CB
CB
CB
TBCTR
P
P
P
P
CA
CA
CA
CA
CB
CB
CB
CB
SW
SW
SW
SW
(CAd)
CMPB
CAu
CMPA
CBd
CAd
ZRO
Zero
T
(CBd)
S/W force
CBu
CMPB
T
CMPA
PRD
Period
T
(PRD)
26
Z
T
(CBu)
TBCTR
(Down)
equals:
Toggle
T
T
C28x Digital Power Supply Workshop
2 – Driving the Power Stage with PWM Waveforms
Simple Waveform Construction
TBCT R
T B PR D
val ue
Z
P
CB
CA
Z
P
CB
CA
Z
P
Z
P
CB
CA
Z
P
CB
CA
Z
P
EPWMA
EPWMB
TB CT R
TB PR D
v a lu e
CA
CB
CA
CB
EPWMA
Z
Z
Z
T
T
T
EPWMB
Fault Management Support
Vin
‘2808
EPW M1A
Iin
EPW M2A
TZ1
TZ2
TZ3
CL2
I1
CL1
EPW M2B
ECAP1
Iin
EPW M1A
Bu ck # 1
I1
Hi Z
I2
ShutDown
EPW M1B
Vout1
IsetC L1
Vout2
Action on
Fault
EPW M2A
Bu ck # 2
I2
Hi Z
IsetC L2
IsetSD
IsetS D
Iin
Trip Zones:
I1
IsetCL1
6 independent zones (TZ1~TZ6)
I2
IsetCL2
Force High, Low or HiZ on trip
One-time trip Æ catastrophic failure
EPWM1A
Cycle-by-cycle Æ current limit mode
TZ1~TZ6 can trigger interrupt
C28x Digital Power Supply Workshop
EPWM2A
27
2 – Driving the Power Stage with PWM Waveforms
Power Stage Topologies and Software Library Support
Multi-Phase Interleaved (MPI)
E xt Syn c In
(o ptiona l)
Master
Phase Reg
En
SyncIn
Φ = 0ο
EPWM1A
CNT=Zero
CNT=CMPB
Vin
EPWM1B
X
1
SyncOut
EPWM1A
EPWM2A
EPWM3A
Slave
Phase Reg
En
SyncIn
Φ = 120ο
EPWM2A
CNT=Zero
EPWM2B
CNT=CMPB
X
2
Vout
SyncOut
EPWM1B
EPWM2B
EPWM3B
Slave
Phase Reg
En
SyncIn
Φ = 240ο
EPWM3A
CNT=Zero
CNT=CMPB
X
3
EPWM3B
SyncOut
Switching Requirements – MPI
P
P
P
I
I
I
P
CA
P
CB
CA
P
A
• Asymmetrical PWM case
• Complementary output
generated by dead-band unit
• CMPB triggers ADC SOC
Pulse Center
INIT-time
EPW M1A
Φ2=120
P
CA
P
CB
CA
A
EPW M2A
Φ3=240
• Period (1,2,3)
• CAu Action (1,2,3)
• PRD Action (1,2,3)
• Phase (2,3)
• PRD Interrupt (1)
• CBu ADC SOC (1,2,3)
• Dead-band
RUN-time
CB
A
CA
P
CA
P
• CMPA (1,2,3)
• CMPB (1,2,3)
EPW M3A
28
C28x Digital Power Supply Workshop
2 – Driving the Power Stage with PWM Waveforms
Half H-Bridge (HHB)
VOUT
VDC_bus
Ext Sync In
(optional)
Master
Phase Reg
En
EPWM1A
CNT=Zero
CNT=CMPB
1
EPWM1A
SyncIn
Φ = 0ο
X
EPWM1B
SyncOut
EPWM1B
Switching Requirements – HHB
CMPA
modulation
range
CA
CB
CMPA
modulation
range
Z
CA
• Up/Down Count
• Asymmetrical PWM
• dead-band on A only
• 50 % max Modulation
(controlled by CMPA)
Z
A
EPWM1B
Z
CB
CA
Z
A
EPWM1A
DBRED
DBRED
CA
INIT-time
• ZRO Action (A,B)
• CAd Action
• CAu Action
• CBd ADC trigger
• CBd ADC trigger
• DBRED
Compare A modulation range:
0 < CMPA < ( PRD – ½ x DBRED )
C28x Digital Power Supply Workshop
RUN-time
• CMPA
• CMPB (optional)
29
2 – Driving the Power Stage with PWM Waveforms
Phase Shifted Full Bridge (PSFB)
Ext Sync In
(optional)
Master
Phase Reg
En
VDC_bus
Φ = 0ο
EPWM1A
CNT=Zero
CNT=CMPB
EPWM1B
X
1
VOUT
SyncIn
EPWM1A
EPWM2A
EPWM1B
EPWM2B
SyncOut
Slave
Phase Reg
En
SyncIn
Φ = Var
EPWM2A
CNT=Zero
EPWM2B
CNT=CMPB
X
2
SyncOut
Switching Requirements – PSFB
Z
Z
Z
I
I
I
Z
CB
CA
Z
A
CB
CA
• Asymmetrical PWM
• Using dead-band module
• Phase (F ) is the control variable
• Duty fixed at ~ 50%
• RED / FED control ZVS trans.
i.e. via resonance
• CMPB can trigger ADC SOC
Z
A
EPWM1A
RED
ZVS
transition
Power
Phase
EPWM1B
FED
ZVS
transition
Φ2 = variable
Z
CB CA
Z
CB CA
A
EPWM2A
EPWM2B
30
Z
A
RED
Power
Phase
FED
INIT-time
• Period (1,2)
• CMPA (1,2) ~ 50%
• CAu action (1,2)
• ZRO action (1,2)
• CBu trigger for ADC SOC
RUN-time
• Phase (2) – every cycle
• FED / RED (1,2) – slow loop
C28x Digital Power Supply Workshop
2 – Driving the Power Stage with PWM Waveforms
Software Driver Module – PSFB
50% duty
PSFB
DRV
Net1
phase
Net2
llegdb
Net3
rlegdb
E
P
W
M
EPWM1A
EPWM1B
EPWM1A
EPWM2A
H
W
llegdb
Left leg
dead-band
EPWM2B
EPWM1B
Power
Phase
llegdb
Φ2 = phase
VOUT
VDC_bus
EPWM1A
EPWM2A
EPWM2A
rlegdb
right leg
dead-band
EPWM1B
EPWM2B
EPWM2B
“Left leg”
Power
Phase
rlegdb
“Right leg”
Software Driver Module – PFC2PHIL
PFC
2PHIL
DRV
Net1
Duty
Net2
Adj
E
P
W
M
EPWM1A
H
W
EPWM1B
+/Adj
EPWM1A
VDC_bus
+/Adj
EPWM1B
EPWM1A
EPWM1B
C28x Digital Power Supply Workshop
Φ = 180 ο
31
Lab2: PWM Generation / Open-Loop Control
Lab2: PWM Generation / Open-Loop Control
¾ Objective
The objective of this lab exercise is to demonstrate the topics discussed in this module and control
the buck output voltage using simple PWM duty cycle adjustments without feedback. Since this
implementation is open-loop without a requirement for high speed feedback, the ADC will be
used to measure various values for instrumentation purposes and will be displayed using CCS.
The PWM duty cycle will be adjusted using watch windows or sliders. The Digital Power
software framework, associated files, and library modules will be used.
Lab2: PWM Generation / Open-Loop Control
Control Buck output voltage using simple PWM
duty cycle adjustment without feedback
Use CCS watch window and slider button features
to conveniently adjust PWM duty cycle
‹
‹
Watch W indow
Dut y1
Duty1
Buck
Single
DRV
E
P
W
M
In
H
W
Buck
Single
DRV
E
P
W
M
In
H
W
Vin
EPWM-1A
Buck-1
Vo ut1
Buck-2
Vo ut2
DRV
Dut y2
Duty1
Watch W indow
EPWM-2A
DRV
Vout1
Duty1
slider
Duty 2
slider
Vout2
Temp1
Temp2
Iout1
Vin
ADC
Casc
Seq
CNF
A
D
C
H
W
Vout1
Vout2
Temp1
Temp2
Iout1
Iout2
Vin
Iout2
¾ Project Overview
Lab exercises 2, 3, and 4 use the TwoChannel project. It makes use of the “C-background/ASMISR” framework. In Lab1 various PWM waveforms were generated using the EPWM modules 3,
4, and 5. The PWM outputs on the workshop EVM were not connected to power stages, but were
looped back as inputs to the ADC. In lab exercises 2, 3, and 4 EPWMs 1 and 2 are used to drive
buck stages Channel 1 and Channel 2, respectively.
The key framework files used in this project are:
TwoChannel-Main.c – this file is used to initialize, run, and manage the application. This is
the “brains” behind the application.
TwoChannel-DevInit.c – this file is responsible for a one time initialization and
configuration of the F280x device, and includes functions such as setting up the clocks, PLL,
GPIO, etc.
32
C28x Digital Power Supply Workshop
Lab2: PWM Generation / Open-Loop Control
TwoChannel-ISR.asm – this file contains all time critical “control type” code. This file has
an initialization section that is executed one time by the C-callable assembly subroutine
_ISR_Init. The _ISR_Run routine executes at the same rate as the PWM timebase which is
used to trigger it.
The Power Library functions (modules) are “called” from this framework. Library modules may
have both a C and an assembly component. In this lab exercise, the following C and
corresponding assembly modules are used:
C configure function
ASM initialization macro
ASM Run time macro
BuckSingle_CNF()
BuckSingle_DRV_INIT n
BuckSingle_DRV
ADC_CascSeqCNF()
none
n
none
The workshop Power EVM consists of two identical buck power stages. The input bus voltage
for both stages is 12V. Shown below is a diagram of the Power EVM and some key features.
Main Pwr (SW1)
Load 2
Load 1
Active Load
12V In
DMM
DC Bus
(SW2)
V1/V2
Select
(SW3)
Buck 2
Buck 1
Comms
12V In
DC power supply from plug pack
Main Pwr
SW1 - Master power switch for entire EVM
DC Bus
SW2 - Power switch for Vin to buck stages only and when off F2808 DIMM
controller card still operates (next to the DC bus switch is a resettable fuse)
Buck 1, 2
Buck power stage modules with temperature/current measurement and over
current protection
Load 1, 2
Load terminals and/or buck converter output - next to each terminal block is a
light bulb or “visual” load (these draw approx 250 mA hot)
C28x Digital Power Supply Workshop
33
Lab2: PWM Generation / Open-Loop Control
Active Load
Software controlled switched load (connected to output of buck 1 only)
DMM
Digital Multi-Meter (has a range of 0~20V, with resolution of 10 mV and is
used to measure output voltage of buck conterters)
V1/V2 Select
SW3 - selects between output voltage of buck 1 and 2
Comms
Serial communications UART (optional for user, not used in lab exercises)
The key signal connections between the F2808 Digital Signal Controller and the 2 buck stages are
listed in the table below. For reference a portion of the shematic is also given.
Signal Name
34
Description
Connection to F2808
EPWM-1A
PWM Duty control signal for buck stage 1
GPIO-00
EPWM-2A
PWM Duty control signal for buck stage 2
GPIO-02
VoutFB-1
Voltage feedback for buck stage 1
ADC-B0
VoutFB-2
Voltage feedback for buck stage 2
ADC-A0
Iout-1
Current monitor / measurement buck stage 1
ADC-B1
Iout-2
Current monitor / measurement buck stage 2
ADC-A1
Temp-1
Temperature monitor / measurement buck stage 1
ADC-B2
Temp-2
Temperature monitor / measurement buck stage 2
ADC-A3
Ifault-1
Over-Current flag, digital output from buck stage 1
GPIO-01
Ifault-2
Over-Current flag, digital output from buck stage 2
GPIO-03
C28x Digital Power Supply Workshop
Lab2: PWM Generation / Open-Loop Control
C28x Digital Power Supply Workshop
35
Lab2: PWM Generation / Open-Loop Control
¾ Lab Exercise Overview
The software in Lab2 has been configured to independently adjust the duty cycle of EPWM-1A
and EPWM-2A. “Net” variable names Duty1 and Duty2 have been declared and “connected”
to the inputs of BuckSingle_DRV macro. Using either the watch window or the appropriate
slider, Duty1 and Duty2 can be directly adjusted. Below is the system diagram for Lab2.
Watch Window
Duty1
Duty1
Buck
Single
DRV
E
P
W
M
In
H
W
Buck
Single
DRV
E
P
W
M
In
H
W
Vin
EPWM-1A
Buck-1
Vout1
Buck-2
Vout2
DRV
Duty2
Duty1
Watch Window
EPWM-2A
DRV
Vout1
Duty1
slider
Duty2
slider
Vout2
Temp1
Temp2
Iout1
Vin
ADC
Casc
Seq
CNF
A
D
C
H
W
Vout1
Vout2
Temp1
Temp2
Iout1
Iout2
Vin
Iout2
In Lab2 (as well as lab exercises 3 and 4) the assembly ISR _ISR_Run routine is triggered by
EPWM1. This is where the BuckSingle_DRV macros are executed. Therefore, the PWM
update rate is equal to the PWM frequency. Since this system is running open-loop, there is not a
requirement for high speed feedback. As a result, the ADC function ADC_CascSeqCNF() is
called in the C background code during initialization, and the ADC measured values are only
used for instrumentation purposes. The update rate can be much slower with no need to be
synchronized to the PWM or ISR. The ADC values are read directly from the ADC result
registers (AdcMirror.ADCRESULTn) by the background C code.
A task state-machine has been implemented as part of the background code. Tasks are arranged
in groups (A1, A2, A3…, B1, B2, B3…, C1, C2, C3…). Each group is executed according to 3
CPU timers which are configured with periods of 1 ms, 4 ms, and 8 ms respectively. Within each
group (e.g. “B”) each task is run in a “round-robin” manner. For example, group B executes
every 4 ms, and there are 3 tasks in group B. Therefore, B1, B2, and B3 execute once every 12
ms. System dashboard measurements are conveniently done by group 3 tasks (i.e. B1 – voltage
measurement, B2 – current measurement, and B3 – temperature measurement).
36
C28x Digital Power Supply Workshop
Lab2: PWM Generation / Open-Loop Control
¾ Procedure
Open a CCS Project
1. Turn on the power (SW1) to the 2-channel buck EVM. Open Code Composer Studio and
maximize it to fill your screen.
2. A project named Lab2.pjt has been created for this lab exercise. Open the project by
clicking:
Project Æ Open…
and look in C:\C28x_DPS\LABS\LAB2.
3. Load the TwoChannel.gel file by clicking:
File Æ Load Gel…
and look in C:\C28x_DPS\LABS\LAB2.
Device Initialization, Main, and ISR Files
Note: DO NOT make any changes to the source files – ONLY INSPECT
4. Open and inspect TwoChannel-DevInit.c by double clicking on the filename in the
project window. Confirm that GPIO00 and GPIO02 are configured to be PWM outputs.
5. Open and inspect TwoChannel-Main.c. Notice the incremental build option 1 (i.e.
IB1). A section of code is shown here for convenience. Comments have been added in
italics. Note that the run-time macros are executed at the PWM rate of 300 kHz.
//=============================================================
#if (IB1)
// Open loop - Channels 1,2
//=============================================================
#define
prd
333
// Period count = 300 KHz @ 100 MHz
#define
NumActvCh
2
// Number of Active Channels
// "Raw" (R) ADC measurement name defines
#define
VoutR1
AdcMirror.ADCRESULT0
#define
VoutR2
AdcMirror.ADCRESULT1
#define
IoutR1
AdcMirror.ADCRESULT2
#define
IoutR2
AdcMirror.ADCRESULT3
#define
TempR1
AdcMirror.ADCRESULT4
#define
TempR2
AdcMirror.ADCRESULT5
#define
VinR
AdcMirror.ADCRESULT6
//
//
//
//
//
//
//
The ChSel array is used as input by function ADC_CascSeqCNF. These values will be used by “B” tasks for dashboard
calculations, and shown in the Watchwindow.
// Channel Selection for Cascaded Sequencer
ChSel[0] = 8;
// B0 - Vout1
ChSel[1] = 0;
// A0 - Vout2
ChSel[2] = 9;
// B1 - Iout1
ChSel[3] = 1;
// A1 - Iout2
ChSel[4] = 10;
// B2 - Temperature-1
ChSel[5] = 2;
// A2 - Temperature-2
C28x Digital Power Supply Workshop
37
Lab2: PWM Generation / Open-Loop Control
ChSel[6] = 11;
// B3 - Vin
The 3 configuration functions below are part of the Power Library.
BuckSingle_CNF(1, prd, 1, 0);
// ePWM1, Period=prd, Master, Phase=Don't Care
BuckSingle_CNF(2, prd, 0, 0);
// ePWM2, Period=prd, Slave, Phase=0
ADC_CascSeqCNF(ChSel, 2, 7, 1); // ACQPS=2, #Conv=7, Mode=Continuous
EPwm1Regs.CMPB = 2;
// ISR trigger point
ISR_Init();
// ASM ISR init
Duty1 and Duty2 variables will directly control the buck duty cycle. Sliders will be used to quickly change these values.
Duty1 = 0x0;
Duty2 = 0x0;
// Module connection to "nets" done here
//---------------------------------------// BUCK_DRV connections
Buck_In1 = &Duty1;
Buck_In2 = &Duty2;
#endif // (IB1)
6. Open and inspect TwoChannel-ISR.asm. Notice the _ISR_Init and _ISR_Run
sections. This is where the PWM driver macro instantiation is done for initialization and
run-time, respectively. The code is shown below for convenience. In Lab2, incremental
build option IB1 is used.
.if(IB1) ; Init time
BuckSingle_DRV_INIT
BuckSingle_DRV_INIT
.endif
.if(IB1) ; Run time
BuckSingle_DRV 1
BuckSingle_DRV 2
.endif
1
2
; EPWM1A
; EPWM2A
; EPWM1A
; EPWM2A
7. Optionally, you can close the inspected files.
Build and Load the Project
8. Click the “Rebuild All” button and watch the tools run in the build window. The
output file should automatically load.
9. Under Debug on the menu bar click “Reset CPU”, “Restart”, and then “Go
Main”. You should now be at the start of Main().
Setup Watch Window
10. Open the watch window to view the variables used in the project.
Click: View Æ Watch Window on the menu bar.
Click the “Watch 1” tab at the bottom of the watch window. In the empty box in the
"Name" column, type the symbol names from the following screen capture and be sure to
modify the “Type” and “Radix” as needed.
38
C28x Digital Power Supply Workshop
Lab2: PWM Generation / Open-Loop Control
The following table gives a description for the variable names:
Variable
Description
VinMeas
Voltage input measurement (i.e. DC bus) to each buck power stage
Vmeas
Voltage output of each channel, 3 element array, zeroth element not used
Imeas
Current output of each channel, 3 element array, zeroth element not used
TdegC
Temperature of each power module, 3 element array, zeroth element not used
Duty1
Q15 value (0~7FFFh) for duty input to BuckSingle_DRV1
Duty2
Q15 value (0~7FFFh) for duty input to BuckSingle_DRV2
Note 7FFFh = 32,768 = 100% duty
Save the Workspace
11. Save the current workspace by naming it Lab2.wks and clicking:
File Æ Workspace Æ Save Workspace As…
and saving in C:\C28x_DPS\LABS\LAB2.
Run the Code – TwoChannel
12. Enable real-time mode by selecting:
Debug Æ Real-time Mode
13. A message box may appear. If so, select YES to enable debug events. This will set bit 1
(DGBM bit) of status register 1 (ST1) to a “0”. The DGBM is the debug enable mask bit.
When the DGBM bit is set to “0”, memory and register values can be passed to the host
processor for updating the debugger windows.
C28x Digital Power Supply Workshop
39
Lab2: PWM Generation / Open-Loop Control
14. Check to see if the windows are set to continuously refresh. Click:
View Æ Real-time Refresh Options…
and check “Global Continuous Refresh”.
15. Run the code by using the <F5> key, or using the Run button on the vertical toolbar, or
using Debug Æ Run on the menu bar.
16. Note that in the watch window all values should be ~ zero, except for temperature, which
should be approximately equal to room temperature of 25° C.
17. Turn on the 12-volt DC bus (SW2) on the 2-channel buck EVM and observe variable
VinMeas in the watch-window. It should now be approximately 12V.
18. Open sliders D1Slider and D2Slider by using GEL Æ 2-Channel Sliders Æ and
move the sliders into the workspace area. D1Slider and D2Slider are used to change
variables Duty1 and Duty2, respectively. Increase the value of Duty1 to approximately
2800 (decimal). Power stage buck 1 module output voltage should be approximately 1V
on the DMM. Be sure that SW3 on the EVM is positioned to select Ch1. With the load
resistor (1Ω) connected to terminal 1, the open-loop voltage for Channel 1 is
approximately given by:
1V
2800
2V
5600
3V
8400
19. Try the same adjustment on Duty2. Be sure SW3 on the EVM is positioned to select
Ch2. Note that Channel 2 buck is only lightly loaded with a lamp (2~3Ω) and hence a
slightly lower Duty2 value will give the same output voltage as in the Ch1 case.
20. Of general interest – during duty/voltage adjustments observe the various watch window
variables such as voltage, current and temperature. Vmeas should reflect approximately
the same value as the DMM display. The current measurement is not very precise as it is
designed to measure a range up to 15A. Hence at low current levels accuracy will be
quite poor. Temperature should track quite well and the channel supplying the most
power will show an observable temperature increase.
21. Turn off the 12-volt DC bus (SW2) on the 2-channel buck EVM. (Do not turn off the
main power SW1).
22. Fully halt the DSP in real-time mode. First, halt the processor by using Shift <F5>, or
using the Halt button on the vertical toolbar, or by using Debug Æ Halt. Then click
Debug Æ Real-time Mode and uncheck the “Real-time mode” to take the
DSP out of real-time mode.
23. In the project window right click on Lab2.pjt and select Close.
40
C28x Digital Power Supply Workshop
Lab2: PWM Generation / Open-Loop Control
24. Do Not Close Code Composer Studio or it will be necessary to setup the debug
environment windows again for the next lab exercise!
End of Exercise
C28x Digital Power Supply Workshop
41
3 – Controlling the Power Stage with Feedback
3 – Controlling the Power Stage with Feedback
Controlling the Power Stage with Feedback
‹
‹
‹
‹
‹
Closed-Loop System Block Diagram
Analog-to-Digital Converter Module
Digital Control of Power Converter
High Resolution PWM Benefits
Soft Start – Starting the Loop
Closed-Loop System Block Diagram
The “Closed-Loop”
Control
“2P2Z”
Vset
Ref
FB
Uout
E
P
W
M
In
H
W
Duty
Vin
Power
Stage
“Loop”
Feedback
42
“PWM”
DRV
“ADC”
DRV
A
D
C
Rslt
H
W
Vout
C28x Digital Power Supply Workshop
3 – Controlling the Power Stage with Feedback
ADC Module Block Diagram
ADC Module Block Diagram
Analog MUX
...
MUX
A
ADCINA7
ADCINB0
ADCINB1
Result MUX
S/H
A
12-bit A/D
Converter
S/H
MUX
...
MUX
B
RESULT0
RESULT1
S/H
B
SOC
RESULT2
Result
Select
EOC
...
ADCINA0
ADCINA1
RESULT15
Autosequencer
ADCINB7
MAX_CONV1
Ch Sel (CONV00)
Ch Sel (CONV01)
Ch Sel (CONV02)
Ch Sel (CONV03)
...
Software
ePWM_SOC_A
ePWM_SOC_B
External Pin
Ch Sel (CONV15)
Start Sequence
Trigger
(GPIO/XINT2_ADCSOC)
Digital Control of Power Converter
Digital Control of Power Converter
ΔVc
Vo
Power Converter
Vin
C
ΔD
RL
Kd
ΔVs
PWM
Digital
Controller
ADC
U(n)
Gc(z)
E(n)
+
Vr
Gc ( z ) =
Vref _ adc
= Vo max ⋅ Kd
+
U ( z ) B0 + B1 z −1 + B2 z −2
=
E ( z ) 1 − A1 z −1 − A2 z −2
U (n) = B0 E ( n) + B1E (n − 1) + B2 E (n − 2) + A1U (n − 1) + A2U (n − 2)
C28x Digital Power Supply Workshop
43
3 – Controlling the Power Stage with Feedback
Digital Control of Power Converter
Steady State Limit Cycle
Vo levels (DPWM duty
ADC levels
error bins
ratio steps)
Volt
ΔVs
ΔVs
ΔVc
Vref
+0010
+0001
0000
-0001
ΔVc
steady state output,
limit cycle
Volt
Vo levels (DPWM duty ADC levels
ratio steps)
ΔVc
ΔVs
ΔVs
Vref
time
error bins
+0010
+0001
0000
-0001
steady state output,
no limit cycle
time
High Frequency PWM
V
TPWM
PWM
T Sysclk
VSTEP
t
t
PWM resolution = Log2 ( TPWM / TSysClk )
F2808 – SysClk = 100 MHz
PWM Freq
(kHz)
100
150
250
500
750
1000
1500
2000
44
Regular resolution
(bits)
(%)
10.0
0.1
9.4
0.2
8.6
0.3
7.6
0.5
7.1
0.8
6.6
1.0
6.1
1.5
5.6
2.0
High resolution
(bits)
(%)
0.002
16.0
0.002
15.4
0.004
14.7
0.008
13.7
0.011
13.1
0.015
12.7
0.023
12.1
0.030
11.7
C28x Digital Power Supply Workshop
3 – Controlling the Power Stage with Feedback
High Resolution PWM (HRPWM)
PWM Period
Regular
PWM Step
(i.e. 10ns)
Device Clock
(i.e. 100MHz)
HRPWM divides a clock
cycle into smaller steps
called Micro Steps
(Step Size ~= 150ps)
ms
ms
ms
ms
ms
ms
Calibration Logic
Calibration Logic tracks the
number of Micro Steps per
clock to account for
variations caused by
Temp/Volt/Process
HRPWM
Micro Step (~150ps)
‹
‹
‹
‹
Significantly increases the resolution of conventionally derived digital PWM
Uses 8-bit extensions to Compare registers (CMPxHR) and Phase register
(TBPHSHR) for edge positioning control
Typically used when PWM resolution falls below ~9-10 bits which occurs at
frequencies greater than ~200 kHz (with system clock of 100 MHz)
Not all ePWM outputs support HRPWM feature (see device data manual)
Resolution Loss – Low Duty Utilization
TPWM
Max Duty
PWM
Not Utilized
t
T SYSCL (10 ns)
0.8
1
1.2
1.8
2.5
3.3
5
94%
93%
92%
91%
90%
89%
87%
93%
92%
90%
89%
88%
86%
83%
91%
90%
88%
87%
85%
83%
80%
87%
85%
82%
80%
78%
74%
70%
82%
79%
75%
72%
69%
64%
58%
76%
73%
67%
63%
59%
53%
45%
64%
58%
50%
44%
38%
29%
17%
Vin
14
12
10
9
8
7
6
C28x Digital Power Supply Workshop
45
3 – Controlling the Power Stage with Feedback
High-Resolution PWM Benefits
Benefit of High Resolution PWM
Watch Window
Voltage
Contro ller
Vref
Vref
CNTL
2P2 Z
Ref
FB
Uout
DutyCmd
HR
BUCK
DRV
E
P
W
M
Duty
H
W
Single Power Stage
Vin1
EPWMnA
Vo ut1
Buck
DRV
1 MHz
DutyCmd
1 MHz
ADC
1CH
DRV
Vout
A
D
C
H
W
rslt0
Ch0
1 MHz
Regular PWM (10ns)
HiRes PWM (150ps)
Limit cycle problem
No Limit cycle
Edge control is precise
Edge jumps around
Managing the “Closed-Loop”
Fault
Trip
Dead
Band
SSartSE Q
Delay
Slope
Out
Target
Coeff set 3
Coeff set 2
CoeffCoeff
- B2 set 1
Coeff - B 2
CoeffCoeff
- B1 - B2
Coeff - B 1
CoeffCoeff
- B0 - B1
Coeff - B 0
CoeffCoeff
- A2 - B0
Coeff - A 2
CoeffCoeff
- A1 - A2
Coeff - A 1
Coeff - A1
46
Vset
Control
“2P2Z”
Ref
FB
Duty
Clamp
“PWM”
DRV
E
P
W
M
In
H
W
“ADC”
DRV
A
D
C
Rslt
H
W
Duty
Uout
Open/Closed
Loop
Feedback
C28x Digital Power Supply Workshop
3 – Controlling the Power Stage with Feedback
Simple User Interface Control
Supervisory - BG
Control Engine(s)
Fault Trip
Dead Band
Open/Closed Loop
Trip
Zone
Duty Clamp
Vset
SSartSEQ
Control
“2P2Z”
Delay
Slope
Out
Target
Coeficient
Tuning
Ref
FB
Coeff set 3
Coeff set 2
Coeff
- B2 set 1
Coeff
Coeff - B2
CoeffCoeff
- B1 - B2
Coeff - B1
CoeffCoeff
- B0 - B1
Coeff - B0
CoeffCoeff
- A2 - B0
Coeff - A2
CoeffCoeff
- A1 - A2
Coeff - A1
Coeff - A1
“PWM”
DRV
Duty
Uout
Voltage
Feedback
E
P
W
M
In
H
W
“ADC”
DRV
A
D
C
Rslt
H
W
Vout Monitor
Duty Monitor
Soft Start – Starting the Loop
Soft-Start and Sequencing Multi Vout
C28x Digital Power Supply Workshop
47
Lab3: Closed-Loop Control
Lab3: Closed-Loop Control
¾ Objective
The objective of this lab exercise is to demonstrate the topics discussed in this module and
regulate the output voltage of a buck power stage using closed-loop feedback control realized in
the form of a software coded loop. Soft-start and shut-down management will be explored using
the CCS watch window and sliders. ADC management for high-speed feedback and slow
instrumentation will be utilized. The Digital Power software framework, associated files, and
library modules will be used.
Lab3: Closed-Loop Control
‹
‹
‹
Regulate the Buck output by using Voltage Mode Control (VMC) with
closed-loop feedback
Soft-start and sequencing function used to ensure an “orderly”
voltage ramp-up/down
Soft-start profile and target voltage is conveniently adjusted by using
the CCS watch window and slider buttons feature
SSta rtSE Q
HR
BUCK
DRV
Voltage
Co ntroller
CNTL
2 P2Z
Delay
Slope
Out
Vref
Target
Ref
Uout
Duty1
Duty
FB
ADC
1CH
DRV
Watc h W indow
Vou t1
r slt0
Single Power Stage
E
P
W
M
H
W
Vin1
EPWMnA
DRV
Vout1
Buck
A
D
C
H
W
Ch0
Vsoft
Graph Wind ow
SlewRate
D ataLog
OnDelay
Mem
Buffer
In
Vsoft
slid er
¾ Project Overview
The following Power Library modules will be used in this lab exercise. (Note: these are the same
library modules used in Lab2 exercise with the addition of other library modules).
48
C configure function
ASM initialization macro
ASM Run time macro
BuckSingle_CNF()
BuckSingleHR_DRV_INIT n
BuckSingleHR_DRV
ADC_DualSeqCNF()
ADC_NchDRV_INIT n
ADC_NchDRV n
none
ControlLaw_2P2Z_INIT n
ControlLaw_2P2Z n
none
DataLogTST_INIT n
DataLogTST n
n
C28x Digital Power Supply Workshop
Lab3: Closed-Loop Control
Below is a description and notes for the Power Library modules used in this lab exercise.
BuckSingleHR_DRV This is the high resolution PWM version of BuckSingle used in Lab2.
The C configure function (BuckSingle_CNF) is applicable for both
high-resolution and non-high-resolution versions of macro.
ADC_NchDRV
Reads 1st N ADC result registers every PWM cycle and stores to N
consecutive memory locations accessible by C. In Lab3, N=1 (i.e. a
single voltage is measured as feedback).
ControlLaw_2P2Z
This is a 2nd order compensator realized from an IIR filter structure.
The 5 coefficients needed for this function are declared in the C
background loop as an array of longs. This function is independent of
any peripherals and therefore does not require a CNF function call.
DataLogTST
Data logging function with time-stamp trigger input. Although not
needed in the application itself, it provides a convenient way to
visualize the output voltage in a CCS graph window. In Lab4 the data
logger will be useful in displaying an output voltage transient.
¾ Lab Exercise Overview
The software in Lab3 has been configured to provide closed-loop voltage control for Channel 1 of
the buck EVM. Additionally, datalogging of the output can be displayed in a CCS graph
window. Below is the system diagram for Lab3.
SStartSEQ
Delay
Slope
Out
Target
Vref
Buck
Single
HR
DRV
CNTL
2P2Z
Ref
FB
Uout
Duty1
Voltage
Controller
Watch Window
In
ADC
1CH
DRV
Vout1
rslt0
E
P
W
M
H
W
Vin1
EPWM1A
A
D
C
H
W
DRV
Vout1
Buck
Single Power Stage
ADC-B0
Vsoft
Graph Window
SlewRate
DataLog
OnDelay
Mem
Buffer
OffDelay
In
Vsoft
slider
C28x Digital Power Supply Workshop
49
Lab3: Closed-Loop Control
The closed-loop consists of only three modules – ADC_1ChDRV, CNTL_2P2Z, and
BuckSingleHR_DRV. When the code is runing these modules execute as in-line code (no
decision making) within the ISR_Run routine which is triggered at the PWM rate. To ensure
proper operation, Vref is kept at zero until a request is received to enable the output voltage. It is
important for a power supply to have a proper start-up and shut-down routine. This is managed
by the soft-start and sequencing code which executes in the main background C code
TwoChannel-Main.c. This code ensures that Vref can never have a step change, as direct
modification of Vref is not allowed. Vref can only be adjusted indirectly via a target value
request. This value will be reached at a given slew-rate. The slew-rate is programmable with
delay-on and delay-off time parameters which are useful for staggered sequencing of multiple
voltage rails.
In Lab3, the target voltage, slew-rate and delay-on/off parameters are conveniently modified via a
watch window. A slider can also be used to adjust the output target voltage by “connecting” it to
the Vsoft variable. The soft-start and sequencing code is “scaleable” and can manage multiple
voltage rails, for example 2, 3,…10 or more Vrefs. The interface to this code is via several
integer arrays and integer flags. The array index “n” is used to designate the channel number (i.e.
n=1 for channel 1, n=2 for channel 2,…etc.) Although in C an index of n=0 is valid, it is not used
here. Below is a summary of the arrays and their usage.
Desired output target voltage in Q15 format
e.g. Vsoft[2]=4000, set channel 2 output voltage to 4000 “units”
Enable (allow) voltage output to reach target value
ChannelEnable[n] e.g. ChannelEnable[3]=1, turn channel 3 “on”
e.g. ChannelEnable[2]=0, turn channel 2 “off”
Step size or rate at which the target voltage is ramped to
SlewStep[n]
e.g. SlewStep[2]=15, increment or decrement by 15 units at every
call
Delay time to turn on from the “global” start command (StartUp=1)
OnDelay[n]
e.g. OnDelay[3]=2000, start channel 3 after delay of 2000 “time
units”
Delay time to turn off from the “global” stop command (StartUp=0)
OffDelay[n]
e.g. OffDelay[3]=1000, stop channel 3 after delay of 1000 “time
units”
Global turn on/off command. Used to synchronize/sequence all
StartUp
channels
e.g. StartUp=1, global turn on command
e.g. StartUp=0, global turn off command
Vsoft[n]
50
C28x Digital Power Supply Workshop
Lab3: Closed-Loop Control
¾ Procedure
Open a CCS Project
1. Code Composer Studio should still be running from the previous lab exercise. If not,
then it will be necessary to setup the debug environment from the previous lab exercise.
2. A project named Lab3.pjt has been created for this lab exercise. Open the project by
clicking:
Project Æ Open…
and look in C:\C28x_DPS\LABS\LAB3.
The TwoChannel.gel file and watch window should still be loaded from the previous lab.
Device Initialization, Main, and ISR Files
Note: DO NOT make any changes to the source files – ONLY INSPECT
3. Open and inspect TwoChannel-Main.c by double clicking on the filename in the
project window. Notice the incremental build option 2 (i.e. IB2). A section of code is
shown here for convenience. Comments have been added in italics.
//=====================================================================
#if (IB2) // Closed Loop Ch-1, with SoftStart using separate lib blocks
//=====================================================================
#define prd
400
// Period count = 250 KHz @ 100 MHz
#define NumActvCh
1
// Number of Active Channels
// "Raw" (R) ADC measurement name defines
#define
VoutR1
AdcMirror.ADCRESULT0
#define
VoutR2
AdcMirror.ADCRESULT8
#define
IoutR1
AdcMirror.ADCRESULT9
#define
IoutR2
AdcMirror.ADCRESULT10
#define
TempR1
AdcMirror.ADCRESULT11
#define
TempR2
AdcMirror.ADCRESULT12
#define
VinR
AdcMirror.ADCRESULT13
//
//
//
//
//
//
//
Soft-Start parameters for channel 1
OnDelay[1] =
0;
OffDelay[1] = 0;
Vsoft[1] =
10900; // 1.8 V
SlewStep[1] = 200;
Used for Scope feature via Graph window
DataLogTrigger = 980000;
ScopeGain = 1;
ScopeACmode = 0;
// DC mode initially
ADC Sequencer 1 - VoutR1 used every PWM cycle
// Channel Selection for Sequencer-1
ChSel[0] = 8; // B0 - Vout1
ADC Sequencer 2 – Instrumentation only, round robin scheme
// Channel Selection for Sequencer-2
ChSel[8] = 0;
// A0 - Vout2
ChSel[9] = 9;
// B1 - Iout1
ChSel[10] = 1; // A1 - Iout2
ChSel[11] = 10; // B2 - Temperature-1
C28x Digital Power Supply Workshop
51
Lab3: Closed-Loop Control
ChSel[12] = 2; // A2 - Temperature-2
ChSel[13] = 11; // B3 - Vin
PWM and ADC configure functions
BuckSingle_CNF(1, prd, 1, 0);
ADC_DualSeqCNF(ChSel, 1, 1, 1);
EPwm1Regs.CMPB = 193;
ISR_Init();
// Lib Module connection to "nets"
//-------------------------------// ADC1CH_DRV connections
ADC_Rslt = &Vfdbk;
// CNTL_2P2Z connections
CNTL_2P2Z_Ref1 = &VrefNetBus[1];
CNTL_2P2Z_Out1 = &Uout;
CNTL_2P2Z_Fdbk1 = &Vfdbk;
CNTL_2P2Z_Coef1 = &Coef2P2Z[0];
//
//
//
//
//
//
//
//
ePWM1, Period=prd, Master, Phase=0
ACQPS=1, Seq1#Conv=1, Seq2#Conv=1
tCMPB1 - ISR trigger point
ASM ISR init
point
point
point
point
to
to
to
to
Vref from SlewRate limiter
Uout
Vfdbk
first coeff for Single Loop
// BUCK_DRV connections
Buck_In1 = &Uout;
Datalogger is an optional feature, not required for loop to run
// Data Logger connections, DLTST = DataLogTimeStampTrigger
DLTST_In1 = &Vfdbk;
DLTST_TimeBase1 = &ECap1Regs.TSCTR;
DLTST_TimeStampTrig1 = &DataLogTrigger;
DLTST_DcOffset1 = 0;
DLTST_Gain1 = ScopeGain;
Compare B event setup to trigger both Sequencer 1 & 2 simultaneously, note: Seq1 has priority
// Trigger ADC SOCA & B from EPWM1
//---------------------------------------EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPB; // SOCA on CMPB event
EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTRU_CMPB; // SOCB on CMPB event
EPwm1Regs.ETSEL.bit.SOCAEN = 1;
// Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCBEN = 1;
// Enable SOC on B group
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST;
// Trigger on every event
EPwm1Regs.ETPS.bit.SOCBPRD = ET_1ST;
// Trigger on every event
#endif // (IB2)
4. Open and inspect TwoChannel-ISR.asm. Notice the _ISR_Init and _ISR_Run
sections. This is where the PWM driver macro instantiation is done for initialization and
run-time, respectively. The code is shown below for convenience. In Lab3, incremental
build option IB2 is used. Note the order for the run time macros – 1) measure feedback,
2) compensate, 3) update PWM. Also, the ADC is not run in continuous mode, but rather
in SOC trigger mode, and therefore needs to be reset every cycle.
.if(IB2) ; Init time
ADC_NchDRV_INIT 1
ControlLaw_2P2Z_INIT 1
BuckSingleHR_DRV_INIT 1
DataLogTST_INIT 1
; 1 Channel, N=1
; EPWM1A
; 1 Channel Data logger
.endif
.if(IB2) ; Run time
ADC_NchDRV 1
ControlLaw_2P2Z 1
BuckSingleHR_DRV 1
DataLogTST 1
ADC_Reset:
MOVW DP,#ADCTRL2>>6
MOV @ADCTRL2,#0x4101
.endif
52
; 1 Channel, N=1
(Measure)
(Compensate)
; EPWM1A
(Update)
; 1 Channel Data logger
; Reset ADC SEQ
; RST_SEQ1=1, SOCA-SEQ1=1, SOCB-SEQ2=1
C28x Digital Power Supply Workshop
Lab3: Closed-Loop Control
5. Optionally, you can close the inspected files.
Build and Load the Project
6. Click the “Rebuild All” button and watch the tools run in the build window. The
output file should automatically load.
7. Under Debug on the menu bar click “Reset CPU”, “Restart”, and then “Go
Main”. You should now be at the start of Main().
Setup Watch Window and Graph
8. Another watch window will be opened in addition to the one used in the previous lab
exercise. Open the watch window to view the variables used in the project.
Click: View Æ Watch Window on the menu bar.
Click the “Watch 1” tab at the bottom of the watch window. In the empty box in the
"Name" column, type the symbol names from the following screen capture and be sure to
modify the “Type” and “Radix” as needed.
Note: ScopeGain, ScopeACmode, and ActiveLoad will be explained and used in the
next lab exercise.
C28x Digital Power Supply Workshop
53
Lab3: Closed-Loop Control
The following table gives a description for the variable names:
Variable
Description
ChannelEnable
Channel enable array
Vsoft
Voltage target array
OnDelay
DelayOn array
OffDelay
DelayOff array
SlewStep
Ramp step size array
StartUp
Global turn-on/turn-off integer flag
9. Open and setup a time graph windows to plot the data log buffer (ADC result register).
Click: View Æ Graph Æ Time/Frequency… and set the following values:
Select OK to save the graph options.
Save the Workspace
10. Save the current workspace by naming it Lab3.wks and clicking:
File Æ Workspace Æ Save Workspace As…
and saving in C:\C28x_DPS\LABS\LAB3.
54
C28x Digital Power Supply Workshop
Lab3: Closed-Loop Control
Run the Code – TwoChannel
11. Enable real-time mode by selecting:
Debug Æ Real-time Mode
12. A message box may appear. If so, select YES to enable debug events. This will set bit 1
(DGBM bit) of status register 1 (ST1) to a “0”. The DGBM is the debug enable mask bit.
When the DGBM bit is set to “0”, memory and register values can be passed to the host
processor for updating the debugger windows.
13. Check to see if the windows are set to continuously refresh. Click:
View Æ Real-time Refresh Options…
and check “Global Continuous Refresh”.
14. Run the code by using the <F5> key, or using the Run button on the vertical toolbar, or
using Debug Æ Run on the menu bar.
15. Turn on the 12-volt DC bus (SW2) on the 2-channel buck EVM and observe variable
VinMeas in the watch-window. It should now be approximately 12V. Also the Graph
window should show a trace hovering at “0”.
16. In the watch window turn on Channel 1 output by setting ChannelEnable[1]=1.
Power stage buck 1 module output voltage should ramp quickly to ~1.8V (be sure that
SW3 on the EVM is positioned to select Ch1). Note that directly turning-on (enabling)
an individual channel ignores the OnDelay and OffDelay parameters since
synchronization to a global trigger is not utilized.
17. Open slider V1softSlider (GEL Æ 2-Channel Sliders Æ) and move the slider
into the workspace area. This slider is used to directly change Vsoft[1]. Increase the
value of Vsoft[1] to approximately 10900 (decimal). Power stage buck 1 module
output voltage should be approximately 1.8V. When you are done turn off Channel 1 by
setting ChannelEnable[1]=0.
18. Channel 1 can also be enabled by using the global turn-on flag – StartUp. In this case
OnDelay and OffDelay parameters are used. Both of these delays are set to zero by
default, but can be modified via the watch-window. For example, modify these values as
follows:
OnDelay[1]=1000
OffDelay[1]=2000
StartUp=1
This will trigger a global turn on and Channel 1 will start ramping up after 1000 time
units. Using StartUp=0 will trigger a global turn off and Channel 1 will ramp down
after 2000 time units.
19. The ramp-up and ramp-down rates can also be modified. In this lab code, up and down
C28x Digital Power Supply Workshop
55
Lab3: Closed-Loop Control
rates are the same and set by parameter SlewStep[1] for channel 1. The default value
in Lab3 is 200 units per step. Change it to 40 in the watch window and see the result.
Follow these steps:
SlewStep[1]=40
ChannelEnable[1]=1
Output should ramp up at slower rate
ChannelEnable[1]=0
Output should ramp down at slower rate
20. Turn off the 12-volt DC bus (SW2) on the 2-channel buck EVM. (Do not turn off the
main power SW1).
21. Fully halt the DSP in real-time mode. First, halt the processor by using Shift <F5>, or
using the Halt button on the vertical toolbar, or by using Debug Æ Halt. Then click
Debug Æ Real-time Mode and uncheck the “Real-time mode” to take the
DSP out of real-time mode.
22. In the project window right click on Lab3.pjt and select Close.
23. Do Not Close Code Composer Studio or it will be necessary to setup the debug
environment windows again for the next lab exercise!
End of Exercise
56
C28x Digital Power Supply Workshop
4 – Tuning the Loop for Good Transient Response
4 – Tuning the Loop for Good Transient Response
Tuning the Loop for Good Transient Response
‹
‹
‹
‹
Digital Power Supply Control Theory
Intuitive Loop Tuning – “Visually
without Math”
Active Load Feature of the Power EVM
Multi-Loop Control
Digital Power Supply Control Theory
The Digital Control System
Digital Processor
G(s)
r(t)
+
e(kT)
Controller
u(kT)
DAC
Actuator
Process
c(t)
D(z)
Sensor
ADC
Advantages
Considerations
• Immunity from environmental effects
• Advanced control strategies possible
• Immunity from component errors
• Improved noise immunity
• Ability to modify and store control parameters
• Ability to implement digital communications
• System fault monitoring and diagnosis
• Data logging capability
• Ability to perform automated calibration
• Sample rate
• Quantization
• Ease of programming
• Controller design
• Cost
• Processor selection
• Requires data converters
• Numeric issues
C28x Digital Power Supply Workshop
57
4 – Tuning the Loop for Good Transient Response
PID Control Review
u(t ) = K e(t) + K ∫ e(t ).dt + K de(t)
P
I
D dt
Gc(s)
KP = Proportional gain
KI = Integral gain
KD = Derivative gain
KP
K
G ( s) = K + I + K s
D
P s
C
KI
∫ e.dt
e(t)
+
KD
de
dt
‹
‹
‹
u(t)
Usually written in “parallel” form:
⎞
⎛
G ( s) = K ⎜⎜1 + 1 + T s ⎟⎟
C
C ⎜ Ti s d ⎟
⎠
⎝
KP = KC
KI = KC/Ti
KD = KCT d
Proportional term controls loop gain
Integral action increases low frequency gain and
reduces/eliminates steady state errors
Derivative action adds phase lead which improves
stability and increases system bandwidth
Tuning the Step Response
‹
‹
Performance of the control loop can be determined from the
output response to a step change in load
We will adjust PID coefficients to minimise deviation from
steady state and settling time of the output voltage
Steady state
Acceptable error
Peak deviation
Settling time
58
C28x Digital Power Supply Workshop
4 – Tuning the Loop for Good Transient Response
Intuitive Loop Tuning – “Visually without Math”
Loop Tuning – Good First Step
U (n) = B0 E (n ) + B1 E (n − 1) + B2 E (n − 2) + A1U (n − 1) + A2U (n − 2)
E(n-1)
E(n)
Z
-1
X
B0
E(n-2)
Z
-1
X
B1
B2
X
U(n)
S
X
A2
U(n-2)
X
Duty
X
A1
Z
PRD-SF
-1
Z
-1
U(n-1)
PID – Intuitive / Interactive
We can also write the controller in transfer function form:
U(z)
B0 + B1*z-1 + B2*z-2
B0z2 + B1*z + B2
------ = ------------------------- = ---------------------E(z)
1 - z-1
z2 – z
Compare with the General 2P2Z transfer function:
U(z)
B0 + B1*z-1 + B2*z-2
B0z2 + B1*z + B2
------ = --------------------------- = ---------------------E(z)
1 + A1*z-1 + A2*z-2
z2 + A 1*z + A 2
We can see that PID is nothing but a special case of 2P2Z control where:
A1 = -1
and
A2 = 0
Change PID coeff. “on fly” in back-ground loop
// Coefficient init
Coef2P2Z_1[0] = Dgain * 67108;
Coef2P2Z_1[1] = (Igain - Pgain - Dgain - Dgain)*67108;
Coef2P2Z_1[2] = (Pgain + Igain + Dgain)*67108;
Coef2P2Z_1[3] = 0;
Coef2P2Z_1[4] = 67108864;
Coef2P2Z_1[5] = Dmax[1] * 67108;
Coef2P2Z_1[6] = 0x00000000;
C28x Digital Power Supply Workshop
//
//
//
//
//
//
//
B2
B1
B0
A2
A1
Clamp Hi limit (Q26)
Clamp Lo
59
4 – Tuning the Loop for Good Transient Response
Control Law Computation
U (n) = B0 E (n ) + B1 E (n − 1) + B2 E (n − 2) + A1U (n − 1) + A2U (n − 2)
U(n)
DBUFF
U(n-1)
XAR7
A1
U(n-2)
A2
E(n)
B0
E(n-1)
B1
E(n-2)
B2
min
max
duty
60
; e(n)=Vref-Vout
MOVU
ACC,@Vref
SUBU
ACC,*XAR2++
LSL
ACC,#8
; ACC=e(n)
(Q24)
MOVL
@VCNTL_DBUFF+4,ACC
ZAPA
; Voltage control law
MOVL
XT,@VCNTL_DBUFF+8 ; XT=e(n-2)
QMPYAL
P,XT,*XAR7++
; b2*e(n-2)
MOVDL
XT,@VCNTL_DBUFF+6 ; XT=e(n-1), e(n-2)=e(n-1)
QMPYAL
P,XT,*XAR7++
; ACC=b2*e(n-2), P=b1*e(n-1)
MOVDL
XT,@VCNTL_DBUFF+4 ; XT=e(n), e(n-1)=e(n)
QMPYAL
P,XT,*XAR7++
; ACC+=b1*e(n-1), P=b0*e(n)
MOVL
XT,@VCNTL_DBUFF+2 ; XT=u(n-2)
QMPYAL
P,XT,*XAR7++
; P=a2*u(n-2)
MOVDL
XT,@VCNTL_DBUFF
; XT=u(n-1), u(n-2)=u(n-1)
QMPYAL
P,XT,*XAR7++
; ACC=a2*u(n-2)
ADDL
ACC,P
; ACC=a2*u(n-2)+a1*u(n-1)
LSL
ACC,#(23-VCNTL_QF+8)
; (Q23)
ADDL
ACC,ACC
; (Q24)
MOVL
@VCNTL_DBUFF,ACC ; ACC=u(n)
; Saturate the result [min,max]
MINL
ACC,*XAR7++
MAXL
ACC,*XAR7++
; Duty Cycle Modulation
MOVL
XT,ACC
QMPYL
P,XT,*XAR7++
;(Q0)
MOV
*XAR3++,P
C28x Digital Power Supply Workshop
4 – Tuning the Loop for Good Transient Response
Type II Controller
Lo
V in
Vout
COMPARATOR
+
-
1
s+
1
R2 C 2
G c (s ) =
R1C1 ⎛
C + C2 ⎞
⎟
s⎜⎜ s + 1
R2C1C 2 ⎟⎠
⎝
Co
Do
DRIVER
CONTROLLER
C1
C2
R2
R1
+
-
REF
B o d e D ia g r a m
80
70
M a g n i tu d e ( d B )
60
R1 = 4.12kΩ
R2 = 124kΩ
C1 = 8.2 pF
C2 = 2.2nF
50
40
30
20
10
0
-10
P has e (d eg )
-20
0
-45
-90
10
2
1 0
3
10
4
10
Fr e qu enc y
5
10
6
10
7
1 0
8
( ra d / s e c )
Digital Type II Controller
Lo
Vin
Gc ( z ) =
Vout
Do
B2 + B1z −1 + B0 z −2
1 + A1z −1 + A0 z − 2
Co
DRIVER
DIGITAL
PROCESSOR
CONTROLLER
B o d e D ia g r a m
B1 = 0.03632
B0 = 9.891
A1 = 1.339
A0 = 0.3391
(Tustin’s transform, Ts = 1 us)
80
60
40
20
0
-20
90
P has e (deg )
B2 = 9.927
M a g n itu d e ( d B )
1 00
45
0
-45
-90
10
2
10
3
10
4
10
Fr e q u e n c y
C28x Digital Power Supply Workshop
5
10
6
10
7
10
8
(r a d / s e c )
61
4 – Tuning the Loop for Good Transient Response
Type III Controller
Lo
Vin
V out
COMPARATOR
+
Do
-
Co
DRIVER
⎛
⎞
1 ⎞⎛
1
⎟
⎜s +
⎟⎜ s +
R2C 2 ⎟⎠⎜⎝ (R1 + R3 )C3 ⎟⎠
R1 + R3 ⎜⎝
Gc (s ) =
R1 R3C1 ⎛ C1 + C 2 ⎞⎛
1 ⎞
s⎜⎜ s +
⎟⎜ s +
⎟
R2C1C2 ⎟⎠⎜⎝
R3C3 ⎟⎠
⎝
CONTROLLER
C1
C2
C3
R2
R3
R1
+
-
REF
B o d e D ia g r a m
3 0
2 0
1 0
0
4 5
P h a s e (d e g )
C2 = 2.7nF
C3 = 6.8nF
M a g n it u d e ( d B )
R1 = 4.12kΩ
R2 = 20.5kΩ
R3 = 150Ω
C1 = 0.22nF
4 0
0
-4 5
-9 0
10
3
10
4
10
F re q u e n c y
5
10
6
10
7
( r a d /s e c )
Digital Type III Controller
Lo
Vin
Gc ( z ) =
Vout
Do
B3 + B2 z −1 + B1 z −2 + B0 z −3
1 + A2 z −1 + A1 z − 2 + A0 z −3
Co
DRIVER
DIGITAL
PROCESSOR
CONTROLLER
B3 = 9.658
B1 = 9.652
B0 = 9.164
A2 = 2.128
M a g n itu d e ( d B )
B2 = 9.158
B o d e Dia g r a m
10 0
(Tustin’s transform, Ts = 1 us)
60
40
20
0
A1 = 1.397
90
P h as e (deg )
A0 = 0.2689
80
45
0
-4 5
-9 0
10
3
10
4
10
5
10
6
10
7
F r e q u e n c y ( r a d /s e c )
62
C28x Digital Power Supply Workshop
4 – Tuning the Loop for Good Transient Response
Active Load Feature of the Power EVM
2-Channel Buck EVM
TI PowerTrain
PTD08A010W
10A module
ƒ
ƒ
ƒ
ƒ
ƒ
Phase Links
Active
Load LEDs
Volt
Meter
Current meas.
Temp meas
Over Current Prot.
Over Current Flag
No Heat-sink needed
2-Channel Buck EVM Schematic
C28x Digital Power Supply Workshop
63
Lab4: Tuning the Loop
Lab4: Tuning the Loop
¾ Objective
The objective of this lab exercise is to demonstrate the topics discussed in this module and tune
the closed-loop buck power stage for improved transient performance using visual “trial and
error” methods rather than a mathematical approach. The transient response will be modified by
interactively adjusting the system proportional (P), integral (I), and derivative (D) gains using
sliders. An active load circuit enabled by software will provide a repetitive step change in load.
The CCS graph window feature will be used to view the transient response in real-time. The
Digital Power software framework, associated files, and library modules will be used.
Lab4: Tuning the Loop
Tune closed-loop Buck power stage for improved transient performance
using visual “trial and error” (rather than mathematical approach)
The 2-channel Buck EVM has an active load circuit when enabled by software
provides a repetitive step change in load
CCS graph window feature used to view the transient in real-time
‹
‹
‹
Š
Transient response can be modified directly until the desired improvement is
achieved by adjusting P, I, D sliders
Fault
Trip
Coefficient “tuning”
P
I
SSartSEQ
D
Vset
Delay
PID
Mapping
( 3 to 5 )
CCS or GUI
sliders
OR
Im
Pole / Zero
to Coef Map
(5 to 5)
Re
Pole / Zero
adjust GU I
Slope
Dead
Band
Out
T arget
Coeff set 3
Coeff set 2
C oeffCoeff
- B2 set 1
Coeff - B2
CoeffCoeff
- B1 - B2
Coeff - B1
CoeffCoeff
- B0 - B1
Coeff - B0
CoeffCoeff
- A2 - B0
Coeff - A2
CoeffCoeff
- A1 - A2
Coeff - A1
Coeff - A1
Control
“2P2Z”
Ref
FB
Duty
Clamp
“PWM”
DRV
E
P
W
M
In
H
W
“ADC”
DRV
A
D
C
Rslt
H
W
Duty
Uout
Open/Closed
Loop
Feedback
Graph Window
DataLog
Mem
Buffer
In
¾ Project Overview
The software code used in Lab4 is exactly the same code as used in Lab3. All of the files and
build options are identical. The five coefficients to be modified are stored in the array
Coef2P2Z[n]. Directly manipulating these five coefficients independently by trial and error is
almost impossible, and requires mathematical analysis and/or assistance from tools such as
matlab, mathcad, etc. These tools offer bode plot, root-locus and other features for determining
phase margin, gain margin, etc.
To keep loop tuning simple and without the need for complex mathematics or analysis tools, the
coefficient selection problem has been reduced from five degrees of freedom to three, by
conveniently mapping the more intuitive coefficient gains of P, I and D to B0, B1, B2, A1, and
A2. This allows P, I and D to be adjusted independently and gradually. This method requires a
periodic transient or disturbance to be present, and a means to observe it while interactively
making adjustments. The data-logging feature introduced in Lab3 provides a convenient way to
64
C28x Digital Power Supply Workshop
Lab4: Tuning the Loop
observe the output transient while the built-in active load on the EVM can provide the periodic
disturbance.
The compensator block (macro) used is CNTL_2P2Z. This block has 2 poles and 2 zeros and is
based on the general IIR filter structure. The transfer function is given by:
U (z )
E (z )
=
b0 + b1 z −1 + b 2 z −2
1 + a1 z −1 + a 2 z −2
The recursive form of the PID controller is given by the difference equation:
u (k ) = u (k − 1) + b0e(k ) + b1e(k − 1) + b 2e(k − 2)
where:
b0 = Kp '+ Ki '+ Kd '
b1 = − Kp '+ Ki '−2 Kd '
b 2 = Kd '
And the z-domain transfer funcion form of this is:
U (z )
E (z )
=
b0 + b1 z −1 + b 2 z −2
1 − z −1
=
b0 z 2 + b1 z + b 2
z2 − z
Comparing this with the general form, we can see that PID is nothing but a special case of
CNTL_2P2Z control where:
a1 = −1 and a 2 = 0
In the lab exercise, you will inspect the C code in which these coefficients are initialized.
¾ Lab Exercise Overview
In Lab3 the software has been configured to provide closed-loop voltage control for Ch1 of the
buck EVM and datalogging of the output which was displayed in a CCS graph window. Lab4
will additionally allow modification of the five coefficients associated with the 2nd order
CNTL_2P2Z compensator block. This modification will be done “on the fly” by using 3 sliders
(P, I and D) while the buck output is put under transient using an active load which is switched
periodically by the ECAP peripheral.
The following figure is the system diagram for Lab4.
C28x Digital Power Supply Workshop
65
Lab4: Tuning the Loop
P
I
D
PID
Mapping
(3 5)
Coeff.
B2
B1
B0
A2
Sliders
A1
SSartSEQ
Delay
Slope
Out
Target
Vref
Buck
Single
HR
DRV
CNTL
2P2Z
Ref
Uout
Duty1
In
E
P
W
M
H
W
Vin1
EPWM1A
DRV
Vout1
Buck
FB
Voltage
Controller
Watch Window
ADC
1CH
DRV
Vout1
rslt0
A
D
C
H
W
Single Power Stage
ADC-B0
Vsoft
Graph Window
SlewRate
1 ohm
1 ohm
DataLog
OnDelay
Mem
Buffer
OffDelay
In
DRV
ECAP1
Vsoft
slider
Active Load
The default coefficient settings chosen for Lab3 provide very poor performance (low gains).
Initially Lab4 will use the same settings. The control loop will be soft-stared to the target Vout
value, the same way it was done in Lab3. At this point, the active load will be enabled and a load
resistor of equal value to the static load will be switched in and out periodically.
In addition to the watch window variables discussed in Lab3, a few others will be used in the loop
tuning process. These include the P, I and D gains, active load enable, and CCS graph window
(scope control). The table below summarises these new variables.
Pgain
Proportional gain; value adjustment : 0 ~ 1000
Igain
Integral gain; value adjustment : 0 ~ 1000
Dgain
Derivative gain; value adjustment : 0 ~ 1000
ActiveLoad
Enable (value=1) / Disable (value=0) flag for the active load circuit
ScopeACmode Sets the CCS Scope (graph window) to operate in AC mode (i.e. removing the
DC component) and is useful for zooming into the transient only
ScopeGain
66
Vertical gain adjustment for the CCS scope (much like a real oscilloscope)
C28x Digital Power Supply Workshop
Lab4: Tuning the Loop
¾ Procedure
Open a CCS Project
1. Code Composer Studio should still be running from the previous lab exercise. If not,
then it will be necessary to setup the debug environment from the previous lab exercise.
2. A project named Lab4.pjt has been created for this lab exercise. Open the project by
clicking:
Project Æ Open…
and look in C:\C28x_DPS\LABS\LAB4.
The TwoChannel.gel file, watch windows and graph window should still be loaded from
the previous lab.
Device Initialization, Main, and ISR Files
Note: DO NOT make any changes to the source files – ONLY INSPECT
3. Open and inspect TwoChannel-Main.c by double clicking on the filename in the
project window. This file is identical to the one used in Lab3. Notice the coefficient
initialization and P, I, and D mapping equation. A section of code is shown here for
convenience.
Pgain = 1;
Igain = 1;
// Coefficient init
Coef2P2Z[0]
Coef2P2Z[1]
Coef2P2Z[2]
Coef2P2Z[3]
Coef2P2Z[4]
Coef2P2Z[5]
Coef2P2Z[6]
Dgain = 5;
// very "loose"
for Single Loop
= Dgain * 67108;
// B2
= (Igain - Pgain - Dgain - Dgain)*67108; // B1
= (Pgain + Igain + Dgain)*67108;
// B0
= 0;
// A2
= 67108864;
// A1 = 1 in Q26
= Dmax[1] * 67108;
// Clamp Hi limit (Q26)
= 0x00000000;
// Clamp Lo
(Note: 67108 = ~ 0.001 in Q26 format)
4. Optionally, you can close the inspected file.
Build and Load the Project
5. Click the “Rebuild All” button and watch the tools run in the build window. The
output file should automatically load.
6. Under Debug on the menu bar click “Reset CPU”, “Restart”, and then “Go
Main”. You should now be at the start of Main().
C28x Digital Power Supply Workshop
67
Lab4: Tuning the Loop
Save the Workspace
7. The watch windows and graph window were setup in the previous lab exercise. A
workspace needs to be saved to include the project for this lab exercise. Save the current
workspace by naming it Lab4.wks and clicking:
File Æ Workspace Æ Save Workspace As…
and saving in C:\C28x_DPS\LABS\LAB4.
Run the Code – TwoChannel
8. Enable real-time mode by selecting:
Debug Æ Real-time Mode
9. A message box may appear. If so, select YES to enable debug events. This will set bit 1
(DGBM bit) of status register 1 (ST1) to a “0”. The DGBM is the debug enable mask bit.
When the DGBM bit is set to “0”, memory and register values can be passed to the host
processor for updating the debugger windows.
10. Check to see if the windows are set to continuously refresh. Click:
View Æ Real-time Refresh Options…
and check “Global Continuous Refresh”.
11. Run the code by using the <F5> key, or using the Run button on the vertical toolbar, or
using Debug Æ Run on the menu bar.
12. Turn on the 12-volt DC bus (SW2) on the 2-channel buck EVM and observe variable
VinMeas in the watch-window. It should now be approximately 12V. Also the Graph
window should show a trace hovering at “0V”.
13. In the watch window turn on Channel 1 output by setting ChannelEnable[1]=1.
Power stage buck 1 module output voltage should ramp quickly to ~1.8V (be sure that
SW3 on the EVM is positioned to select Ch1).
14. Enable the active load circuit by setting variable ActiveLoad = 1 in the watch
window. To better view only the transient or AC component of the output voltage, set
the graph to AC mode by changing variable ScopeACmode = 1. This should put the
output waveform at the graph “zero” line. Optionally, set the scope gain higher by
changing variable ScopeGain = 4. If lab is working correctly, then the graph
window should look something like the following:
68
C28x Digital Power Supply Workshop
Lab4: Tuning the Loop
The negative going transient is when the extra load is switched in and the positive going
overshoot is when the extra load is removed.
15. Open the sliders for P, I and D adjustment (GEL Æ 2-Channel Sliders Æ)
Pgain_Slider, Igain_Slider and Dgain_Slider. Optionally, if you want to adjust the output
voltage via a slider, then open VsoftSlider, too. Move the sliders into the workspace
area.
16. By observing the transient in real time, gradually adjust each slider to get the best
transient response (i.e. least pertubation from the zero line). Gradual adjustment can be
best achieved by selecting the slider (mouse click) and then using the up/down arrows. A
large movement of the slider may cause the system to go unstable. A suggested
procedure is given below:
• Start with Igain first, increase gradually until the negative going transient flattens
out near the zero line
• Increase Pgain until some oscillation (2~3 cycles) occurs
• Increase Dgain to remove some of the oscillation
• Increase Igain again
• keep iterating very gradually until an acceptable transient is achieved – this may
look something like the graph shown below:
C28x Digital Power Supply Workshop
69
Lab4: Tuning the Loop
17. Reduce the scope vertical gain back to 1 (ScopeGain = 1) and set the graph back in
DC mode (ScopeACmode = 0). The voltage output response should look something
like this now:
18. With the active load still enabled, try shutting down Channel 1 output and then bringing it
back up under “soft” shut-down and start-up conditions. The closed loop should be
stable during the ramping even during the switching transients.
19. Turn off the 12-volt DC bus (SW2) on the 2-channel buck EVM. (Do not turn off the
main power SW1).
20. Fully halt the DSP in real-time mode. First, halt the processor by using Shift <F5>, or
using the Halt button on the vertical toolbar, or by using Debug Æ Halt. Then click
Debug Æ Real-time Mode and uncheck the “Real-time mode” to take the
DSP out of real-time mode.
21. Close Code Composer Studio and turn off the power (SW1) to the 2-channel buck EVM.
End of Exercise
70
C28x Digital Power Supply Workshop
Lab4: Tuning the Loop
Multi-Loop Control
Multi-Loop Control
Supervisory BG
Control Engine(s)
Coef[1]
Loop-1 mgmt
Vref[1]
2 pole /
2 Zero
Ref
FB
ePWM
module
Uout[1]
Uout
Controller1
Duty PWM
PWM-1
ADC
module
ADC-1
In
Out
Coef[2]
Loop-2 mgmt
Vref[2]
2 pole /
2 Zero
Ref
FB
ePWM
module
Uout[2]
Uout
Controller2
Duty PWM
PWM-2
ADC
module
ADC-2
In
Out
Coef[N]
Loop-N mgmt
Vref[N]
2 pole /
2 Zero
Ref
FB
ePWM
module
Uout[N]
Uout
Controller N
Duty PWM
PWM-N
ADC
module
ADC-N
In
Out
Diag, slow
adjustment.
ADC
module
In
Out
ADC GenPurp
PFC (2PHIL) Software Control Flow
VpfcSetSlewed
1 kHz
SLEW
LIMIT
385 V
VpfcSet
VpfcSlewRate
In
Out
Incr
VpfcCntl
VpfcOvp
1 kHz
100 kHz
100 kHz
CNTL
2P2Z
PFC
OVP
PFC
ICMD
Ref
Out
In
CNTL
2P2Z
V1
Out
Fdbk
Out
Ref
PfcIcmd
V2
Vmon
Voltage
Controller
2
100 kHz
PFC
2PHIL
DRV
100 kHz
Out
PfcDuty
Duty
Fdbk
Vac
Adj
Current
Controller
Vboost
E
P
W
M
EPWM1A
H
W
EPWM1B
Vboost
PfcShareAdj
VpfcSet
InvVavgSqr
Ipfc
385 V
160 V
50 kHz
50 kHz
200 kHz
200 kHz
INV
SQR
FILT
BIQUAD
AC
LINE
RECT
FILT
2P2Z
50mS
Out
In
Out
In
Out
In
Out
200 kHz
Ipfc
Vboost
In
VacLine
rslt0
rslt1
rslt2
rslt3
Vavg
VacLineAvg
VacLineRect
IN0
ADC
SEQ1
DRV
VacLineFilt
rslt4
BOX
CAR
AVG
IphA
100 Hz
IpfcAvgA
PFC
ISHARE
PfcShareAdj
Out
In
BOX
CAR
AVG
Ia
Ib
Out
IpfcAvgB
Out
50 kHz
In
rslt5
A
D
C
H
W
IN1
IN2
IN3
IN4
IN5
IpfcPhaseA
HalfVref
50 kHz
IpfcPhaseB
IphB
C28x Digital Power Supply Workshop
71
Lab4: Tuning the Loop
DC-DC (ZVSFB) Software Control Flow
200 kHz
200 kHz
SLEW
LIMIT
48 V
2
VoutSet
In
VoutSlewRate
Incr
200 kHz
VoutSetSlewed
Ref
Out
Voltage
Controller
CNTL
2P2Z
Out
VdcCntl
Fdbk
Vout
V
I
Out
Fv
48 V
Ri
50 kHz
PSFB
DB
DRV
Fi
CNTL
2P2Z
0V
12 A
100m s
IoutSet
Ipri
Ref
Out
Fdbk
200 ns
DbAdjL
llegdb
180 ns
DbAdjR
rlegdb
EPWM1B
EPWM2A
E
P
W
M
phase
PhaseCntl
Rv
V outSe t
EPWM1A
PSFB
DRV
200 kHz
I_FOLD
BACK
EPWM2B
H
W
IdcCntl
200 kHz
200 kHz
Current Controller
Ipri
Ipri
rslt0
Vout
Vout
rslt1
ADC
SEQ2
DRV
A
D
C
IN0
H
W
IN1
CPU Bandwidth Utilization
MIPS = 100
# TS = 4
S. rate = 200
IS R
All
Rate
# inst / us = 100
# inst / time slice = 500
Sampling period = 5.0
Function / Activity
200 kHz Context Save / Restore
200 kHz ISR Call / Return / Ack
TS1
TS2
TS3
TS4
# Cyc
32
12
200 kHz ADCSEQ2_DRV
14
200 kHz CNTL _2P2Z 1 (V loop )
36
200 kHz CNTL _2P2Z 2 ( I lo op)
36
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
25
14
57
35
7
100 kHz PFC_OVP
25
100 kHz PFC_ICMD
100 kHz CNTL _2P2Z 4 (I loop)
100 kHz PFC2PHIL_DRV
30
36
26
50 kHz BOXCAR_AVG 1
42
50 kHz
100 Hz
50 kHz
1 kHz
42
15
10
36
BOXCAR_AVG 2
PFC_ISHARE
Execution Pre-scaler(1:50)
CNTL _2P2Z 3 (V loop )
Tot. Cyc.
292
100 kHz PFC_OVP
25
100 kHz PFC_ICMD
100 kHz CNTL _2P2Z 4 (I loop)
100 kHz PFC2PHIL_DRV
30
36
26
50 kHz F ILT_BIQUAD
46
50 kHz INV_SQR
78
FW_Isr
200 kHz
Stats
% Util
58%
24
200 kHz Time slice Mgmt
I_FOLD_BACK
ZVSFB_DRV
ADCSEQ1_DRV
F ILT_2P2Z
AC_LINE_RECT
PWM (kHz) = 200
PWM (bits) = 9.0
Every ISR call
Context Save
ADCSEQ2_DRV
CNTL_2P2Z(1)
CNTL_2P2Z(2)
ZVSFB_DRV
ADCSEQ1_DRV
FILT_2P2Z
AC_LINE_RECT
117
% Util
Time Slice mgr
82%
#Cyc. Rem.
91
145
% Util
87%
#Cyc. Rem.
63
117
% Util
82%
#Cyc. Rem.
91
124
50 kHz
50 kHz
50 kHz
50 kHz
TS1
TS2
TS3
TS4
PFC_OVP
PFC_ICMD
CNTL_2P2Z(4)
PFC2PHIL_DRV
BOXCAR_AVG (1)
BOXCAR_AVG (2)
PFC_ISHARE
ExecPS (1 :50)
CNTL_2P2Z(3)
PFC_OVP
PFC_ICMD
CNTL_2P2Z(4)
PFC2PHIL_DRV
FILT_BIQUAD
INV_SQR
% Util
83%
#Cyc. Rem.
84
BG
Function / Activity
Comms + Supervisory
+ Soft-Start + Other ?
SLEW_LIMIT 1
SLEW_LIMIT 2
# inst.
400
Stats
Int Ack
Context restore
17
17
% ISR utilization =
Spare ISR MIPS =
BG loop rate (kHz ) / (us) =
72
Tot.Cyc.
434
Return
87%
12.6
29.0
34.4
C28x Digital Power Supply Workshop
5 – Summary and Conclusion
5 – Summary and Conclusion
Summary and Conclusion
‹
‹
‹
Review of Workshop Topics and
Exercises
TI Digital Power Products
Š C2000 Digital Signal Controller
Family
Š UCD9xxx Digital Power Controller
Family
Where to Find More Information
Review of Workshop Topics and Exercises
Workshop Topics and Exercises Review
‹
C28x DSC family provides ideal controller
for Digital Power Supply design
Š
Š
‹
‹
‹
Scalable ePWM peripherals, ADC and fault
management support
Code Composer Studio, DPS Library and TI
Buck EVM
Controlled Buck output voltage using
PWM waveform and duty cycle without
feedback
Controlled Buck output using Voltage
Mode Control with feedback
Tuned closed-loop Buck power stage
visually using CCS features
C28x Digital Power Supply Workshop
73
5 – Summary and Conclusion
TI Digital Power Products
TI Is The Right Digital Power Partner
TI solutions cover the spectrum of power applications
Flexibility
TMS320F282x
TMS320F281x
TMS320F283x
TMS320F280x
Fully Programmable,
Control Focused
UCD9111
UCD9112
UCD9220
UCD9240
Power-Optimized
Controllers
System Complexity
TI’s Digital Power Solutions Span the
Industry
Non-Isolated DC/DC POL
Isolated DC/DC &
Offline AC/DC
• UCD91xx Single-Output Digital Controller • TMS320C2000 Digital Signal Controllers
• UCD92xx Multi-Output Digital Controller
• TMS320C2000 Digital Signal Controllers
DC/AC Inverters
• TMS320C2000 32-bit controller
solutions for green energy (solar, wind,
fuel cells) and UPS battery backup
74
System Management
Only
• UCD9080 Power Supply Sequencer
and Monitor
C28x Digital Power Supply Workshop
5 – Summary and Conclusion
C2000 Digital Signal Controller Family
C2000 Family Roadmap
Future
Future
C28xxx
C28xxx
ance
m
r
o
F283xx
Perf
300 MFLOPS
FPU, DMA
F282xx
F282xx
150
150 MHz
MHz
DMA
DMA
F281x
F281x
150
150 MHz
MHz
88 Devices
Devices
n
ratio
g
e
t
In
Future
C28xxx
F280x
F280xx
100
MHz
100MHz
150ps PWM
PWM
150ps
F280xx
F280xx
60 MHz
MHz
60
150ps PWM
PWM
150ps
TMS320F280xx Digital Signal Controllers
High Performance Signal Processing
Code security
32-256
KB
Flash
12-36
KB
RAM
ƒ
8KB
Boot
ROM
ƒ
PWM
Event Capture
Memory Bus
C28xTM 32-bit DSC
32x32-bit
Multiplier
R‚M‚W
Atomic
ALU
32-bit
Timers (3)
Real-Time
JTAG
Peripheral Bus
Interrupt Management
QEP
12-bit ADC
Watchdog
ƒ
Memory Sub-System
Fast program execution out of both RAM and
Flash memory
ƒ 80 MIPS with Flash Acceleration Technology
ƒ 100 MIPS out of RAM for time-critical code
Control Peripherals
CAN 2.0 B
I2C
SCI
32-bit
Register
File
ƒ
Up to 100 MHz performance
Single cycle 32 x32-bit MAC (or dual 16 x16 MAC)
Very Fast Interrupt Response
Single cycle read-modify-write
SPI
GPIO
Up to 16 PWM channels and 4 event captures
150 ps High-Resolution PWM
Ultra-Fast 12-bit ADC
ƒ 6.25 MSPS throughput
ƒ Dual sample&holds enable simultaneous sampling
ƒ Auto Sequencer, up to 16 conversions w/o CPU
Communications Ports
Multiple standard communication ports provide
simple interfaces to other components
Datasheet available at: http://www-s.ti.com/sc/ds/tms320f2808.pdf
C28x Digital Power Supply Workshop
75
5 – Summary and Conclusion
F280xx Controller Portfolio
All Devices are 100% Hardware, Software & Pin Compatible
MHz
Flash
KB
RAM
KB
12-bit
16-ch
ADC
PWM/
Hi-Res.
CAP/
QEP
Communication
Ports
F28015
60
32
12
267ns
10/4
2/0
SPI, SCI, I2C
F28016
60
32
12
267ns
10/4
2/0
SPI, SCI, CAN, I2C
F2801-60
60
32
12
267ns
8/3
2/1
2x SPI, SCI, CAN, I2C
F2802-60
60
64
12
267ns
8/3
2/1
2x SPI, SCI, CAN, I2C
F2801
100
32
12
160ns
8/3
2/1
2x SPI, SCI, CAN, I2C
F2802
100
64
12
160ns
8/3
2/1
2x SPI, SCI, CAN, I2C
F2806
100
64
20
160ns
16/4
4/2
4x SPI, 2x SCI, CAN, I2C
F2808
100
128
36
160ns
16/4
4/2
4x SPI, 2x SCI, 2x CAN, I2C
F2809
100
256
36
80ns
16/6
4/2
4x SPI, 2x SCI, 2x CAN, I2C
F28044
100
128
20
80ns
16/16
0
SPI, SCI, I2C
TMS320
100-pin LQFP and u*BGA; Also available in -40 to 125 C and Automotive Q100
TMS320F283xx Digital Signal Controllers
High Performance Signal Processing
Code security
128-512
KB
Flash
ƒ
52-68
KB
RAM
8KB
Boot
ROM
PWM
Event Capture
Memory Bus
Interrupt Management
TM
C28x 32-bit DSC
32x32-bit
Multiplier
R‚M‚W
Atomic
ALU
32-bit
Timers (3)
Real-Time
JTAG
Peripheral Bus
DMA
QEP
12-bit ADC
Watchdog
ƒ
Memory Sub-System
Fast program execution out of both RAM and
Flash memory
ƒ 120 MIPS with Flash Acceleration Technology
ƒ 150 MIPS out of RAM for time-critical code
Control Peripherals
CAN 2.0 B
I2C
SCI
32-bit
FloatingPoint Unit
ƒ
Up to 150 MHz performance with 32-bit floatingpoint unit
Six-channel DMA speeds data throughput
Very Fast Interrupt Response
SPI
McBSP
Up to 16 PWM channels and 4 event captures
150 ps High-Resolution PWM
Ultra-Fast 12-bit ADC
ƒ 12.5 MSPS throughput
ƒ Dual sample&holds enable simultaneous sampling
ƒ Auto Sequencer, up to 16 conversions w/o CPU
Communications Ports
Multiple standard communication ports provide
simple interfaces to other components
Datasheet available at: http://www-s.ti.com/sc/ds/tms320f28335.pdf
76
C28x Digital Power Supply Workshop
5 – Summary and Conclusion
F283xx & F282xx Controller Portfolio
TMS320
MHz
FPU
Flash
KB
RAM
KB
12-bit
16-ch ADC
DMA
PWM/
HRPW M
CAP/
QEP
F28335
150
Yes
512
68
80 ns
Yes
18/6
6/2
F28334
150
Yes
256
68
80 ns
Yes
18/6
4/2
F28332
100
Yes
128
52
80 ns
Yes
16/4
4/2
F28235
150
No
512
68
80 ns
Yes
18/6
6/2
F28234
150
No
256
68
80 ns
Yes
18/6
4/2
F28232
100
No
128
52
80 ns
Yes
16/4
4/2
Communication
Ports
SPI, 3x SCI, I2C,
2x McBSP, 2x
CAN
SPI, 3x SCI, I2C,
2x McBSP, 2x
CAN
SPI, 2x SCI, I2C,
McBSP, 2x CAN
SPI, 3x SCI, I2C,
2x McBSP, 2x
CAN
SPI, 3x SCI, I2C,
2x McBSP, 2x
CAN
SPI, 2x SCI, I2C,
McBSP, 2x CAN
• 176-pin/ball LQFP/PBGA; 179-ball u*BGA; -40 to 125 C and Q100 in PBGA
• IQMath library provides software compatibility between floating-point and
fixed-point!
C2000 controlCARDs
‹
‹
‹
‹
‹
‹
‹
F2808
F28335
only $59!
only $69!
New low cost single-board controllers perfect for initial
software development and small volume system builds.
Small form factor (9cm x 2.5cm) with standard 100-pin DIMM
interface
F28x analog I/O, digital I/O, and JTAG signals available at
DIMM interface
Isolated RS-232 interface
Single 5V power supply required
controlCARDs available for 100MHz fixed-point
TMS320F2808, TMS320F28044, and 150 MHz
TMS320F28335 floating-point controller
controlCARDs are available individually through TI distributors
and on the web:
Š
Part Number: TMDSCNCD2808, TMDSCNCD28044,
TMDSCNCD28335
C28x Digital Power Supply Workshop
77
5 – Summary and Conclusion
Digital Power Experimenter Kit
DPEK
only $229!
‹
DPEK includes
Š
Š
Š
Š
Š
Š
Š
‹
2-rail DC/DC EVM using TI
PowerTrain™ modules (10A)
On-board digital multi-meter and
active load for transient
response tuning
F2808 controlCARD
C2000 Applications Software CD
with example code and full
hardware details
Digital Power Supply Workshop
teaching material and lab
software
Code Composer Studio v3.3 with
code size limit of 32KB
9VDC power supply
DPEK available through TI
authorized distributors and on
the web
Š
Part Number:TMDSDCDC2KIT
C2000 DC/DC Developer’s Kit
Only
$325!
‹
DC/DC Kit includes
Š
Š
Š
Š
Š
‹
Available through TI
authorized distributors and on
the web
Š
78
8-rail DC/DC EVM using TI
PowerTrain™ modules (10A)
F28044 controlCARD
C2000 Applications Software CD
with example code and full
hardware details
Code Composer Studio v3.3 with
code size limit of 32KB
9VDC power supply
Part Number: TMDSDCDC8KIT
C28x Digital Power Supply Workshop
5 – Summary and Conclusion
C2000 AC/DC Developer’s Kit
Only
‹
AC/DC Kit includes
Š
$695!
Š
Š
Š
‹
AC/DC EVM features
Š
Š
Š
Š
Š
‹
AC/DC EVM with interleaved PFC
and phase-shifted full-bridge
F2808 controlCARD
C2000 Applications Software CD
with example code and full
hardware details
Code Composer Studio v3.3 with
code size limit of 32KB
12VAC in, 80W/10A output
Primary side control
Synchronous rectification
Peak current mode control
Two-phase PFC with current
balancing
AC/DC Kit available through TI
authorized distributors and on the
web
Š
Part Number: TMDSACDCKIT
Emulation Solutions for C2000 Controllers
‹
BlackHawk USB2000
Controller only $299
Š Full CCS compatibility
Š Bi-Color Status LED
(red/green)
Š 3.3/5.0 volt device I/O
Š
‹
‹
Optional Isolation Adaptor for
$299
http://www.blackhawkdsp.com/Resellers.aspx
C28x Digital Power Supply Workshop
‹
Spectrum Digital XDS510-LC
only $249
Š Full CCS compatibility
Š Supports SDFlash
programming utility
Š Supports XMLGUI for
interfacing to ‘C’ – provides
scripting capability
http://www.spectrumdigital.com
79
5 – Summary and Conclusion
VisSim Graphical Programming
for C2000
‹
‹
‹
‹
‹
www.vissim.com
Model based design for
simulation, code generation,
and interactive debugging
Efficient code generation
near hand code quality
Automatic code generation
for F28xx peripherals: ADC,
SCI, SPI, I2C, CAN, ePWM,
GPIO
High speed target
acquisition for wave form
display on PC
Watch ‘how to’ tutorials on
Visual Solutions web site
UCD9xxx Digital Power Controller Family
Performance
UCD9xxx Digital Power Controller Family
UCD92xx
UCD9240
4 ind outputs
64 & 80 pin
UCD9230
3 ind outputs
48 pin
UCD9220
2 ind outputs
32 pin
UCD9112
1 output, 2 phase
32 pin
UCD9111
1 output, 1 phase
32 pin
UCD91xx
Integration
80
C28x Digital Power Supply Workshop
5 – Summary and Conclusion
Where to Find More Information
Recommended Next Step:
One-day Training Course
TMS320C28x 1-Day Workshop Outline
- Workshop Introduction
- Architecture Overview
- Programming Development Environment
- Peripheral Register Header Files
- Reset, Interrupts and System Initialization
- Control Peripherals
- IQ Math Library and DSP/BIOS
- Flash Programming
Introduction to
TMS320F2808
Design and
Peripheral Training
- The Next Step…
Recommended Next Step:
Multi-day Training Course
TMS320C28x Multi-day Workshop Outline
- Architectural Overview
- Programming Development Environment
- Peripheral Register Header Files
- Reset and Interrupts
- System Initialization
- Analog-to-Digital Converter
- Control Peripherals
- Numerical Concepts and IQmath
In-depth
TMS320F2808
Design and
Peripheral Training
C28x Digital Power Supply Workshop
- Using DSP/BIOS
- System Design
- Communications
- Support Resources
81
5 – Summary and Conclusion
For More Information . . .
Internet
Website: http://www.ti.com
FAQ: http://www-k.ext.ti.com/sc/technical_support/knowledgebase.htm
Š Device information
Š my.ti.com
Š Application notes
Š News and events
Š Technical documentation
Š Training
Enroll in Technical Training: http://www.ti.com/sc/training
USA - Product Information Center ( PIC )
Phone: 800-477-8924 or 972-644-5580
Email: support@ti.com
Š Information and support for all TI Semiconductor products/tools
Š Submit suggestions and errata for tools, silicon and documents
European Product Information Center (EPIC)
Web: http://www-k.ext.ti.com/sc/technical_support/pic/euro.htm
Phone: Language
Belgium (English)
France
Germany
Israel (English)
Italy
Netherlands (English)
Spain
Sweden (English)
United Kingdom
Finland (English)
Fax: All Languages
Number
+32 (0) 27 45 55 32
+33 (0) 1 30 70 11 64
+49 (0) 8161 80 33 11
1800 949 0107 (free phone)
800 79 11 37 (free phone)
+31 (0) 546 87 95 45
+34 902 35 40 28
+46 (0) 8587 555 22
+44 (0) 1604 66 33 99
+358(0) 9 25 17 39 48
+49 (0) 8161 80 2045
Email: epic@ti.com
Š Literature, Sample Requests and Analog EVM Ordering
Š Information, Technical and Design support for all Catalog TI
Semiconductor products/tools
Š Submit suggestions and errata for tools, silicon and documents
82
C28x Digital Power Supply Workshop