40V Precision Instrumentation Amplifier with
Differential ADC Driver
ISL28617
Features
The ISL28617 is a high performance, differential input, differential
output instrumentation amplifier designed for precision analog to
digital applications. It can operate over a supply range of 8V (±4V) to
40V (±20V) and features a differential input voltage range up to
±34V. The output stage has rail-to-rail output drive capability
optimized for differential ADC driver applications. Its versatility and
small package makes it suitable for a variety of general purpose
applications. Additional features not found in other instrumentation
amplifiers enable high levels of DC precision and excellent AC
performance.
• Rail-to-rail Differential Output ADC Driver
• High Voltage Interface to Low Voltage Circuits
• Wide Operating Voltage Range . . . . . . . . . . . . . . ±4V to ±20V
• Low Input Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30μV
• Excellent CMRR and PSRR . . . . . . . . . . . . . . . . . . . . . . . 120dB
• Closed Loop -3dB BW . .0.3MHz (AV = 1k) to 5MHz (AV = 0.1)
• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
• Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ld TSSOP
The gain of the ISL28617 can be programmed from 0.1 to
10,000 via two external resistors, RIN and RFB. The gain accuracy
is determined by the matching of RIN and RFB. The gain resistors
have Kelvin sensing, which removes gain error due to PC trace
resistance. The input and output stages have individual power
supply pins, which enable input signals riding on a high common
mode voltage to be level shifted to a low voltage device, such as
an A/D converter. The rail-to-rail output stage can be powered
from the same supplies as the ADC, which preserves the ADC
maximum input dynamic range and eliminates ADC input
overdrive.
Applications
• Precision Test and Measurement
• High Voltage Industrial Process Control
• Signal Conditioning Amplifier for Remote Powered Sensors
• Weigh Scales
• ECG and Biomedical Sense Amplifiers
140
120
The ISL28617 is offered in the 24 Ld TSSOP package, and is
guaranteed over -40°C to +125°C operation.
CMRR (dB)
100
Related Literature
• “ISL28617VYXXEV1Z User’s Guide” AN1753
80
AV = 1000
60
AV = 100
40
• “ISL28617SMXXEV1Z User’s Guide” AN1748
AV = 10
AV = 1
20
0
AV = 0.1
1
10
100
1k
10k
100k
1M
FREQUENCY(Hz)
FIGURE 1. CMRR RF = 121k
FULL BRIDGE STRAIN GAUGE AMPLIFIER AND DIFFERENTIAL ADC DRIVER
IN+
+5V
TO
+20V
RIN
BRIDGE
EXCITATION
-5V
TO
-20V
RFB
VCC
+RIN
+RINSENSE
-RINSENSE
-RIN
ISL28617
+RFB
+RFBSENSE
-RFBSENSE
-RFB V GND
EE
IN-
VCO
+VFB
+VOUT
R
C
-VOUT
-VFB
VCMO
+IN
-IN
R
VEO
VDD
A-D
CONVERTER
ISL26132
VREF GND
+5V
VREF
ISL21090
AV = RFB/RIN RANGE FROM 0.1 TO 10,000
FIGURE 2. BASIC APPLICATION CIRCUIT
May 25, 2012
FN6562.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL28617
Pin Descriptions
SL28617
(24 LD TSSOP)
TOP VIEW
NC 1
24 IN+
DNC 2
23 IN-
DNC 3
22 DNC
21 +RIN
+RFB 4
+RFB SENSE 5
20 +RIN SENSE
-RFB SENSE 6
19 -RIN SENSE
-RFB 7
18 -RIN
GND 8
17 VCMO
VCC 9
16 VEE
VCO 10
15 VEO
+VFB 11
14 -VFB
13 -VOUT
+VOUT 12
PIN
NAME
PIN NUMBERS
NC
1
DNC
2, 3, 22
DESCRIPTION
No Internal Connection
For internal use; Do Not Connect
+RFB
4
Feedback Resistor, RFB+ pin
+RFB SENSE
5
+RFB, Positive Sense pin connects to the
resistor RFB+ terminal to form the RFB+
Kelvin connection
-RFB SENSE
6
-RFB, Negative Sense pin connects to the
resistor RFB- terminal to form the RFBKelvin connection
-RFB
7
Feedback Resistor, Negative Terminal
GND
8
Ground Pin is capacitively coupled to the
internal ESD circuit and should be
connected to power supply common or
signal GND.
VCC
9
Positive Supply for Input Stage and
Feedback Amp
VCO
10
Positive Supply for Output Stage
+VFB
11
Positive Output Feedback
+VOUT
12
Positive Output
-VOUT
13
Negative Output
-VFB
14
Negative Output Feedback
VEO
15
Negative Supply for Output Stage
VEE
16
Negative Supply for Input Stage and
Feedback Amp
VCMO
17
Output Common Mode Reference input
-RIN
18
Input Resistor, Negative Terminal
-RIN SENSE
19
-RIN, Negative Sense pin connects to the
resistor RIN- terminal to form the RINKelvin connection
+RIN SENSE
20
+RIN, Positive Sense pin connects to the
resistor RIN+ terminal to form the RIN+
Kelvin connection
+RIN
21
Input Resistor, Positive Terminal
IN-
23
Negative Input
IN+
24
Positive Input
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL28617FVZ
28617 FVZ
TEMP RANGE
(°C)
-40°C to +125°C
PACKAGE
(Pb-Free)
24 Ld TSSOP
PKG.
DWG. #
M24.173
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28617. For more information on MSL please see tech brief TB363.
2
FN6562.0
May 25, 2012
ISL28617
Simplified Block Diagram
+15V
IN+
ISL28617
VCC
IN+
+RINSENSE
VCO
VCC
+RIN
RIN
-RIN
-RINSENSE
IN-
VEE
+VOUT
IN-
-VOUT
+VFB
+RFBSENSE
+OUT
RL
-OUT
VCMO
VCC
+RFB
RFB
-RFB
-RFBSENSE
-VFB
VEE
VEE
-15V
3
GND
VEO
GND
FN6562.0
May 25, 2012
ISL28617
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage (VCC to VEE or GND) . . . . . . . . . . . . . . . . . . . . 42V
Maximum Supply Voltage (VCO to VEO or GND) . . . . . . . . . . . . . . . . . . . . 42V
Maximum Voltage (VCO to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.5V, -40V
Maximum Voltage (VEO to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V, +40V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Max/Min Input Current for Input Voltage >VCC or <VEE . . . . . . . . . . . . . ±10mA
Maximum Input Current (±RIN, ±RFB, ±RINSENSE, ±RFBSENSE) . . . .±5mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . .(VEE - 0.5V) to (VCC +0.5V)
Output Short-Circuit Duration (1 Output at a Time) . . . . . . . . . . . . . Continuous
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Thermal Resistance (Typical, Note 4)
θJA (°C/W)
24 Ld TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VCC, VEE Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . ±4V to ±20V
VCO, VE+ Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . ±1.5V to ±20V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted,
all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = 10kΩ, RFB = RIN = 30.1kΩ, TA = +25°C, unless otherwise
specified. Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
VCC -3V
V
100
µV
275
µV
INPUT DC SPECIFICATIONS
VCMIRIN
VOSIN
IN+, IN- Common Mode Input Voltage Range
VEE +3V
Input Offset Voltage
-100
±30
-275
TCVOSIN
IBIN
Input Offset Voltage Temperature Coefficient
Input Bias Current
-2.75
±0.3
2.75
µV/°C
-1
±0.2
1
nA
1.3
nA
0.75
nA
1
nA
117
µA
-1.3
IOSIN
Input Offset Current
-0.75
±0.2
-1
IRIN
Input Resistor Drive Current
RINCM
Common Mode Input Resistance
CMRR
Common Mode Rejection Ratio
(Note 9)
87
VEE +3V < VCM < VCC -3V
G=1
110
VEE +3V < VCM < VCC -3V
G = 100
130
102
80
GΩ
120
dB
107
dB
150
dB
110
dB
FEEDBACK DC SPECIFICATIONS
VCMIRFB
VOSFB
+FB, -FB Common Mode Input Voltage Range
Feedback Input Offset Voltage
VEE +3V
-1600
±400
-3000
IBVFB+,-
Input Bias Current at VFB ± Inputs
4
15
VCC -3V
V
1600
µV
3000
µV
nA
FN6562.0
May 25, 2012
ISL28617
Electrical Specifications VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = 10kΩ, RFB = RIN = 30.1kΩ, TA = +25°C, unless otherwise
specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
TYP
MAX
(Note 5)
UNIT
VCC = +15V, VEE = -15V,
VCO = +4V, VEO = -4V
RIN = RF = 121kΩ, IOUT = 1.5mA
150
200
mV
200
mV
VCC = +15V, VEE = -15V,
VCO = +4V, VEO = -4V
RIN = RF = 121kΩ, IOUT = 1.5mA
150
200
mV
200
mV
RL = 0Ω to GND
±45
DESCRIPTION
CONDITIONS
MIN
(Note 5)
OUTPUT DC SPECIFICATIONS
VOL
VOH
ISC
Output Voltage Low, VOUT to V-
Output Voltage High, V+ to VOUT
Output Short Circuit Current
-20
IERR
Total Internal Offset Error Current (Note 8)
-17
±5
-90
EG
Gain Error (Notes 6, 7)
mA
20
mA
17
nA
90
nA
VOUT = -10V to +10V, RF = 121kΩ
G=1
±0.003
%
G = 100
±0.004
%
±0.0005
%
VOUT = -2.5V to +2.5V, RF = 30.1kΩ
G=1
OUTPUT COMMON MODE SPECIFICATIONS
VCMOCMIR
VOSCM
IBVCMO
Output Common Mode Control Input Voltage
Range
VEE +3V
Output Common Mode Offset Voltage from
VCMO Input
-1.3
±0.5
-4.75
Input Bias Current at VCMO Input
-0.6
±0.2
-1.75
VCC -3V
V
1.3
mV
4.75
mV
0.6
µA
1.75
µA
2.2
mA
2.85
mA
2.6
mA
2.85
mA
POWER SUPPLY SPECIFICATIONS
ICC
ICO
VCC to VEE
VCO to VEO
Supply Current, VCC to VEE
Supply Current, VCO to VEO
Input Supply Voltage
Output Supply Voltage
RL = OPEN
RL = OPEN
2.25
Dual Supply
±4
±20
V
Single Supply
8
40
V
±1.5
±20
V
3
40
V
Dual Supply
Single Supply
PSRR VCC to VEE Power Supply Rejection Ratio
2.05
VCC to VEE = ±4V to ±20V
G = 100
123
130
118
PSRR VCO to VEO Power Supply Rejection Ratio
VCO to VEO = ±4V to ±20V
110
dB
dB
120
110
dB
dB
AC SPECIFICATIONS
eN
eNrms
Input Noise Voltage Density
f = 1kHz
8.6
nV/√Hz
Input rms Noise Voltage
f = 0.1 to 10Hz
85
nVrms
5
FN6562.0
May 25, 2012
ISL28617
Electrical Specifications VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = 10kΩ, RFB = RIN = 30.1kΩ, TA = +25°C, unless otherwise
specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
iN
iNIERR
iNIERR rms
-3dB BW
-3dB BW
DESCRIPTION
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
Input Noise Current Density
f = 1kHz
150
fA/√Hz
Total Internal Noise Current Density
f = 1kHz
2.6
pA/√Hz
0.1 to 10Hz Total Internal rms Noise Current
f = 0.1 to 10Hz
4
pArms
-3dB Bandwidth vs. Closed Loop Gain,
RFB = 30.1k
RFB = 30.1kΩ; RIN = 301kΩ; G = 0.1
5.5
MHz
RFB = 30.1kΩ; RIN = 30.1kΩ; G = 1
2.6
MHz
RFB = 30.1kΩ; RIN = 3.01kΩ; G = 10
2.2
MHz
RFB = 30.1kΩ; RIN = 301Ω; G = 100
2.0
MHz
RFB = 30.1kΩ; RIN = 30.1Ω; G = 1000
0.3
MHz
RFB = 121kΩ; RIN = 1.21MΩ; G = 0.1
5.0
MHz
RFB = 121kΩ; RIN = 121kΩ; G = 1
1.4
MHz
RFB = 121kΩ; RIN = 12.1kΩ; G = 10
0.5
MHz
RFB = 121kΩ; RIN = 1.21kΩ; G = 100
0.45
MHz
RFB = 121kΩ; RIN = 121Ω; G = 1000
0.4
MHz
4
V/µs
VOUT = +2.4V, RF = 30.1kΩ
3
µs
VOUT = +9.6V, RF = 121kΩ
11
µs
-3dB Bandwidth vs. Closed Loop Gain,
RFB = 121k
SR
Slew Rate
tS
Settling Time to 0.01%
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Differential Gain(AV) = RFB/RIN.
7. ±VOUT, clipping ~ IRF*RFB.
8. VOS,OUT = AV*VOS,IN + VOS,FB + IERR * RFB.
9. Compliance to datasheet limits is assured by Design simulation.
6
FN6562.0
May 25, 2012
ISL28617
Typical Performance Curves
VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = Open, unless otherwise specified.
20
20
15
10
10
Ierr (nA)
Ierr (nA)
5
0
-5
-10
0
-10
-15
-20
-15
-20
-10
-5
0
5
10
15
0
5
10
15
VCM (V)
1000
1000
800
800
600
600
400
400
200
0
-200
-600
-800
-800
-1000
-1000
5
10
0
15
1000
1000
800
800
600
600
400
400
200
200
0
-200
-400
-600
-800
-800
-1000
-1000
15
20
25
30
VSUP (VCC - VEE)
35
40
FIGURE 7. IOS vs SUPPLY VOLTAGE (VCC - VEE)
7
45
5
10
15
20
25
30
VSUP (VCC - VEE)
35
40
45
50
0
-600
10
50
-200
-400
5
45
FIGURE 6. VOSFB vs SUPPLY VOLTAGE (VCC - VEE)
IOS (pA)
IOS (pA)
FIGURE 5. VOSFB vs INPUT COMMON MODE VOLTAGE
0
40
-200
-400
0
VCM (V)
35
0
-600
-5
30
200
-400
-10
25
FIGURE 4. IERR vs SUPPLY VOLTAGE (VCC - VEE)
VOSFB (mV)
VOSFB (mV)
FIGURE 3. IERR vs INPUT COMMON MODE VOLTAGE
-15
20
VSUP (VCC - V EE)
50
0
5
10
15
20
25
30
VSUP (VCC - VEE)
35
40
45
50
FIGURE 8. IOS vs SUPPLY VOLTAGE (VCC - VEE)
FN6562.0
May 25, 2012
ISL28617
Typical Performance Curves
VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = Open, unless otherwise specified.
1000
1000
800
800
+IB
600
400
400
200
200
IB (pA)
IB (pA)
600
0
-200
0
-200
-IB
-400
-IB
-400
-600
-600
-800
-800
-1000
-15
+IB
-10
-5
0
5
10
-1000
0
15
5
10
15
25
30
35
40
45
50
VSUP (VCC- VEE)
VCM (V)
FIGURE 9. IB vs INPUT COMMON MODE VOLTAGE
FIGURE 10. IB vs SUPPLY VOLTAGE (VCC - VEE)
100
100
80
80
60
60
40
40
VOS IN (mV)
VOS IN (mV)
20
20
0
-20
20
0
-20
-40
-40
-60
-60
-80
-80
-100
-15
-10
-5
0
5
10
15
-100
0
5
10
15
20
25
30
35
40
45
50
VSUP (VCC - VEE)
VCM (V)
FIGURE 11. VOSIN vs INPUT COMMON MODE VOLTAGE
FIGURE 12. VOSIN vs SUPPLY VOLTAGE (VCC - VEE)
5
3
4
SUPPLY CURRENT (mA)
3
IBVCMO (mA)
2
1
0
-1
-2
-3
2
-4
-5
-15
-10
-5
0
5
10
VCMO (V)
FIGURE 13. IBVCMO vs VCMO INPUT VOLTAGE RANGE
8
15
1
0
10
20
30
40
50
SUPPLY VOLTAGE (VCC - VEE)
FIGURE 14. ICC vs SUPPLY VOLTAGE (VCC - VEE)
FN6562.0
May 25, 2012
ISL28617
Typical Performance Curves
VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = Open, unless otherwise specified.
80
RIN = 301
RFB = 30.1k
AV = 100
40
2
RIN = 30.1, RFB = 30.1k
AV = 1000
60
GAIN (dB)
SUPPLY CURRENT (mA)
3
RIN = 3.01k, RFB = 30.1k
AV = 10
20
RIN = 30.1k, RFB = 30.1k
AV = 1
0
AV = 0.1
-20
RIN = 301k, RFB = 30.1k
1
0
10
20
30
40
-40
10
50
100
SUPPLY VOLTAGE (VCO - VEO)
GAIN (dB)
RIN = 12.1k, RFB = 121k
AV = 10
20
RIN = 121k, RFB = 121k
AV = 1
0
AV = 0.1
-20
10
100
1k
10k
100k
1M
100
80
AV = 1000
60 A = 100
V
40 AV = 10
AV = 1
10M
AV = 0.1
0
1
100M
10
160
160
140
140
120
120
100
AV = 1000
AV = 100
40
AV = 10
20
0
1
AV = 1
AV = 0.1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 19. NEGATIVE PSRR VEE & VCC (RF = 30.1k)
9
1k
10k
100k
1M
FIGURE 18. POSITIVE PSRR VEE & VCC (RF = 30.1k)
POSITIVE PSRR (dB)
NEGATIVE PSRR (dB)
FIGURE 17. CLOSED LOOP GAIN (RFB= 121k) vs FREQUENCY
60
100
FREQUENCY (Hz)
FREQUENCY (Hz)
80
100M
120
20
RIN = 1.21M, RFB = 121k
-40
10M
140
RIN = 1.21k
RFB = 121k
AV = 100
40
1M
160
POSITIVE PSRR (dB)
60
100k
FIGURE 16. CLOSED LOOP GAIN (RFB = 30.1k) vs FREQUENCY)
RIN = 121, RFB = 121k
AV = 1000
10k
FREQUENCY (Hz)
FIGURE 15. ICO vs SUPPLY VOLTAGE (VCO - VEO)
80
1k
1M
100
80
AV = 1000
60
AV = 100
40
AV = 10
20
AV = 1
0
1
AV = 0.1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 20. POSITIVE PSRR VEE & VCC (RF = 121k)
FN6562.0
May 25, 2012
ISL28617
VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = Open, unless otherwise specified.
160
180
140
160
120
POSITIVE PSRR (dB)
NEGATIVE PSRR (dB)
Typical Performance Curves
100
80
60
AV = 1000
AV = 100
40
AV = 10
20
AV = 1
0
1
120
100
80
60
40
20
AV = 0.1
10
140
100
1k
10k
100k
0
1
1M
AV = 1000
AV = 100
AV = 10
AV = 1
AV = 0.1
10
180
200
160
180
140
160
120
100
80 A = 1000
V
60 AV = 100
40 AV = 10
1k
10k
100k
80
60
40
AV = 1000
AV = 100
AV = 10
AV = 1
AV = 0.1
10
120
CMRR RFB = 30.1k (dB)
NEGATIVE PSRR (dB)
140
120
100
80
AV = 1000
AV = 100
40 A = 10
V
100k
FREQUENCY (Hz)
FIGURE 25. NEGATIVE PSRR VE0 & VCO (RF = 121k)
10
10k
100k
1M
100
80
60
40
20
10k
1k
FIGURE 24. POSITIVE PSRR VEO & VCO (RF = 121k)
140
1k
100
FREQUENCY (Hz)
160
100
1M
100
0
1
1M
FIGURE 23. NEGATIVE PSRR VEO & VCO (RF = 30.1k)
20 AV = 1
AV = 0.1
0
1
10
100k
120
FREQUENCY (Hz)
60
10k
140
20
100
1k
FIGURE 22. POSITIVE PSRR VE0 & VC0 (RF = 30.1k)
POSITIVE PSRR (dB)
NEGATIVE PSRR (dB)
FIGURE 21. NEGATIVE PSRR VEE & VCC (RF = 121k)
20 AV = 1
A = 0.1
0 V
1
10
100
FREQUENCY (Hz)
FREQUENCY (Hz)
1M
0
1
AV = 1000
AV = 100
AV = 10
AV = 1
AV = 0.1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 26. CMRR RF = 30.1k
FN6562.0
May 25, 2012
ISL28617
Typical Performance Curves
VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = Open, unless otherwise specified.
140
CMRR RFB = 121k (dB)
120
100
100nV
80
60
40
20
0
1
AV = 1000
AV = 100
AV = 10
AV = 1
AV = 0.1
10
100
1k
10k
100k
1pA
iN
10nV
0.1pA
eN
1nV
0.1
1M
INPUT NOISE CURRENT (A/√Hz)
INPUT NOISE VOLTAGE (V/√Hz)
1000nV
1
10
100
1k
10k
0.01pA
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 27. CMRR RF = 121k
FIGURE 28. INPUT VOLTAGE AND CURRENT NOISE
INPUT
FEEDBACK
OUTPUT
STAGE
STAGE
STAGE
VCO
VCC
0.1µF
A5
0.1µF
I2
I1
IN-
IN+
I3
+VOUT
I1, I3
I2, I4
I4
+
A6
-
VFB-
500Ω
500Ω
-VOUT
+
A1
-
Q1
Q2
+
A2
-
+
A3
-
IS1
VFB+
+
A4
-
VCMO
100µA
100µA
VEE
Q4
Q3
IS3 IS4
IS2
VEO
0.1µF
0.1µF
+RIN
RIN
-RIN
-RINSENSE
+RINSENSE
+RFB
-RFBSENSE
RFB
-RFB
GND
+RFBSENSE
GAIN RESISTORS AND
KELVIN CONNECTIONS
FIGURE 29. ISL28617 FUNCTIONAL BLOCK DIAGRAM
11
FN6562.0
May 25, 2012
ISL28617
Applications Information
Feedback GM Amplifier
Section 1 contains the ISL28617 functional and performance
objectives and description of operation.
The feedback amplifiers A3, A4 form a differential trans
conductance amplifier identical to the input stage. The input
terminals (VFB+, VFB-) connect to the ISL28617 differential output
terminals (+VOUT, -VOUT) so that the output voltage also appears
across the feedback gain resistor RFB.
Section 2 contains the application circuit design equations and
guidelines for achieving the desired DC and AC performance
levels.
Section 3 provides equations for predicting DC offset voltage and
noise of the finished design.
Operation is the same as the input GM stage and the differential
currents I3, I4 are given by:
I3 = 100µA - {(+VOUT) - (-VOUT)}/RFB
(EQ. 3)
The ISL28617 Instrumentation Amplifier was developed to
accomplish the following:
I4 =100µA +{(+VOUT) - (-VOUT)}/RFB
(EQ. 4)
• Provide a fully differential, rail-to-rail output for optimally
driving ADCs.
Error Amplifier A5, Output Amplifier A6
(Figure 29)
• Limit the output swing to prevent output overdrive.
Amplifiers A5 and A6 act together to form a high gain,
differential I/O trans-impedance amplifier. Differential current
amplifier A5 sums the differential currents (I1+I3, I2+I4) from
the input and feedback GM amplifiers. From that summation, a
differential error voltage is sent to A6, which generates the railto-rail differential output drive to the +VOUT and -VOUT pins.
1. General Description
• Allow any gain, including attenuation.
• Maximize gain accuracy by removing on-chip component
tolerances and external PC board parasitic resistance.
• Enable user control of amplifier precision level with choice of
external resistor tolerance.
• Maintain CMRR>100dB and remove CMRR sensitivity to gain
resistor tolerance.
• Provide a level shift interface from bipolar analog input signal
sources to unipolar, and bipolar ADC output terminations.
Functional Description (Figure 29)
Figure 29 shows the functional block diagram for the ISL28617.
The external connection of the output pins to the feedback
amplifier closes a servo loop where a change in the differential
input voltage is converted into differential current imbalances at
I1, I2 (Equations 1, 2) at the summing node inputs to A5. Current
I1 sums with current I3 from the feedback stage, and I2 sums
with I4. A5 senses the difference between current pairs I1, I3 and
I2, I4. A difference voltage is generated, amplified and fed back
to the feedback amplifier, which creates correction currents at I3,
I4 to match the currents at I1, I2 (Equations 3, 4).
Input GM Amplifier
Therefore, at equilibrium:
The input stage consists of high performance, wide band
amplifiers A1, A2, GM drive transistors Q1, Q2, and input gain
resistor RIN. Current drive for Q1 and Q2 emitters are provided by
matched pair of 100µA current sinks. A unity gain buffer from
each input (IN+, IN-) to the terminals of the input resistor, RIN, is
formed by the connection of the Kelvin resistor sense pins and
drive pins to the terminals of the input resistor, as shown in
Figure 29. In this configuration, the voltage across the input
resistor RIN is equal to the input differential voltage across IN+
and IN-.
I1 = I3 and I2 = I4
The input GM stage operates by creating a current difference in
the collector currents Q1 and Q2 in response to the voltage
difference between the IN+ and IN- pins. When the input voltage
applied to the IN+ and IN- pins is zero, the voltage across the
terminals of the gain resistor RIN, is also zero. Since there is no
current flow through the gain resistor, the transistors Q1, and Q2
collector currents I1, I2 are equal.
Combining Equations 1 and 3, (and their complements I2 and
I4), and solving for VOUT as a function of VIN, RIN and RFB, yields
Equation 6:
VOUT = VIN*RFB/RIN ;
Where VOUT = (+VOUT) - (-VOUT) and VIN = IN+ - IN-
(EQ. 6)
Equation 6 can be rearranged to form the gain Equation 7:
Gain = VOUT/VIN = RFB/RIN
(EQ. 7)
which is general form of the gain Equation for the ISL28617.
2. Designing with the ISL28617
To complete a working design, the following procedure is
recommended and explained in this section:
A change in the input differential voltage causes an equivalent
voltage drop across the input gain resistor RIN, and the resulting
current flow through RIN, causes an imbalance in Q1, Q2
collector currents I1, I2, given by:
1. Define the output voltage swing.
I1= 100µA + (VIN+- VIN-)/RIN
(EQ. 1)
3. Set the VCO, VEO power supply voltages
I2= 100µA - (VIN+- VIN-)/RIN
(EQ. 2)
4. Set the VCC and VEE supply voltages
12
(EQ. 5)
2. Set the feedback resistor value, RFB
3. Set the input gain resistor value, RIN
FN6562.0
May 25, 2012
ISL28617
The gain of the instrumentation amplifier is set by the resistor
ratio RFB/RIN (Equation 7), and the maximum output swing is set
by the absolute value of the feedback resistor RFB (Equation 8).
VCO and VEO supply power to the rail-to-rail output stage and
define the maximum output voltage swing at the ±VOUT
différentiel output pins. Power supply pins VCC and VEE power the
feedback amplifiers which, require an additional ±3V beyond the
VCO and VEO voltages to maintain linear operation of the
feedback GM stage.
Setting the Feedback Gain Resistor RFB
(Figures 29, 30)
Resistor RFB defines the maximum differential voltage at output
terminals +VOUT to -VOUT. External resistor RFB and the differential
100µA current sources define the maximum dynamic range of
the feedback stage, which defines the maximum differential
output swing of the output stage. Overload circuitry allows
>100µA to flow through RFB to maintain feedback, but linearity is
degraded. Therefore, it is a good practice to keep the maximum
linear dynamic range to within ±80% of the maximum I*R across
the resistor.
VOUTDIFF= ±80µA * RFB
Output voltages that exceed the maximum dynamic range of the
feedback amplifier can degrade phase margin and cause
instability. The plot in Figure 30 shows the maximum differential
output voltage swing vs. resistor value for RFB and RIN using the
80% and 50% current source levels.
DYNAMIC VOLTAGE RANGE (±V)
There are a few cases where the input stage can be over driven,
which must be considered in the application. An input signal that
exceeds the maximum dynamic range of the gain resistor RIN,
calculated previously, can cause the ESD diodes to conduct.
When this occurs, a low impedance path from the inputs to the
input gain resistor RIN will result in signal distortion.
High speed input signals that remain within the maximum
dynamic range of the input stage can cause distortion if the input
slew rate exceeds the input stage slew rate (~4V/µs). When the
input slews at a faster rate than the GM stage can follow, the
voltage difference appears across the input ESD diodes from
each input and resistor RIN. When the voltage difference is large
enough to cause the diodes to conduct, the input terminals are
shunted to RIN through the 500Ω input protection resistors,
causing distortion during the rise and fall times of the transient
pulse. The distortion will last until the resistor voltage catches up
to the input voltage.
(EQ. 8)
In cases where large pulse overshoot is expected, the maximum
current in Equation 8 could be reduced to 50% for additional
margin (See “AC Performance Considerations” on page 15.) The
penalty for increasing the feedback resistor value is higher DC
offset voltage and noise.
35
IN-
500Ω
VCC
IN+
500Ω
+
A1
-
Q1
RIN
Q2
+
A2
ESD
PROTECTION
ESD
PROTECTION
100µA
100µA
VEE
30
FIGURE 31. INPUT STAGE ESD PROTECTION DIODES
25
Setting the Power Supply Voltages
VOUT (V) @ 80%
20
15
10
VOUT (V) @ 50%
5
0
Input Stage Overdrive Considerations
(Figure 31)
0
50
100
150
200
250
300
350
400
RFB, RIN VALUE (kΩ)
FIGURE 30. RFB, RIN vs. DYNAMIC RANGE
Setting the Input Gain Resistor RIN
(Figures 29, 30)
The input gain resistor RIN is scaled to the feedback resistor
according to the gain Equation 9:
RIN = RFB/Gain
(EQ. 9)
The input GM stage uses the same differential current source
arrangement as the feedback stage. Therefore, the amount of
overdrive margin (50%, 80%) included in the calculation for RFB
is also included in the calculation for RIN.
13
The ISL28617 power supplies are partitioned so that the input
stage and feedback stages are powered from a separate pair of
supply pins (VCC, VEE) than the differential output stage (VCO,
VEO). This partitioning provides the user with the ability to adapt
the ISL28617 to a wide variety of input signal power sources that
would not be possible if the supplies were strapped together
internally (VCC = VCO & VEE = VEO). However, powering the input
and output supplies from unequal supplies has restrictions that
are described in the next section.
Powering the Input and Feedback Stages
(VCC, VEE)
The input pins IN+, IN- cannot swing rail-to-rail, but have a
maximum input voltage range given by Equation 10:
VEE+ 3V < (VCMIRIN + VIN) < VCC - 3V;
where VIN = maximum differential voltage IN+ to IN-
(EQ. 10)
This requires the sum of the common mode input voltage and
the differential input voltage to remain within 3V of either the VCC
or VEE rail, otherwise distortion will result.
FN6562.0
May 25, 2012
ISL28617
The feedback pins VFB+ and VFB- have the same input common
mode voltage constraint as the input pins IN+, IN-. The maximum
input voltage range of the feedback pins is given by Equation 11:
VEE+ 3V < VCMIRFB < VCC - 3V
where VCMIRFB = (+VOUT - -VOUT) +VCMO
(EQ. 11)
To maintain stability, it is critical to respect the ±3V requirement
in Equation 11.
Powering the Rail-to-rail Output Stage
(VCO, VEO)
The output stage (A6) is of rail-to-rail design, and is powered by
the VCO and VEO pins. The differential output pins +VOUT, -VOUT
connect to the VFB+, VFB- pins to close the output feedback loop.
The feedback stage is powered from VCC and VEE pins. The VFB+,
VFB- have a common mode input range 3V below the VCC rail and
3V above the and VEE rail. If the output voltage exceeds the
feedback common mode input voltage, loop instability will result.
Therefore, the voltages at the ±VOUT pins should always be 3V
away from either rail, as shown in Equation 12.
VEE+ 3V < VOUT < VCC - 3V;
where VOUT = |+VOUT| or |-VOUT|
(EQ. 12)
Rail-to-rail Differential ADC Driver
The differential output stage of the ISL28617 is designed to drive
the differential input stage of an ADC. In this configuration, the
VCO, VEO power supply pins connect directly to the ADC power
supply pins. This output swing arrangement is ideal for driving
rail-to-rail ADC drive without the possibility of over driving the
ADC input.
The output stage is capable of rail-to-rail operation when VCO, VEO
are powered from a single supply or from split supplies. It has a
single supply voltage range (VCO) from 3V to 15V (with VEO at
GND), and a ±1.5V to ±15V split supply voltage range. Under all
power supply conditions, VCC must be greater than VCO by 3V, and
VEE must be less than VEO by 3V to maintain the rail-to-rail output
drive capability.
The VCMO pin is an input to a very low bias current terminal, and
sets the output common mode reference voltage when driving a
differential input ADC, such that the output would have a ± input
signal span centered around an external DC reference voltage
applied to the VCMO pin.
Power Supply Voltages by Application
The ISL28617 can be adapted to a wide variety of
instrumentation amplifier applications where the signal source is
powered from supply voltages that are different from the supply
voltages powering downstream circuits. The following examples
are included as a guide to the proper connection and voltages
applied to the supply pins VCC, VEE, VCO and VEO.
14
There are a common set of requirements across all power
applications:
1. A common ground connection from the input supplies, (VCC,
VEE) to the output supplies (VCO, VEO) is required for all
powering options.
2. The signal input pins IN+, IN- cannot float, and must have a DC
return path to ground.
3. The input and output supplies cannot both be operated in
single supply mode due to the 3V feedback amplifier
common mode headroom requirement in Equation 11.
The following are typical power examples:
EXAMPLE 1: BIPOLAR INPUT TO SINGLE SUPPLY
OUTPUT
The ISL28617 is configured as a 5V ADC driver in a high gain
sensor bridge amplifier powered from a ±10V excitation source.
In this application, the ISL28617 must extract the low level
bipolar sensor signal and shift the level to the 0V to +5V
differential rail-to-rail signal needed by the ADC. The following
powering option is recommended:
• VCC = +10V, VEE = -10V
• VCO = +5V, VEO = GND
• VCMO = +2.5V
• VCC, VEE power supply common connects to GND
EXAMPLE 2: HIGH VOLTAGE BIPOLAR I/O BUFFER
The ISL28617 is configured as a high impedance buffer
instrumentation amplifier in a ±15V industrial sensor
application. In this application, the ISL28617 must extract and
amplify the high impedance sensor signal and send it
downstream to a differential ADC operating from ±15V supplies.
The following powering options are recommended:
1. Input and output supplies are strapped to the same supplies
and rail-to-rail input to the ADC is not required.
-
VCC = VCO = +15V
VEE = VEO = -15V
VCMO = GND
VCC, VEE power supply common connects to GND
and VOUT = ±12V.
2. ±15V Rail-to-rail output is required, then:
- VCC = +18V, VEE= -18V
- VCO = +15V, VEO= -15V
- VCMO = GND
- VCC, VEE power supply common connects to GND
The VCO and VEO power supply pins connect to the ADC ±15V
power supply pins. Rail-to-rail output swing requires that
VCC = VCO +3V and VEE =VEO -3V, or ±18V.
FN6562.0
May 25, 2012
ISL28617
EXAMPLE 3: GAINS LESS THAN 1
The ISL28617 is configured to a gain of 0.2V/V driving a a
rail-to-rail 3V ADC. In this application, the maximum input
dynamic range is ±15V.
- VCC = +18V, VEE = -18V
- VCO = +3V, VEO = GND
- VCMO = +1.5V
- VCC, VEE power supply common connects to GND
In this attenuator configuration, the input signal range is ±15V,
which requires an additional ±3V of input overhead from the
input supplies. Thus, VCC and VEE = ±18V.
AC Performance Considerations
The ISL28617 closed loop frequency response is formed by the
feedback GM amplifier and gain resistor RFB and has the
characteristics of a current feedback amplifier. Therefore, the
-3dB gain does not significantly decrease at high gains as is the
case with the constant gain-bandwidth response of the classic
voltage feedback amplifier.
There are four behaviors of current feedback amplifiers that
must be considered:
• Frequency response increases with decreasing values of RFB.
A comparison of the G = 100, -3db response (Figures 16, 17)
RFB at 30.1kΩ vs. 121kΩ shows almost a 4X decrease from
2MHz to 0.5MHz.
• Gain peaking tends to increase with decreasing values of RFB
• Wide band applications at gains less than 1 (Figures 16, 17)
can have high gain peaking resulting in high levels of
overshoot with pulsed input signals
• Parasitic capacitance at the feedback resistor terminals (+RFB,
-RFB) and the Kelvin sense terminals (+RFBSENSE, -RFBSENSE)
will result in increasing levels of peaking and transient
response overshoot.
To minimize peaking external PC parasitic capacitance should be
minimized as much as possible. The ISL28617 is designed to be
stable with PC board parasitic capacitance up to 20pF and
feedback resistor values down to 30.1kΩ. At gains less than 1,
the maximum parasitic capacitance may have to be limited
further to avoid additional compensation.
Uncorrected gain peaking and high overshoot in the feedback
stage can cause loss of feedback loop stability if the transient
causes the feedback voltage to exceed the common mode input
range of the feedback amplifier or the maximum linear range of
the feedback resistor RFB. Corrective actions include increasing
the size of the feedback resistor (see Figure 30) and re-scaling
the input gain resistor RIN, or adding input frequency
compensation described in the next section.
The penalty of increasing the RFB (and RIN re-scaling) is increased
noise, so this is generally not the corrective action of choice
AC Compensation Techniques
Input compensation with a low pass filter (Figure 32) can be an
effective way to block high frequency signals from the
differential amplifier inputs. It does not change the gain peaking
behavior of the feedback loop, but it does block signals from
15
creating overdrive instability. This method is useful after other
corrective measures have been implemented, and when there is
little control over the input signal frequency content.
R/2
DIFFERENTIAL
INPUT SIGNAL
IN-
500Ω
IN+
500Ω
C
R/2
COMMON
MODE ERROR
TRACE
CAPACITANCE
GND
FIGURE 32. INPUT DIFFERENTIAL LOW PASS FILTER AND
PARASITIC CAPACITANCE
Input Common Mode Rejection
Considerations
The ISL28617 is capable of a very high level (120dB) of CMRR
performance from DC to as high as 1kHz. (Figure 1; CMRR vs.
Frequency). This high level of performance over frequency is
made possible by the high common mode input impedance
(80GΩ) but requires careful attention to the matching of the IN+
and IN- external impedances to GND.
A mismatch in the series impedance in conjunction with parasitic
capacitance at the IN+, IN- terminals (Figure 32) will cause a
common mode amplitude imbalance that will show up as a
differential input signal, rapidly degrading CMRR as the common
mode frequency increases.
Maximum CMRR performance is achieved with attention to
balancing external components and attention to PC layout.
Layout Guidelines
The ISL28617 is a high precision device with wide band AC
performance. Maximizing DC precision requires attention to the
layout of the gain resistors. Achieving good AC response requires
attention to parasitic capacitance at the gain resistor terminals,
and CMRR performance over frequency is ensured with
symmetrical component placement and layout of the input
differential signals to the IN+ and IN- terminals.
To ensure the highest DC precision, the location of the gain
resistors and PC trace connections to the Kelvin connections are
most important. Proper Kelvin connections remove trace
resistance errors so that the amplifier gain accuracy, and gain
temperature coefficients are determined by the gain resistor
matching tolerance. Interconnect constraints preclude mounting
the gain resistors next to each other, so they should be located on
either side of the ISL28617 and as close to the device as
possible. The Kelvin connections are formed at the junction of
the sense pins (±RINSENSE, ±RFBSENSE) and the gain resistor
current drive terminals (±RIN, ±RFB) terminals. This junction
should be made at the terminal pads directly under the ends of
each resistor.
FN6562.0
May 25, 2012
ISL28617
Reduced trace lengths that maintain DC accuracy are also
important for minimizing the capacitance that can degrade AC
stability. This is especially true at gains less then 1. Layout
techniques for precision applications using larger size precision
gain resistors at very low gains (G = 0.1V/V) include removing a
section of the underlying PC ground plane directly under the gain
resistor terminals and body.
of the error box, and not a typical value given that these sources
are uncorrelated.
Layout guidelines for high CMRR include matching trace lengths
and symmetrical component placement on the circuit that
connects the signal source to the IN+, IN- pins. This ensures
matching of the IN+ and IN- input impedances (Figure 32).
VOS(RTO)TYP = √[(AV×VOS(I))²+(VOS(FB))²+(IERR×RFB)²]
Power Supply De-coupling
Standard power supply de-coupling consists of a single 0.1µF
50V ceramic capacitor at the power supply terminals located as
close to the device as possible. In applications where the input
and output supplies are strapped to the same voltage (VEE = VEO,
VCC = VCO) the connection point should be as close to the device
as possible, with a single 0.1µF 50V ceramic capacitor at the
junction. Applications using separate supplies require 0.1µF 50V
ceramic de-coupling capacitors at each power supply terminal.
(EQ. 13)
VOS(RTO) = [(AV × VOS(I)) + (VOS(FB)) + (IERR × RFB)]
Equation 14 expresses the total DC error as the rms, or square
root of the sum of the squares to provide an estimate of a typical
value.
(EQ. 14)
Equation 15 converts the output offset error (Equation 13) range
(Equation 13) to an input referred error range [VOS(RTI)] and
enables a comparison with the DC component of the input signal.
(EQ. 15)
VOS(RTI) = [(VOS(I)) + (VOS(FB)/AV) + (IERR × RFB)/AV]
Similarly, Equation 16 shows the typical DC offset value
(Equation 14) referred to the input.
VOS(RTI)TYP = √[VOS(I))² + (VOS(FB)/AV)² + (IERR × RFB)/AV)²]
(EQ. 16)
These results are summarized in Table 1.
Calculating Noise Voltage
3. Estimating Amplifier DC and Noise
Performance
The gain resistor ohmic values and ratios are all that is required
to estimate DC offset and noise. The following sections illustrate
methods to calculate DC offset and noise performance. These
estimates are useful for optimizing resistor values for noise and
DC offset.
Calculating DC Offset Voltage
Output offset voltage, like output noise, has several contributors.
Also similar to output noise, the major offset contributor depends
on the gain configuration. In high-gain, VOS(I) dominates, while in
low-gain, offset due to IERR dominates.
The summation of DC offsets to arrive at total DC offset error is
performed in two ways. Equation 13 is a simple addition of the
DC offsets appearing at the output, and is useful when defining
the minimum to maximum range of offset that can be expected.
The drawback is that the result defines the corner of the corners
The calculation of noise spectral density at the output [eN(RTO)]
from all noise sources is given by Equation 17. Equation 18
eN(RTO) = √[(AV × eN(I))² + (2 × AV × iN(I) × 500Ω)² +
(AV)² x (4kT × RIN) + (4kT × RFB) + (RFB × iN(IERR))²+(eN(FB))²]
(EQ. 17)
converts the output noise to the input referred value when
evaluating the input signal to noise ratio.
eN(RTI) = eN(RTO)/AV
(EQ. 18)
Table 2 provides examples of the noise contribution of each
source by circuit gain and output voltage span.
In a high-gain configuration, the input noise is the dominant
noise source. In a low-gain configuration, the noise voltage from
the product of the internal noise current, IN(err), and the feedback
resistor, RFB dominates. The contribution of the internal noise
current, IN(err) increases in proportion to RFB, but the
corresponding increase in output voltage with RFB keeps the ratio
of this noise voltage to output voltage constant.
TABLE 1. COMPUTING TYPICAL OUTPUT OFFSET VOLTAGE RANGES
VOS(FB)
(µV)
(Note 10)
IERR (5nA)
x RFB
(µV)
(Note 10)
EQ. 13
VOS(RTO)
(µV)
EQ. 15
VOS(RTI)
(µV)
EQ. 14
TYPICAL
VOS(RTO)
(µV)
EQ. 16
TYPICAL
VOS(RTI)
(µV)
AV
VO(LIN)
RIN
(kΩ)
RFB
(kΩ)
AV x VOS(I)
(µV)
(Note 10)
1
±2.5
30
30
±30
±400
±150
±580
428
1
±10
120
120
±15
±400
±600
±1015
721
100
±2.5
0.3
30
±1500
±400
±150
±2000
±20
1560
15.6
100
±10
1.2
120
±1500
±400
±600
±2500
±25
1669
16.7
NOTE:
10. Chosen for illustration purposes and does not reflect actual device performance.
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TABLE 2. 1kHz INPUT NOISE AND THERMAL NOISE CONTRIBUTIONS
eN (RTI)
INPUT
REFERRED
NOISE
(nV/√Hz)
eN (RTO)
OUTPUT
REFERRED
NOISE
(nV/√Hz)
AV
RIN
(kΩ)
RFB
(kΩ)
AV x eN(I)
(nV/√Hz)
2 x AV x iN(I)
x 500Ω
(nV/√Hz)
AV x √(4kT
x RIN)
(nV/√Hz)
√(4kT x RFB)
(nV/√Hz)
RFB x iN(IERR)
(nV/√Hz)
eN(FB)
(nV/√Hz)
1
30
30
8.6
0.15
22.3
22.3
78
8.6
86
1
120
120
8.6
0.15
44.6
44.6
300
8.6
307
100
0.3
30
860
15
223
22.3
78
8.6
892
8.9
100
1.2
120
860
15
446
44.6
300
8.6
1015
10.15
NOTE:
11. eN and iN values are chosen for illustration purposes and may not reflect actual device performance.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
May 25, 2012
FN6562.0
CHANGE
Initial release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL28617
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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17
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ISL28617
Package Outline Drawing
M24.173
24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
A
1
3
7.80 ±0.10
SEE DETAIL "X"
13
24
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
12
0.15 +0.05
-0.06
B
0.65
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
C
0.90 +0.15
-0.10
1.20 MAX
GAUGE
PLANE
SEATING PLANE
0.25 +0.05
-0.06
0.10 M C B A
0.10 C
5
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60± 0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
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