Data Sheet

TDF8599A
I2C-bus controlled dual channel 135 W/4 , single channel
250 W/2  class-D power amplifier with load diagnostics
Rev. 3 — 2 May 2013
Product data sheet
1. General description
The TDF8599A is a dual Bridge-Tied Load (BTL) car audio amplifier comprising an
NDMOST-NDMOST output stage based on SOI BCDMOS technology. Low power
dissipation enables the TDF8599A high-efficiency, class-D amplifier to be used with a
smaller heat sink than those normally used with standard class-AB amplifiers.
The TDF8599A can operate in either non-I2C-bus mode or I2C-bus mode. When in
I2C-bus mode, DC load detection results and fault conditions can be easily read back from
the device. Up to 15 I2C-bus addresses can be selected depending on the value of the
external resistor connected to pins ADS and MOD.
When pin ADS is short circuited to ground, the TDF8599A operates in non-I2C-bus mode.
Switching between Operating mode and Mute mode in non-I2C-bus mode is only possible
using pins EN and SEL_MUTE.
2. Features and benefits















High-efficiency
Low quiescent current
Operating voltage from 8 V to 35 V
Two 4 /2  capable BTL channels or one 1  capable BTL channel
Differential inputs
I2C-bus mode with 15 I2C-bus addresses or non-I2C-bus mode operation
Clip detect
Independent short circuit protection for each channel
Advanced short circuit protection for load, GND and supply
Load dump protection
Thermal foldback and thermal protection
DC offset protection
Selectable AD or BD modulation
Parallel channel mode for high current drive capability
Advanced clocking:
 Switchable oscillator clock source: internal for Master mode or external for Slave
mode
 Spread spectrum mode
 Phase staggering
 Frequency hopping
 No ‘pop noise’ caused by DC output offset voltage
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
 I2C-bus mode:
 DC load detection
 AC load detection
 Thermal pre-warning diagnostic level setting
 Identification of activated protections or warnings
 Selectable diagnostic information available using pins DIAG and CLIP
 Qualified in accordance with AEC-Q100
3. Applications
 Car audio
4. Quick reference data
Table 1.
Quick reference data
VP = 14.4 V unless otherwise stated.
Symbol
Parameter
Conditions
Min
[1]
Typ
Max
Unit
VP
supply voltage
8
14.4
35
V
IP
supply current
off state; Tj  85 C; VP = 14.4 V
-
2
10
A
Iq(tot)
total quiescent current
Operating mode; no load, snubbers and
filter connected
-
90
120
mA
Po
output power
Stereo mode:
VP = 14.4 V; THD = 1 %; RL = 4 
18
20
-
W
VP = 14.4 V; THD = 10 %; RL = 4 
23
25
-
W
square wave (EIAJ); RL = 4 
-
40
-
W
[2]
VP = 35 V; THD = 10 %; RL = 4 
-
135
-
W
VP = 14.4 V; THD = 1 %; RL = 2 
26
29
-
W
VP = 14.4 V; THD = 10 %; RL = 2 
34
38
-
W
-
60
-
W
VP = 14.4 V; THD = 10 %; RL = 2 
-
50
-
W
VP = 35 V; THD = 10 %; RL = 2 
-
250
-
W
VP = 25 V; THD = 1 %; RL = 1 
135
150
-
W
square wave (EIAJ); RL = 2 
Parallel mode:
[1]
In this data sheet supply voltage VP describes VP1, VP2 and VPA.
[2]
Output power is measured indirectly based on RDSon measurement.
[2]
5. Ordering information
Table 2.
Ordering information
Type number
TDF8599ATH
TDF8599A
Product data sheet
Package
Name
Description
Version
HSOP36
plastic, heatsink small outline package; 36 leads; low stand-off height
SOT851-2
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I2C-bus controlled dual channel class-D power amplifier
6. Block diagram
VDDA
10
AGND
SVRR
VP1
VP2
31
24
34
STABI1
9
32
8
VP1
33
PWM
CONTROL
1
OUT1N
DRIVER
LOW
PGND1
29
VP1
IN1N
BOOT1N
DRIVER
HIGH
TDF8599A
IN1P
VSTAB1
2
BOOT1P
DRIVER
HIGH
28
PWM
CONTROL
OUT1P
DRIVER
LOW
ACGND
PGND1
5
+
23
VP2
BOOT2N
DRIVER
HIGH
22
PWM
CONTROL
IN2P
3
PGND2
26
VP2
IN2N
OUT2N
DRIVER
LOW
4
BOOT2P
DRIVER
HIGH
27
PWM
CONTROL
OUT2P
DRIVER
LOW
OSCSET
OSCIO
SSM
MOD
VDDD
EN
SEL_MUTE
SCL
SDA
ADS
18
PGND2
19
17
OSCILLATOR
12
35
5 V STABI
16
15
MODE
SELECT
+
I2C-BUS
DIAGNOSTICS
Product data sheet
PROTECTION
OVP, OCP, OTP
UVP, TFP, WP, DCP
11
GNDD/HW
TDF8599A
VSTAB2
6
7
14
36
Fig 1.
21
STABI2
DIAG
13
20
CLIP DCP
30
25
PGND1
PGND2
001aak071
Block diagram
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
7. Pinning information
7.1 Pinning
GNDD/HW 36
1
VDDD 35
2
IN1N
VSTAB1 34
3
IN2P
IN1P
OUT1N 33
4
IN2N
BOOT1N 32
5
ACGND
VP1 31
6
EN
PGND1 30
7
SEL_MUTE
BOOT1P 29
8
SVRR
OUT1P 28
9
AGND
OUT2P 27
TDF8599ATH
10 VDDA
BOOT2P 26
11 ADS
PGND2 25
12 MOD
VP2 24
13 CLIP
BOOT2N 23
14 DIAG
OUT2N 22
15 SDA
VSTAB2 21
16 SCL
DCP 20
17 SSM
18 OSCSET
OSCIO 19
001aak072
Fig 2.
Heatsink up (top view) pin configuration TDF8599ATH
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type[1]
Description
IN1P
1
I
channel 1 positive audio input
IN1N
2
I
channel 1 negative audio input
IN2P
3
I
channel 2 positive audio input
IN2N
4
I
channel 2 negative audio input
ACGND
5
I
decoupling for input reference voltage
EN
6
I
enable input:
non-I2C-bus mode: switch between off and Mute mode
I2C-bus mode: off and Standby mode
SEL_MUTE
7
I
select mute or unmute
SVRR
8
I
decoupling for internal half supply reference voltage
AGND
9
G
analog supply ground
VDDA
10
P
analog supply voltage
ADS
11
I
non-I2C-bus mode: connected to ground
I2C-bus mode: selection and address selection pin
MOD
TDF8599A
Product data sheet
12
I
modulation mode, phase shift and parallel mode select
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
Table 3.
Pin description …continued
Symbol
Pin
Type[1]
Description
CLIP
13
O
clip output; open-drain
DIAG
14
O
diagnostic output; open-drain
SDA
15
I/O
I2C-bus data input and output
SCL
16
I
I2C-bus clock input
SSM
17
master setting: Spread spectrum mode frequency
slave setting: phase lock operation
OSCSET
18
master/slave oscillator setting
master only setting: set internal oscillator frequency
OSCIO
19
I/O
external oscillator slave setting: input
internal oscillator master setting: output
DCP
20
I
DC protection input for the filtered output voltages
VSTAB2
21
OUT2N
22
BOOT2N
23
VP2[2]
24
P
channel 2 power supply voltage
PGND2
25
G
channel 2 power ground
BOOT2P
26
OUT2P
27
O
channel 2 positive PWM output
OUT1P
28
O
channel 1 positive PWM output
BOOT1P
29
PGND1
30
G
channel 1 power ground
VP1[2]
31
P
channel 1 power supply voltage
BOOT1N
32
OUT1N
33
VSTAB1
34
decoupling internal stabilizer 1 for DMOST drivers
VDDD
35
decoupling of the internal 5 V logic supply
GNDD/HW
36
decoupling internal stabilizer 2 for DMOST drivers
O
channel 2 negative PWM output
boot 2 negative bootstrap capacitor
boot 2 positive bootstrap capacitor
boot 1 positive bootstrap capacitor
boot 1 negative bootstrap capacitor
O
G
channel 1 negative PWM output
ground digital supply voltage
handle wafer connection
[1]
I = input, O = output, I/O = input/output, G = ground and P = power supply.
[2]
In this data sheet supply voltage VP describes VP1, VP2 and VPA.
8. Functional description
8.1 General
The TDF8599A is a dual full bridge (BTL) audio power amplifier using class-D technology.
The audio input signal is converted into a Pulse-Width Modulated (PWM) signal using the
analog input and PWM control stages. A PWM signal is applied to driver circuits for both
high-side and low-side enabling the DMOS power output transistors to be driven. An
external 2nd order low-pass filter converts the PWM signal into an analog audio signal
across the loudspeakers.
TDF8599A
Product data sheet
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
The TDF8599A includes integrated common circuits for all channels such as the oscillator,
all reference sources, mode functionality and a digital timing manager. In addition, the
built-in protection includes thermal foldback, temperature, overcurrent and overvoltage
(load dump).
The TDF8599A operates in either I2C-bus mode or non-I2C-bus mode. In I2C-bus mode,
DC load detection, frequency hopping and extended configuration functions are provided
together with enhanced diagnostic information.
8.2 Mode selection
The mode pins EN, ADS and SEL_MUTE enable mute state, I2C-bus mode and
Operating mode switching.
Pin SEL_MUTE is used to mute and unmute the device and must be connected to an
external capacitor (CON). This capacitor generates a time constant which is used to
ensure smooth fade-in and fade-out of the input signal.
The TDF8599A is enabled when pin EN is HIGH. When pin EN is LOW, the TDF8599A is
off and the supply current is at its lowest value (typically 2 A). When off, the TDF8599A is
completely deactivated and will not react to I2C-bus commands.
I2C-bus mode is selected by connecting a resistor between pins ADS and AGND. In
I2C-bus mode with pin EN HIGH, the TDF8599A waits for further commands (see
Table 4). I2C-bus mode is described in Section 9 on page 23.
Non-I2C-bus mode is selected by connecting pin ADS to pin AGND. In non-I2C-bus mode,
the default TDF8599A state is Mute mode. The amplifiers switch idle (50 % duty cycle)
and the audio signal is suppressed at the output. In addition, the capacitor (CSVRR) is
charged to half the supply voltage. To enter Operating mode, pin SEL_MUTE must be
HGH with S1 open, enabling capacitor (CON) charged by an internal pull-up (see
Figure 3). In addition, pin EN must be driven HIGH.
S2
3.3 V
S2
EN
EN
3.3 V
TDF8599A
ADS
TDF8599A
SEL_MUTE
ADS
SEL_MUTE
RADS
AGND
AGND
CON
CON
S1
001aak073
a. Non-I2C-bus mode
001aak074
b. I2C-bus mode
See Table 13 for detailed information on
RADS.
Fig 3.
Mode selection
I2C-bus mode and non-I2C-bus mode control are described in Table 4 on page 7 and
Table 5 on page 7. Switches S1 and S2 are shown in Figure 3.
TDF8599A
Product data sheet
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
Table 4.
I2C-bus mode operation
Pin EN
Pin SEL_MUTE
Bit IB1[D0]
Bit IB2[D0]
Mode
HIGH (S2 closed)
HIGH
1
0
Operating mode
LOW (S2 open)
[1]
LOW
1
1
Mute mode
LOW
0
X[1]
Standby mode
X[1]
X[1]
X[1]
off (default)
X = do not care.
Table 5.
Non-I2C-bus mode operation
Pin EN
Pin SEL_MUTE
Mode
HIGH (S2 closed)
HIGH (S1 open)
Operating mode
LOW (S1 closed)
Mute mode (default)
X[1]
off
LOW (S2 open)
[1]
X = do not care.
8.3 Pulse-width modulation frequency
The output signal from the amplifier is a PWM signal with a clock frequency of fosc. This
frequency is set by connecting a resistor (Rosc) between pins OSCSET and AGND. The
optimal clock frequency setting is between 300 kHz and 400 kHz. Connecting a resistor
with a value of 39 k, for example, sets the clock frequency to 320 kHz (see Figure 5).
The external capacitor (Cosc) has no influence on the oscillator frequency. It does
however, reduce jitter and sensitivity to disturbance. Using a 2nd order LC demodulation
filter in the application generates an analog audio signal across the loudspeaker.
8.3.1 Master and slave mode selection
In a master and slave configuration, multiple TDF8599A devices are daisy-chained
together in one audio application with a single device providing the clock frequency signal
for all other devices. In this situation, it is recommended that the oscillators of all devices
are synchronized for optimum EMI behavior as follows:
All OSCIO pins are connected together and one TDF8599A in the application is
configured as the clock-master. All other TDF8599A devices are configured as
clock-slaves (see Figure 5).
• The clock-master pin OSCIO is configured as the oscillator output. When a resistor
(Rosc) is connected between pins OSCSET and AGND, the TDF8599A is in Master
mode.
• The clock-slave pins OSCIO are configured as the oscillator inputs. When pin
OSCSET is directly connected to pin AGND (see Table 6), the TDF8599A is in Slave
mode.
Table 6.
TDF8599A
Product data sheet
Mode setting pin OSCIO
Mode
Settings
Pin OSCSET
Pin OSCIO
Master
Rosc > 26 k
output
Slave
Rosc = 0 ; shorted to pin AGND
input
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
The value of the resistor Rosc sets the clock frequency based on Equation 1:
9
12.45  10
f osc = ----------------------------  Hz 
R osc
(1)
001aai771
50
Rosc
(kΩ)
40
30
20
10
0
300
Fig 4.
350
400
450
500
fosc (kHz)
Clock frequency as a function of Rosc
OSCSET
TDF8599A
Rosc
Cosc
OSCSET
OSCSET
TDF8599A
TDF8599A
OSCIO
OSCIO
OSCIO
Master
fosc
R
Slave 1
Slave 2
001aak075
Fig 5.
Master and slave configuration
In Master mode, Spread spectrum mode and frequency hopping can be enabled. In Slave
mode, phase staggering and phase lock operation can be selected. An external clock can
be used as the master-clock on pin OSCIO of the slave devices. When using an external
clock, it must remain active during the shutdown sequence to ensure that all devices are
switched off and able to enter the off state as described in Section 8.2 on page 6.
In Slave mode, an internal watchdog timer on pin OSCIO is triggered when the TDF8599A
is switched off by pulling down pin EN. If the external clock fails, the watchdog timer forces
the TDF8599A to switch off.
8.3.2 Spread spectrum mode (Master mode)
Spread spectrum mode is a technique of modulating the oscillator frequency with a slowly
varying signal to broaden the switching spectrum, thereby reducing the spectral density of
the EMI. Connecting a capacitor (CSSM) to pin SSM enables Spread spectrum mode (see
Figure 6). When pin SSM is connected to pin AGND, Spread spectrum mode is disabled.
TDF8599A
Product data sheet
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
The capacitor on pin SSM (CSSM) sets the spreading frequency when Spread spectrum
mode is active. The current (ISSM) flowing in and out of pin SSM is typically 5 A. This
gives a triangular voltage on pin SSM that sweeps around the voltage set by pin OSCSET
 5 %. The voltage on pin SSM is used to modulate the oscillator frequency.
The spread spectrum frequency (fSSM) can be calculated using Equation 2:
I SSM
f SSM = -----------------------------------------------------  Hz 
2  C SSM  V 1  10 %
(2)
where the voltage on pin OSCSET = V1 and is calculated as 100 A  Rosc (V) with
ISSM = 5 A.
100 μA
100 μA
OSCSET
Rosc
OSCSET
Cosc
Cosc
Rosc
5 μA
ISSM
SSM
SSM
CSSM
001aai773
001aai774
a. Off
Fig 6.
b. On
Spread spectrum mode
The frequency swings between 0.95  fosc and 1.05  fosc; see Figure 7.
OSCIO
max(V)
min(V)
t (ms)
SSM
001aai775
Fig 7.
Spread spectrum operation in Master mode
8.3.3 Frequency hopping (Master mode)
Frequency hopping is a technique used to change the oscillator frequency for AM tuner
compatibility. In Master mode, the resistor connected between pins OSCSET and AGND
sets the oscillator frequency (fosc). In I2C-bus mode, this frequency can be varied by
 10 %. Set bit IB1[D4] to logic 1 and bit IB1[D3] to either logic 0 (0.9  fosc) or logic 1
(1.1  fosc).
TDF8599A
Product data sheet
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I2C-bus controlled dual channel class-D power amplifier
8.3.4 Phase lock operation (Slave mode)
In Slave mode, Phase-Locked Loop (PLL) operation can be used to reduce the jitter effect
of the external oscillator signal connected to pin OSCIO. Phase lock operation is also
needed to enable phase staggering, see Section 8.4.2 on page 13. Phase lock operation
is enabled when the oscillator is in Slave mode by connecting two capacitors (CPLL_s and
CPLL_p) and a resistor (RPLL) between pin SSM and pin AGND (see Figure 8). Connecting
pin SSM to pin AGND disables phase lock operation and causes the slave to directly use
the external oscillator signal. Values for CPLL_s, CPLL_p and RPLL depend on the desired
loop bandwidth (BPLL) of the PLL. RPLL is given by: RPLL = 8.4  BPLL . The
corresponding values for CPLL_s and CPLL_p are given by Equation 3 and Equation 4:
0.032
C PLL_p = ------------------------------  F 
R PLL  B PLL
(3)
Remark: CPLL_p is only needed when 1⁄4  phase shift is selected. See Section 8.4.2 for
more detailed information.
0.8
C PLL_s = ------------------------------  F 
R PLL  B PLL
(4)
When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,
the PLL loop bandwidth BPLL should be 100  fSSM.
100 μA
OSCSET
100 μA
OSCSET
PLL
PLL
SSM
CPLL_s
SSM
RPLL
001aai776
CPLL_p(1)
001aai777
(1) Only needed when 1⁄4  phase shift is
selected
a. Off
Fig 8.
b. On
Phase lock operation
Table 7 lists all oscillator modes.
Table 7.
TDF8599A
Product data sheet
Oscillator modes
OSCSET pin
OSCIO pin
SSM pin
Oscillator modes
Rosc > 26 k
output
CSSM to pin AGND
master, spread spectrum
Rosc > 26 k
output
shorted to pin AGND
master, no spread spectrum
Rosc = 0 
input
CPLL + RPLL to pin AGND
slave, PLL enabled
Rosc = 0 
input
shorted to pin AGND
slave, PLL disabled
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
8.4 Operation mode selection
Pin MOD is used to select specific operating modes. The resistor (RMOD) connected
between pins MOD and AGND together with the non-I2C-bus/I2C-bus mode determine the
operating mode (see Table 8). The mode of operation depends on whether non-I2C-bus
mode or I2C-bus mode is active. This in turn is determined by the resistor value connected
between pins ADS and AGND.
In non-I2C-bus mode, pin MOD is used to select:
• AD or BD modulation (see Section 8.4.1).
• 1⁄2  phase shift when oscillator is used in Slave mode (see Section 8.4.2).
• Parallel mode operation (see Section 8.4.3).
In I2C-bus mode, pin MOD can only select Parallel mode. In addition, the modulation
mode and phase shift are programmed using I2C-bus commands.
Table 8.
RMOD (k)
Operation mode selection with the MOD pin
I2C-bus mode[1]
Non-I2C-bus mode[2]
0 (short to AGND) Stereo mode
AD modulation: no phase shift in Slave mode
4.7
BD modulation: no phase shift in Slave mode
13
AD modulation: 1⁄2  phase shift in Slave mode
Parallel mode[3]
33
BD modulation: 1⁄2  phase shift in Slave mode
100
AD modulation: no phase shift in Slave mode
 (open)
BD modulation: no phase shift in Slave mode
[1]
RADS  4.7 k; See Table 13 on page 23.
[2]
RADS = 0 ; pin ADS is short circuited to pin AGND.
[3]
See Section 8.4.3 on page 14 for more detailed information.
In I2C-bus mode, pin MOD is latched using the I2C-bus command IB3[D7] = 1. This avoids
amplifier switching interference generating incorrect information on pin MOD.
In non-I2C-bus mode or when IB3[D7] = 0, the information on pin MOD is latched when
one of the TDF8599A’s outputs starts switching.
8.4.1 Modulation mode
In non-I2C-bus mode, pin MOD is used to select either AD or BD modulation mode (see
Table 8). In I2C-bus mode, the modulation mode is selected using an I2C-bus command.
• AD modulation mode: the bridge halves switch in opposite phase.
• BD modulation mode: the bridge halves switch in phase but the input signal for the
modulators is inverted.
Figure 10 and Figure 11 show simplified representations of AD and BD modulation.
TDF8599A
Product data sheet
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I2C-bus controlled dual channel class-D power amplifier
+VP
INxP
+VP
OUTP OUTN
INxN
AD
BD
001aai778
Fig 9.
AD/BD modulation switching circuit
INxP
OUTxP
001aai779
a. Bridge half 1.
INxN
OUTxN
001aai780
b. Bridge half 2 switched in the opposite phase to bridge half 1.
Fig 10. AD modulation
TDF8599A
Product data sheet
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I2C-bus controlled dual channel class-D power amplifier
INxP
OUTxP
OUTxP - OUTxN
001aai781
a. Phase switching cycle.
INxN
OUTxN
001aai782
b. Inverted signal to the modulator.
Fig 11. BD modulation
8.4.2 Phase staggering (Slave mode)
In Slave mode with phase lock operation enabled, a phase shift with respect to the
incoming clock signal can be selected to distribute the switching moments over time. In
non-I2C-bus mode, 1⁄2  phase shift can be programmed using pin MOD. In I2C-bus mode,
five different phase shifts (1⁄4 , 1⁄3 , 1⁄2 , 2⁄3 , 3⁄4 ) can be selected using the I2C-bus
bits (IB3[D1:D3]). See Table 8 for selection of the phase shift in non-I2C-bus mode with pin
MOD. An additional capacitor must be connected to pin SSM when 1⁄4  phase shift is
used (see Figure 8). An example of using 1⁄2  phase shift for BD modulation is shown in
Figure 12.
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I2C-bus controlled dual channel class-D power amplifier
OUT1P
phase
0
OUT1N
master
OUT2P
π
OUT2N
OUT1P
1π
2
OUT1N
slave
OUT2P
2π
3
OUT2N
001aai783
Fig 12. Master and slave operation with 1⁄2  phase shift
8.4.3 Parallel mode
In Parallel mode; the two output stages operate in parallel to enlarge the drive capability.
The inputs and outputs for Parallel mode must be connected on the Printed-Circuit Board
(PCB) as shown in Figure 13. The parallel connection can be made after the output filter,
as shown in Figure 13 or directly to the device output pins (OUTxP and OUTxN).
+
−
IN1P
OUT1N
IN1N
OUT1P
−
IN2N
TDF8599A
IN2P
OUT2P
MOD
OUT2N
+
RMOD
001aak077
Fig 13. Parallel mode
In Parallel mode, the channel 1 I2C-bus bits can be programmed using the I2C-bus.
8.5 Protection
The TDF8599A includes a range of built-in protection functions. How the TDF8599A
manages the various possible fault conditions for each protection is described in the
following sections:
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I2C-bus controlled dual channel class-D power amplifier
Table 9.
Overview of protection types
Protection type
Reference
Thermal foldback
Section 8.5.1
Overtemperature
Section 8.5.2
Overcurrent
Section 8.5.3
Window
Section 8.5.4
DC Offset
Section 8.5.5
Undervoltage
Section 8.5.6
Overvoltage
Section 8.5.6
8.5.1 Thermal foldback
Thermal Foldback Protection (TFP) is tripped when the average junction temperature
exceeds the threshold level (145 C). TFP decreases amplifier gain such that the
combination of power dissipation and Rth(j-a) create a junction temperature around the
threshold level. The device will not completely switch off but remains operational at the
lower output power levels. If the average junction temperature continues to increase, a
second built-in temperature protection threshold level shuts down the amplifier
completely.
8.5.2 Overtemperature protection
If the average junction temperature (Tj) > 160 C, OverTemperature Protection (OTP) is
tripped and the power stage shuts down immediately.
8.5.3 Overcurrent protection
OverCurrent Protection (OCP) is tripped when the output current exceeds the maximum
output current of 8 A. OCP regulates the output voltage such that the maximum output
current is limited to 8 A. The amplifier outputs keep switching and the amplifier is NOT
shutdown completely. This is called current limiting.
OCP also detects when the loudspeaker terminals are short circuited or one of the
amplifier’s demodulated outputs is short circuited to one of the supply lines. In either case,
the shorted channel(s) are switched off.
The amplifier can distinguish between loudspeaker impedance drops and a low-ohmic
short across the load or one of the supply lines. This impedance threshold depends on the
supply voltage used. When a short is made across the load causing the impedance to
drop below the threshold level, the shorted channel(s) are switched off. They try to restart
every 50 ms. If the short circuit condition is still present after 50 ms, the cycle repeats. The
average power dissipation will be low because of this reduced duty cycle.
When a channel is switched off due to a short circuit on one of the supply lines, Window
Protection (WP) is activated. WP ensures the amplifier does not start-up after 50 ms until
the supply line short circuit is removed.
8.5.4 Window protection
Window Protection (WP) checks the PWM output voltage before switching from Standby
mode to Mute mode (with both outputs switching) and is activated as follows:
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• During the start-up sequence:
– When the TDF8599A is switched from standby to mute (td(stb-mute)). When a short
circuit on one of the output terminals (i.e. between VP or GND) is detected, the
start-up procedure is interrupted and the TDF8599A waits for open circuit outputs.
No large currents flow in the event of a short circuit to the supply lines because the
check is performed before the power stages are enabled.
• During operation:
–
A short to one of the supply lines trips OCP causing the amplifier channel to
shutdown. After 50 ms the amplifier channel restarts and WP is activated.
However, the corresponding amplifier channel will not start-up until the supply line
short circuit has been removed.
8.5.5 DC offset protection
DC Protection (DCP) is activated when the DC content in the demodulated output voltage
exceeds a set threshold (typically 2 V). DCP is active in both Mute mode and Operating
mode. Figure 14 shows how false triggering of the DCP by low frequencies in the audio
signal is prevented using the external capacitor (CF) to generate a cut-off frequency.
OUT1P
OUT1N
OUT2P
OUT2N
V to I
Vref
V to I
50 kΩ
IB1[D6]
IB2[D6]
DCP
CF
DIAG
IB1[D7]
DB1[D2]
S
Q
S4
IB2[D7]
S3
switch off channels
001aak078
Fig 14. DC offset protection and diagnostic output
In I2C-bus mode, DC offsets generate a voltage shift around the bias voltage. When the
voltage shift exceeds threshold values, the offset alarm bit DB1[D2] is set and if bit
IB1[D7] is not set, diagnostic information is also given. Any detected offset shuts down
both channels when bit IB2[D7] is not set. To restart the TDF8599A in I2C-bus mode, pin
EN must be toggled or DCP disabled by connecting pin DCP to pin AGND.
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I2C-bus controlled dual channel class-D power amplifier
In non-I2C-bus mode, when an offset is detected, DCP always gives diagnostic
information on pin DIAG and shuts down both channels.
Connecting a capacitor between pins DCP and AGND enables DC offset protection.
Connecting pin DCP to pin AGND disables DCP in both I2C-bus and non-I2C-bus mode.
8.5.6 Supply voltages
UnderVoltage Protection (UVP) is activated when the supply voltage drops below the UVP
threshold. UVP triggers the UVP circuit causing the system to first mute and then stop
switching. When the supply voltage rises above the threshold level, the system restarts.
OverVoltage Protection (OVP) is activated when the supply voltage exceeds the OVP
threshold. The OVP (or load dump) circuit is activated and the power stages are
shutdown.
An overview of all protection circuits and the amplifier states is given in Table 10.
8.5.7 Overview of protection circuits and amplifier states
Table 10.
Overview of TDF8599A protection circuits and amplifier states
Protection circuit name
Amplifier state
Complete
shutdown
Channel
shutdown
Restart[1]
TFP
N[2]
N[2]
Y[3]
OTP
Y
N
Y[3]
OCP
N
Y
Y[4]
WP
N
Y
Y
DCP
Y
N
N[5]
UVP
Y
N
Y[6]
OVP
Y
N
Y
[1]
When fault is removed.
[2]
Amplifier gain depends on the junction temperature and size of the heat sink.
[3]
TFP influences restart timing depending on heat sink size.
[4]
Shorted load causes a restart of the channel every 50 ms.
[5]
Latched protection is reset by toggling pin EN or by disabling DCP in I2C-bus mode.
[6]
In I2C-bus mode deep supply voltage drops will cause a Power-On Reset (POR). The restart requires an
I2C-bus command.
8.6 Diagnostic output
8.6.1 Diagnostic table
The diagnostic information for I2C-bus mode and non-I2C-bus mode is shown in Table 11.
The instruction bitmap and data bytes are described in Table 14 and Table 15.
Pins DIAG and CLIP have an open-drain output which must have an external pull-up
resistor connected to an external voltage. Pins CLIP and DIAG can show both fixed and
I2C-bus selectable information.
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Pin DIAG goes LOW when a short circuit to one of the amplifier outputs occurs. The
microprocessor reads the failure information using the I2C-bus. The I2C-bus bits are set
for a short circuit. These bits can be reset with the I2C-bus read command.
Even after the short has been removed, the microprocessor knows what was wrong after
reading the I2C-bus. Old information is read when a single I2C-bus read command is
used. To read the current information, two read commands must be sent, one after
another.
When selected, pin DIAG gives the current diagnostic information. Pin DIAG is released
instantly when the failure is removed, independent of the I2C-bus latches.
Table 11.
Available data on pins DIAG and CLIP
Diagnostic
Power-on reset
I2C-bus mode
Non-I2C-bus mode
Pin DIAG
Pin CLIP
Pin DIAG
Pin CLIP
yes
yes
yes
yes
UVP or OVP
yes
no
yes
no
Clip detection
no
selectable
no
yes
Temperature pre-warning
no
selectable
no
yes
OCP/WP
yes
no
yes
no
DCP
selectable
no
yes
no
OTP
yes
no
yes
no
When OCP is triggered, the open-drain DIAG output is activated. The diagnostic output
signal during different short circuit conditions is illustrated in Figure 15.
shorted load
short to GND or VP line
AMPLIFIER
RESTART
NO
RESTART
pull up V
AGND = 0 V
≈50 ms ≈50 ms ≈50 ms
001aai786
Fig 15. Diagnostic output for short circuit conditions
8.6.2 Load identification (I2C-bus mode only)
8.6.2.1
DC load detection
DC load detection is only available in I2C-bus mode and is controlled using bit IB2[D2].
The default setting is logic 0 for bit IB2[D2] which disables DC load detection. DC load
detection is enabled when bit IB2[D2] = 1. Load detection takes place before the class-D
amplifier output stage starts switching in Mute mode and the start-up time from Standby
mode to Mute mode is increased by tdet(DCload) (see Figure 16).
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I2C-bus controlled dual channel class-D power amplifier
VP
DRIVER
HIGH
B
OUTN
PWM
CONTROL
DRIVER
LOW
PGND1
RL
VP
DRIVER
HIGH
OUTP
PWM
CONTROL
DRIVER
LOW
PGND2
001aai787
Fig 16. DC load detection circuit
out (V)
out−
out+
t (s)
tdet(DCload)
td(stb-mute)
001aai788
Fig 17. DC load detection procedure
The capacitor connected to pin SEL_MUTE (see Figure 3 on page 6) is used to create an
inaudible current test pulse, drawn from the positive amplifier output. The diagnostic
‘speaker load’ (or ‘open load’), based on the voltage difference between pins OUTxP and
OUTxN is shown in Figure 18.
SPEAKER LOAD
0Ω
OPEN LOAD
25 Ω
350 Ω
001aaj956
Fig 18. DC load detection limits
Remark: DC load detection identifies a short circuited speaker as a valid speaker load.
OCP detection, using byte DB1[D3] for channel 1 and byte DB2[D3] for channel 2,
performs diagnostics on shorted loads. However, the diagnostics are performed after the
DC load detection cycle has finished and once the amplifier is in Operating mode.
The result of the DC load detection is stored in bits DB1[D4] and DB2[D4].
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I2C-bus controlled dual channel class-D power amplifier
Table 12.
Interpretation of DC load detection bits
DC load bits DB1[D4] and DB2[D4]
OCP bits DB1[D3] and DB2[D3]
Description
0
0
speaker load
0
1
shorted load
1
0
open load
Remark: After DC load detection has been performed, the DC load valid bit DB1[D6] must
be set. The DC load data bits are only valid when bit DB1[D6] = 1. When DC load
detection is interrupted by a sudden large change in supply voltage (triggered by UVP or
OVP) or if the amplifier hangs up, the DC load valid bit is reset to DB1[D6] = 0. The DC
load detection enable bit IB2[D2] must be reset after the DC load protection cycle to
release any amplifier hang-up. Once the DC load detection cycle has finished, DC load
detection can be restarted by toggling the DC load detection enable bit IB2[D2]. However,
this can only be used if both amplifier channels have not been enabled with bit IB1[D1] or
bit IB2[D1]. See Section 8.6.2.2 “Recommended start-up sequence with DC load
detection enabled” for detailed information.
8.6.2.2
Recommended start-up sequence with DC load detection enabled
The flow diagram (Figure 19) illustrates the TDF8599A’s ability to perform a DC load
detection without starting the amplifiers. After a DC load detection cycle finishes without
setting the DC load valid bit DB1[D6], DC load detection is repeated (when bit IB2[D2] is
toggled).
To limit the maximum number of DC load detection cycle loops, a counter and limit have
been added. The loop exits after the predefined number of cycles (COUNTMAX), if the
DC load detection cycle finishes with an invalid detection.
Depending on the application needs, the invalid DC load detection cycle can be handled
as follows:
• the amplifier can be started without DC load detection
• the DC load detection loop can be executed again
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I2C-bus controlled dual channel class-D power amplifier
I2C-bus TX
startup
enable DC load
disable channel 1
disable channel 2
IB1[D0] = 1
IB2[D2] = 1
IB1[D1] = 1
IB2[D1] = 1
COUNT = 0
WAIT DC load
DB1[D4] = 1
DB2[D4] = 1
DB1[D6] = 1
IB1[D0] = 1
IB2[D2] = 1
IB1[D1] = 1
IB2[D1] = 1
I2C-bus RX
channel 1 open load
channel 2 open load
DC load valid
I2C-bus TX
startup
enable DC load
disable channel 1
disable channel 2
COUNT ≤ COUNTMAX
COUNT = COUNT + 1
YES
ERROR HANDLING
start amplifier
anyway
I2C-bus TX
IB1[D0] = 1
IB2[D2] = 0
IB1[D1] = 1
IB2[D1] = 1
DB1[D6] = 1
DC load valid
restart
DC load
NO
startup
disable DC load
disable channel 1
disable channel 2
NO
YES
IB1[D0] = 1
IB2[D2] = 0
IB1[D1] = 0
IB2[D1] = 0
I2C-bus TX
startup
disable DC load
enable channel 1
enable channel 2
001aaj061
Fig 19. Recommended start-up sequence with DC load detection enabled
8.6.2.3
AC load detection
AC load detection is only available in I2C-bus mode and is controlled using bit IB3[D4].
The default setting for bit IB3[D4] = 0 disables AC load detection. When AC load detection
is enabled (bit IB3[D4] = 1), the amplifier load current is measured and compared with a
reference level. Pin CLIP is activated when this threshold is reached. Using this
information, AC load detection can be performed using a predetermined input signal
frequency and level. The frequency and signal level should be chosen so that the load
current exceeds the programmed current threshold when the AC coupled load (tweeter) is
present.
8.6.2.4
CLIP detection
CLIP detection gives information for clip levels  0.2 %. Pin CLIP is used as the output for
the clip detection circuitry on both channel 1 and channel 2. Setting either bit IB1[D5] or bit
IB2[D5] to logic 0 defines which channel reports clip information on the CLIP pin.
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8.6.3 Start-up and shutdown sequence
To prevent switch on or switch off ‘pop noises’, a capacitor (CSVRR) connected to pin
SVRR is used to smooth start-up and shutdown. During start-up and shutdown, the output
voltage tracks the voltage on pin SVRR. Increasing CSVRR results in a longer start-up and
shutdown time. Enhanced pop noise performance is achieved by muting the amplifier until
the SVRR voltage reaches its final value and the outputs start switching. The capacitor
value on pin SEL_MUTE (CON) determines the unmute and mute timing. The voltage on
pin SEL_MUTE determines the amplifier gain. Increasing CON increases the unmute and
mute times. In addition, a larger CON value increases the DC load detection cycle.
When the amplifier is switched off with an I2C-bus command or by pulling pin EN LOW,
the amplifier is first muted and then capacitor (CSVRR) is discharged.
In Slave mode, the device enters the off state immediately after capacitor (CSVRR) is
discharged. In Master mode, the clock is kept active by an additional delay (td(2)) of
approximately 50 ms to allow slave devices to enter the off state.
When an external clock is connected to pin OSCIO (in Slave mode), the clock must
remain active during the shutdown sequence for delay (td(1)) to ensure that the slaved
TDF8599A devices are able to enter the off state.
VDDA
DIAG
td(1)
EN
ACGND
td(3)
IB1[D0] and
IB2[D0] = 0
td(mute-fgain)
mute delay
td(2)
SEL_MUTE
SVRR
twake
td(stb-mute)
tdet(DCload)
OUTn
001aai790
(1) Shutdown hold delay.
(2) Master mode shutdown delay.
(3) Shutdown delay.
Fig 20. Start-up and shutdown timing in I2C-bus mode with DC load detection
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I2C-bus controlled dual channel class-D power amplifier
VDDA
DIAG
td(2)
td(1)
EN
ACGND
td(mute-fgain)
td(3)
SEL_MUTE
SVRR
td(stb-mute)
OUTn
001aai791
(1) Shutdown hold delay.
(2) Shutdown delay.
(3) Master mode shutdown delay.
Fig 21. Start-up and shutdown timing in non-I2C-bus mode
9. I2C-bus specification
TDF8599A address with hardware address select.
Table 13.
I2C-bus write address selection using pins MOD and ADS
RADS[1] (k)
RMOD[1] (k)
R/W
Stereo mode
Parallel mode
0[2]
4.7
13
33
100
open
Open
58h
68h
78h
58h
68h
78h
1 = Read from TDF8599A
100
56h
66h
76h
56h
66h
76h
0 = Write to TDF8599A
33
54h
64h
74h
54h
64h
74h
13
52h
62h
72h
52h
62h
72h
4.7
50h
60h
70h
50h
60h
70h
0[2]
non-I2C-bus
mode select
[1]
Required external resistor accuracy is 1 %.
[2]
Short circuited to ground.
In I2C-bus mode, pins MOD and ADS can be latched using the I2C-bus command
IB3[D7] = 1. This avoids disturbances from amplifier outputs of other TDF8599A devices
in the same application switching and generating incorrect information on the MOD and
ADS pins.
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In non-I2C mode or when IB3[D7] = 0, the information on the MOD and ADS pins is
latched when one of the TDF8599A’s outputs starts switching.
SCL
SCL
SDA
SDA
Mμp
START
Mμp
STOP
SLAVE
(1)
SLAVE
(1)
(2)
001aai793
001aai792
(1) When SCL is HIGH, SDA changes to form the start or
stop condition.
Fig 22.
I2C-bus
(1) SDA is allowed to change.
(2) All data bits must be valid on the positive edges of SCL.
start and stop conditions
SCL
1
MSB − 1
MSB
SDA
2
Mμp START
Fig 23. Data bits sent from Master microprocessor
(Mp)
7
8
LSB + 1
ADDRESS
9
ACK
1
2
MSB − 1
MSB
WRITE
SLAVE
7
LSB + 1
8
LSB
9
ACK
WRITE DATA
STOP
ACK(1)
ACK
001aai794
(1) To stop the transfer after the last acknowledge a stop condition must be generated.
Fig 24. I2C-bus write
SCL
1
MSB
SDA
Mμp
START
SLAVE
2
7
MSB − 1
LSB + 1
ADDRESS
8
9
ACK
1
MSB
2
7
MSB − 1
LSB + 1
8
9
LSB
ACK(1)
READ
ACKNOWLEDGE
STOP
READ DATA
001aai795
(1) To stop the transfer, the last byte must not be acknowledged (SDA is HIGH) and a stop condition must be generated.
Fig 25. I2C-bus read
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9.1 Instruction bytes
If R/W bit = 0, the TDF8599A expects three instruction bytes: IB1, IB2 and IB3. After a
power-on reset, all unspecified instruction bits must be set to zero.
Table 14.
Instruction byte descriptions
Bit
Value
Description
Instruction byte IB1
Instruction byte IB2
Instruction byte IB3
D7
0
offset detection on pin DIAG
offset protection on
latch information on pins ADS
and MOD when the amplifier
starts switching
1
no offset detection on pin DIAG
offset protection off
latch information on pins ADS
and MOD; see Section 9 on
page 23
D6
0
channel 1 offset monitoring on
channel 2 offset monitoring on
-
1
channel 1 offset monitoring off
channel 2 offset monitoring off
-
D5
0
channel 1 clip detect on pin CLIP
channel 2 clip detect on pin CLIP
-
1
channel 1 no clip detect on pin CLIP
channel 2 no clip detect on pin CLIP
-
0
disable frequency hopping
thermal pre-warning on pin CLIP
disable AC load detection
D4
D3
D2
D1
D0
hopping[1]
1
enable frequency
no thermal pre warning on pin CLIP
enable AC load detection
0
oscillator frequency as set with
Rosc  10 %
temperature pre-warning at 140 C
oscillator phase shift bits
IB3[D3] to IB3[D1][2]
1
oscillator frequency as set with
Rosc + 10 %
temperature pre-warning at 120 C
0
-
DC-load detection disabled
1
-
DC-load detection enabled
0
channel 1 enabled
channel 2 enabled
1
channel 1 disabled
channel 2 disabled
0
TDF8599A in Standby mode
all channels operating
AD modulation
1
TDF8599A in Mute or Operating
modes[3]
all channels muted
BD modulation
[1]
See Section 8.3.3 on page 9 for information on IB1[D4] and IB1[D3].
[2]
See Table 15 “Phase shift bit settings” for information on IB3[D3] to IB3[D1].
[3]
See Table 4 for information on IB1[D0] and IB2[D0].
Table 15.
D3
D2
D1
Phase
0
0
0
0
0
0
1
1⁄
4

0
1⁄
3

1
1⁄
2



0
0
TDF8599A
Product data sheet
Phase shift bit settings
1
1
1
0
0
2⁄
3
1
0
1
3⁄
4
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9.2 Data bytes
If R/W = 1, the TDF8599A sends two data bytes to the microprocessor (DB1 and DB2). All
short diagnostic and offset protection bits are latched. In addition, all bits are reset after a
read operation except the DC load detection bits (DBx[D4], DB1[D6]). The default setting
for all bits is logic 0.
In Parallel mode, the diagnostic information is stored in byte DB1.
Table 16.
Description of data bytes
Bit
Value
DB1 channel 1
DB2 channel 2
D7
0
at least 1 instruction bit set to logic 1
below maximum temperature
1
all instruction bits are set to logic 0
maximum temperature protection
activated
0
invalid DC load data
no temperature warning
1
valid DC load data
temperature pre-warning active
0
no overvoltage
no undervoltage
1
overvoltage protection active
undervoltage protection active
0
speaker load channel 1
speaker load channel 2
1
open load channel 1
open load channel 2
0
no shorted load channel 1
no shorted load channel 2
1
shorted load channel 1
shorted load channel 2
0
no offset
reserved
1
offset detected
reserved
D1
0
no short to VP channel 1
no short to VP channel 2
1
short to VP channel 1
short to VP channel 2
D0
0
no short to ground channel 1
no short to ground channel 2
1
short to ground channel 1
short to ground channel 2
D6
D5
D4
D3
D2
Data byte DB1[D7] indicates whether the instruction bits have been set to logic 0. In
principle, DB1[D7] is set after a POR or when all the instruction bits are programmed to
logic 0. Pin DIAG is driven HIGH when bit DB1[D7] = 1.
TDF8599A
Product data sheet
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
10. Limiting values
Table 17. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VP
supply voltage
Operating mode
40
V
+50
V
V
8
-
A
stereo mode
-
18
A
parallel mode
-
12
A
pins SCL, SDA, ADS,
MOD, SSM, OSCIO, EN
and SEL_MUTE
0
5.5
V
pins IN1N, IN1P, IN2N
and IN2P
0
10
V
repetitive peak output
current
maximum output current
limiting
IOM
peak output current
maximum; non-repetitive
[2]
Vo
output voltage
pins DIAG and CLIP
0
10
V
RESR
equivalent series resistance
as seen between pins VP
and PGNDn
-
350
m
Tj
junction temperature
-
150
C
Tstg
storage temperature
55
+150
C
Tamb
ambient temperature
40
+85
C
-
2000
V
-
500
V
electrostatic discharge
voltage
HBM
[3]
C = 100 pF;
Rs = 1.5 k
CDM
[4]
non-corner pins
corner pins
V(prot)
Product data sheet
-
50
IORM
VESD
TDF8599A
Unit
-
[1]
load dump; duration
50 ms; tr > 2.5 ms
input voltage
Max
1
off state
Vi
Min
protection voltage
AC and DC short circuit
voltage of output pins
across load and to
supply and ground
[5]
-
750
V
0
VP
V
[1]
Floating condition assumed for outputs.
[2]
Current limiting concept.
[3]
Human Body Model (HBM).
[4]
Charged-Device Model (CDM).
[5]
The output pins are defined as the output pins of the filter connected between the TDF8599A output pins
and the load.
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
11. Thermal characteristics
Table 18.
Thermal characteristics
Symbol
Parameter
Rth(j-a)
Rth(j-c)
Conditions
Typ
Unit
thermal resistance from junction to ambient in free air
35
K/W
thermal resistance from junction to case
1
K/W
12. Static characteristics
Table 19. Static characteristics
VP = VDDA = 14.4 V; fosc = 320 kHz; 40 C < Tamb < +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
8
14.4
35
V
Supply
VP
supply voltage
IP
supply current
off state; Tj  85 C; VP = 14.4 V
-
2
10
A
Iq(tot)
total quiescent current
Operating mode; no load,
snubbers and filter connected
-
90
120
mA
Tj = 25 C
-
170
180
m
Tj = 100 C
-
235
250
m
Series resistance output switches
RDSon
I2C-bus
drain-source on-state
resistance
power switch;
interface: pins SCL and SDA
VIL
LOW-level input voltage
0
-
1.5
V
VIH
HIGH-level input voltage
2.3
-
5.5
V
VOL
LOW-level output voltage
0
-
0.4
V
pin SDA; Iload = 5 mA
Address, phase shift and modulation mode select: pins ADS and MOD
Vi
input voltage
pins not connected
[1]
1.5
2
2.7
V
Ii
input current
pins shorted to GND
[1]
80
105
160
A
0
-
0.8
V
2
-
5
V
pin EN; Mute mode or Operating
mode; non-I2C-bus mode
2
-
5
V
pin SEL_MUTE; Mute mode;
voltage on pin EN > 2 V
0
-
0.8
V
pin SEL_MUTE; Operating mode;
voltage on pin EN > 2 V
3
-
5
V
Enable and SEL_MUTE input: pins EN and SEL_MUTE
Vi
input voltage
pin EN; off state
pin EN; Standby mode;
mode
Ii
TDF8599A
Product data sheet
input current
I2C-bus
pin EN; 2.5 V
-
-
5
A
pin SEL_MUTE; Operating mode;
0.8 V
-
-
50
A
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
Table 19. Static characteristics …continued
VP = VDDA = 14.4 V; fosc = 320 kHz; 40 C < Tamb < +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
0.2
-
%
1
2
3
V
Diagnostic output
THDclip
total harmonic distortion clip
detection level
Vth(offset)
threshold voltage for offset
detection
VOL
LOW-level output voltage
DIAG or CLIP pins activated;
Io = 1 mA
-
-
0.3
V
IL
leakage current
DIAG and CLIP pins; diagnostic
not activated
-
-
50
A
-
2.45
-
V
input ACGND pin
2
2.45
3
V
half supply reference SVRR pin
6.9
7.2
7.5
V
-
-
25
mV
-
-
70
mV
stabilizer output in Mute mode and
Operating mode
8
10
12
V
undervoltage; amplifier is muted
6.8
7.2
8
V
overvoltage; load dump protection
is activated
37
38
-
V
VP that a POR occurs at
3
3.7
4.6
V
current limiting concept
8
9.5
11
A
155
-
160
C
[2][3]
Audio inputs; pins IN1N, IN1P, IN2N and IN2P
Vi
input voltage
SVRR voltage and ACGND input bias voltage in Mute and Operating modes
Vref
reference voltage
Amplifier outputs; pins OUT1N, OUT1P, OUT2N and OUT2P
VO(offset)
output offset voltage
BTL; Mute mode
BTL; Operating mode
[4][6]
Stabilizer output; pins VSTAB1 and VSTAB2
Vo
output voltage
Voltage protections
V(prot)
protection voltage
Current protection
IO(ocp)
overcurrent protection output
current
Temperature protection
Tprot
protection temperature
Tact(th_fold)
thermal foldback activation
temperature
gain = 1 dB
140
-
150
C
Tj(AV)(warn1)
average junction temperature
for pre-warning 1
IB2[D3] = 0; non-I2C-bus mode
-
140
150
C
Tj(AV)(warn2)
average junction temperature
for pre-warning 2
IB2[D3] = 1
-
120
130
C
DC load detection levels: I2C-bus mode only[7]
Zth(load)
load detection threshold
impedance
for normal speaker load;
DB1[D4] = 0; DB2[D4] = 0
-
-
25

Zth(open)
open load detection threshold
impedance
DB1[D4] = 1; DB2[D4] = 1
350
-
-

250
500
700
mA
AC load detection levels: I2C-bus mode only
Ith(o)det(load)AC
TDF8599A
Product data sheet
AC load detection output
threshold current
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
Table 19. Static characteristics …continued
VP = VDDA = 14.4 V; fosc = 320 kHz; 40 C < Tamb < +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Start-up/shut-down/mute timing
twake
wake-up time
on pin EN before first I2C-bus
transmission is recognized
[5]
-
-
500
s
tdet(DCload)
DC load detection time
CON = 470 nF
[5]
-
380
-
ms
td(stb-mute)
delay time from standby to
mute
measured from amplifier enabling
to start of unmute (no DC load
detection); CSVRR = 47 F
CON = 470 nF
-
140
-
ms
td(mute-fgain)
mute to full gain delay time
CON = 470 nF
-
15
-
ms
td
delay time
shutdown delay time from EN pin
LOW to SVRR LOW; voltage on
pin SVRR < 0.1 V; CSVRR = 47 F
200
350
550
ms
shutdown delay time from EN pin
LOW to SVRR LOW; voltage on
pin SVRR < 0.1 V; CSVRR = 47 F;
VP = 35 V
300
400
700
ms
shutdown hold delay time from pin
EN LOW to ACGND LOW; voltage
on pin ACGND < 0.1 V; Master
mode
-
370
-
ms
hold delay in Master mode to allow
slaved devices to shutdown
fosc = 320 kHz
-
50
-
ms
stereo mode
1.6
4
-

parallel mode
0.8
-
-

stereo mode
3.2
4
-

parallel mode
1.6
-
-

[6]
Speaker load impedance
RL
load resistance
at supply voltage equal to or below
25 V
at supply voltage equal to or below
35 V
[1]
Required resistor accuracy for pins ADS and MOD is 1 %; see Section 9 on page 23.
[2]
Maximum leakage current from DCP pin to ground = 3 A.
[3]
The output offset values can be either positive or negative. The Vth(offset) limit values (excluding Typ) are the valid absolute values.
[4]
DC output offset voltage is applied to the output gradually during the transition between Mute mode and Operating mode.
[5]
I2C-bus mode only.
[6]
The transition time between Mute mode and Operating mode is determined by the time constant on the SEL_MUTE pin.
[7]
The DC load valid bit DB1[D6] must be used; Section 8.6.2.1 on page 18. The DC load enable bit IB2[D2] must be reset after each load
detection cycle to prevent amplifier hang-up incidents.
TDF8599A
Product data sheet
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
12.1 Switching characteristics
Table 20. Switching characteristics
VP = VDDA = 14.4 V; 40 C < Tamb < +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
external clock frequency;
Rosc = 39 k
-
320
-
kHz
internal fixed frequency and Spread
spectrum mode frequency based on
the resistor value connected to pin
OSCSET for the master setting
300
-
450
kHz
Internal oscillator
fosc
oscillator frequency
Master/slave setting (OSCIO pin)
Rosc
oscillator resistance
resistor value on pin OSCSET;
master setting
26
39
49
k
VOL
LOW-level output voltage
output
-
-
0.8
V
VOH
HIGH-level output voltage
output
4
-
-
V
VIL
LOW-level input voltage
input
-
-
0.8
V
VIH
HIGH-level input voltage
input
4
-
-
V
ftrack
tracking frequency
PLL enabled
300
-
500
kHz
Nslave
number of slaves
driven by one master
12
-
-
Spread spectrum mode setting
fosc
oscillator frequency variation
between maximum and minimum
values; Spread spectrum mode
activated
-
10
-
%
fsw
switching frequency
Spread spectrum mode activated;
CSSM = 1 F
-
7
-
Hz
change positive; IB1[D4] = 1;
IB1[D3] = 1
-
fosc + 10 % -
kHz
change negative; IB1[D4] = 1;
IB1[D3] = 0
-
fosc  10 % -
kHz
Frequency hopping
fosc(int)
internal oscillator frequency
Timing
tr
rise time
PWM output; Io = 0 A
-
10
-
ns
tf
fall time
PWM output; Io = 0 A
-
10
-
ns
tw(min)
minimum pulse width
Io = 0 A
-
80
-
ns
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
13. Dynamic characteristics
Table 21. Dynamic characteristics
VP = VDDA = 14.4 V; RL = 4 ; fi = 1 kHz; fosc = 320 kHz; Rs(L) < 0.04 [1]; 40 C < Tamb < +85 C; Stereo mode; unless
otherwise specified.
Symbol
Parameter
output power
Po
Conditions
Min
Typ
Max
Unit
VP = 14.4 V; THD = 1 %; RL = 4 
18
20
-
W
VP = 14.4 V; THD = 10 %; RL = 4 
23
25
-
W
square wave (EIAJ); RL = 4 
-
40
-
W
VP = 35 V; THD = 10 %; RL = 4 
-
135
-
W
VP = 14.4 V; THD = 1 %; RL = 2 
26
29
-
W
VP = 14.4 V; THD = 10 %; RL = 2 
34
38
-
W
-
60
-
W
VP = 14.4 V; THD = 10 %; RL = 2 
-
50
-
W
VP = 35 V; THD = 10 %; RL = 2 
-
250
-
W
Stereo mode:
[2]
square wave (EIAJ); RL = 2 
Parallel mode:
[2]
VP = 25 V; THD = 1 %; RL = 1 
THD
total harmonic distortion
135
150
-
W
fi = 1 kHz; Po = 1 W
[3]
-
0.02
0.1
%
fi = 10 kHz; Po = 1 W
[3]
-
0.02
0.1
%
25
26
27
dB
-
70
-
dB
Gv(cl)
closed-loop voltage gain
cs
channel separation
fi = 1 kHz; Po = 1 W
SVRR
supply voltage rejection ratio
Operating mode
fripple = 100 Hz
[4]
60
70
-
dB
fripple = 1 kHz
[4]
60
70
-
dB
[4]
60
70
-
dB
[4]
-
90
-
dB
60
100
150
k
Mute mode
fripple = 1 kHz
off state and Standby mode
fripple = 1 kHz
Zi(dif)
differential input impedance
Vn(o)
output noise voltage
Operating mode
BD mode
[5]
-
60
77
V
AD mode
[5]
-
100
140
V
BD mode
[6]
-
25
32
V
AD mode
[6]
-
85
110
V
-
0
1
dB
66
-
-
dB
Mute mode
bal(ch)
channel balance
mute
mute attenuation
CMRR
common mode rejection ratio
Vi(cm) = 1 V RMS
65
80
-
dB
po
output power efficiency
Po = 20 W
-
90
-
%
[7]
[1]
Rs(L) is the sum of the inductor series resistance from the low-pass LC filter in the application together with all resistance from PCB
traces or wiring between the output pin of the TDF8599A and the inductor to the measurement point. LC filter dimensioning is
L = 10 H, C = 1 F for 4  load and L = 5 H, C = 2.2 F for 2  load.
[2]
Output power is measured indirectly based on RDSon measurement.
TDF8599A
Product data sheet
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
[3]
Total harmonic distortion is measured at the bandwidth of 22 Hz to 20 kHz, AES brick wall. The maximum limit is guaranteed but may
not be 100 % tested.
[4]
Vripple = Vripple(max) = 2 V (p-p); Rs = 0 .
[5]
B = 22 Hz to 20 kHz, AES brick wall, Rs = 0 .
[6]
B = 22 Hz to 20 kHz, AES brick wall, independent of Rs.
[7]
Vi = Vi(max) = 0.5 V RMS.
14. Application information
14.1 Output power estimation (Stereo mode)
The output power, just before clipping, can be estimated using Equation 5:
2
RL
f osc
  1 – t
  ---------------------------------------------------- --------  V P 
w

min

  R L + 2   R DSon + R s  

2 
P o = -------------------------------------------------------------------------------------------------------------------------------------  W 
2  RL
(5)
Where,
•
•
•
•
•
•
VP = supply voltage (V)
RL = load impedance ()
RDSon = drain source on-state resistance ()
Rs = series resistance of the output inductor ()
tw(min) = minimum pulse width(s) depending on output current (s)
fosc = oscillator frequency in Hz (typically 320 kHz)
The output power at 10 % THD can be estimated by: P o  2  = 1.25  P o  1  where
Po(1) = 0.5 % and Po(2) = 10 %.
Figure 26 and Figure 27 show the estimated output power at THD = 0.5 % and
THD = 10 % as a function of supply voltage for different load impedances in stereo mode.
TDF8599A
Product data sheet
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
001aaj181
140
Po
(W)
120
001aaj182
160
Po
(W)
120
100
80
(1)
80
(1)
(2)
60
(2)
40
40
20
0
0
8
16
24
32
40
8
16
VP (V)
24
32
40
VP (V)
THD = 0.5 %.
THD = 10 %.
RDSon = 0.2  (at Tj = 100 C), Rs = 0.05 ,
tw(min) = 190 ns and IO(ocp) = 8 A (minimum).
RDSon = 0.2  (at Tj = 100 C), Rs = 0.05 ,
tw(min) = 190 ns and IO(ocp) = 8 A (minimum).
(1) RL = 2 .
(1) RL = 2 .
(2) RL = 4 .
(2) RL = 4 .
Fig 26. Po as a function of VP in stereo mode with
THD = 0.5 %
Fig 27. Po as a function of VP in stereo mode with
THD = 10 %
14.2 Output power estimation (Parallel mode)
Figure 28 and Figure 29 show the estimated output power at THD = 0.5 % and
THD = 10 % as a function of the supply voltage for different load impedances in parallel
mode.
TDF8599A
Product data sheet
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
001aaj183
250
001aaj184
300
Po
(W)
250
Po
(W)
200
200
150
(1)
(1)
150
(2)
100
100
(2)
(3)
(3)
50
50
0
0
8
16
24
32
40
8
16
VP (V)
24
32
40
VP (V)
THD = 0.5 %.
THD = 10 %.
RDSon = 0.1  (at Tj = 100 C), Rs = 0.025 ,
tw(min) = 190 ns and IO(ocp) = 16 A (minimum).
RDSon = 0.1  (at Tj = 100 C), Rs = 0.025 ,
tw(min) = 190 ns and IO(ocp) = 16 A (minimum).
(1) RL = 1 .
(1) RL = 1 .
(2) RL = 2 .
(2) RL = 2 .
(3) RL = 4 .
(3) RL = 4 .
Fig 28. Po as a function of VP in parallel mode with
THD = 0.5 %
Fig 29. Po as a function of VP parallel mode with
THD = 10 %
14.3 Output current limiting
The peak output current is internally limited to 8 A maximum. During normal operation, the
output current should not exceed this threshold level otherwise the output signal will be
distorted. The peak output current can be estimated using Equation 6:
VP
I o  -----------------------------------------------------  8 [A]
R L + 2   R DSon + R s 
•
•
•
•
•
(6)
Io = output current (A)
VP = supply voltage (V)
RL = load impedance ()
RDSon = on-resistance of power switch ()
Rs = series resistance of output inductor ()
Example: A 2  speaker can be used with a supply voltage of 19 V before current limiting
is triggered.
Current limiting (clipping) avoids audio holes but can cause distortion similar to voltage
clipping. In Parallel mode, the output current is internally limited above 16 A.
TDF8599A
Product data sheet
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
14.4 Speaker configuration and impedance
A flat-frequency response (due to a 2nd order Butterworth filter) is obtained by changing
the low-pass filter components (LLC, CLC) based on the speaker configuration and
impedance. Table 22 shows the required values.
Table 22.
Filter component values
Load impedance ()
LLC (H)
CLC (F)
1
2.5
4.4
2
5
2.2
4
10
1
Remark: When using a 1  load impedance in Parallel mode, the outputs are shorted
after the low-pass filter switches two 2  filters in parallel.
14.5 Heat sink requirements
In most applications, it is necessary to connect an external heat sink to the TDF8599A.
Thermal foldback activates at Tj = 140 C. The expression below shows the relationship
between the maximum power dissipation before activation of thermal foldback and the
total thermal resistance from junction to ambient:
T j  max  – T amb
R th  j-a  = -----------------------------------  K/W 
P max
(7)
Pmax is determined by the efficiency () of the TDF8599A. The efficiency measured as a
function of output power is given in Figure 43. The power dissipation can be derived as a
function of output power (see Figure 42).
Example 1:
•
•
•
•
•
•
VP = 14.4 V
Po = 2  25 W into 4  (THD = 10 % continuous)
Tj(max) = 140 C
Tamb = 25 C
Pmax = 5.8 W (from Figure 42)
The required Rth(j-a) = 115 C / 5.8 W = 19 K/W
The total thermal resistance Rth(j-a) consists of: Rth(j-c) + Rth(c-h) + Rth(h-a)
Where:
• Thermal resistance from junction to case (Rth(j-c)) = 1 K/W
• Thermal resistance from case to heat sink (Rth(c-h)) = 0.5 K/W to 1 K/W (depending on
mounting)
• Thermal resistance from heat sink to ambient (Rth(h-a)) would then be
19  (1 + 1) = 17 K/W.
If an audio signal has a crest factor of 10 (the ratio between peak power and average
power = 10 dB) then Tj will be much lower.
TDF8599A
Product data sheet
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Rev. 3 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
36 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
Example 2:
•
•
•
•
•
•
VP = 14.4 V
Po = 2  (25 W / 10) = 2  2.5 W into 4  (audio with crest factor of 10)
Tamb = 25 C
Pmax = 2.5 W
Rth(j-a) = 19 K/W
Tj(max) = 25 C + (2.5 W  19 K/W) = 72 C
14.6 Curves measured in reference design
001aaj185
102
THD + N
(%)
THD + N
(%)
10
10
1
1
10−1
10−1
(3)
(1)
10−3
10−1
(3)
(2)
(2)
10−2
001aaj186
102
10−2
1
102
10
(1)
10−3
10−1
1
Po (W)
(1) VP = 14.4 V; RL = 2  at 100 Hz.
(1) VP = 14.4 V; RL = 4  at 100 Hz.
(2) VP = 14.4 V; RL = 2  at 1 kHz.
(2) VP = 14.4 V; RL = 4  at 1 kHz.
(3) VP = 14.4 V, RL = 2  at 6 kHz.
(3) VP = 14.4 V, RL = 4  at 6 kHz.
Fig 30. THD + N as a function of output power with a
2  load; VP = 14.4 V
TDF8599A
Product data sheet
102
10
Po (W)
Fig 31. THD + N as a function of output power with a
4  load; VP = 14.4 V
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© NXP B.V. 2013. All rights reserved.
37 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
001aaj187
102
001aaj188
102
THD + N
(%)
10
THD + N
(%)
10
1
1
(3)
10−1
(2)
(1)
10−2
10−3
10−1
(3)
10−1
(2)
10−2
1
10
102
103
(1)
10−3
10−1
1
10
102
Po (W)
(1) VP = 35 V; RL = 2  at 100 Hz.
(1) VP = 35 V; RL = 4  at 100 Hz.
(2) VP = 35 V; RL = 2  at 1 kHz.
(2) VP = 35 V; RL = 4  at 1 kHz.
(3) VP = 35 V, RL = 2  at 6 kHz.
(3) VP = 35 V, RL = 4  at 6 kHz.
Fig 32. THD + N as a function of output power with a
2  load; VP = 35 V
001aaj190
1
103
Po (W)
Fig 33. THD + N as a function of output power with a
4  load; VP = 35 V
001aaj189
1
THD + N
(%)
THD + N
(%)
10−1
10−1
(2)
10−2
(2)
10−2
(1)
(1)
10−3
10
102
103
104
105
10−3
10
102
103
f (Hz)
(1) VP = 14.4 V; RL = 2  at 1 W.
(1) VP = 14.4 V; RL = 4  at 1 W.
(2) VP = 14.4 V; RL = 4  at 10 W.
Fig 34. THD + N as a function of frequency with a 2 
load, BD modulation; VP = 14.4 V
Product data sheet
105
f (Hz)
(2) VP = 14.4 V; RL = 2  at 10 W.
TDF8599A
104
Fig 35. THD + N as a function of frequency with a 4 
load, BD modulation; VP = 14.4 V
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Rev. 3 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
38 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
001aaj191
1
001aaj192
30
G
(dB)
THD + N
(%)
28
10−1
26
24
10−2
(2)
(1)
22
10−3
10
102
103
104
105
20
10
102
103
104
f (Hz)
105
f (Hz)
(1) VP = 35 V; RL = 2  at 1 W.
(2) VP = 35 V; RL = 2  at 10 W.
Fig 36. THD + N as a function of frequency with a 2 
load, BD modulation; VP = 35 V
001aaj193
160
Po
(W)
Fig 37. Gain as a function of frequency
001aaj194
240
Po
(W)
200
(3)
120
(3)
160
(2)
80
120
(2)
(1)
80
(1)
40
40
0
0
10
14
18
22
26
30
10
15
20
VP (V)
35
f = 1 kHz; RL = 4 .
(1) THD = 1 %.
(1) THD = 1 %.
(2) THD = 10 %.
(2) THD = 10 %.
(3) Maximum output power.
(3) Maximum output power.
Fig 38. Output power as a function of supply voltage
with a 2  load
Product data sheet
30
VP (V)
f = 1 kHz; RL = 2 .
TDF8599A
25
Fig 39. Output power as a function of supply voltage
with a 4  load
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Rev. 3 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
39 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
001aaj195
−60
αcs
(dB)
−70
001aaj196
−60
(2)
αcs
(dB)
−70
(1)
−80
−80
−90
−90
(2)
−100
10
102
103
104
105
−100
(1)
102
10
103
104
f (Hz)
105
f (Hz)
VP = 14.4 V; Ri = 4 ; Po = 1 W.
VP = 14.4 V; Ri = 4 ; Po = 10 W.
(1) Channel 1 to channel 2.
(1) Channel 1 to channel 2.
(2) Channel 2 to channel 1.
(2) Channel 2 to channel 1.
Fig 40. Channel separation as a function of frequency
with 1 W output power
001aaj197
30
Fig 41. Channel separation as a function of frequency
with 10 W output power
001aaj198
100
η
(%)
PD
(W)
(1)
80
(2)
20
60
(2)
40
10
(1)
20
0
0
0
10
20
30
40
50
0
10
20
30
Po (W)
(1) VP = 14.4 V; RL = 2  at 1 kHz.
(1) VP = 14.4 V; RL = 2  at 1 kHz.
(2) VP = 14.4 V; RL = 4  at 1 kHz.
Fig 42. Power dissipation as a function of output
power
Product data sheet
50
Po (W)
(2) VP = 14.4 V; RL = 4  at 1 kHz.
TDF8599A
40
Fig 43. Efficiency as a function of total output power
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Rev. 3 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
40 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
001aaj199
40
001aaj200
100
η
(%)
PD
(W)
80
30
60
20
40
10
20
0
0
0
30
60
90
120
150
Po (W)
0
VP = 35 V; RL = 4 .
30
60
90
120
150
Po (W)
VP = 35 V; RL = 4 .
Fig 44. Power dissipation as a function of total output
power with both channels driven
Fig 45. Efficiency as a function of output power of one
channel with both channels driven
001aak079
−70
CMRR
(dB)
−74
−78
−82
−86
−90
10
102
103
104
105
f (Hz)
VP = 14.4 V; Vi = 1 V RMS.
Fig 46. CMRR as a function of frequency
TDF8599A
Product data sheet
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Rev. 3 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
41 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
14.7 Typical application schematics
bead
100 μF
35 V
bead
bead
VP
100 μF
35 V
VP1
VP2
VPA
PGND1
1000 μF
35 V
GND
PGND2
GNDD/HW
100 nF
VDDD
220 nF
LLC
OUT1N
OUT1N
100 nF
CLC
15 nF
10 Ω
22 Ω
470 pF
470 pF
470 pF
CLC
10 Ω
OUT1P
LLC
OUT2P
OUT2P
100 nF
CLC
15 nF
10 Ω
22 Ω
470 pF
470 pF
VP2
470 pF
470 pF
CLC
100 nF
OUT2N
BOOT2P
PGND2 PGND2
VP2
VP2
BOOT2N
10 Ω
15 nF
LLC
33
2
3
4
32
5
31
6
IN1P CIN1P
470 nF
IN1N CIN1N
470 nF
CIN2P
470 nF
IN2N CIN2N
470 nF
IN2P
ACGND
EN
28
7
IN1P
IN1N
IN2P
IN2N
CACGND
100 nF
enable(1)
8
9
TDF8599A
27
10
26
11
25
12
24
13
SEL_MUTE
220 nF
OUT2N
VSTAB2
DCP
(3)
OSCIO
23
14
22
15
21
16
20
17
19
18
mute/on(1)
470 nF
SVRR
47 μF
AGND
VDDA
2.2 μF
bead
VPA
non-I2C-bus
mode
ADS
MOD
4.7 kΩ
CLIP
10 kΩ
DIAG
10 kΩ
100 nF
PGND2
22 Ω
34
PGND1
30
PGND1
BOOT1P
29
15 nF
LLC
OUT1P
VP1
35
1
100 nF
PGND1
22 Ω
BOOT1N
VP1
470 pF
VP1
100 nF
VSTAB1
36
BD modulation
setting
VPull-up
VPull-up
SDA
SCL
SSM
OSCSET
1 μF(2)
100 nF
39 kΩ
MASTER
MODE
001aak080
Dual BTL mode (stereo) in non-I2C-bus mode with DC offset protection disabled, Spread spectrum
mode enabled BD modulation.
(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 8 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 47. Example application diagram: dual BTL in non-I2C-bus mode
TDF8599A
Product data sheet
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Rev. 3 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
42 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
bead
100 μF
35 V
bead
bead
VP
100 μF
35 V
VP1
VP2
VPA
PGND1
1000 μF
35 V
GND
PGND2
GNDD/HW
100 nF
VDDD
220 nF
LLC
OUT1N
OUT1N
100 nF
CLC
15 nF
10 Ω
22 Ω
470 pF
470 pF
470 pF
100 nF
10 Ω
OUT1P
LLC
OUT2P
OUT2P
100 nF
CLC
15 nF
10 Ω
22 Ω
470 pF
470 pF
VP2
470 pF
470 pF
CLC
100 nF
OUT2N
BOOT2P
PGND2 PGND2
VP2
VP2
BOOT2N
10 Ω
15 nF
LLC
220 nF
OUT2N
VSTAB2
DCP
(3)
2
34
3
33
4
32
5
31
6
7
8
28
9
TDF8599A
27
10
26
11
25
12
24
13
IN1P CIN1P
470 nF
IN1N CIN1N
470 nF
IN2P CIN2P
470 nF
IN2N CIN2N
470 nF
ACGND
EN
4.7 μF
OSCIO
23
14
22
15
21
16
20
17
19
18
IN1P
IN1N
IN2P
IN2N
CACGND
100 nF
enable(1)
SEL_MUTE(1)
470 nF
SVRR
47 μF
AGND
VDDA
2.2 μF
ADS
bead
RADS
MOD
≤ 13 kΩ
100 nF
PGND2
22 Ω
35
PGND1
30
PGND1
BOOT1P
29
15 nF
LLC
OUT1P
VP1
1
100 nF
PGND1
22 Ω
BOOT1N
VP1
470 pF
VP1
CLC
VSTAB1
36
CLIP
10 kΩ
DIAG
10 kΩ
VPA
I2C-bus
address select
stereo mode
setting
VPull-up
VPull-up
SDA
connect
to μP
SCL
SSM
OSCSET
(2)
100 nF
39 kΩ
MASTER
MODE
001aak081
Dual BTL mode (stereo) in I2C-bus mode with DC offset protection enabled, Spread spectrum
mode disabled.
(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 8 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 48. Example application diagram: dual BTL in I2C-bus mode
TDF8599A
Product data sheet
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Rev. 3 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
43 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
bead
100 μF
35 V
bead
bead
VP
100 μF
35 V
VP1
VP2
VPA
PGND1
1000 μF
35 V
GND
PGND2
GNDD/HW
100 nF
VDDD
220 nF
LLC
OUT1N
15 nF
10 Ω
470 pF
470 pF
CLC
10 Ω
22 Ω
VP1
OUT1P
LLC
22 Ω
100 nF
OUT2P
BOOT2P
CLC
470 pF
OUTP
15 nF
10 Ω
470 pF
VP2
PGND2 PGND2
100 nF
PGND2
470 pF
470 pF
VP2
VP2
BOOT2N
10 Ω
15 nF
LLC
220 nF
OUT2N
VSTAB2
DCP
(3)
35
2
34
3
33
4
32
5
31
6
PGND1
30
PGND1
BOOT1P
29
15 nF
LLC
1
100 nF
PGND1
470 pF
100 nF
BOOT1N
VP1
470 pF
VP1
OUTN
VSTAB1
36
4.7 μF
OSCIO
7
8
28
9
TDF8599A
27
10
26
11
25
12
24
13
23
14
22
15
21
16
20
17
19
18
IN1P
IN1N
CINP
CINN
470 nF
INP
470 nF
INN
IN2P
IN2N
ACGND
EN
CACGND
100 nF
enable(1)
SEL_MUTE(1)
470 nF
SVRR
47 μF
AGND
VDDA
2.2 μF
ADS
bead
RADS
MOD
≥ 33 kΩ
CLIP
10 kΩ
DIAG
10 kΩ
VPA
I2C-bus
address select
parallel mode
setting
VPull-up
VPull-up
SDA
connect
to μP
SCL
SSM
OSCSET
100 nF
39 kΩ
fixed
frequency(2)
MASTER
MODE
001aak082
Single BTL mode (parallel) in I2C-bus mode with DC offset protection enabled, Spread spectrum
mode disabled.
(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 8 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 49. Example application diagram: single BTL in I2C-bus mode
TDF8599A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
44 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
bead
100 μF
35 V
bead
100 μF
35 V
bead
VP
GND
VP1
VP2
GNDD/HW
VPA
PGND1
1000 μF
35 V
100 nF
PGND2
VDDD
220 nF
LLC
OUT1N
OUT1N
100 nF
CLC
15 nF
10 Ω
22 Ω
470 pF
470 pF
22 Ω
100 nF
10 Ω
PGND1
PGND1
BOOT1P
15 nF
LLC
OUT1P
VP1
OUT1P
LLC
OUT2P
OUT2P
100 nF
CLC
15 nF
10 Ω
22 Ω
470 pF
470 pF
VP2
470 pF
CLC
100 nF
470 pF
100 nF
VP2
VP2
BOOT2N
10 Ω
15 nF
LLC
OUT2N
BOOT2P
PGND2 PGND2
PGND2
22 Ω
OUT2N
220 nF
VSTAB2
DCP
DC offset
protection enabled
1
35
2
34
3
33
4
32
5
31
6
30
7
29
8
100 nF
PGND1
470 pF
BOOT1N
VP1
470 pF
VP1
CLC
VSTAB1
36
4.7 μF
OSCIO
(3)
28
9
TDF8599A
27 MASTER 10
26
11
25
12
24
13
23
14
22
15
21
16
20
17
19
18
IN1P CIN1P
470 nF
IN1N CIN1N
470 nF
IN2P CIN2P
470 nF
IN2N CIN2N
470 nF
GNDD/HW
VDDD
220 nF
LLC
470 pF
15 nF
470 pF
470 pF
10 Ω
22 Ω
VP1
OUT1P
LLC
22 Ω
OUT2P
15 nF
10 Ω
BOOT2P
CLC
470 pF
470 pF
VP2
PGND2 PGND2
100 nF
PGND2
470 pF
470 pF
VP2
VP2
BOOT2N
10 Ω
15 nF
LLC
220 nF
OUT2N
VSTAB2
DCP
DC offset
protection enabled
1
35
2
34
3
33
4
32
5
31
6
PGND1
30
PGND1
BOOT1P
29
15 nF
LLC
36
100 nF
PGND1
CLC
BOOT1N
VP1
470 pF
VP1
OUT3N
VSTAB1
OUT1N
10 Ω
OUT3P
IN2P
IN2N
100 nF
EN(1)
enable
SEL_MUTE(1)
470 nF
SVRR
47 μF
AGND
2.2 μF
VDDA
ADS
bead
RADS
MOD
≤ 13 kΩ
CLIP
10 kΩ
DIAG
10 kΩ
VPA
I2C-bus
address select
stereo mode
setting
VPull-up
VPAPull-up
SDA
SCL
1 μF
SSM
OSCSET
spread
spectrum
mode(2)
100 nF
MASTER
MODE
39 kΩ
100 nF
100 nF
IN1N
CACGND
ACGND
20 kΩ
100 nF
IN1P
4.7 μF
(3)
OSCIO
7
8
28
9
TDF8599A
27 SLAVE 10
26
25
11
12
24
13
23
14
22
15
21
16
20
17
19
18
IN1P
CINP
470 nF
IN1N
CINN
470 nF
IN3P
IN3N
IN2P
IN2N
CACGND
ACGND
100 nF
EN(1)
SEL_MUTE(1)
470 nF
SVRR
47 μF
AGND
2.2 μF
VDDA
ADS
bead
RADS
MOD
≥ 33 kΩ
CLIP
10 kΩ
DIAG
10 kΩ
VPA
I2C-bus
address select
parallel mode
setting
VPull-up
VPull-up
SDA
connect
to μP
SCL
5.1 kΩ
SSM
OSCSET
270 nF
10 nF
SLAVE MODE
phase lock
operation
(4)
001aak083
I2C-bus mode: dual BTL in Master mode, one BTL in Slave mode; DC offset protection enabled.
(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 8 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on disabling DC offset protection.
(4) See Section 8.3.4 on page 10 for detailed information on PLL operation.
Fig 50. Example application diagram: dual BTL master, single BTL slave in I2C-bus mode
TDF8599A
Product data sheet
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Rev. 3 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
45 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
15. Package outline
HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height
SOT851-2
D
E
A
x
c
y
X
E2
v
HE
M
A
D1
D2
1
18
pin 1 index
Q
A
A2
E1
(A 3)
A4
θ
Lp
detail X
36
19
z
w
bp
e
M
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max. A2
mm
3.5
A3
A4(1)
+0.08
3.5
0.35
−0.04
3.2
D1
D2
E (2)
E1
E2
e
HE
Lp
Q
0.38 0.32 16.0 13.0
0.25 0.23 15.8 12.6
1.1
0.9
11.1
10.9
6.2
5.8
2.9
2.5
0.65
14.5
13.9
1.1
0.8
1.7
1.5
bp
c
D (2)
v
w
x
y
0.25 0.12 0.03 0.07
Z
θ
2.55
2.20
8°
0°
Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
SOT851-2
EUROPEAN
PROJECTION
ISSUE DATE
04-05-04
Fig 51. Package outline SOT851-2 (HSOP36)
TDF8599A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
46 of 55
TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
16. Handling information
In accordance with SNW-FQ-611-D. The number of the quality specification can be found
in the Quality Reference Handbook. The handbook can be ordered using the code
9398 510 63011.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
TDF8599A
Product data sheet
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 52) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 23 and 24
Table 23.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 24.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 52.
TDF8599A
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 52. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Abbreviations
Table 25.
TDF8599A
Product data sheet
Abbreviations
Abbreviation
Description
BCDMOS
Bipolar Complementary and double Diffused Metal-Oxide Semiconductor
BTL
Bridge-Tied Load
DCP
DC offset Protection
DMOST
double Diffused Metal-Oxide Semiconductor Transistor
EMI
ElectroMagnetic Interference
I2C
Inter-Integrated Circuit
LSB
Least Significant Bit
Mp
Master microprocessor
MSB
Most Significant Bit
NDMOST
N-type double Diffused Metal-Oxide Semiconductor Transistor
OCP
OverCurrent Protection
OTP
OverTemperature Protection
OVP
OverVoltage Protection
PLL
Phase-Locked Loop
POR
Power-On Reset
PWM
Pulse-Width Modulation
SOI
Silicon On Insulator
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
Table 25.
Abbreviations …continued
Abbreviation
Description
TFP
Thermal Foldback Protection
UVP
UnderVoltage Protection
WP
Window Protection
19. Revision history
Table 26.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TDF8599A v.3
20130502
Product data sheet
-
TDF8599A v.2
-
TDF8599A v.1
Modifications:
TDF8599A v.2
Modifications:
TDF8599A v.1
TDF8599A
Product data sheet
•
Changed title Figure 45.
20090630
•
•
•
•
•
•
•
•
Product data sheet
Data sheet status changed from Objective data sheet to Product data sheet.
Various minor textual inconsistencies in the data sheet corrected.
Changed Section 8.2: Figure 3 on page 6.
Changed Section 8.2: Table 4 on page 7.
Changed Section 8.2: Table 5 on page 7.
Changed Section 8.6.3: Figure 20 on page 22.
Changed Section 8.6.3: Figure 21 on page 23.
Changed Section 14.7: Figure 47 on page 42, Figure 48 on page 43, Figure 49 on page 44
and Figure 50 on page 45.
20090602
Objective data sheet
-
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Rev. 3 — 2 May 2013
-
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20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TDF8599A
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
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I2C-bus controlled dual channel class-D power amplifier
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
20.4 Trademarks
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
TDF8599A
Product data sheet
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
I2C-bus mode operation . . . . . . . . . . . . . . . . . . .7
Non-I2C-bus mode operation . . . . . . . . . . . . . . .7
Mode setting pin OSCIO . . . . . . . . . . . . . . . . . .7
Oscillator modes . . . . . . . . . . . . . . . . . . . . . . .10
Operation mode selection with the MOD pin . . 11
Overview of protection types . . . . . . . . . . . . . .15
Overview of TDF8599A protection circuits and
amplifier states . . . . . . . . . . . . . . . . . . . . . . . . .17
Available data on pins DIAG and CLIP . . . . . .18
Interpretation of DC load detection bits . . . . . .20
I2C-bus write address selection using pins
MOD and ADS . . . . . . . . . . . . . . . . . . . . . . . . .23
Instruction byte descriptions . . . . . . . . . . . . . .25
Phase shift bit settings . . . . . . . . . . . . . . . . . . .25
Description of data bytes . . . . . . . . . . . . . . . . .26
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27
Thermal characteristics . . . . . . . . . . . . . . . . . .28
Static characteristics . . . . . . . . . . . . . . . . . . . .28
Switching characteristics . . . . . . . . . . . . . . . . .31
Dynamic characteristics . . . . . . . . . . . . . . . . . .32
Filter component values . . . . . . . . . . . . . . . . .36
SnPb eutectic process (from J-STD-020D) . . .48
Lead-free process (from J-STD-020D) . . . . . .48
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .49
Revision history . . . . . . . . . . . . . . . . . . . . . . . .50
TDF8599A
Product data sheet
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TDF8599A
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Fig 31.
Fig 32.
Fig 33.
Fig 34.
Fig 35.
Fig 36.
Fig 37.
Fig 38.
Fig 39.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Heatsink up (top view) pin configuration
TDF8599ATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Clock frequency as a function of Rosc . . . . . . . . . .8
Master and slave configuration . . . . . . . . . . . . . . .8
Spread spectrum mode . . . . . . . . . . . . . . . . . . . . .9
Spread spectrum operation in Master mode . . . . .9
Phase lock operation . . . . . . . . . . . . . . . . . . . . . .10
AD/BD modulation switching circuit . . . . . . . . . . .12
AD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .12
BD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Master and slave operation with 1⁄2 p phase shift 14
Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DC offset protection and diagnostic output . . . . .16
Diagnostic output for short circuit conditions . . . .18
DC load detection circuit . . . . . . . . . . . . . . . . . . .19
DC load detection procedure . . . . . . . . . . . . . . . .19
DC load detection limits . . . . . . . . . . . . . . . . . . . .19
Recommended start-up sequence with DC load
detection enabled . . . . . . . . . . . . . . . . . . . . . . . .21
Start-up and shutdown timing in I2C-bus mode
with DC load detection . . . . . . . . . . . . . . . . . . . . .22
Start-up and shutdown timing in non-I2C-bus
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
I2C-bus start and stop conditions. . . . . . . . . . . . .24
Data bits sent from Master microprocessor
(Mmp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
I2C-bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
I2C-bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Po as a function of VP in stereo mode with
THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Po as a function of VP in stereo mode with
THD = 10 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Po as a function of VP in parallel mode with
THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Po as a function of VP parallel mode with
THD = 10 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
THD + N as a function of output power with a
2  load; VP = 14.4 V. . . . . . . . . . . . . . . . . . . . . .37
THD + N as a function of output power with a
4  load; VP = 14.4 V. . . . . . . . . . . . . . . . . . . . . .37
THD + N as a function of output power with a
2  load; VP = 35 V . . . . . . . . . . . . . . . . . . . . . . .38
THD + N as a function of output power with a
4  load; VP = 35 V . . . . . . . . . . . . . . . . . . . . . . .38
THD + N as a function of frequency with a 2 
load, BD modulation; VP = 14.4 V . . . . . . . . . . . .38
THD + N as a function of frequency with a 4 
load, BD modulation; VP = 14.4 V . . . . . . . . . . . .38
THD + N as a function of frequency with a 2 
load, BD modulation; VP = 35 V. . . . . . . . . . . . . .39
Gain as a function of frequency . . . . . . . . . . . . . .39
Output power as a function of supply voltage
with a 2  load . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Output power as a function of supply voltage
TDF8599A
Product data sheet
with a 4  load . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Fig 40. Channel separation as a function of frequency
with 1 W output power. . . . . . . . . . . . . . . . . . . . . 40
Fig 41. Channel separation as a function of frequency
with 10 W output power. . . . . . . . . . . . . . . . . . . . 40
Fig 42. Power dissipation as a function of output power . 40
Fig 43. Efficiency as a function of total output power . . . 40
Fig 44. Power dissipation as a function of total output
power with both channels driven. . . . . . . . . . . . . 41
Fig 45. Efficiency as a function of output power of one
channel with both channels driven . . . . . . . . . . . 41
Fig 46. CMRR as a function of frequency . . . . . . . . . . . . 41
Fig 47. Example application diagram: dual BTL in
non-I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . 42
Fig 48. Example application diagram: dual BTL in
I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Fig 49. Example application diagram: single BTL in
I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Fig 50. Example application diagram: dual BTL master,
single BTL slave in I2C-bus mode . . . . . . . . . . . . 45
Fig 51. Package outline SOT851-2 (HSOP36) . . . . . . . . 46
Fig 52. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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TDF8599A
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I2C-bus controlled dual channel class-D power amplifier
24. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
8.4.1
8.4.2
8.4.3
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.6
8.6.1
8.6.2
8.6.2.1
8.6.2.2
8.6.2.3
8.6.2.4
8.6.3
9
9.1
9.2
10
11
12
12.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pulse-width modulation frequency . . . . . . . . . . 7
Master and slave mode selection . . . . . . . . . . . 7
Spread spectrum mode (Master mode) . . . . . . 8
Frequency hopping (Master mode). . . . . . . . . . 9
Phase lock operation (Slave mode) . . . . . . . . 10
Operation mode selection. . . . . . . . . . . . . . . . 11
Modulation mode . . . . . . . . . . . . . . . . . . . . . . 11
Phase staggering (Slave mode) . . . . . . . . . . . 13
Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal foldback . . . . . . . . . . . . . . . . . . . . . . 15
Overtemperature protection . . . . . . . . . . . . . . 15
Overcurrent protection . . . . . . . . . . . . . . . . . . 15
Window protection . . . . . . . . . . . . . . . . . . . . . 15
DC offset protection . . . . . . . . . . . . . . . . . . . . 16
Supply voltages . . . . . . . . . . . . . . . . . . . . . . . 17
Overview of protection circuits and amplifier
states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Diagnostic output . . . . . . . . . . . . . . . . . . . . . . 17
Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . 17
Load identification (I2C-bus mode only) . . . . . 18
DC load detection . . . . . . . . . . . . . . . . . . . . . . 18
Recommended start-up sequence with DC
load detection enabled . . . . . . . . . . . . . . . . . . 20
AC load detection . . . . . . . . . . . . . . . . . . . . . . 21
CLIP detection . . . . . . . . . . . . . . . . . . . . . . . . 21
Start-up and shutdown sequence . . . . . . . . . . 22
I2C-bus specification . . . . . . . . . . . . . . . . . . . . 23
Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 25
Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27
Thermal characteristics . . . . . . . . . . . . . . . . . 28
Static characteristics. . . . . . . . . . . . . . . . . . . . 28
Switching characteristics . . . . . . . . . . . . . . . . 31
13
14
14.1
14.2
14.3
14.4
14.5
14.6
14.7
15
16
17
17.1
17.2
17.3
17.4
18
19
20
20.1
20.2
20.3
20.4
21
22
23
24
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Output power estimation (Stereo mode) . . . .
Output power estimation (Parallel mode). . . .
Output current limiting . . . . . . . . . . . . . . . . . .
Speaker configuration and impedance. . . . . .
Heat sink requirements . . . . . . . . . . . . . . . . .
Curves measured in reference design . . . . . .
Typical application schematics. . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
33
33
34
35
36
36
37
42
46
47
47
47
47
47
48
49
50
51
51
51
51
52
52
53
54
55
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 2 May 2013
Document identifier: TDF8599A
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