Compact Synchronous Buck Regulators ISL8002, ISL8002A, ISL80019, ISL80019A ISL8002, ISL8002A, ISL80019 and ISL80019A are highly Features efficient, monolithic, synchronous step-down DC/DC converters • VIN range 2.7V to 5.5V that can deliver up to 2A of continuous output current from a 2.7V to 5.5V input supply. They use peak current mode control architecture to allow very low duty cycle operation. They operate at either 1MHz or 2MHz switching frequency, thereby providing superior transient response and allowing for the use of small inductors. They also have excellent stability and provide both internal and external compensation options. • VOUT range is 0.6V to VIN • IOUT maximum is 1.5A or 2A (see Table 1 on page 3) • Switching frequency is 1MHz or 2MHz (see Table 1 on page 3) • Internal or external compensation option ISL8002, ISL8002A, ISL80019 and ISL80019A integrate very low rDS(ON) MOSFETs in order to maximize efficiency. In addition, since the high side MOSFET is a PMOS, the need for a Boot capacitor is eliminated, thereby reducing external component count. They can operate at 100% duty cycle (at 1MHz) with a dropout of 200mV at 2A output current. • Selectable PFM or PWM operation option • Overcurrent and short circuit protection • Over-temperature/thermal protection • VIN Undervoltage Lockout and VOUT Overvoltage Protection • Up to 95% peak efficiency These devices can be configured for either PFM (discontinuous conduction) or PWM (continuous conduction) operation at light load. PFM provides high efficiency by reducing switching losses at light loads and PWM reduces noise susceptibility and RF interference. Applications • General purpose point of load DC/DC • Set-top boxes and cable modems These devices are offered in a space saving 8 pin 2mmx2mm TDFN lead free package with exposed pad for improved thermal performance. The complete converter occupies less than 0.10in2 area. • FPGA power • DVD, HDD drives, LCD panels, TV Related Literature • See AN1803, “1.5A/2A Low Quiescent Current High Efficiency Synchronous Buck Regulator” VIN GND EN PG C1 22μF 2 3 4 PHASE 8 VIN PGND EN FB MODE PG COMP PAD L1 1.2μH 100 +1.8V/2A C5 22μF VOUT C6 22μF R1 6 +0.6V 200kΩ 1% 5 R2 100kΩ 1% 9 80 70 60 50 VO R 1 = R 2 ⎛ ----------- – 1⎞ ⎝ VFB ⎠ (EQ. 1) FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION (INTERNAL COMPENSATION OPTION) January 7, 2013 FN7888.1 90 GND 7 EFFICIENCY (%) ISL8002 +2.7V …+5.5V 1 1 40 0.0 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0.9VOUT 0.8VOUT 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT LOAD (A) 1.6 1.8 2.0 FIGURE 2. EFFICIENCY vs LOAD FSW = 1MHz, VIN = 3.3V, MODE = PFM, TA = +25°C CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL8002, ISL8002A, ISL80019, ISL80019A Table of Contents Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Load Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PFM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Short-Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 UVLO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Enable, Disable, and Soft Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 100% Duty Cycle (1MHz Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A TABLE 1. SUMMARY OF KEY DIFFERENCES PART# IOUT (MAX) (A) FSW (MHz) ISL80019 1.5 1 ISL80019A 1.5 2 ISL8002 2 1 ISL8002A 2 2 VIN RANGE (V) VOUT RANGE (V) PACKAGE SIZE 2.7 to 5.5 0.6 to 5.5 8 pin 2mmx2mm TDFN NOTE: In this datasheet, the parts in the table above are collectively called "device". TABLE 2. COMPONENT VALUE SELECTION TABLE VOUT (V) C1 (µF) C5, C6 (µF) C4 (pF) L1 (µH) R1 (kΩ) R2 (kΩ) 0.8 22 22 22 1.0~2.2 33 100 1.2 22 22 22 1.0~2.2 100 100 1.5 22 22 22 1.0~2.2 150 100 1.8 22 22 22 1.0~3.3 200 100 2.5 22 22 22 1.5~3.3 316 100 3.3 22 22 22 1.5~4.7 450 100 3 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Pin Configuration ISL8002, ISL8002A, ISL80019, ISL80019A (8 LD 2x2 TDFN) TOP VIEW VIN 1 EN 2 MODE 3 PG 4 THERMAL PAD (GND) PAD PIN 9 8 PHASE 7 PGND 6 FB 5 COMP Pin Descriptions PIN NUMBER SYMBOL PIN DESCRIPTION 1 VIN The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides bias for the IC. Place a minimum of 10µF ceramic capacitance from VIN to GND and as close as possible to the IC for decoupling. 2 EN Device enable input. When the voltage on this pin rises above 0.6V, the device is enabled. The device is disabled when the pin is pulled to ground. When the device is disabled, a 100Ω resistor discharges the output through the PHASE pin. See Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5 for details. 3 MODE Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM mode. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case the MODE pin is left floating, however, it is not recommended to leave this pin floating. 4 PG Power Good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation limits. There is an internal 5MΩ internal pull-up resistor on this pin. 5 COMP COMP is the output of the error amplifier. When COMP is tied high to VIN, compensation is internal. When COMP is connected with a series resistor and capacitor to GND, compensation is external. See “Loop Compensation Design” on page 19 for more detail. 6 FB Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. The output voltage is set by an external resistor divider connected to FB. In addition, the Power Good PWM regulator’s power-good and Undervoltage protection circuits use FB to monitor the output voltage. 7 PGND Power and analog ground connections. Connect directly to the board GROUND plane. 8 PHASE Power stage switching node for output voltage regulation. Connect to the output inductor. This pin is discharged by an 100Ω resistor when the device is disabled. See Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5 for details. 9 THERMAL PAD Power ground. This thermal pad provides a return path for the power stage and switching currents, as well as a thermal (T-PAD) path for removing heat from the IC to the board. Place thermal vias to the PGND plane in this pad. 4 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Functional Block Diagram COMP MODE 27pF SOFTSoft START * SHUTDOWN 200kΩ + VREF BANDGAP VIN OSCILLATOR + EN + EAMP COMP - - P PWM/PFM LOGIC CONTROLLER PROTECTION SHUTDOWN 3pF PHASE N HS DRIVER + PGND FB SLOPE Slope COMP 1.15*VREF 6kΩ + - CSA OV + + OCP - 0.85*VREF + UV + VIN SKIP 5MΩ PG 1ms DELAY - NEG CURRENT SENSING ZERO-CROSS SENSING 0.3V SCP + 100Ω SHUTDOWN * By default, when COMP is tied to VIN, the voltage loop is internally compensated with the 27pF and 200kΩ RC network. Please see "COMP" pin in the “Pin Descriptions” table on page 4 for more details. FIGURE 3. FUNCTIONAL BLOCK DIAGRAM 5 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Ordering Information PART NUMBER (Notes 1, 2, 3) TAPE AND REEL QUANTITY PART MARKING TECHNICAL SPECIFICATIONS TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL8002IRZ-T 1000 002 2A, 1MHz -40 to +85 8 Ld TDFN L8.2x2C ISL8002IRZ-T7A 250 002 2A, 1MHz -40 to +85 8 Ld TDFN L8.2x2C ISL8002AIRZ-T 1000 02A 2A, 2MHz -40 to +85 8 Ld TDFN L8.2x2C ISL8002AIRZ-T7A 250 02A 2A, 2MHz -40 to +85 8 Ld TDFN L8.2x2C ISL80019IRZ-T 1000 019 1.5A, 1MHz -40 to +85 8 Ld TDFN L8.2x2C ISL80019IRZ-T7A 250 019 1.5A, 1MHz -40 to +85 8 Ld TDFN L8.2x2C ISL80019AIRZ-T 1000 19A 1.5A, 2MHz -40 to +85 8 Ld TDFN L8.2x2C ISL80019AIRZ-T7A 250 19A 1.5A, 2MHz -40 to +85 8 Ld TDFN L8.2x2C NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8002, ISL8002A, ISL80019, ISL80019A. For more information on MSL please see techbrief TB363. 6 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Absolute Maximum Ratings Thermal Information VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms) PHASE . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6V (DC) or 7V (20ms) EN, COMP, PG, MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V Thermal Resistance (Typical, Notes 4, 5) θJA (°C/W) θJC (°C/W) 2x2 TDFN Package . . . . . . . . . . . . . . . . . . . 71 7 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications TA = -40°C to +85°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS 2.5 2.7 V INPUT SUPPLY VIN Undervoltage Lockout Threshold VUVLO Rising, no load Falling, no load Quiescent Supply Current IVIN Shut Down Supply Current ISD 2.2 2.4 V MODE = PFM (GND), FSW = 2MHz, no load at the output 35 60 µA MODE = PWM (VIN), FSW = 1MHz, no load at the output 7 15 mA MODE = PWM (VIN), FSW = 2MHz, no load at the output 10 22 mA MODE = PFM (GND), VIN = 5.5V, EN = low 5 10 µA 0.600 0.605 V OUTPUT REGULATION Reference Voltage VREF VFB Bias Current IVFB Line Regulation 0.595 VFB = 0.75V 0.1 µA VIN = VO + 0.5V to 5.5V (minimal 2.7V) 0.2 %/V 1 ms Soft-Start Ramp Time Cycle PROTECTIONS Positive Peak Current Limit IPLIMIT 2A application 1.5A application Peak Skip Limit ISKIP 3.5 4 A 2.1 2.5 2.9 A VIN = 3.6, VOUT = 1.8V (See “Applications Information” on page 18 for more detail) Zero Cross Threshold Negative Current Limit 3 INLIMIT 450 mA -170 -70 30 mA -2.3 -1.5 -1 A Thermal Shutdown Temperature rising 150 °C Thermal Shutdown Hysteresis Temperature falling 25 °C 7 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Electrical Specifications TA = -40°C to +85°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS COMPENSATION Error Amplifier Trans-Conductance Trans-Resistance COMP tied VIN 40 µA/V COMP with RC 120 µA/V RT 0.24 0.3 0.40 Ω LX P-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA 117 mΩ N-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA 86 mΩ 100 % LX Maximum Duty Cycle LX Minimum On-Time MODE = PWM (High) 1MHz 60 80 ns OSCILLATOR Nominal Switching Frequency FSW ISL8002, ISL80019 850 1000 1150 kHz ISL8002A, ISL80019A 1700 2000 2300 kHz 0.3 V 2 ms PG Output Low Voltage 1mA sinking current Delay Time (Rising Edge) 0.5 PGOOD Delay Time (Falling Edge) 1 15 PG Pin Leakage Current PG = VIN OVP PG Rising Threshold 110 OVP PG Hysteresis µs 0.01 0.1 µA 115 120 % 5 UVP PG Rising Threshold 80 UVP PG Hysteresis 85 % 90 5 % % EN AND MODE LOGIC Logic Input Low 0.4 Logic Input High 1.4 Logic Input Leakage Current IMODE Pulled up to 5.5V V V 5.5 8 µA NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A 100 100 90 90 80 80 EFFICIENCY (%) EFFICIENCY (%) Typical Performance Curves 70 60 50 40 0.0 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0.9VOUT 0.8VOUT 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT LOAD (A) 1.4 1.6 1.8 40 0.0 2.0 90 90 80 80 EFFICIENCY (%) EFFICIENCY (%) 100 70 50 40 0.0 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0.9VOUT 0.8VOUT 0.2 0.4 0.8 1.0 1.2 OUTPUT LOAD (A) 1.4 1.6 1.8 60 40 0.0 2.0 100 90 90 80 80 EFFICIENCY (%) 100 70 50 40 0.0 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0.9VOUT 0.2 0.4 0.8 1.0 1.2 OUTPUT LOAD (A) 1.4 1.6 1.8 FIGURE 8. EFFICIENCY vs LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C 9 0.8 1.0 1.2 OUTPUT LOAD (A) 1.4 1.6 1.8 2.0 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0.9VOUT 0.8VOUT 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT LOAD (A) 1.4 1.6 1.8 2.0 70 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0.9VOUT 60 50 0.6 0.6 FIGURE 7. EFFICIENCY vs LOAD FSW = 1MHz, VIN = 3.3V, MODE = PWM, TA = +25°C FIGURE 6. EFFICIENCY vs LOAD FSW = 1MHz, VIN = 3.3V, MODE = PFM, TA = +25°C 60 0.4 70 50 0.6 0.2 FIGURE 5. EFFICIENCY vs LOAD FSW = 2MHz, VIN = 3.3V, MODE = PWM, TA = +25°C 100 60 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0.9VOUT 0.8VOUT 60 50 FIGURE 4. EFFICIENCY vs LOAD FSW = 2MHz, VIN = 3.3V, MODE = PFM, TA = +25°C EFFICIENCY (%) 70 2.0 40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT LOAD (A) 1.4 1.6 1.8 2.0 FIGURE 9. EFFICIENCY vs LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A (Continued) 100 100 90 90 80 80 70 60 50 40 0.0 EFFICIENCY (%) EFFICIENCY (%) Typical Performance Curves 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0.9VOUT 0.8VOUT 0.2 0.4 70 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0.9VOUT 0.8VOUT 60 50 0.6 0.8 1.0 1.2 1.4 1.6 1.8 40 0.0 2.0 0.2 0.4 0.6 OUTPUT LOAD (A) 1.6 1.8 FIGURE 11. EFFICIENCY vs LOAD FSW = 1MHz, VIN = 5V, MODE = PWM, TA = +25°C 0.925 1.230 5VIN PFM 5VIN PWM 3.3VIN PWM 3.3VIN PFM 0.915 0.910 0.905 0.900 0.895 0.0 1.220 1.215 1.210 1.205 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT LOAD (A) 1.4 1.6 1.8 1.200 0.0 2.0 FIGURE 12. VOUT REGULATION vs LOAD, FSW = 2MHz, VOUT = 0.9V, TA = +25°C 0.6 0.8 1.0 1.2 OUTPUT LOAD (A) 1.4 1.6 1.8 2.0 5VIN PFM 5VIN PWM 3.3VIN PWM 3.3VIN PFM 1.805 OUTPUT VOLTAGE (V) 1.510 0.4 1.810 5VIN PFM 5VIN PWM 3.3VIN PWM 3.3VIN PFM 1.515 0.2 FIGURE 13. VOUT REGULATION vs LOAD, FSW = 2MHz, VOUT = 1.2V, TA = +25°C 1.520 1.505 1.500 1.800 1.795 1.790 1.785 1.495 1.490 0.0 2.0 5VIN PFM 5VIN PWM 3.3VIN PWM 3.3VIN PFM 1.225 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.4 FIGURE 10. EFFICIENCY vs LOAD FSW = 1MHz, VIN = 5V, MODE = PFM, TA = +25°C 0.920 OUTPUT VOLTAGE (V) 0.8 1.0 1.2 OUTPUT LOAD (A) 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT LOAD (A) 1.4 FIGURE 14. VOUT REGULATION vs LOAD, FSW = 2MHz, VOUT = 1.5V, TA = +25°C 10 1.6 1.8 2.0 1.780 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT LOAD (A) FIGURE 15. VOUT REGULATION vs LOAD, FSW = 2MHz, VOUT = 1.8V, TA = +25°C FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) 3.335 2.505 OUTPUT VOLTAGE (V) 2.500 2.495 2.490 2.485 3.325 3.320 3.315 3.310 2.480 2.475 0.0 5VIN PFM MODE 5VIN PWM MODE 3.330 OUTPUT VOLTAGE (V) 5VIN PFM 5VIN PWM 3.3VIN PWM 3.3VIN PFM 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT LOAD (A) FIGURE 16. VOUT REGULATION vs LOAD, FSW = 2MHz, VOUT = 2.5V, TA = +25°C 3.305 0.0 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT LOAD (A) 1.4 1.6 1.8 2.0 FIGURE 17. VOUT REGULATION vs LOAD, FSW = 2MHz, VOUT = 3.3V, TA = +25°C LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 1V/DIV VEN 2V/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 18. START-UP AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 2V/DIV VEN 2V/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV FIGURE 20. SHUTDOWN AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C 11 FIGURE 19. START-UP AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C 1ms/DIV FIGURE 21. SHUTDOWN AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 2V/DIV PG 5V/DIV VEN 2V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 22. START-UP AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C FIGURE 23. SHUTDOWN AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 2V/DIV PG 5V/DIV VEN 2V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 24. START-UP AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C FIGURE 25. SHUTDOWN AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C VEN 5V/DIV VEN 5V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV PG 5V/DIV IL 1A/DIV PG 5V/DIV 1ms/DIV FIGURE 26. START-UP AT 1.5A LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C 12 1ms/DIV FIGURE 27. SHUTDOWN AT 1.5A LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) VEN 5V/DIV VEN 5V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV PLACEHOLDER PG 5V/DIV IL 1A/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 28. START-UP AT 1.5A LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C FIGURE 29. SHUTDOWN AT 1.5A LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C VIN 5V/DIV VIN 5V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 1A/DIV PG 5V/DIV PG 5V/DIV 500µs/DIV 500µs/DIV FIGURE 30. START-UP VIN AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C FIGURE 31. START-UP VIN AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C VIN 5V/DIV VIN 5V/DIV IL 1A/DIV IL 1A/DIV VOUT 1V/DIV VOUT 1V/DIV PG 5V/DIV 1ms/DIV FIGURE 32. SHUTDOWN VIN AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C 13 PG 5V/DIV 1ms/DIV FIGURE 33. SHUTDOWN VIN AT 2A LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VIN 5V/DIV VIN 5V/DIV PG 5V/DIV PG 5V/DIV 500µs/DIV 500µs/DIV FIGURE 34. START-UP VIN AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C FIGURE 35. START-UP VIN AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VIN 5V/DIV VIN 5V/DIV PG 5V/DIV PG 5V/DIV 100ms/DIV 50ms/DIV FIGURE 36. SHUTDOWN VIN AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C FIGURE 37. SHUTDOWN VIN AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C LX 1V/DIV 10ns/DIV FIGURE 38. JITTER AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C 14 LX 1V/DIV 10ns/DIV FIGURE 39. JITTER AT FULL LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) LX 5V/DIV LX 5V/DIV VOUT 20mV/DIV VOUT 10mV/DIV IL 0.5A/DIV IL 0.5A/DIV 50ms/DIV 500ns/DIV FIGURE 40. STEADY STATE AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C FIGURE 41. STEADY STATE AT NO LOAD FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C VOUT RIPPLE 50mV/DIV VOUT RIPPLE 50mV/DIV IL 1A/DIV 200µs/DIV IL 1A/DIV 200µs/DIV FIGURE 42. LOAD TRANSIENT FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C FIGURE 43. LOAD TRANSIENT FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C LX 5V/DIV VOUT 0.5V/DIV IL 1A/DIV IL 2A/DIV VOUT 1V/DIV PG 5V/DIV PG 5V/DIV 5µs/DIV FIGURE 44. OUTPUT SHORT-CIRCUIT FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C 15 500µs/DIV FIGURE 45. OVERCURRENT PROTECTION FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Typical Performance Curves (Continued) LX 5V/DIV LX 5V/DIV 675mA MODE TRANSITION, COMPLETELY ENTER TO PWM AT 770mA BACK TO PFM AT 121mA VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV IL 2A/DIV IL 1A/DIV 2µs/DIV 2µs/DIV FIGURE 46. PFM TO PWM TRANSITION FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C FIGURE 47. PWM TO PFM TRANSITION FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C LX 5V/DIV IL 2A/DIV VOUT 0.5V/DIV VOUT 2V/DIV PG 2V/DIV PG 5V/DIV 10µs/DIV FIGURE 48. OVERVOLTAGE PROTECTION FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C 16 1ms/DIV FIGURE 49. OVER-TEMPERATURE PROTECTION FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +163°C FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Theory of Operation VEAMP The device is a step-down switching regulator optimized for battery powered applications. It operates at high switching frequency (1MHz or 2MHz) which enables the use of smaller inductors resulting in small form factor, while also providing excellent efficiency. Further, at light loads while in PFM mode, the regulator reduces the switching frequency, thereby minimizing the switching loss and maximizing battery life. The quiescent current when the output is not loaded is typically only 35µA. The supply current is typically only 5µA when the regulator is shut down. VCSA DUTY CYCLE IL VOUT PWM Control Scheme Pulling the MODE pin HI (>2.5V) forces the converter into PWM mode, regardless of output current. The device employs the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Page 5 shows the “Functional Block Diagram”. The current loop consists of the oscillator, the PWM comparator, current sensing circuit and the slope compensation for the current loop stability. The slope compensation is 900mV/Ts, which changes with frequency. The gain for the current sensing circuit is typically 300mV/A. The control reference for the current loops comes from the error amplifier's (EAMP) output. FIGURE 50. PWM OPERATION WAVEFORMS The output voltage is regulated by controlling the VEAMP voltage to the current loop. The bandgap circuit outputs a 0.6V reference voltage to the voltage loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated with the 27pF and 200kΩ RC network. The maximum EAMP voltage output is precisely clamped to 1.6V. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA and the slope compensation reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-FET and turn on the N-Channel MOSFET. The N-FET stays on until the end of the PWM cycle. Figure 50 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier’s CSA output. PWM PFM Mode Pulling the MODE pin LO (<0.4V) forces the converter into PFM mode. The device enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 51 illustrates the skip-mode operation. A zero-cross sensing circuit shown in Figure 51 monitors the N-FET current for zero crossing. When 16 consecutive cycles of the inductor current crossing zero are detected, the regulator enters the skip mode. During the eight detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. PFM PWM CLOCK 16 CYCLES IL PFM CURRENT LIMIT LOAD CURRENT 0 NOMINAL +1.5% VOUT NOMINAL NOMINAL -1.5% FIGURE 51. SKIP MODE OPERATION WAVEFORMS 17 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Once the skip mode is entered, the pulse modulation starts being controlled by the SKIP comparator shown in the “Functional Block Diagram” on page 5. Each pulse cycle is still synchronized by the PWM clock. The P-FET is turned on at the clock's rising edge and turned off when the output is higher than 1.5% of the nominal regulation or when its current reaches the peak Skip current limit value. Then the inductor current is discharging to 0A and stays at zero. The internal clock is disabled. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-FET will be turned on again at the rising edge of the internal clock as it repeats the previous operations. The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage. Overcurrent Protection The overcurrent protection is realized by monitoring the CSA output with the OCP comparator, as shown in the “Functional Block Diagram” on page 5. The current sensing circuit has a gain of 300mV/A, from the P-FET current to the CSA output. When the CSA output reaches a threshold, the OCP comparator is tripped to turn off the P-FET immediately. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFET. Upon detection of overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. If the overcurrent condition goes away, the output will resume back into regulation point after the hiccup mode expires. Short-Circuit Protection The short-circuit protection (SCP) comparator monitors the VFB pin voltage for output short-circuit protection. When the VFB is lower than 0.3V, the SCP comparator forces the PWM oscillator frequency to drop to 1/3 of the normal operation value. This comparator is effective during start-up or an output short-circuit event. Negative Current Protection Similar to the overcurrent, the negative current protection is realized by monitoring the current across the lowside N-FET, as shown in the “Functional Block Diagram” on page 5. When the valley point of the inductor current reaches -1.5A for 2 consecutive cycles, both P-FET and N-FET shut off. The 100Ω in parallel to the N-FET will activate discharging the output into regulation. The control will begin to switch when output is within regulation. The regulator will be in PFM for 20µs before switching to PWM if necessary. PG PG is an output of a window comparator that continuously monitors the buck regulator output voltage. PG is actively held low when EN is low and during the buck regulator soft-start period. After 1ms delay of the soft-start period, PG becomes high impedance as long as the output voltage is within nominal regulation voltage set by VFB. When VFB drops 15% below or raises 15% above the nominal regulation voltage, the device pulls PG low. Any fault condition forces PG low until the fault condition is cleared by attempts to soft-start. There is an internal 5MΩ pull-up resistor to fit most applications. An 18 external resistor can be added from PG to VIN for more pull-up strength. UVLO When the input voltage is below the undervoltage lock-out (UVLO) threshold, the regulator is disabled. Enable, Disable, and Soft Start-Up After the VIN pin exceeds its rising POR trip point (nominal 2.7V), the device begins operation. If the EN pin is held low externally, nothing happens until this pin is released. Once the EN is released and above the logic threshold, the internal default soft-start time is 1ms. Discharge Mode (Soft-Stop) When a transition to shutdown mode occurs or the VIN UVLO is set, the outputs discharge to GND through an internal 100Ω switch. 100% Duty Cycle (1MHz Version) The device features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the device can no longer maintain the regulation at the output, the regulator completely turns on the P-FET. The maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the ON-resistance of the P-FET. Thermal Shut-Down The device has built-in thermal protection. When the internal temperature reaches +150°C, the regulator is completely shut down. As the temperature drops to +125°C, the device resumes operation by stepping through the soft-start. Applications Information Output Inductor and Capacitor Selection To consider steady state and transient operations, ISL8002A/ISL80019A typically requires a 1.2µH and ISL8002/ISL80019 typically requires a 2.2µH output inductor. Higher or lower inductor value can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V application, in order to decrease the inductor ripple current and output voltage ripple, the output inductor value can be increased. It is recommended to set the inductor ripple current to be approximately 30% of the maximum output current for optimized performance. The inductor ripple current can be expressed as shown in Equation 2: VO ⎞ ⎛ V O • ⎜ 1 – --------⎟ V IN⎠ ⎝ ΔI = --------------------------------------L • F SW (EQ. 2) The inductor’s saturation current rating needs to be at least larger than the peak current. The device uses internal compensation network and the output capacitor value is dependent on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Output Voltage Selection If using electrolytic capacitors then: The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. Refer to Figure 35. V OUTripple = ΔI*ESR VO R 1 = R 2 ⎛ ----------- – 1⎞ ⎝ VFB ⎠ (EQ. 3) If the output voltage desired is 0.6V, then R2 is left unpopulated and R1 is shorted. There is a leakage current from VIN to LX. It is recommended to preload the output with 10µA minimum. For better performance, add 22pF in parallel with R1. Check loop analysis before use in application. Input Capacitor Selection The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. At least two 22µF X5R or X7R ceramic capacitors are a good starting point for the input capacitor selection. Output Capacitor Selection An output capacitor is required to filter the inductor current. Output ripple voltage and transient response are 2 critical factors when considering output capacitance choice. The current mode control loop allows for the usage of low ESR ceramic capacitors and thus smaller board layout. Electrolytic and polymer capacitors may also be used. The following equations allow calculation of the required capacitance to meet a desired ripple voltage level. Additional capacitance may be used. For the ceramic capacitors (low ESR) = ΔI V OUTripple = --------------------------------------8∗ F SW∗ C OUT (EQ. 4) I OUT 2 * L C OUT = -------------------------------------------------------------------------------------------V OUT 2 * ( V OUTMAX ⁄ V OUT ) 2 – 1 ) (EQ. 6) where VOUTMAX/VOUT is the relative maximum overshoot allowed during the removal of the load. For an overshoot of 5%, the equation becomes as follows: I OUT 2 * L C OUT = ---------------------------------------------------V OUT 2 * ( 1.05 2 – 1 ) (EQ. 7) Loop Compensation Design When COMP is not connected to VDD, the COMP pin is active for external loop compensation. The ISL8002, ISL8002A, ISL80019, and ISL80019A use constant frequency peak current mode control architecture to achieve fast loop transient response. An accurate current sensing pilot device in parallel with the upper MOSFET is used for peak current control signal and overcurrent protection. The inductor is not considered as a state variable since its peak current is constant, and the system becomes a single order system. It is much easier to design a type II compensator to stabilize the loop than to implement voltage mode control. Peak current mode control has an inherent input voltage feed-forward function to achieve good line regulation. Figure 52 shows the small signal model of the synchronous buck regulator. ^ i in ^ Vin + Additional consideration applies to ceramic capacitors. While they offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. Ceramic capacitors are rated using large peak-to-peak voltage swings and with no DC bias. In the DC/DC converter application, these conditions do not reflect reality. As a result, the actual capacitance may be considerably lower than the advertised value. Consult the manufacturers data sheet to determine the actual in-application capacitance. Most manufacturers publish capacitance vs DC bias so that this effect can be easily accommodated. The effects of AC voltage are not frequently published, but an assumption of ~20% further reduction will generally suffice. The result of these considerations can easily result in an effective capacitance 50% lower than the rated value. Nonetheless, they are a very good choice in many applications due to their reliability and extremely low ESR. Regarding transient response needs, a good starting point is to determine the allowable overshoot in VOUT if the load is suddenly removed. In this case, energy stored in the inductor will be transferred to COUT causing its voltage to rise. After calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. The following equation determines the required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. ILd^ 1:D ^ iL LP ^ vo RLP Vin d^ + GAIN (VLOOP (S(fi)) The output voltage programming resistor, R2, will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. The value for the feedback resistor is typically between 10kΩ and 100kΩ, as shown in Equation 3. (EQ. 5) RT Rc Ro Co T i(S) d^ K Fm + Tv (S) He(S) v^comp -Av(S) FIGURE 52. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR where ΔI is the inductor’s peak to peak ripple current, FSW is the switching frequency and COUT is the output capacitor. 19 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Put compensator zero 2 to 5 times fc: VOUT R1 1 C 4 = ---------------πf c R 1 C4 VFB VREF R2 - (EQ. 12) Example: VIN = 5V, VOUT = 1.8V, IO = 2A, FSW = 1MHz, R1 = 200kΩ, R2 = 100kΩ, COUT = 2x22µF/3mΩ, L = 2.2µH, fc = 100kHz, then compensator resistance R14: VCOMP GM + 3 (EQ. 13) R 14 = 26 ×10 ⋅ 100kHz ⋅ 1.8V ⋅ 44μF = 205kΩ R14 C8 Using the closest standard value for R14 value is fine (200kΩ). C7 1.8V ⋅ 44 μF C 7 = -------------------------------- = 198pF 2A ⋅ 200kΩ (EQ. 14) 3mΩ ⋅ 44μF 1 C 8 = max (---------------------------------,------------------------------------------------) = (1pF,2.3pF) 200kΩ π ⋅ 1MHz ( 200kΩ ) (EQ. 15) FIGURE 53. TYPE II COMPENSATOR Figure 53 shows the type II compensator and its transfer function is expressed as Equation 8: S ⎞⎛ S ⎛ 1 + ------------ 1 + -------------⎞ ⎝ GM ⋅ R 2 ω cz1⎠ ⎝ ω cz2⎠ vˆ comp - = -------------------------------------------------------- --------------------------------------------------------------A v ( S ) = ---------------( C7 + C8 ) ⋅ ( R1 + R2 ) ⎛ S S vˆ FB S 1 + -------------⎞ ⎛ 1 + -------------⎞ ⎝ ω cp2⎠ ω cp1⎠ ⎝ (EQ. 8) where, C7 + C8 R1 + R2 1 1 ω cz1 = ------------------ , ω cz2 = ---------------, ω cp1 = --------------------------, ω cp2 = ---------------------R 14 C 7 C 8 R 14 C 7 C4 R1 R2 R1 C4 The closest standard values for C7 and C8 are also fine. There is approximately 3pF parasitic capacitance from VCOMP to GND; Therefore, C8 is optional. Use C7 = 220pF and C8 = OPEN. 1 C 4 = ------------------------------------------------ = 16pF π100kHz ⋅ 200kΩ (EQ. 16) Use C4 = 15pF. Note that C4 may increase the loop bandwidth from previously estimated value. Figure 54 shows the simulated voltage loop gain. It is shown that it has 114kHz loop bandwidth with 52° phase margin and 10dB gain margin. It may be more desirable to achieve more phase margin. This can be accomplished by lowering R14 by 20% to 50%. 60 COMPENSATOR DESIGN GOAL 45 • High DC gain • Choose Loop bandwidth fc less than 100kHz 30 GAIN (dB) • Gain margin: >10dB • Phase margin: >50° The compensator design procedure is as follows: The loop gain at crossover frequency of fc has unity gain. Therefore, the compensator resistance R14 is determined by Equation 9. 2πf c V o C o R t 3 - = 26 ×10 ⋅ f c V o C o R 14 = --------------------------------GM ⋅ V FB -30 100 (EQ. 9) 10k 100k 1M 100k 1M 180 150 (EQ. 11) An optional zero can boost the phase margin. ωCZ2 is a zero due to R1 and C4. 120 PHASE (°) (EQ. 10) Rc Co 1 C 8 = max (--------------,-------------------) R 14 πf s R 14 1k FREQUENCY (Hz) Compensator capacitors C7 and C8 are then given by Equations 10 and 11. Vo Co -------------I o R 14 0 -15 Where GM is the trans-conductance of the voltage error amplifier. Ro Co C 7 = --------------- = R 14 15 90 60 30 0 100 1k 10k FREQUENCY (Hz) FIGURE 54. SIMULATED LOOP GAIN 20 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Layout Considerations The PCB layout is a very important converter design step to make sure the designed converter works well. The power loop is composed of the output inductor L’s, the output capacitor COUT, the PHASE’s pins, and the PGND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. The switching node of the converter, the PHASE pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. The input capacitor should be placed as closely as possible to the VIN pin and the ground of the input and output capacitors should be connected as closely as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for better EMI performance. It is recommended to add at least 4 vias ground connection within the pad for the best thermal relief. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE January 7, 2013 REVISION CHANGE FN7888.1 Initial release. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page. Also, please check the product information page to ensure that you have the most updated datasheet: ISL8002, ISL8002A, ISL80019, ISL80019A To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. 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For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN7888.1 January 7, 2013 ISL8002, ISL8002A, ISL80019, ISL80019A Package Outline Drawing L8.2x2C 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) WITH E-PAD Rev 0, 07/08 2.00 6 PIN #1 INDEX AREA A B 6 PIN 1 INDEX AREA 8 1 0.50 2.00 1.45±0.050 Exp.DAP (4X) 0.15 0.10 M C A B 0.25 ( 8x0.30 ) TOP VIEW 0.80±0.050 Exp.DAP BOTTOM VIEW ( 8x0.20 ) Package Outline ( 8x0.30 ) SEE DETAIL "X" ( 6x0.50 ) 1.45 2.00 0.10 C 0 . 75 ( 0 . 80 max) C BASE PLANE SEATING PLANE 0.08 C SIDE VIEW ( 8x0.25 ) 0.80 2.00 TYPICAL RECOMMENDED LAND PATTERN C 0 . 2 REF 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 22 FN7888.1 January 7, 2013