A3904 Datasheet

A3904
Low Voltage Voice Coil Motor Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: March 4, 2013
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A3904
Low Voltage Voice Coil Motor Driver
Features and Benefits
Description
▪ Fixed I2C logic thresholds
▪ 8-bit D-to-A converter
▪ 500 μA resolution
▪ Low voltage I2C serial interface
▪ Low current-draw sleep mode
▪ 2.4 to 5.5 V operation
▪ 1.1 mm × 0.7 mm, 0.5 mm maximum overall height WLCSP
The A3904 is a voice coil motor (VCM) driver, with an
I2C-compatible serial interface. Designed for camera autofocus
and zoom applications, this high accuracy digital IC is provided
in a WLCSP package ideal for portable devices. Its operating
voltage range is 2.4 to 5.5 V, and its maximum output current
is 127 mA.
Output current is programmed via the I2C interface, in 500 uA
increments, with clock rates up to 400 kHz. I2C inputs set the
internal D-to-A converter output voltage that is the reference
for linear current control via a MOSFET output sink transistor.
To conserve battery power, a logic low signal on the SLEEPZ
input disables the output MOSFET and reduces the supply
current to <0.5 μA.
Package: 6-ball wafer-level chip scale
package (CG)
A3904 internal protection features include thermal shutdown
and undervoltage lockout. Logic input levels are independent
of the supply voltage. The operating temperature range is
–40°C to 85°C.
The A3904 is available in a bumped wafer level chip scale
package (WLCSP) (suffix CG).
1.1 mm × 0.7 mm
Not to scale
Functional Block Diagram
2.4 to 5.5 V
1.8 V
VDD
1.8 kΩ
1.8 kΩ
I2C
Master
Bandgap
Ref
SDA
SCL
I2C
IOUT
8 Bit DAC
I2C Serial
Interface
2.4 Ω
GND
SLEEPZ
Slave
PAD
EW only
3904-DS, Rev. 4
A3904
Low Voltage Voice Coil Motor Driver
Selection Guide
Part Number
Packing
A3904ECGTR
Package
Pb-Free
Bumped wafer-level chip-scale
package (WLCSP)
4000 pieces per reel
Pb-free chip with high-temperature solder balls
(RoHS compliant)
Absolute Maximum Ratings
Characteristic
Symbol
Supply Voltage
VDD
Logic Input Voltage Range
VIN
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
Pin-out Diagram
CG Package
A1
A2
A3
B1
B2
B3
Orientation mark
on bump side
Notes
Rating
Units
6
V
–0.3 to VDD+0.3
V
–40 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Range E
Terminal List
Number
Name
A1
SDA
I2C data input/output
Description
A2
SCL
I2C clock
A3
VDD
Power supply
B3
GND
Ground
B2
IOUT
B1
SLEEPZ
Sink drive output
Standby mode control
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3904
Low Voltage Voice Coil Motor Driver
ELECTRICAL CHARACTERISTICS Valid at TA= 25°C, VDD = 2.4 to 5.5 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
General
Supply Current
IDD
UVLO Enable Threshold
VUV(th)
UVLO Hysteresis
VUV(hys)
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Power-Up Delay
TJTSD
.TJTSD(hys)
–
0.5
2
mA
Sleep mode (SLEEPZ = Low)
–
<100
500
nA
VDD rising
–
2.1
2.395
V
100
–
–
mV
Temperature increasing
–
165
–
°C
TJTSD(hys) = TJTSD – TJ(recover)
–
15
–
°C
–
10
–
μs
td(on)
D-to-A Converter
Resolution
Res
Target = 500 μA / LSB
–
8
–
bit
LSB Relative Accuracy
INL
Code = 16 to 255, Endpoint method
–
±4
–
LSB
LSB Differential Nonlinearity
DNL
Guaranteed monotonic
–
–
±1
LSB
Maximum Output Current
Imax
Code = 255
–
127.5
–
mA
errA
TJ = 25°C, Code 16 to 255,
VDD = 2.6 to 3.0 V
–10
<3
10
%FS
TJ = –40°C to 125°C
–
0.2
–
LSB/°C
Code = 1
0
1
5
mA
Code = 16
0.5
–
–
mA
0.500
–
VDD–0.1
V
–
3
–
Ω
Gain Error
Gain Error Drift*
Offset Error
∆errA
IerrOS
Output
Output Voltage Range
VOUT
Output On Resistance
RDS(on)
RSENSE + RSINK, IOUT = 127.5 mA
I2C Interface
tBUF
1.3
–
–
μs
Hold Time Start Condition
Bus Free Time Between Stop and Start
thdSTA
0.6
–
–
μs
Setup Time for Repeated Start Condition
tsuSTA
0.6
–
–
μs
SCL Low Time
tLOW
1.3
–
–
μs
SCL High Time
tHIGH
0.6
–
–
μs
Data Setup Time
tsuDAT
100
–
–
ns
Data Hold Time
thdDAT
0
Setup Time for Stop Condition
tsuSTO
0.6
900
ns
–
–
μs
Logic Input Low Level (SDA, SCL pins)
VIL
–
–
0.84
V
Logic Input High Level (SDA, SCL pins)
VIH
1.26
–
–
V
Input Hysteresis (SDA, SCL pins)
Vhys
–
100
–
mV
V
SLEEPZ Input Low Level
VinSLP
–
–
0.7
SLEEPZ Input High Level
VinSLP
1.5
–
–
V
–1
0
1
μA
Logic Input Current
IIN
VIN = 0 V to VDD
ILOAD = 1.5 mA
Output Voltage (SDA pin)
VOL
Clock Frequency (SCL pin)
fCLK
Output Fall Time (SDA pin)
tfO
VIH to VIL
–
–
0.36
V
–
–
400
kHz
–
–
250
ns
*Guaranteed by design and characterization, not production tested
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3904
Low Voltage Voice Coil Motor Driver
I2C Interface Timing Diagram
tsuSTA thdSTA
tsuDAT
thdDAT
tsuSTO
tBUF
SDA
SCL
tLOW
tHIGH
Write Register Bit Definition and Timing Diagram
Acknowledge
(from A3904)
Acknowledge
(from A3904)
Write
Start
Address
Stop
Control Data
SDA
0
0
0
1
1
x
x
0
AK
SCL
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
AK
I2C Control Register Bit Definition
Bit
Name
Function
0
D0
DAC LSB
1
D1
2
D2
3
D3
4
D4
5
D5
6
D6
7
D7
DAC MSB
A3904 Slave Address Bit Definition
Bit
0
1
2
3
4
5
6
0
0
0
1
1
x
X
7
Operation
1
Read
0
Write
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3904
Low Voltage Voice Coil Motor Driver
Functional Description
The A3904 output current is controlled by programming the D-toA converter value via the I2C serial port. The target output current
can be calculated by:
IOUT = DAC × 500 μA ,
where DAC = 1 to 255. Code = 0 is a disable state for the output
sink drive. The DAC will be set to code = 0 upon power-up or a
fault condition on VDD.
SLEEPZ A logic low input disables all of the internal circuitry
and prevents the IC from draining battery power.
Output Range The voltage on the IOUT pin should be greater
than 500 mV to guarantee the accuracy and linearity of the programmed current. The output voltage is a function of the battery
voltage, motor resistance, and the programmed load current.
Clamp Diode When the output is turned off, the load inductance causes the output voltage to rise. A clamp diode, from
IOUT to VDD, is integrated in the IC to ensure that the output
voltage remains at a safe level.
I2C Interface This is a serial interface that uses two bus lines,
SCL and SDA, to access the internal Control registers. Data is
exchanged between a microcontroller (master) and the A3904
(slave). The clock input to SCL is generated by the master, while
the SDA line functions as either an input or an open drain output,
depending on the direction of the data. The I2C input thresholds
do not depend on the VDD voltage of the A3904. The levels are
fixed at approximately 1 V. The fixed levels allow the SDA and
SCL lines to be pulled-up to a different logic level than the VDD
supply of the 3904.
Timing Considerations The control sequence of the communication through the I2C interface is composed of several steps
in the following sequence:
1. Start Condition. Defined by a negative edge on the SDA
line, while SCL is high.
2. Address Cycle. 7 bits of address, plus 1 bit to indicate
write (0) or read (1), and an acknowledge bit. The address setting is 0x18, 0x1A, 0x1C or 0x1E.
3. Data Cycles. Write 8 bits of data that address the internal
Control register, followed by an acknowledge bit.
4. Stop Condition. Defined by a positive edge on the SDA
line, while SCL is high.
Except to indicate a Start or Stop condition, SDA must be stable
while the clock is high. SDA can only be changed while SCL is
low. It is possible for the Start or Stop condition to occur at any
time during a data transfer. The A3904 always responds by resetting the data transfer sequence.
The Read/Write bit is set low to indicate a write cycle. Multiple
writes are allowed before issuing a Stop condition. There are no
readback functions incorporated into the A3904.
The master monitors for an acknowledge pulse to determine if the
slave device is responding to the address byte sent to the A3904.
When the A3904 decodes the 7-bit address field as a valid
address, it responds by pulling SDA low during the ninth clock
cycle.
During a data write from the master, the A3904 pulls SDA low
during the clock cycle that follows the data byte, in order to indicate that the data has been successfully received.
After sending either an address byte or a data byte, the master
device must release the SDA line before the ninth clock cycle, in
order to allow this handshaking to occur.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A3904
Low Voltage Voice Coil Motor Driver
Application Information
Headroom The current may not reach the programmed level
be positive for each incremental step, according to the following
if there is not adequate headroom in the output circuit. The IC
output voltage must be over 500 mV to guarantee normal linear
operation. VDD, ILOAD, and RLOAD can be adjusted to ensure that
the device operates in the linear range.
formula:
If the equation shown below is not satisfied, the load current
will be limited by the series impedance, and may not reach the
programmed level
Offset error The measured output current at input Code = 16,
VDD(min) – RLOAD(max) × IOUT(max) ≥ 500 mV .
DNL = (IOUT(n+1) – IOUT(n) ) / LSB – 1 (LSB) .
where n is in the range 16 to 255.
compared to the ideal value according to the transfer function
(8 mA).
Gain Error The difference in the slopes of the ideal transfer
function and the actual transfer function. The gain error is calcu-
IOUT Errors
Relative accuracy (INL) This error is calculated by measuring
the worse case deviation from a straight line, defined from end
points. The straight line end points are defined by the actual measured values at Code = 16 and Code = 255. See figure 1.
Differential nonlinearity (DNL) A measure of the monotonicity of the D-to-A converter. The slope of the line must always
lated by subtracting out the offset error, at Code = 16, from the
actual transfer function. This calculated value is compared to the
ideal transfer function and reported as a percentage of the ideal
full scale value (127.5 mA). See figure 2.
Gain Error Drift The change in slope of the transfer function
due to temperature, expressed as LSB/°C.
127.5
Offset
Error
Gain
Error
127.5
64.0
IOUT (mA)
IOUT (mA)
INL
96.0
32.0
0
0
0
16
128
255
0
16
128
Code
Straight line between measured Codes 16 and 255
Relative Accuracy ( Codes 16-255), errors exaggerated for clarity
Figure 1. Relative accuracy error
255
Code
Ideal DAC
Actual DAC, errors exaggerated for clarity
Calculated Gain Error, Offset Error removed
Figure 2. Gain error
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A3904
Low Voltage Voice Coil Motor Driver
CG Package, 6-Bump WLCSP
1.055
1
A
2
3
1
X…148
2
3
A
B
0.370
0.705
B
B
0.370
0.740
C
SEATING
PLANE
All dimensions nominal, not for tooling use
Dimensions in millimeters
Exact configuration at supplier discretion within limits shown
0.500 MAX
C
6X
PCB Layout Reference View
0.05 C
…0.170
A Die orientation mark
A
B
B
Terminal #A1 mark area
C
Reference view of typical layout for solder pads
All pads a minimum of 0.20 mm from all adjacent pads;
adjust as necessary to meet application process
requirements and PCB layout tolerances
0.370
A
1
0.167
0.158
2
3
0.370
0.740
Copyright ©2007-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
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