TLE8080EM Data Sheet (1.4 MB, EN)

TLE8080EM
Engine Management IC for Small Engines
TLE8080EM
TLE8080-2EM
Data Sheet
Rev. 1.1, 2012-10-19
Automotive Power
TLE8080EM
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
5.1
5.2
5.3
5.4
5V Supply, Reset and Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5V Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power On Reset and Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Characteristics 5V Supply, Reset and Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
6.1
6.2
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Low Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical Characteristics Low Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
7.1
Variable Reluctance Sensor (VRS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical Characteristics VR Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
8.1
8.2
8.2.1
8.2.2
8.3
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set and Reset of Diagnosis Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9.1
9.2
K-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
K-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electrical Characteristics K-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Sheet
2
24
24
24
26
28
31
Rev. 1.1, 2012-10-19
Engine Management IC for Small Engines
1
TLE8080EM
Overview
Features
•
•
•
•
•
•
•
•
•
•
Supply 5V (+/-2%), 250mA
K-line transceiver (ISO 9141)
Serial Peripheral Interface (SPI)
4 low side driver for inductive loads with overtemperature and
overcurrent protection and open load/short to GND in off diagnosis:
– 2 low side switches with maximum operation of 2.6A
– 2 low side switches with maximum operation of 350mA
1 low side driver for resistive loads with maximum operation current
of 3A including overtemperature and overcurrent protection
Configurable variable reluctance sensor interface
Reset output and 5V undervoltage detection
Watchdog
Green product (RoHS compliant)
AEC qualified
PG-SSOP24
Description
The TLE8080EM is an engine management IC based on Infineon Smart Power Technology (SPT). It is protected
by embedded protection functions and integrates a power supply, K-line, SPI, variable reluctance sensor interface
and power stages to drive different loads in an engine management system. It provides a compact and cost
optimized solution for engine management systems. It is very suitable for one cylinder motorcycle engine
management systems.
TLE8080-2EM
This version differs from the main version in the parameters “V5DD Reset Threshold for TLE8080-2EM” and
“Power On Reset Delay Time” in Chapter 5.4.
For ordering conditions please contact the nearest Infineon Technologies office.
Type
Package
Marking
TLE8080EM
PG-SSOP24
TLE8080EM
TLE8080-2EM
PG-SSOP24
TLE8080-2EM
Data Sheet
3
Rev. 1.1, 2012-10-19
TLE8080EM
Block Diagram
2
Block Diagram
VS
5V Voltage
Supply
V5DD
Undervoltage
Detection
WD_DIS
CSN; SI;
SO; SCLK
4
SPI
Watchdog
Reset
NRO
LS Driver
OUT5
inductive loads
350 mA
LS Driver
OUT4
inductive loads
350mA
LS Driver
IN3
OUT3
inductive loads
2.6A
LS Driver
resistive loads
3A
OUT2
LS Driver
IN1
VR_IN1; VR_IN2
2
2
VR_OUT
VR Sensor
KIO
K-Line
AGND
PGND
RX; TX
OUT1
inductive loads
2.6A
Figure 1
Data Sheet
Block Diagram
4
Rev. 1.1, 2012-10-19
TLE8080EM
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
KIO
1
2
24
23
TX
VS
OUT5
3
22
AGND
OUT4
4
21
OUT3
5
20
V5DD
NRO
PGND
OUT2
6
7
19
18
OUT1
8
17
IN1
CSN
PGND
25
PGND
RX
IN3
9
16
SCLK
VR_IN1
10
SI
VR_IN2
WD_DIS
11
15
14
12
13
SO
VR_OUT
Pg-ssop-24 .vsd
Figure 2
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Function
1
KIO
K-Line Bus Connection
2
VS
Battery Voltage: Block to AGND directly at the IC with min. 100nF ceramic
capacitor
3
OUT5
Output Channel 5
4
OUT4
Output Channel 4
5
OUT3
Output Channel 3
6
PGND
Power Ground: internally connected to pin 9, connect externally to pin 9
7
OUT2
Output Channel 2
8
OUT1
Output Channel 1
9
PGND
Power Ground: internally connected to pin 6, connect externally to pin 6
10
VR_IN1
VR Sensor Interface Input 1
11
VR_IN2
VR Sensor Interface Input 2
12
WD_DIS
Watchdog Disable: high active; internal pull down
13
VR_OUT
VR Sensor Output
14
SO
SPI Slave Output: high impedance
15
SI
SPI Slave Input: internal pull down
16
SCLK
SPI Clock Input: internal pull down
17
CSN
SPI Chip Select Input: low active; internal pull up
Data Sheet
5
Rev. 1.1, 2012-10-19
TLE8080EM
Pin Configuration
Pin
Symbol
Function
18
IN1
Control Input Channel 1: internal pull down
19
IN3
Control Input Channel 3: internal pull down
20
NRO
Reset Output: low active, open drain
21
V5DD
5V Supply Output: connected to external blocking capacitor
22
AGND
Analog Ground: connected to system logic ground
23
RX
K-Line Receive Output: logic output of data received from the K-Line bus KIO
24
TX
K-Line Transmit Input: logic level input for data to be transmitted on the K-Line bus
KIO; internal pull up
25
Exposed Pad
Substrate Connection: must be connected to PGND externally on PCB
Data Sheet
6
Rev. 1.1, 2012-10-19
TLE8080EM
General Product Characteristics
4
General Product Characteristics
Table 1
Absolute Maximum Ratings 1)
Tj= -40°C to +150°C: All voltages with respect to ground unless otherwise specified.
Positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
VVS
VV5DD
Vx
-0.3
–
40
V
–
4.1.1
-0.3
–
5.5
V
–
4.1.2
-0.3
–
5.5
V
–
4.1.3
Input Voltage on Pins CSN,
TX
Vx
-0.3
–
V5DD
+0.3V
V
–
4.1.3
Input Voltage VR_IN1,
VR_IN2
VVR_IN1/2
-0.3
–
5.5
V
see also 4.2.1
and 4.2.2
4.1.4
DC Voltage on Pins OUT1-5, Vx
KIO
-0.3
–
30
V
respect to PGND
all channels and
KIO are switched
off
4.1.5
DC Voltage on Pins
VR_OUT, SO, RX, NRO
Vx
-0.3
–
5.5
V
Ix<1mA
4.1.6
DC Voltage AGND to PGND
Vx
VKIO
-0.3
–
0.3
V
-0.3
–
35
Voltages
Supply Voltage VS
Supply Voltage V5DD
Input Voltage on Pins IN1,
IN3, SCLK, SI, WD_DIS
DC Voltage on Pin KIO
4.1.7
V
respect to PGND
KIO is switched off
4.1.8
Currents
Input Current between
VR_IN1 and VR_IN2
IVR_IN1,VR_IN2 -–
–
50
mA
–
4.2.1
Input Current VR_IN1,
VR_IN2 to GND
IVR_IN1/2,GND -–
–
10
mA
–
4.2.2
Tj
Tstg
-40
–
150
°C
–
4.3.1
-55
–
150
°C
–
4.3.2
ESD Resistivity all Pins to
GND
VESD
-2
–
2
kV
HBM2)
4.4.1
ESD Resistivity all Pins to
GND
VESD
-500
–
500
V
CDM3)
4.4.2
ESD Resistivity Pin 1, 12, 13, VESD1,19,20,36 -750
24 (corner pins) to GND
–
750
V
CDM3)
4.4.3
Temperatures
Junction Temperature
Storage Temperature
ESD Susceptibility
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to EIA/JESD 22-A114B
3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1
Data Sheet
7
Rev. 1.1, 2012-10-19
TLE8080EM
General Product Characteristics
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Table 2
Functional Range
Parameter
Symbol
Supply Voltage
Junction Temperature
VS
Tj
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
6
–
18
V
–
4.5.1
-40
–
150
°C
–
4.5.2
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Table 3
Thermal Resistance
Parameter
Junction to Case
Junction to Ambient
Symbol
RthJC
RthJA
Values
Min.
Typ.
Max.
–
7
–
–
29
–
Unit
Note /
Test Condition
Number
K/W
1)
4.6.1
K/W
1) 2)
4.6.2
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Data Sheet
8
Rev. 1.1, 2012-10-19
TLE8080EM
5V Supply, Reset and Supervision
5
5V Supply, Reset and Supervision
5.1
5V Supply
The TLE8080EM integrates a voltage regulator for load currents up to 250mA. The input voltage at VS is regulated
to 5V on V5DD with a precision of ±2%. The design allows to achieve stable operation even with ceramic output
capacitors down to 470 nF. It is protected against overload, short circuit, and over temperature conditions. For low
drop operation, a charge pump is implemented.
VS
Vref
I VS
+
-
V5DD
IV5DD
e.g. µC
Figure 3
5V Supply
5.2
Power On Reset and Reset Output
The reset output NRO is an open drain output. When the level of VV5DD reaches the reset threshold (VRT)
(increasing voltage VV5DD) the signal at NRO remains low for the power-up reset delay time (tRD). The reset
function and timing is illustrated in Figure 4. The reset reaction time (tRR) avoids wrong triggering caused by short
“glitches” on the V5DD-line. In case of V5DD power down (decreasing voltage; VV5DD < VRT for t > tRR) a logic low
signal is generated at the pin NRO to reset an external micro controller. The level of the reset threshold for
increasing VV5DD is for the hysteresis (VRH) higher than the level for decreasing VV5DD.
With an active reset all power stages and the K-Line output are disabled and SPI commands are ignored.
Data Sheet
9
Rev. 1.1, 2012-10-19
TLE8080EM
5V Supply, Reset and Supervision
Vs
t
VV5DD
<
tRR
VRT
V NRO
tRR
t RD
t RD
tRR
t
VNRO_H
V NRO_L
t
Figure 4
Reset Timing Diagram
5.3
Watchdog Operation
The TLE8088EE integrates a watchdog function which monitors the correct SPI communication with the micro
controller. A watchdog disable pin ( WD_DIS ) with an internal pull down current source is implemented. With a
high level the watchdog function is disabled.
For enabled watchdog function after power-up reset delay time ( tRD ), valid SPI communication from the micro
controller must occur within the watchdog period ( tWP ) specified in the electrical characteristics. A restart of the
watchdog period is done with a low to high transition of the CSN pin of a valid transmission of a 16 bit message.
A reset is generated (NRO goes LOW) for the time ( tWR ) if there is no restart during the watchdog period as shown
in Figure 5.
Status after watchdog overflow:
•
•
•
•
all outputs are switched off
SPI registers are not influenced
Watchdog Time Out bit in SPI status register is set
first answer to SPI communication is the content of the status register
Switching of Outputs and reset of Watchdog Time Out Bit after watchdog overflow:
•
•
•
Outputs 1 and 3 will be switched on with an positive edge at IN1 respectively IN3
Outputs 2, 4 and 5 will be switched on with a write command to CMD register
the watchdog time out bit will be reset with the rising edge of CSN of the first read command of the status
register
Data Sheet
10
Rev. 1.1, 2012-10-19
TLE8080EM
5V Supply, Reset and Supervision
Vs
t
V5DD
VRT
t
VNRO
tWR
t RD
Normal operation
trr
t
Watchdog
Period
t
restart
tWP
CSN
t
SI
16 Bits
16 Bits
16 Bits
Data Sheet
t
No correct SPI
communication
within the
Watchdog Period
causing reset
1. correct SPI
communication
Figure 5
e.g. 4 Bits
Watchdog Timing Diagram
11
Rev. 1.1, 2012-10-19
TLE8080EM
5V Supply, Reset and Supervision
5.4
Electrical Characteristics 5V Supply, Reset and Supervision
Table 4
Electrical Characteristics: 5V Supply, Reset and Supervision
VS=13.5V, Tj= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Number
5V Supply
Output Voltage
VV5DD
4.9
5
5.1
V
0 mA < IV5DD <
250mA
6V < VS < 18V
5.1.1
Output Current Limitation
IV5DD
ΔVV5DD, Lo
250
–
650
mA
5.1.2
–
–
50
mV
VV5DD = 0V
1 mA < IV5DD <
Load Regulation
5.1.3
250mA
Line Regulation
ΔVV5DD, Li
–
–
10
mV
Power Supply Rejection
PSRR
–
60
–
dB
IV5DD = 1mA
10V < VS < 18V
f = 100Hz
VS, ripple = 0.5
5.1.4
nF
1)
5.1.6
5.1.7
5.1.8
5.1.5
Vpp1)
Output Capacitor
Output Capacitor ESR
Current Consumption
CV5DD
470
ESR(CV5DD) –
IVS
–
–
–
–
10
Ω
1)
5.5
8
mA
IV5DD= 0mA, all
channels and KLine off
Low Drop Voltage
VV5DD
4.8
–
5
V
4.15
–
5
V
IV5DD = 1mA
VS =5V
IV5DD = 250mA
VS =5V;
5.1.9
5.1.10
after device
ramp-up (VS >9V)
Over Temperature Protection
Over Temperature Threshold TOT
Over Temperature Hysteresis TOT,Hys
150
–
200
°C
1)
5.2.1
5.2.2
–
20
–
°C
1)
VV5DD decreasing 5.3.1
only at version
TLE8080EM
Under Voltage Detection
V5DD Reset Threshold
VRT
4.00
4.25
4.50
V
Reset Hysteresis
VRH
VRT
10
–
150
mV
3.4
3.65
3.9
V
V5DD Reset Threshold for
TLE8080-2EM
Data Sheet
12
5.3.2
VV5DD decreasing 5.3.3
only at version
TLE8080-2EM
Rev. 1.1, 2012-10-19
TLE8080EM
5V Supply, Reset and Supervision
Table 4
Electrical Characteristics: 5V Supply, Reset and Supervision (cont’d)
VS=13.5V, Tj= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
10
15
20
ms
only at version
TLE8080EM
5.4.1
30
40
50
ms
only at version
TLE8080-2EM
5.4.2
tRR
10
15
20
μs
VNRO,L
–
–
1.1
V
tWP
tWR
50
60
70
ms
5.6.1
120
240
360
μs
5.6.2
–
–
1
V
5.7.1
2
–
–
V
5.7.2
20
50
100
μA
at VIN= 5V
5.7.3
2.4
–
–
μA
at VIN= 0.6V
5.7.4
250
mV
Power On Reset
Power On Reset Delay Time tRD
Reset Reaction Time
5.4.3
Reset Output NRO
Low Level Output Voltage
INRO = 1mA
5.5.1
Watchdog
Watchdog Period
Watchdog Reset Time
Input Characteristics WD_DIS
Low Level Input Voltage
High Level Input Voltage
Pull Down Current
Pull Down Current
Hysteresis
VWD_DIS,L
VWD_DIS,H
IWD_DIS,pd
IWD_DIS,pd
VWD_DIS,Hys
30
5.7.5
1) Not subject to production test, specified by design
Data Sheet
13
Rev. 1.1, 2012-10-19
TLE8080EM
Power Stages
6
Power Stages
6.1
Low Side Switches
The power stages are built by N-channel power MOSFET transistors. The channels are universal multi channel
switches, but are mostly suitable to be used in engine management systems. Within an engine management
system, the best fit of the channels to the typical loads is:
•
•
•
Channel 1 and 3 for injector valves or similar sized solenoids with a maximum operation current requirement
of 2.6A
Channel 2 for malfunction indication lamps or other resistive loads with a maximum current requirement of 3A
Channel 4 and 5 for relays or other inductive loads with a maximum current requirement of 350mA
The channels are switched off while reset is active (pin NRO is low). After an power on reset the channels will be
switched on with a positive edge at IN1 respectively IN3 or with a switch on command over SPI.
V bat
V bat
ID
OUT
V
L,
RL
OUT
V DS
R
V DS
DScl
GND
GND
Channel 1, 3, 4, 5
Figure 6
ID
Channel2
Low Side Switches
In Table 5 the control concept, typical loads, the implemented protection and monitor functions are illustrated.
Table 5
Overview Diagnosis Function
Channel
Control
Recommended
Load
Over
Over Current
Temperature
1
Pin IN1
Injector Valve
x
Latch1)
x
2
SPI CMD Register
Bit 0
MIL (max. 3W)
x
repetitive switching;
off time toc,off1)
–
3
Pin IN3
Valve
x
Latch1)
x
1)
x
x
4
SPI CMD Register
Bit 1
Relay
Latch
one
temperature
sensor for
channel 4 and
channel 5
5
SPI CMD Register
Bit 2
Relay
Latch1)
one
temperature
sensor for
channel 4 and
channel 5
Open
Load/Short
to GND
1)Reset behavior of the diagnosis bits see Chapter 8.2
Data Sheet
14
Rev. 1.1, 2012-10-19
TLE8080EM
Power Stages
In overcurrent condition the affected channel will be switched off. There are two different implementations for
switching on again after an over current event.
For channels 1, 3, 4 and 5 the switch off state is latched. The input pins IN1, IN3 must be set to low to reset the
latch before the channel can be switched on again.
For channels 4 and 5 the over current status is reset with a write command to the CMD register. The switching
state is according to the status of bit 1 and 2.
Channel 2 will be switched off and after toc_off = 5ms typically the channel will be switched on again automatically.
The result is repetitive switching with a fixed off time of toc,off. The overcurrent status of channel 2 is internally
latched. For releasing the over current diagnosis bit after over current condition, channel 2 must stay switched on
for at least toc,St.
The bits 0 to 4 in the Stat register reflect the actual switching status of the channels.
For detailed description see Chapter 8.2.2.
All the channels are protected from over temperature. In an overtemperature situation the affected channel will be
switched off. The channel will restart operation if the junction temperature decreases by thermal shutdown
hysteresis TOT,Hys. Channels 4 and 5 are using a common temperature sensor. Therefore, the two channels are
switched together during over temperature.
For channels 1, 3, 4 and 5 an open load/short to GND in off detection with a pull down current source (active in
off) and a comparator is implemented. In case of switch off and the output voltage is below the open load detection
threshold (Voutx < Vol,th), the open load in off timer is started. After the open load in off delay time tol,d , the open
load is detected (timing see Figure 9 and Figure 10).
The diagnosis status of the channels is monitored in the SPI Diagnosis Register DIAG (see Chapter 8.2).
Data Sheet
15
Rev. 1.1, 2012-10-19
TLE8080EM
Power Stages
6.2
Electrical Characteristics Low Side Switches
Table 6
Electrical Characteristics: Power Stage
VS=13.5V, Tj= -40°C to +150°C: All voltages with respect to ground.
Positive current flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Number
IOUTx_nom = 1.3A;
Tj = 150°C
IOUTx = 0.02A
6.1.1
Output Channel 1 and 3
On Resistance
ROUTx_on
–
0.6
0.7
Ω
Output Clamping Voltage
VOUTx_cl
IOUTx_oc
30
35
40
V
2.6
–
5
A
6.1.3
Over-current Switch Off Filter toc,f
Time
0.5
–
3
μs
6.1.4
Over Temperature Switch Off TOT
150
–
200
°C
6.1.5
Over Temperature Hysteresis TOT,Hys
–
20
–
°C
6.1.6
6.1.7
Over-current Switch Off
Threshold
Open Load in Off Detection
Threshold
Vol,th
2
2.8
3.2
V
Open Load in Off Pull Down
Diagnosis Current
Iol
50
100
150
μA
Open Load in Off Diagnosis
Delay Time
tol,d
100
–
200
μs
Turn On Delay Time
td,ON
–
0.25
1
μs
VOUTx = 13.5V
6.1.2
6.1.8
6.1.9
VOUTx = 13.5V
IOUTx = 1.3A,
6.1.10
VOUTx = 13.5V
IOUTx = 1.3A,
6.1.11
VOUTx = 13.5V
IOUTx = 1.3A,
6.1.12
VOUTx = 13.5V
IOUTx = 1.3A,
6.1.13
resistive load1)
Turn Off Delay Time
td,OFF
–
0.9
1.5
μs
resistive load1)
Turn On Time
ts,ON
–
0.6
1.2
μs
resistive load1)
Turn Off Time
ts,OFF
–
0.6
1.2
μs
resistive load1)
IOUTx_off
–
–
3
μA
VOUTx = 13.5V
Tj = 150°C2)
6.1.14
On Resistance
ROUTx_on
–
1.1
1.2
Ω
IOUTx_nom = 0.3A;
Tj = 150°C
6.2.1
Over-current Switch Off
Threshold
IOUTx_oc
3
–
6.5
A
6.2.2
Over-current Switch Off Filter toc,f
Time
0.5
–
3
μs
6.2.3
Over-current Switch Off Time toc,off
3
–
8
ms
6.2.4
Output Leakage Current in
Off Mode
Output Channel 2
Data Sheet
16
Rev. 1.1, 2012-10-19
TLE8080EM
Power Stages
Table 6
Electrical Characteristics: Power Stage (cont’d)
VS=13.5V, Tj= -40°C to +150°C: All voltages with respect to ground.
Positive current flowing into pin (unless otherwise specified).
Parameter
Symbol
toc,St
Over Temperature Switch Off TOT
Over Temperature Hysteresis TOT,Hys
Turn On Delay Time
td,ON
Over-current Status Time
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
1
–
12
ms
6.2.5
150
–
200
°C
6.2.6
–
20
–
°C
6.2.7
–
0.6
1.2
μs
VOUTx = 13.5V
IOUTx = 1.3A,
6.2.8
VOUTx = 13.5V
IOUTx = 1.3A,
6.2.9
VOUTx = 13.5V
IOUTx = 1.3A,
6.2.10
VOUTx = 13.5V
IOUTx = 1.3A,
6.2.11
resistive load1)
Turn Off Delay Time
td,OFF
–
0.7
1.5
μs
resistive load1)
Turn On Time
ts,ON
–
0.4
1
μs
resistive load1)
Turn Off Time
ts,OFF
–
0.4
1
μs
resistive load1)
IOUTx_off
–
–
3
μA
VOUTx = 13.5V
Tj = 150°C
6.2.12
On Resistance
ROUTx_on
–
3.3
3.6
Ω
6.3.1
Output Clamping Voltage
VOUTx_cl
IOUTx_oc
30
35
40
V
IOUTx_nom = 0.3A;
Tj = 150°C
IOUTx = 0.02A
350
–
600
mA
6.3.3
Over-current Switch Off Filter toc,f
Time
0.8
–
2.4
μs
6.3.4
Over Temperature Switch Off TOT
150
–
200
°C
6.3.5
Over Temperature Hysteresis TOT,Hys
–
20
–
°C
6.3.6
6.3.7
Output Leakage Current in
Off Mode
Output Channel 4 and 5
Over-current Switch Off
Threshold
Open Load in Off Detection
Threshold
Vol,th
2
2.8
3.2
V
Open Load in Off Pull Down
Diagnosis Current
Iol
50
100
150
μA
Open Load in Off Diagnosis
Delay Time
tol,d
100
–
200
μs
Turn On Delay Time
td,ON
–
0.5
1.2
μs
VOUTx = 13.5V
6.3.2
6.3.8
6.3.9
VOUTx = 13.5V
IOUTx = 0.3A,
6.3.10
VOUTx = 13.5V
IOUTx = 0.3A,
6.3.11
resistive load1)
Turn Off Delay Time
td,OFF
–
0.7
1.5
μs
resistive load1)
Data Sheet
17
Rev. 1.1, 2012-10-19
TLE8080EM
Power Stages
Table 6
Electrical Characteristics: Power Stage (cont’d)
VS=13.5V, Tj= -40°C to +150°C: All voltages with respect to ground.
Positive current flowing into pin (unless otherwise specified).
Parameter
Symbol
Turn On Time
ts,ON
Values
Min.
Typ.
Max.
–
0.1
0.8
Unit
Note /
Test Condition
Number
μs
VOUTx = 13.5V
IOUTx = 0.3A,
6.3.12
VOUTx = 13.5V
IOUTx = 0.3A,
6.3.13
VOUTx = 13.5V
Tj = 150°C2)
6.3.14
resistive load1)
Turn Off Time
ts,OFF
–
0.1
0.8
μs
resistive load1)
Output Leakage Current in
Off Mode
IOUTx_off
–
–
2
μA
–
–
1
V
6.4.1
2
–
–
V
6.4.2
50
110
250
mV
6.4.3
20
50
100
μA
–
–
μA
Input Characteristic IN1 and IN3
Low Level Input Voltage
High Level Input Voltage
Input Voltage Hysteresis
Pull Down Current
VIN,L
VIN,H
VIN,Hys
IIN,PD
IIN,PD
Pull Down Current
2.4
1)definition of timing see Figure 7 or Figure 8
VIN = 5V
VIN = 0.6V
6.4.4
6.4.5
2) in OFF mode open load diagnosis pull down current active
VINx
50%
VOUTx
t
VBATT
80%
20%
t
td, ON
Figure 7
Data Sheet
t s, ON
td,OFF
t s, OFF
Timing Low Side Switches Channel 1 and 3
18
Rev. 1.1, 2012-10-19
TLE8080EM
Power Stages
VCSN
50%
t
VOUTx
VBATT
80%
20%
t
td, ON
Figure 8
td,OFF
t s, ON
t s, OFF
Timing Low Side Switches Channel 2,4 and 5
VINx
50%
t
VOUTx
VBATT
open
open
Vol.th
tol.d
t ol.d
t
CHx_OL
t
Figure 9
Data Sheet
Timing Open Load/Short to GND in Off Detection Channel 1 and 3
19
Rev. 1.1, 2012-10-19
TLE8080EM
Power Stages
VCSN
50%
t
VOUTx
VBATT
open
open
Vol.th
tol.d
t ol.d
t
CHx_OL
t
Figure 10
Data Sheet
Timing Open Load/Short to GND in Off Detection Channel 2,4 and 5
20
Rev. 1.1, 2012-10-19
TLE8080EM
Variable Reluctance Sensor ( VRS ) Interface
7
Variable Reluctance Sensor ( VRS ) Interface
The variable reluctance (VR) sensor interface converts an output signal of a VR sensor into a logic level signal
suited for µC 5V input ports. The voltage difference between the two input pins, VR_IN1 and VR_IN2, which are
connected to the two output pins of the VR sensor, is detected and the output pin VR_OUT is switched depending
on the sign of the voltage difference ( see Figure 12 )The amplitude of the VR sensor signal is limited by an internal
clamping circuit to avoid damage of the device due to over voltage caused by the VR sensor signal.
VR_IN1
Select Load
Clamp
&
Load
2,5V
Buffer
Detection
VR_OUT
VR_IN2
Select Threshold
Figure 11
Data Sheet
VR Sensor Interface Block Diagram
21
Rev. 1.1, 2012-10-19
TLE8080EM
Variable Reluctance Sensor ( VRS ) Interface
7.1
Electrical Characteristics VR Sensor Interface
Table 7
Electrical Characteristics: VR Sensor Interface
VS=13.5V, Tj= -40°C to +150°C: All voltages with respect to ground.
Positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
positive VR Sensor Interface VVR,th_pos
Detection Threshold
-30
0
30
mV
negative VR Sensor Interface VVR,th_neg
Detection Threshold
-80
-50
-20
mV
CMD Register:
VR_T[1:0] = “00”
Reset State
7.1.2
-130
-100
-70
mV
CMD Register:
VR_T[1:0] = “01”
7.1.3
-550
-500
-450
mV
CMD Register:
VR_T[1:0] = “10”
7.1.4
-1.1
-1
-0.9
V
CMD Register:
VR_T[1:0] = “11”
7.1.5
30
75
120
kΩ
Tj = 25°C;
CMD Register:
VR_L[1:0] = “00”
Reset State
7.1.6
90
kΩ
Tj = -40°C;
CMD Register:
VR_L[1:0] = “00”
Reset State
60
kΩ
Tj = 150°C;
CMD Register:
VR_L[1:0] = “00”
Reset State
Input Characteristics:
VR Sensor Interface Load
Selection
RVR,Load
7.1.1
3
4.5
8
kΩ
CMD Register:
VR_L[1:0] = “01”
7.1.7
1.5
2.2
3.3
kΩ
CMD Register:
VR_L[1:0] = “10”
7.1.8
0.7
1.2
1.9
kΩ
CMD Register:
VR_L[1:0] = “11”
7.1.9
VR Sensor Interface Input
Clamping Current
IVR,clamp
–
–
±50
mA
VR Sensor Interface Input
Clamping Voltage
VVR,clamp
±2.5
±3
±3.5
V
IVR,clamp= ±50mA
VVR_OUT,L
VVR_OUT,H
–
–
0.3
V
–
V
IVR_OUT = 100μA 7.2.1
IVR_OUT = -100μA 7.2.2
7.1.10
7.1.11
Output Characteristics:
Low Level Output Voltage
High Level Output Voltage
Data Sheet
V5DD- –
0.3
22
Rev. 1.1, 2012-10-19
TLE8080EM
Variable Reluctance Sensor ( VRS ) Interface
Table 7
Electrical Characteristics: VR Sensor Interface (cont’d)
VS=13.5V, Tj= -40°C to +150°C: All voltages with respect to ground.
Positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
Delay Time Input to VR_OUT tdr
falling edge
1
1.5
2.5
μs
7.3.1
Delay Time Input to VR_OUT tdf
rising edge
1
1.5
2.5
μs
7.3.2
Transfer Characteristics:
VVR_IN1 – VR_IN2
V V RT h_pos =0V
VVR_OUT
V V RT h_neg
t dr
t
tdf
50%
t
Figure 12
Data Sheet
Timing Characteristics of the VR Sensor Interface
23
Rev. 1.1, 2012-10-19
TLE8080EM
Serial Peripheral Interface (SPI)
8
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a 16 bit full duplex synchronous serial slave interface, which uses four lines: SI, SO, SCLK and CSN.
8.1
SPI Signal Description
CSN - Chip Select:
The system micro controller selects the IC by means of the CSN pin. Whenever the pin is in low state, data transfer
can take place. As long as CSN is in high state, all signals at the SCLK and SI pins are ignored and SO is forced
to high impedance.
CSN - High to Low Transition:
SO changes from high impedance to high or low state depending on the Status Flag (see Chapter 8.2).
CSN - Low to High Transition:
End of transmission, the validation check of the communication is done (number of bits and valid command) and
valid commands are executed.
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts information out on the rising edge of the serial clock. It is essential
that the SCLK pin is in low state whenever chip select CSN makes any transition.
SI - Serial Input:
Serial input data bits are shifted in at this pin, the most significant bit (MSB) first. SI information is read on the falling
edge of SCLK. Please refer to Section 8.2 for further information.
SO - Serial Output:
Data is shifted out serially at this pin, the MSB first. SO is in high impedance until the CSN pin goes to low. The
output level before the first rising edge of SCLK depends on the status flag. New data will appear at the SO pin
following the rising edge of SCLK. Please refer to Section 8.2 for further information.
8.2
SPI Protocol
The principle of the SPI communication is shown in Figure 13. The message from the micro controller must be
sent MSB first. The data from the SO pin is sent MSB first. The TLE8080EM samples data from the SI pin on the
falling edge of SCLK and shifts data out of the SO pin on the rising edge of SCLK. Each access must be terminated
by a rising edge of CSN.
All SPI messages must be exactly 16-bits long, otherwise the SPI message is discarded.
There is a one message delay in the response to each message (i.e. the response for message N will be returned
during message N+1).
The SPI protocol of the TLE8080EM provides three registers. The control register, the diagnosis, and the status
register. The control register contains the set up bits for the VR sensor interface and the control bits of channels
2, 4 and 5. The diagnosis register contains the diagnosis bits of the five low side switches. The status register
contains the status bits of the five low side switches, the watchdog status bit, and the watchdog time out bit. After
power-on reset, all register bits are set to reset state (see Chapter 8.2.1).
Data Sheet
24
Rev. 1.1, 2012-10-19
TLE8080EM
Serial Peripheral Interface (SPI)
There are four ways of valid access:
•
•
•
•
Write access to the command register: the answer is 1 for the R/W bit, 00 for the address and the content of
the register
Read access to the command register: the answer is 0 for the R/W bit, 00 for the address and the content of
the register
Read access to the diagnosis register: the answer is 0 for the R/W bit, 01 for the address and the content of
the register
Read access to the status register: the answer is 0 for the R/W bit, 10 for the address and the content of the
register
Any other access is recognized as an invalid message.
Status Flag Indication: after the falling edge of CSN and before the first rising edge of SCLK, the level of the SO
indicates the status of the diagnosis register:
•
•
SO = “0”: no error condition detected; all diagnosis register bits are “0”
SO = “1”: one or more error conditions are detected; one or more diagnosis register bits are “1”
With this feature during every SPI communication a check of the diagnosis status can be done without additional
read access of the diagnosis register.
CSN
SCLK
time
clock
1
don’t care
SI
tristate
Status
Flag
*
Figure 13
)
Bit 15
MSB
don’t care
SO
*
)
Bit 15
MSB
clock
2
clock
3
Bit 14
Bit 14
clock
15
Bit 13
Bit 13
clock
16
don’t care
Bit 1
Bit 0
LSB
Bit 1
Bit 0
LSB
time
don’t care
time
tristate
time
active clock edge for reading data at SI
SPI Protocol
SPI Answers:
•
•
•
•
•
•
during power on reset: SPI commands are ignored, SO is always low
after power on reset: the content of the command register is transmitted with the next SPI transmission
during watchdog reset: SPI commands are ignored, SO has the value of the status flag
after watchdog overflow: the content of the status register is transmitted with the first SPI transmission after
the low to high transition of NRO
after a read or write command: the content of the selected register is transmitted with the next SPI transmission
after an invalid communication: the content of the diagnosis register is transmitted with the next SPI
transmission
Data Sheet
25
Rev. 1.1, 2012-10-19
TLE8080EM
Serial Peripheral Interface (SPI)
8.2.1
SPI Register
Overview
15
14
13
R/W
AD1
AD0
12
11
10
9
8
7
6
Field
Bits
Type
Description
AD1:AD0]
[14:13]
w
Address Bits:
00B Control Register
01B Diagnosis Register
10B Status Register
R/W
15
w
Read - Write Bit:
0B Read Access
1B Write Access
5
4
3
2
1
0
CMD Register
Command Register (Identifier x00x xxxx xxxx xxxxB)Reset Value: 0H
15
14
R/W
AD1
13
12
11
10
9
8
7
6
5
4
3
2
AD0 VR_T1 VR_T0 VR_L1 VR_L0
rw
rw
rw
0
CTR5 CTR4 CTR2
rw
rw
Field
Bits
Type
Description
CTR2
0
rw
Control Bit Channel 2:
0B Channel 2 is switched off (Reset State)
1B Channel 2 is switched on
CTR4
1
rw
Control Bit Channel 4:
0B Channel 4 is switched off (Reset State)
1B Channel 4 is switched on
CTR5
2
rw
Control Bit Channel 5:
0B Channel 5 is switched off (Reset State)
1B Channel 5 is switched on
VR_L1: VR_L0
[10:9]
rw
Load Register of VR Interface:
( c.f. VR Sensor Interface Load Selection )
00B RLoad = 75kΩ (Reset State)
01B RLoad = 4.5kΩ
10B RLoad = 2.2kΩ
11B RLoad = 1.2kΩ
Data Sheet
1
26
rw
rw
Rev. 1.1, 2012-10-19
TLE8080EM
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description
VR_T1: VR_T0
[12:11]
rw
Threshold Register of VR Interface:
00B -50mV (Reset State)
01B −100mV
10B −500mV
11B −1V
Diag Register
Diagnosis Register (Identifier x01x xxxx xxxx xxxxB)Reset Value: 0H
15
R/W
14
13
AD1 AD0
12
11
10
9
8
7
6
5
4
3
2
0
CH45_ CH5_ CH5_ CH4_ CH4_ CH3_ CH3_ CH3_ CH2_ CH2_ CH1_ CH1_ CH1_
OT
OC
OL
OC
OL
OT
OC
OL
OT
OC
OT
OC
OL
r
r
r
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
CH1_OL
0
r
Open Load Diagnosis Bit of Channel 1:
0B no open load in off detected (Reset State)
1B open load in off detected
CH1_OC
1
r
Over Current Diagnosis Bit of Channel 1:
0B no over current detected (Reset State)
1B over current detected
CH1_OT
2
r
Over Temperature Diagnosis Bit of Channel 1:
0B no over temperature detected (Reset State)
1B over temperature detected
CH2_OC
3
r
Over Current Diagnosis Bit of Channel 2:
0B no over current detected (Reset State)
1B over current detected
CH2_OT
4
r
Over Temperature Diagnosis Bit of Channel 2:
0B no over temperature detected (Reset State)
1B over temperature detected
CH3_OL
5
r
Open Load Diagnosis Bit of Channel 3:
0B no open load in off detected (Reset State)
1B open load in off detected
CH3_OC
6
r
Over Current Diagnosis Bit of Channel 3:
0B no over current detected (Reset State)
1B over current detected
CH3_OT
7
r
Over Temperature Diagnosis Bit of Channel 3:
0B no over temperature detected (Reset State)
1B over temperature detected
CH4_OL
8
r
Open Load Diagnosis Bit of Channel 4:
0B no open load in off detected (Reset State)
1B open load in off detected
CH4_OC
9
r
Over Current Diagnosis Bit of Channel 4:
0B no over current detected (Reset State)
1B over current detected
Data Sheet
1
27
r
r
Rev. 1.1, 2012-10-19
TLE8080EM
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description
CH5_OL
10
r
Open Load Diagnosis Bit of Channel 5:
0B no open load in off detected (Reset State)
1B open load in off detected
CH5_OC
11
r
Over Current Diagnosis Bit of Channel 5:
0B no over current detected (Reset State)
1B over current detected
CH45_OT
12
r
Over Temperature Diagnosis Bit of Channel 4 and 5:
0B no over temperature detected (Reset State)
1B over temperature detected
Stat Register
Status Register (Identifier x10x xxxx xxxx xxxxB)Reset Value: 0H
15
14
R/W
AD1
13
12
11
10
9
8
7
6
5
AD0 WD_DIS WD_TO
r
r
4
3
2
1
0
ST5
ST4
ST3
ST2
ST1
r
r
r
r
r
Field
Bits
Type
Description
ST1
0
r
Status Bit Channel 1:
0B Channel 1 is switched off (Reset State)
1B Channel 1 is switched on
ST2
1
r
Status Bit Channel 2:
0B Channel 2 is switched off (Reset State)
1B Channel 2 is switched on
ST3
2
r
Status Bit Channel 3:
0B Channel 3 is switched off (Reset State)
1B Channel 3 is switched on
ST4
3
r
Status Bit Channel 4:
0B Channel 4 is switched off (Reset State)
1B Channel 4 is switched on
ST5
4
r
Status Bit Channel 5:
0B Channel 5 is switched off (Reset State)
1B Channel 5 is switched on
WD_TO
11
r
Watchdog Time Out Bit:
0B no watchdog time out
1B watchdog time out occurred
WD_DIS
12
r
Watchdog Status Bit:
0B Watchdog enabled (VWD_DIS = 0V)
1B Watchdog disabled (VWD_DIS = 5V)
8.2.2
Set and Reset of Diagnosis Register Bits
Set of the over current diagnosis bits of channels 1, 3, 4 and 5:
The over current diagnosis bits of channels 1, 3, 4 and 5 are set asynchronously of the internal clock with the
output signal of the detection circuit (details see Chapter 6.1).
Data Sheet
28
Rev. 1.1, 2012-10-19
TLE8080EM
Serial Peripheral Interface (SPI)
Reset of the over current diagnosis bits of channels 1 and 3:
•
•
Diagnosis register was read out:
– input pin INx remains high: no reset of the over current diagnosis bit, the channel remains switched off
– input pin INx transition from high to low: the over current diagnosis bit is reset, the channel could be switched
on again
Diagnosis register was not read out
– channel remains switched off and no reset of the over current diagnosis bit is done
– input pin INx is low: with the next read access of the diagnosis register the diagnosis bits are reset
Reset of the over current diagnosis bits of channels 4 and 5:
•
•
Diagnosis register was not read out
– channel remains switched off and no reset of the over current diagnosis bit is done
Diagnosis register was read out:
– SPI command register write command is not sent: no reset of the over current diagnosis bit, the channel
remains switched off
– SPI command register write command is sent: the over current diagnosis bit is reset, the channel will be
switched according the status of the control bit
Set and Reset of the over current diagnosis bit of channel 2:
The over current diagnosis register bit for channel 2 is set asynchronously of the internal clock with the output
signal of the detection circuit. With this signal the output is switched off and the counter for the off time toc,off of the
repetitive switching cycle starts. After toc,off the channel will be switched on again. With an remaining over current
condition the channel will be switched on repetitively. This internal overcurrent status of the channel is latched
internally. The internal over current status is reset in two situations.
•
•
over current condition exists no longer: the internal over current status is reset after the time toc,St
over current condition remains and the channel is switched off: the internal over current status is reset after
the time toc,off
The reset of the over current diagnosis register bit for channel 2 is related to the internal over current status. In
Figure 14 and Figure 15 the behavior of the diagnosis with temporary and permanent over current condition is
drawn.
Data Sheet
29
Rev. 1.1, 2012-10-19
TLE8080EM
Serial Peripheral Interface (SPI)
Over Current
No Over Current
Cont Reg.
Bit 1
toc,f
t oc,f
t oc,f
IOUT2
ID,oc
t oc,off
Internal Over
Current Status
t oc,off
toc,St
Diag Reg.
Bit 3
SPI Diag Reg.
Read Out
Figure 14
SPI Diag Reg.
Read Out
SPI Diag Reg.
Read Out
Behavior of diagnosis with temporary over current condition at channel 2
Permanent Over Current
Cont Reg.
Bit 1
toc,f
t oc,f
t oc,f
IOUT2
ID,oc
Internal Over
Current Status
t oc,off
t oc,off
toc,off
Diag Reg.
Bit 3
SPI Diag SPI Diag
Reg.
Reg.
Read Out Read Out
Figure 15
SPI Diag Reg.
Read Out
Behavior if diagnosis with permanent over current condition at channel 2
Reset of the over temperature diagnosis bits:
Data Sheet
30
Rev. 1.1, 2012-10-19
TLE8080EM
Serial Peripheral Interface (SPI)
The over temperature diagnosis bits will be reset with read access of the diagnosis register if no over temperature
condition is detected.
Reset of the open load in off diagnosis bits:
The open load in off diagnosis bits will be reset with read access of the diagnosis register if no open load condition
is detected.
Data Sheet
31
Rev. 1.1, 2012-10-19
TLE8080EM
Serial Peripheral Interface (SPI)
8.3
Electrical Characteristics SPI
Table 8
Electrical Characteristics: SPI
VS=13.5V, Tj= -40°C to +150°C: All voltages with respect to ground.
Positive current flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
Vx,L
Vx,H
Vx,Hys
Ix,pu
Ix.pu
–
–
1
V
8.1.1
2
–
–
V
8.1.2
250
mV
Input Characteristics (CSN, SCLK, SI):
Low Level Input Voltage
High Level Input Voltage
Hysteresis
50
-25
-50
-100
μA
at VIN = 0V
8.1.3
-25
–
–
μA
at VIN = VV5DD 0.6V
8.1.4
Ix,pu
Ix.pu
20
50
100
μA
at VIN = VV5DD
8.1.5
2.4
–
–
μA
at VIN = 0.6V
8.1.6
VSo,L
VSO,H
–
–
0.4
V
8.2.1
V5DD- –
0.4
–
V
Ix = 100μA
Ix = -100μA
ISO,TRI
-3
–
3
μA
0V < VSO < 5V
8.2.3
Lead Time
t1
210
–
–
ns
CSN falling to
SCLK rising
8.3.1
Lag Time
t2
75
–
–
ns
SCLK falling to
CSN rising
8.3.2
CSN High Time
t3
550
–
–
ns
CSN rising to
CSN falling
8.3.3
Period of SCLK
t4
t5
200
–
–
ns
10
–
–
ns
60
–
–
ns
CSN to SCLK Hold Time
t7
t8
15
–
–
ns
CSN rising to
SCLK rising
8.3.7
SI Set Up Time
t9
30
–
–
ns
SI set up time to
SCLK falling
8.3.8
SI Hold Up Time
t10
30
–
–
ns
SI holdup time
8.3.9
after SCLK falling
SO Enable Time
t11
–
–
165
ns
CSN falling to SO 8.3.10
active
SO Valid Time
t12
–
–
120
ns
SO data valid
8.3.11
after SCLK rising
Pull Up Current CSN
Pull Up Current CSN
Pull Down Current SCLK, SI
Pull Down Current SCLK, SI
Output Characteristics (SO):
Low Level Output Voltage
High Level Output Voltage
Output High Impedance
Leakage Current
8.2.2
Timings:
SCLK to CSN Set Up Time
SCLK Low Time
Data Sheet
32
8.3.4
SCLK falling to
CSN falling
8.3.5
8.3.6
Rev. 1.1, 2012-10-19
TLE8080EM
Serial Peripheral Interface (SPI)
Table 8
Electrical Characteristics: SPI (cont’d)
VS=13.5V, Tj= -40°C to +150°C: All voltages with respect to ground.
Positive current flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
t13
SO Disable Time
Number of Clock Pulses while
CSN = low
Unit
Note /
Test Condition
Number
SO high
impedance after
CSN rising
8.3.12
Min.
Typ.
Max.
–
–
165
ns
16
–
16
pulses
8.3.13
SO Rise Time
tSO_rise
–
–
75
ns
20% to 80%,
Cload=1.6pF
8.3.14
SO Fall Time
tSO_fall
–
–
75
ns
80% to 20%
Cload=1.6pF
8.3.15
t1
t2
t3
CSN
time
t4
t5
SCLK
t6
clock
1
don’t care
t9
SI
t7
clock
2
Bit 15
MSB
don’t care
Figure 16
Data Sheet
tristate
clock
3
clock
15
clock
16
don’t care
Bit 14
Bit 13
Bit 1
Bit 0
LSB
t12
Status
Flag
time
t10
t11
SO
t8
Bit 15
MSB
don’t care
time
t13
Bit 14
Bit 13
Bit 1
Bit 0
LSB
tristate
time
SPI Timing Diagram
33
Rev. 1.1, 2012-10-19
TLE8080EM
K-Line
9
K-Line
9.1
K-Line
The K-Line module is a serial link bus interface device designed to provide bi-directional half-duplex
communication interfacing. It is designed to interface vehicles via the special ISO K-Line and meets the ISO
standard 9141. The device’s K-Line bus driver’s output is protected against bus shorts.
VS
RX
KIO
V5DD
TX
Driver &
Protection
Figure 17
Data Sheet
K-Line Block Diagram
33
Rev. 1.1, 2012-10-19
TLE8080EM
K-Line
9.2
Electrical Characteristics K-Line
Table 9
Electrical Characteristics: K-Line
VS=13.5V, Tj= -40°C to +150°C: All voltages with respect to ground.
Positive current flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
IRX = 100μA
IRX = -100μA
9.1.1
Min.
Typ.
Max.
VRX,L
VRX,H
–
–
0,4
V
V5DD- –
0.4
–
V
VTX,L
VTX,H
VTX,Hys
IPU_L
IPU_L
–
–
1
V
9.2.1
3.2
–
–
V
9.2.2
280
500
700
mV
9.2.3
-70
-100
-150
μA
at VTX = 0V
9.2.4
-30
–
–
μA
at VTX = VV5DD 0.6V
9.2.5
TX = low,
RKIO=480Ω
9.3.1
Output RX
Low Level Output Voltage
High Level Output Voltage
9.1.2
Input TX
Low Level Input Voltage
High Level Input Voltage
Hysteresis
Pull Up Current
Pull Up Current
K-Line Bus Driver Input/Output KIO
Low Level Output Voltage
VKIO,O,L
–
–
1.4
V
Current Limitation
40
–
140
mA
–
–
0.4*VS V
9.3.3
0.6*VS –
–
V
9.3.4
Hysteresis
IKIO(lim)
VKIO,I,L
VKIO,I,H
VKIO,I,Hys
0.02
*VS
–
0.175
*VS
V
9.3.5
Pull Down Current
IKIO,pd
5
10
15
μA
9.3.6
fKIO,rec
Transmit Frequency
fKIO,tran
Delay Time KIO -> RX rising tdrR
–
–
500
kHz
–
–
100
kHz
0.05
–
0.5
μs
CRX,load = 1.6pF
9.4.3
Delay Time KIO -> RX falling tdfR
edge1)
0.05
–
0.5
μs
CRX,load = 1.6pF
9.4.4
tdrT
0.05
–
0.5
μs
CKIO,load = 1.6pF
9.4.5
Delay Time TX -> KIO falling tdfT
edge1)
0.05
–
0.5
μs
CKIO,load = 1.6pF
9.4.6
Low Level Input Voltage
High Level Input Voltage
9.3.2
Transfer Characteristics
CRX = 25pF; RKIO = 540Ω; CKIO ≤ 1.3nF
Receive Frequency
edge1)
Delay Time TX -> KIO rising
edge1)2)
CKIO = 0pF
9.4.1
9.4.2
1) For definition see Figure 18
2) Not subject of production test, behavior defined by external devices
Data Sheet
34
Rev. 1.1, 2012-10-19
TLE8080EM
K-Line
VTxD
VV5DD
0.5*VV5DD
t
Vbus
tdfT
t drT
VS
0.7*VS
0.3*VS
t
VRxD
t drR
tdfR
VV5DD
0.5*VV5DD
t
Figure 18
Data Sheet
K-Line Transfer Characteristics
35
Rev. 1.1, 2012-10-19
TLE8080EM
Package Outlines
2)
0.2
M
0.1 C D
3.9 ±0.11)
0.08 C
Seating Plane
C A-B D 24x
0.64 ±0.25
6 ±0.2
D
M
D
1
12
24
13
13
12
B
8.65 ±0.1
Index Marking
2.65 ±0.25
Bottom View
A
24
1
0.2
8˚ MAX.
2x
0.19 +0.06
0.35 x 45˚
1.7 MAX.
C
0.65
0.25 ±0.05
Stand Off
(1.47)
Package Outlines
0.1+0
-0.1
10
6.4 ±0.25
0.1 C A-B 2x
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
PG-SSOP-24-4-PO V01
Figure 19
PG-SSOP24
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products, and to be compliant with
government regulations, the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
36
Dimensions in mm
Rev. 1.1, 2012-10-19
TLE8080EM
Revision History
11
Revision History
Revision
Date
Changes
1.0
2012-09-12
Data sheet
1.1
2012-12-19
parameter 5.4.3, page 13 reset reaction time increased
Data Sheet
37
Rev. 1.1, 2012-10-19
Edition 2012-10-19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
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and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
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