ECP5 Versa Development Kit User Guide

ECP5™ Versa Development Board User Guide
EB98 Version 2.1, November 2015
ECP5 Versa Development Board
Introduction
The ECP5™ Versa Development Board allows designers to investigate and experiment with the features of the
ECP5 Field-Programmable Gate Array. The features of the ECP5 Versa Development Board can assist engineers
with rapid prototyping and testing of their specific designs. The ECP5 Versa Development Board is part of the
ECP5 Versa Development Kit. The guide is intended to be referenced in conjunction with demo user guides to
demonstrate the ECP5 FPGA.
Figure 1. ECP5 Versa Development Board, Top Side
SERDES Test
SMA Connectors
Push-buttons
LED
Display
Configuration
Mode Switches
DDR3
Memory
Expansion Connectors
User
Switches
Status LEDs
Dual RJ45
Ethernet Ports
USB Programming
SPI Flash
Configuration
Memory
JTAG
Interface
Dual RJ45
Ethernet Ports
ECP5
Device
On-Board
Clock
Management
PCI Express x1
Features
• Half-length PCI Express form-factor
—Allows demonstration of PCI Express x1 interconnection
• Electrical testing of one full-duplex SERDES channel via SMA connections
• USB-B connection for UART and device programming
• Two RJ45 interfaces to 10/100/1000 Ethernet to RGMII
• On-board Boot Flash
—128M Serial SPI Flash
• DDR3-1866 memory components (64Mb/x16)
• Expansion mezzanine interconnection for prototyping
• 14-segment alpha-numeric display
• Switches, LEDs and displays for demo purposes
• Diamond® programming support
• On-board reference clock sources
2
12 V DC
Power Input
ECP5 Versa Development Board
The contents of this user guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics.
Caution: The ECP5 Versa Development Board contains ESD-sensitive components. ESD safe practices should be
followed while handling and using the evaluation board.
ECP5 Device
This board features an ECP5 FPGA with a 1.1 V core supply. It can accommodate all pin-compatible ECP5 devices
in the 381 ball caBGA package. A complete description of this device can be found in DS1044, ECP5 Family Data
Sheet.
Note: The connections referenced in this document refer to the LFE5UM-45F-8BG381C device.
Applying Power to the Board
The ECP5 Versa Development Board is ready to power on. The board can be supplied with power from a PCI
Express host system or standalone with an external wall power module.
The 12 V DC input power source is fused with a surface mounted fuse, as noted in Table 1.
Table 1. Board Power Supply Fuses (See Appendix A, Sheet 2, Figure 11- Voltage Regulators)
Fuse Designator
F1
Description
12 V Input Supply Fuse
The board may be plugged into a host PC. Only plug the board into a PCI Express slot when the system is powered
off. Once inserted, the PC can be safely powered on.
Using the evaluation board outside of a PC chassis supply requires the factory-supplied wall supply module. Use of
other supplies is not suggested.
Figure 2. Power Distribution Scheme (See Appendix A, Sheet 2, Figure 11- Voltage Regulators)
EN
LDO
SERDES VCCA0: 1.1 V, 0.5 A
Status LED: D12
EN
LDO
12 V, 5 A fused
Status LED: D13
SERDES VCCHTX0: 1.1 V, 0.5 A
2.5 V, 1.1 A
Status LED: D31
SW
EN
SW
3.3 V, 1.35 A
Status LED: D9
SW
1.5 V, 1.1 A
Status LED: D11
EN
VCC Core: 1.1 V, 1.35 A
Status LED: D10
SW
3
ECP5 Versa Development Board
Programming/FPGA Configuration
The ECP5 Versa Development Board has a built-in download controller for programming the ECP5 FPGA. The
built-in module consists of a USB Type-B connector and a USB UART device. To use the built-in download cable,
simply connect a standard USB cable (a USB-B to USB-A cable is included with the ECP5 Versa Development Kit)
from J2 to your PC (with Diamond programming software installed). The USB hub on the PC will detect the addition
of the USB function, making the built-in cable available for use with the Diamond programming software. The USB
cable is connected in parallel to J3.
Alternate Programmer Download Interface
J3 is a 10 pin JTAG connector that is provided for use with an external Lattice download cable (available separately). A USB download cable can be attached to the board using J3 to interface with the FPGA (U1).
Note: Resistors R38, R33, R32 and R36 need to be removed for programming with J3.
The same interface can be used to access the ispClock 5406D clock device (U13) by reconfiguring the jumpers on
J50 (See Appendix A, Sheet 3, Figure 12 - Programming). U13 is factory-programmed for use with the reference
designs and should only be altered for customized designs.
Table 2. JTAG Connector Pinout (J3) (See Appendix A, Sheet 3, Figure 12 - Programming)
Pin
Function
1
PWR
2
TDO
3
TDI
4
PROGRAMn
5
N/C
6
TMS
7
GND
8
TCK
9
DONE
10
INITn
Diamond Programmer Requirements
Note: This board includes the built-in download module and only requires the USB cable included with the board.
After initial board setup, use the following procedure to program the board. Instructions assume that Diamond Programmer software has been installed on a local PC.
Requirements:
• PC with Diamond Programmer 3.5.1 (or later) programming software, installed with appropriate drivers (USB
driver for USB cable).
Note: An option to install these drivers is included as part of the Diamond Programmer setup.
4
ECP5 Versa Development Board
Setting the Configuration Mode
The ECP5 device on the ECP5 Versa Development Board supports a variety of configuration modes, including
1149.1 JTAG and Master SPI. Refer to TN1260, ECP5 sysCONFIG Usage Guide. On the PCB version Rev B, use
the CFG Setting Dip Switch SW4 described in Table 3.
Table 3. CFG[2:0] Selection – Rev B
CFG[2:0]
SW4.3
SW4.2
SW4.1
1149.1 JTAG only
Configuration Mode
000
Down
Down
Down
Slave SPI
001
Down
Down
Up
Master SPI
010
Down
Up
Down
SCM (Slave_Serial)
101
Up
Down
Up
SCM (Slave_Parallel)
111
Up
Up
Up
Board Programming
Configuration Status Indicators
(See Appendix A, Sheet 3, Figure 12 - Programming)
Figure 3. ECP5 Status LEDs and Push-button Controls
The LEDs indicate the configuration status of the ECP5 FPGA.
• D17 (red) illuminated indicates that programming was aborted or reinitialized, driving the INITN output low.
• D20 (green) illuminated indicates the successful completion of configuration by releasing the open collector
DONE output pin.
• D19 (red) illuminated indicates that PROGRAMN is low.
• D18 (red) illuminated indicates that GSRN is low.
5
ECP5 Versa Development Board
PROGRAMN and GSRN
These push-button switches assert/de-assert the logic levels on PROGRAMN (SW2) and GSRN (SW1). Depressing the button drives a logic level “0” to the device.
Programming Serial SPI Flash Memory
A serial SPI (16-pin TSSOP, 128M) Flash memory device (U52) is on-board for non-volatile configuration memory
storage. A Micron N25Q128A device is populated on-board.
The Serial SPI Flash memory device can be configured easily via the ECP5 JTAG port. This mode enables the
FPGA to be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
1. Connect the ECP5 Versa Development Board.
2. Scan the board or select the LFE5UM-45F device in the ECP5UM device family.
3. From the Edit pull down menu select Device Properties. Set the Access mode to SPI Flash Background Programming and Operation to SPI Flash Erase, Program, Verify.
Figure 4. Diamond Programmer Main Screen
4. Under the SPI Flash Options, select Family to SPI Serial Flash, Vendor to Micron, Device to SPI-N25Q128A,
Package to 16-pin SO16.
6
ECP5 Versa Development Board
Figure 5. Device Properties Dialog Box
5. Click OK in the Device Properties dialog box. You will return to the main configuration screen.
6. Set J50 jumper to ECP5 programming (See Appendix A, sheet 3 "Programming")
7. From the main programming window, select Program from the top toolbar. This begins the SPI Serial Flash
programming. Note that the SPI Flash Background Programming operation is only possible when the ECP5
device is either erased or the active design has the MASTER_SPI_PORT mode enabled. For more details see
TN1260, ECP5 sysCONFIG Usage Guide.
7
ECP5 Versa Development Board
On-Board Clock Capabilities
(See Appendix A, Sheet 9, Figure 18 - Reference Clock Generator)
The ECP5 Versa Development Board allows for several clock source options. Some of these options are controlled
via the ispClock5406D programmable clock manager device. The ispClock5406D enables the reference clock from
the PCI Express interface to provide a reference clock to the SERDES. This is true only when the board is in a PCI
Express host socket. When the board is not in a PCI Express host socket, the clock will be supplied by a 156.25
MHz clock on-board oscillator. Both clock inputs can be fanned out to the dedicated SERDES reference inputs,
FPGA inputs, and to the expansion connectors. The factory default programming only connects the SERDES reference clock inputs. Factory-defined demonstration designs will control and manage the clock.
Figure 6. Clock Controller Scheme
PCLKT0
A4
FPGA Clock
PCLKC0
A5
PCIE_PRSNT#
SERDES D0
Reference
Clock
PCI Express
0
156.25 MHz
On-board
Oscillator
1
REFCLKP_D0
Y11
REFCLKN_D0
Y12
Factory Default
Clock Programming
SERDES D1
Reference
Clock
REFCLKP_D1
Y19
REFCLKN_D1
W20
Expansion Interface
Clock(X3)
8
ECP5 Versa Development Board
General Purpose Clock Source
An on-board 100 MHz LVDS oscillator is provided for general purpose use. This clock source is connected to differential inputs P3 and P4 and must be used as LVDS inputs to the FPGA. This pin pair also provides optimal interface to the FPGA PLL for customized use.
The PCI Express add-in card specification requires add-in boards to include capabilities to tell the host of its presence. The ECP5 Versa Development Board allows this optional connection via a board jumper. Using the board
with a PCI Express host requires the setting shown in Figure 7 below.
Figure 7. PCI Express PRSNT Control Connection
J4
1
2
3
4
5
6
PCI Express PRSNT
Jumper Selector
SERDES
The ECP5 Dual Channel Unit (DCU) SERDES FPGA is utilized on the board for several purposes. DCU0, Channel
0 is provisioned to provide a single, full-duplex PCI Express channel. The high-speed signals are connected to the
PCI Express edge connection. DCU0, Channel 1 is connected to the SMA connectors for external electrical demonstrations.
Table 4. PCI Express Channel Interconnections
Signal Name
SERDES Port
FPGA Ball Number
PETp0
HDRXP0_D0CH0
Y5
PETn0
HDRXN0_D0CH0
Y6
PERp0
HDTXP0_D0CH0
W4
PERn0
HDTXN0_D0CH0
W5
SERDES Port
FPGA Ball Number
J5
HDRXP0_D0CH1
Y7
J6
HDRXN0_D0CH1
Y8
J7
HDTXP0_D0CH1
W8
J8
HDTXN0_D0CH1
W9
Table 5. SMA Test Interconnections
Connector
9
ECP5 Versa Development Board
FPGA Test Pins
(See Appendix A, Sheet 8, Figure 17 - LEDs and Switches)
General Purpose DIP Switches
General purpose FPGA pins are available for user applications. FPGA pins are connected to switch SW3, a SPST
slide-actuated DIP switch. The switches are connected to logic level 0 when moved to the ON position. Switch position 1 is indicated with an arrow. Inputs 1-4 are within a 1.5 V bank and inputs 5-8 are within a 2.5 V bank. The user
must program inputs 1-4 to be the LVCMOS15 type and inputs 5-8 to be the LVCMOS25 type in the design.
Figure 9 shows the switches. Note the silk marking associated with SW3-7 is incorrect in revision B, SW3-7 is
mapped to K19, per Table 6.
Figure 8. ECP5 Versa Development Board LEDs and Switches
The designated pins are connected according to Table 6.
Table 6. FPGA Ball to DIP Switch Position
FPGA Ball Number
SW3 DIP Switch Position
H2
1
K3
2
G3
3
F2
4
J18
5
K18
6
K19
7
K20
8
10
ECP5 Versa Development Board
General Purpose LEDs
(See Appendix A, Sheet 8, Figure 17 - LEDs and Switches)
The LEDs provided on the ECP5 Versa Development Board are connected to general purpose FPGA I/Os. These
LEDs provide status for user designs and must be included in the design. The LEDs illuminate when the FPGA output is driven LOW. Table 7 shows the LED and associated FPGA pins. These pins are within an I/O bank connected to 2.5 V and the user should program these to be LVCMOS25 type outputs in the design.
Table 7. LED Definitions
LED Designator
FPGA Ball Number
LED Color
D25
E16
Yellow
D24
D17
Yellow
D22
D18
Green
D21
E18
Green
D26
F17
Red
D27
F18
Red
D28
E17
Red
D29
F16
Red
Alpha-numeric LED Display
(See Appendix A, Sheet 8, Figure 17 - LEDs and Switches)
A 14-segment alpha-numeric display is provided on the board (D23). These LED segments are connected to general-purpose FPGA I/Os. The LEDs must be included in the FPGA design. The LEDs illuminate when the FPGA
output is driven LOW. Table 8 shows the LED and associated FPGA pins. These pins are within an I/O bank connected to 2.5 V and the user should program these to be LVCMOS25 outputs in the design.
Figure 9. 14-Segment Display
11
ECP5 Versa Development Board
Table 8. Alpha-numeric LED Definitions
Display
FPGA Ball Number
Display
FPGA Ball Number
A
B
M20
J
N18
L18
K
P17
C
D
M19
L
N17
L16
M
P16
E
L17
N
R16
F
M18
P
R17
G
N16
DP
U1
H
M17
DDR3 Memory Device
(See Appendix A, Sheet 7, Figure 16 - DDR3 Memory)
• The ECP5 Versa Development Board is equipped with an SDRAM memory device (1.5 V, 64 Mb/x16, 96-ball
FBGA, 933 MHz, DDR3-1866) such as the Micron MT41K64M16TW-107:J device.
• The DDR3 memory includes a 16-bit wide memory controller interface.
• The board includes termination of data, address and command signals. It includes all power and external components needed to demonstrate the memory controller of the ECP5 device.
• A 100 MHz on-board clock oscillator is available to provide a DDR3 reference clock.
12
ECP5 Versa Development Board
Table 9. DDR3 Memory Controller Interconnections
FPGA Ball
Number
DDR3 Signal
FPGA Ball
Number
DDR3 Signal
DQ0
L5
A0
P2
DQ1
F1
A1
C4
DQ2
K4
A2
E5
DQ3
G1
A3
F5
DQ4
L4
A4
B3
DQ5
H1
A5
F4
DQ6
G2
A6
B5
DQ7
J3
A7
E4
DQ8
D1
A8
C5
DQ9
C1
A9
E3
DQ10
E2
A10
D5
DQ11
C2
A11
B4
DQ12
F3
A12
C3
DQ13
A2
K_0
M4
DQ14
E1
K_0#
N5
DQ15
B1
CAS#
L1
DQS0
K2
BA0
P5
DQS0#
J1
BA1
N3
DQS1
H4
BA2
M3
DQS1#
G5
ODT
L2
CE0
N2
CS0#
K1
RAS#
P1
WE#
M1
CLKP
P3
VREF
K5
CLKN
P4
DM0
J4
RST#
N4
DM1
H5
13
ECP5 Versa Development Board
Ethernet Interfaces
(See Appendix A, sheets 5 and 6 "10/100/1000-T PHY#x/RJ45")
Two Marvell 88E1512 Gigabit Ethernet transceiver devices (U14 and U15) are included on the board. These physical layer devices support 1000BASE-T, 100BASE-TX, and 10BASE-T applications via a standard media interface
to a dual RJ45 connection. The RJ45 connection includes network magnetics providing the proper signal conditioning, electro-magnetic interference suppression and signal isolation. Each connector includes two LEDs which are
controlled by the 88E1512 devices. Detailed descriptions are available in the Marvell device data sheet.
Table 10. PHY Status Indicators
LED
Status Description
RJ45 (Yellow)
Data RX/TX
RJ45 (Green/Orange)
Link State
Each Marvell 88E1512 device communicates via a RGMII interface to the ECP5 device.
Table 11. FPGA GPIO to RGMII Interfaces
Phy1
Phy2
CLK125
Signal
L19
J20
CLK125Pll
U16
C18
Config
T17
G20
Resetn
U17
F20
TXCLK
P19
C20
TX_D0
N19
J17
TX_D1
N20
J16
TX_D2
P18
D19
TX_D3
P20
D20
TXCTRL
R20
E19
RXCLK
L20
J19
RX_D0
T20
G18
RX_D1
U20
G16
RX_D2
T19
H18
RX_D3
R18
H17
RXCTRL
U19
F19
MDIO
U18
H20
MDC
T18
G19
14
ECP5 Versa Development Board
Table 12. Expansion Connections
X3 Expansion Connector
Pin
X4 Expansion Connector
FPGA Ball
Number
Signal
Pin
FPGA Ball
Number
Signal
1
RESOUT#
A8
2
GND
—
2V5
—
—
—
3
IO0
A12
4
IO29
B19
4
IO1
A13
5
IO30
B12
5
IO2
B13
6
IO31
B9
6
IO3
C13
7
IO32
E6
7
IO4
D13
8
IO33
D6
8
IO5
E13
9
IO34
E7
9
IO6
A14
10
IO35
D7
10
IO7
C14
11
IO36
B11
11
IO8
D14
12
IO37
B6
12
IO9
E14
13
IO38
E9
13
IO10
D11
14
IO39
D9
14
IO11
C10
15
IO40
B8
15
IO12
A9
16
IO41
C8
16
IO13
B10
17
IO42
D8
17
IO14
D12
18
IO43
E8
18
IO15
E12
19
IO44
C7
19
GND
20
IO45
C6
20
3V3
—
—
21
5VIN
21
IO16
B15
22
GND
22
GND
—
23
2V5
23
IO17
C15
24
GND
24
GND
—
25
3V3
25
IO18
D15
26
GND
26
GND
—
27
3V3
27
IO19
E15
28
GND
28
IO20
A16
29
OSC
29
IO21
B16
30
GND
—
—
—
—
—
—
—
—
—
—
30
GND
—
31
CLKIN
A10
31
IO22
C16
1
GND
2
NC
3
32
GND
—
32
IO23
D16
33
CLKOUT
E11
33
IO24
B17
34
GND
GND
—
3V3
35
IO25
C17
36
GND
36
IO26
A17
37
3V3
37
IO27
B18
38
GND
38
CARDSEL#
A7
39
3V3
39
IO28
A18
40
GND
—
—
—
—
—
—
—
34
35
40
GND
—
15
ECP5 Versa Development Board
References
• DS1044, ECP5 Family Data Sheet
• UG98, PCI Express Demos for the ECP5 Versa Development Board
• UG97, DDR3 Demo for the ECP5 Versa Development Board
• UG93, SERDES Eye Demo for the ECP5 Versa Development Board
• UG92, SEU (Single Event Upset) Demo for the ECP5 Versa Development Board
Ordering Information
Description
Ordering Part Number
ECP5 Versa Development Board
LFE5UM-45F-VERSA-EVN
China RoHS Environment-Friendly
Use Period (EFUP)
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
Revision History
Date
Version
Change Summary
November 2015
2.1
Updated Introduction section. Indicated Dual RJ45 Ethernet ports and
corrected USB Programming callout in Figure 1, ECP5 Versa Development Board, Top Side.
Updated General Purpose LEDs section. Revised FPGA ball numbers
in Table 7, LED Definitions.
Updated Appendix A. Schematics section. Revised LEDs signal map in
Figure 17, LEDs and Switches.
Updated Appendix B. Bill of Materials section. Revised description of
item 111.
Updated Setting the Configuration Mode section in Appendix C.
Changed Figure 20, CFG[2:0] Setting Resistor Field – Revision A.
August 2015
2.0
Updated to support Rev B of development board.
July 2015
1.1
Added Setting the Configuration Mode section.
Updated Technical Support Assistance section.
Added ECP5 Versa Development Board Bill of Materials section.
March 2015
1.0
Initial release.
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
16
17
A
B
C
RefClk
5
156.25M OSC
PCIe
100.00M
DIFF OSC
CLK5406
Device
Power
Pins
REFERENCE
CLOCKS
DDR3
1.5V
16-Bit
4
Expansion Clk
General Clk
SERDES D0
RefClk
3
PCIe X1
CH#0
Bank
8
Bank 6
Bank 7
3
SMA Test
CH#3
Bank 3
Bank 2
Bank 1
SERDES
ECP5
FPGA
Bank 0
Expansion
Port- 3.3V
Designator U1 is the FPGA DUT.
Expansion
Port-3.3V
Programming
3.3V SPI
PLL
Power
4
PCSA
D
5
2.5V
RGMII
PHY#2
2.5V
RGMII
PHY#1
2
2
Date:
B
Size
Friday, August 21, 2015
ECP5 VERSA Eval Board
Project
1
Sheet
Lattice Semiconductor Applications
Email: [email protected]
Board Block Diagram
Title
LED SEGMENT
ARRAY
1
Bank 6,7
USER DIP
SWITCH
JPB
EK
Bank 2
Rev A Final Design
Rev B Final Design
USER LEDS
Revision History:
Nov 13, 2014
March 27, 2015
Schematic Rev
Board Rev
of 11
1
B
B
A
B
C
D
ECP5 Versa Development Board
Appendix A. Schematics
Figure 10. Board Block Design
A
B
C
D
RESERVED2
RESERVED1
NC1
NC2
VCCAUXA1
VCCAUXA1
VCCAUXA0
VCCAUXA0
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCA1
VCCA1
VCCA0
VCCA0
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
U10
U11
U12
U13
U14
U7
U8
U9
V12
V13
V14
V15
V16
V19
V20
V5
V6
V7
V8
V9
W12
W15
W16
W19
W6
W7
Right angle
mount, cable
to board edge
J11
12_0V
12_0V
TP3
+11v to +16v
5
POWER INPUT
VCCA0
C3
+
C20
C36
C4
10NF-0402SMT
10NF-0402SMT
FB4
BLM41PG600SN1
2_5V
C23
TP1
SW
D14
SCHOTTKY/VISHAY-V12P10
12_0VIN
TP4
1_5V, +1.5 V, 1.1 A
SW
LED_BLUE_0603
D13
4
12VIN GOOD
1_8K-1206SMT
R25
12_0V
C25
+
3_3V
R22
Q1
2N2222/SOT23
R27
1
10K-0603SMT
D10
2_5V
8
7
6
5
TP5
C41
R185
110K-0603SMT
LT3085
TP15
TP20
C55
R23
1_8K-1206SMT
3
VCCA
L1
RLP-133
TP21
L3
RLP-133
C63
100pF-0402SMT
R21
10K-0603SMT
1%
C245
R15
3_83K-0603SMT
1%
0.1
4.7uH-SPD62R-472M
1%
D7
cr2010_alt1
DFLS220L
R67
C52
220NF-0402SMT
16V
Vout = 0.8*(R7/R9+1) = 2.52
22uF,6.3V-0805SMT
10K-0603SMT
R9
1%
R28
1
10K-0603SMT
Q3
2N2222/SOT23
R24
1_8K-1206SMT
12_0V
R70
3_3V
R29
1
10K-0603SMT
LED_GREEN_0603
D12
VCCA
1.1V
Analog
FB3
22
23
24
2
1
8
7
8
7
1%
22
23
24
RT/SYNC
PG1
VC1
RT/SYNC
PG1
VC1
TRACK/SS1
FB1
SW1
BOOST1
FB2
SW2
BOOST2
PG2
VC2
2
3.3V
R26
220R-0603SMT
R179
220R-0603SMT
D9
LED_GREEN_0603
3_3V
20
19
17
18
11
12
20
19
17
18
11
12
U4
LT3508EUF
12_0V
TRACK/SS2
R14
51K-0402SMT
PG2
VC2
TRACK/SS2
FB2
SW2
BOOST2
U3
LT3508EUF
12_0V
DNI
1
D2
1N4448W
3_3V
3_3V
Date:
C
Size
Friday, August 21, 2015
1
Sheet
Lattice Semiconductor Applications
Email: [email protected]
Board Rev
of 11
2
Schematic Rev
v
22uF,6.3V-0805SMT
RLP-133
1_5V
C58
ECP5 VERSA Eval Board
Project
+1.5v
1.1 A
1.2v/ms
RLP-133
Vout = 0.8*(R16/R17+1) = 1.51
1.2v/ms
1.5V
DDR3
TP18
0.1
1%
cr2010_alt1
R66
C64
22uF,6.3V-0805SMT
100pF-0402SMT
R17
16_9K-0603SMT
1%
C246
15K-0603SMT
R16 1%
D8
DFLS220L
Voltage Regulators
Title
R20
20K-0402SMT
TP19
1_5V Current
4.7uH-SPD62R-472M
L4
C53
220NF-0402SMT
16V
v
22uF,6.3V-0805SMT
RLP-133
C42
+3.3 v
1.35 A
3.3V
3_3V
TP17
0.1
1%
cr2010_alt1
R64
RLP-133
C50
22uF,6.3V-0805SMT
1%
R13
11_5K-0603SMT
1%
R8
35_7K-0603SMT
D4
DFLS220L
Vout = 0.8*(R8/R13+1) = 3.28
C57 1000pF-0402SMT
D6
1N4448W
R12
51K-0402SMT
TP16
3_3V Current
4.7uH-SPD62R-472M
L2
C39
220NF-0402SMT
16V
SERDES VCCA
1.1V Power
SERDES VCCHTX
1.2V Power
C44 1000pF-0402SMT
+1.1 v
500 mA
1UF-16V-0805SMT
C101
VCCA1
1UF-16V-0805SMT
C27
VCCA0
1UF-16V-0805SMT
C103
+1.2 v
500 mA
1UF-16V-0805SMT
VCCHTX1
R6
51K-0402SMT
TRACK/SS1
FB1
SW1
BOOST1
VCCHTX0
C19
2.5V
D31
+ C102
22UF-16V-TANTBSMT
BLM41PG600SN1
FB7
LED_GREEN_0603
2_5V
+ C26
22UF-16V-TANTBSMT
BLM41PG600SN1
C51
10uF,25V-1206SMT
RLP-134
v
+ C104
22UF-16V-TANTBSMT
BLM41PG600SN1
FB8
1000pF-0402SMT
DNI
+ C18
22UF-16V-TANTBSMT
1
C56 1000pF-0402SMT
2
D5
1N4448W
v
C43
D1
1N4448W
3_3V
VCCA
current
FB2
BLM41PG600SN1
2
C37
10uF,25V-1206SMT
RLP-134
TP23
0.1
1%
cr2010_alt1
TP22
Vout = 0.8*(R15/R21+1) = 1.10
TP25
0.01
1% cr2512_alt1
R140
VCCHTX
current
TP24
C38
16V
220NF-0402SMT
100NFX5R-0402SMT
C248
C393
RLP-133
R7
21_5K-0603SMT
1%
C49
LED_GREEN_0603
D11
1_5V
1.5V
C247
0.1
4.7uH-SPD62R-472M
1%
D3
cr2010_alt1
DFLS220L
R63
VCCHTX
C392
RLP-133
100NFX5R-0402SMT
22uF,6.3V-0805SMT
22uF,6.3V-0805SMT
12_0V
Q2
2N2222/SOT23
9
1
2
3
4
1_1V Current
RLP-133
VCC_CORE
1.2v/ms
C54
22uF,6.3V-0805SMT
RLP-133
U54
Pad
IN_8 OUT_1
IN_7 OUT_2
IN_6 OUT_3
VCtrl SET
22uF,6.3V-0805SMT
+1.1 v
1.35 A
9
1
2
3
4
R184
121K-0603SMT
LT3085
RLP-133
Core Power
VCC_CORE
U53
Pad
IN_8 OUT_1
IN_7 OUT_2
IN_6 OUT_3
VCtrl SET
2_5V Current
2_5V
C40
22uF,6.3V-0805SMT
RLP-133
1.2v/ms
+2.5v
1.1 A
2.5V
C394
1UF-16V-0805SMT
RLP-133
1.1V
VCC_CORE
LED_GREEN_0603
12_0V
8
7
6
5
Voltage Regulators
0.45 v drop at 500 mA max
C391
1UF-16V-0805SMT
RLP-133
2_5V
3
10uF-6.3V-0805SMT
C11
C24
C9
1_8K-1206SMT
VCC_CORE, +1.1 V, 1.35 A
3_3V, +3.3 V, 1.35 A
EN
100NF-0402SMT
SERDES VCCHTX0, +1.1 V, 0.5A
2_5V, +2.5V, 1.1 A
LDO
EN
C8
100NF-0402SMT
SERDES VCCA0, +1.1 V, 0.5A
SW
EN
SW
LDO
EN
C7
C22
C6
C21
C5
Power Supply Block Diagram
C35
C2
C34
C1
C33
C31
VCCA1
C94
C32
(5A fused)
TP2
NC
NC
NC
NC
C29
VCCA1
C95
VCCA0
VCCAUX
C28
C30
F1251CT-ND
F1
W11
W10
K16
K17
V17
V18
V10
V11
F15
F6
P15
P6
T15
U15
T6
U6
100NF-0402SMT
5A Fast-Blo SMT Socketed Fuse
12_0VIN
1
LFE5UM-45F-BG381
Schematic symbols rev 4.1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U1I
LFE5UM-45F-BG381
Schematic symbols rev 4.1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
10NF-0402SMT
10NF-0402SMT
U1J
Male Power Jack 2.1mm
3
PJ-002A
B14
B7
C19
D4
F13
F14
F7
F8
G10
G11
G12
G13
G14
G15
G17
G4
G6
G7
G8
G9
H19
J10
J11
J12
J14
J2
J7
J9
K10
K11
K12
K14
K15
K6
K7
K9
L10
L11
L12
L9
M10
M11
M12
M14
M16
M2
M7
M9
N14
N15
N6
N7
P11
P12
P13
P14
P7
P8
R19
H10
H11
H12
H13
H8
H9
J13
J8
K13
K8
L13
L8
M13
M8
N10
N11
N12
N13
N8
N9
2
10NF-0402SMT
1NF-0402SMT
100NF-0402SMT
1NF-0402SMT
10NF-0402SMT
1NF-0402SMT
100NF-0402SMT
10NF-0402SMT
1UF-16V-0805SMT
10NF-0402SMT
22UF-16V-TANTBSMT
10NF-0402SMT
10NF-0402SMT
100NF-0402SMT
100NF-0402SMT
100NF-0402SMT
1UF-16V-0805SMT
100NF-0402SMT
100NF-0402SMT
G
21
VCC_CORE
G
1
2
10uF-6.3V-0805SMT
C45
330pF-0402SMT
2
1
10
22UF-16V-TANTBSMT
G
3
2
G
3
2
3
2
1
2
C46
10pF-0402SMT
C60
10pF-0402SMT
2
1
C59
330pF-0402SMT
R11
34K-0402SMT
R18
63_4K-0402SMT
21
9
VIN1
GND5
4
G
R10
51K-0402SMT
R19
30_1K-0402SMT
1%
SHDN
GND1
GND2
GND3
GND4
3
4
5
6
SHDN
GND1
GND2
GND3
GND4
3
4
5
6
9
25
C48
330pF-0402SMT
VIN2
GND6
GND7
GND8
GND9
13
14
15
16
10
25
VIN1
GND5
G
C47
10pF-0402SMT
C61
10pF-0402SMT
1
2
2
1
2
1
C62
330pF-0402SMT
VIN2
GND6
GND7
GND8
GND9
13
14
15
16
1
18
2
5
B
B
A
B
C
D
ECP5 Versa Development Board
Figure 11. Voltage Regulators
A
B
C
8
TP49
TP50
TP51
PROGRAMN
FPGA GSRN
SW1
A2 B2
A1 B1
4
3
A2 B2
A1 B1
4
3
SpiCSSPIN
SpiSI
DQ2
5
GSRN
3_3V
TP42
TP43
TP44
TP45
7
8
9
10
3
4
5
6
8
7
6
5
CS
CLK
DI
DO
2
1
1
2
3
4
U52
N25QxxxA13xSF
S#
VCC
DQ1
HOLD#/DQ3
W#/VPP/DQ2
C
VSS
DQ0
DNU_3
DNU_14
DNU_4
DNU_13
DNU_5
DNU_12
DNU_6
DNU_11
3
R35 0R-0402SMT
R39 0R-0402SMT
2
1
16
15
14
13
12
11
3_3V
680R-0603SMT
R55
3_3V
Q4
2N2222/SOT23
C286
20pF-0603SMT
DNI
TP38
TP39
TP40
TP41
0R-0402SMT
0R-0402SMT
R133
4
DQ3
SpiMCLK
SpiSO
TP46
TP47
TP48
C244
100NFX5R-0402SMT
R131
C243
C287
20pF-0603SMT
DNI
R95
RLP-101
4_7K-0603SMT
13
3
2
63
62
61
INITN
FT2232H
TP14
C85
3_3V
DONE
C84
DONE
1
R65
10K-0603SMT
P10
P9
3_3V
PWREN#
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
Bank 8
R68
10K-0402SMT
36
60
48
52
53
54
55
57
58
59
38
39
40
41
43
44
45
46
26
27
28
29
30
32
33
34
3
LFE5UM-45F-BG381
Schematic symbols rev 4.1
C69
R58
R57
3_3V
3_3V
SpiMCLK
50R-0603SMT
SEG14
SDA
[9]
[8]
[9]
CLK_RESETn [9]
SCL
CFG0
CFG1
CFG2
2
DONE
INITn
R190
TCK
TMS
NC
VCC
7
1
3_3V
2
4
6
HEADER 3X2
1
3
5
J50
TMS
GND
TCK
DONE
INITn
+3.3V
TDO
TDI
PROGRAMn
Local JTAG
header (ispVM)
100NF-0603SMT
ispCLOCK_TDI
[9]
ispCLOCK_TDO [9]
FTDI_TDI
FTDI_TMS
FTDI_TCK
1
1
418311170804
2
Date:
C
Size
3
4
5
SW4
6
7
8
ECP5
only
Friday, August 21, 2015
1
Sheet
[9]
[9]
Board Rev
of 11
3
Schematic Rev
FTDI_TMS
FTDI_TCK
Lattice Semiconductor Applications
Email: [email protected]
ispCLOCK
only
ECP5 VERSA Eval Board
Project
Programming
Title
1K-0603SMT
R192
ECP5 +
ispCLOCK
Default Jumper Settings:1&2, 3&4, 5&6
ECP5_TDI
ECP5_TDO
FTDI_TDO
HEADER 10
INITN
GND
ispEN_N
TDI
TDO
DONE
J3
2
3
4
5
6
8
9
10
1K-0603SMT
R191
3_3V
PROGRAMn
1K-0603SMT
Remove internal names in symbol?
DONE
INITN
SpiSI
SpiSO
FPGA_CSN
FPGA_CS1N
SpiCSSPIN
SCL
FPGA_WRITEN
CLK_RESETn
GSRN
SEG14
SDA
DQ3
DQ2
PROGRAMN
FTDI_TCK
ECP5_TDI
ECP5_TDO
FTDI_TMS
R187
Place R187 near U1
U3
U4
T4
R4
Y3
V3
V2
W2
T2
U2
R2
R3
T3
R1
T1
U1
V1
W1
Y2
W3
T5
R5
V4
U5
D15
3_3V
TXD_UART [9]
RXD_UART [9]
R75
2_2K-0603SMT-DNI
DNI
4_7K-0603SMT
R59
D16
R76
0R-0603SMT-DNI
DNI
TXD_UART
RXD_UART
UART_ACT
FTDI_TMS
FTDI_TCK
R49
4_7K-0603SMT
3_3V
3_3V
2
R45
R46
R47
4_7K-0603SMT
4_7K-0603SMT
4_7K-0603SMT
FTDI_TDO
FTDI_TDI
C70
R71
2_2K-0603SMT-DNI
DNI
R36 0R-0603SMT
R32 0R-0603SMT
R33 0R-0603SMT
R38 0R-0603SMT
JTAG_ACT
4_7K-0603SMT
R69
10K-0402SMT
SUSPEND#
3_3V
16
17
18
19
21
22
23
24
C68
C67
3_3V
100NF-0402SMT
CCLK/MCLK/SCK
CFG_0
CFG_1
CFG_2
DONE
INITN
PB11A/D1/MISO/IO1
PB11B/D0/MOSI/IO0
PB13A/SN/CSN/SCAN_SHFT_EN
PB13B/CS1N
PB15A/HOLDN/DI/BUSY/CSSPIN/CEN
PB15B/DOUT/CSON/ATB_FORCE
PB18A/WRITEN/ATB_SENSE
PB4A/D7/IO7
PB4B/D6/IO6
PB6A/D5/MISO2/IO5
PB6B/D4/MOSI2/IO4
PB9A/D3/IO3
PB9B/D2/IO2
PROGRAMN
TCK/TEST_CLK
TDI
TDO
VCCIO8
TMS
VCCIO8
U1G
TP9
DONE indicator will light when
configuration is successfully
completed
INITN
LED_RED_0603
FTVCC1_8V
FTDI High-Speed USB
TEST
OSCO
OSCI
EECS
EECLK
EEDATA
REF
RESET#
DM
DP
VREGOUT
VREGIN
INITN indicator will light
if an error occurs during
configuration programming
R60
D17
680R-0603SMT
R
3_3V
14
7
8
49
50
U5
FT2232HL
6
R44
12K-0603SMT
R40
4_7K-0402SMT
3_3V
C72
100NF-0402SMT
C66
100NF-0402SMT
2_2K-0603SMT
D20
DI
PROGRAMN
D19
LED_RED_0603
680R-0603SMT
R56
R48
USB_N_i
USB_P_i
CONFIG Status LEDs
GSRN
D18
3_3V
R50
1M-0603SMT
DI
+
FTVCC1_8V
C71
4_7UF-10V-SMT
C65
4_7UF-10V-SMT
C74
3_3UF-10V-SMT
2
FB6
MPZ1608Y600B +
DI
1
C80
12PF-0603SMT
DI
LED_RED_0603
4
3
3_3V
12MHZ
DI
G1 G2
1
Y1
USB1_CS
USB1_SK
USB1_D
USB1_Q
R96
1K-0603SMT
RLP-101
128Mb SPI Flash
TP8
TP7
USB_N
USB_P
R41
R42
R43
10K-0402SMT 10K-0402SMT 10K-0402SMT
93LC56C-I/SN
VCC
NU
ORG
VSS
U6
C79
12PF-0603SMT
DI
R135
4_7K-0603SMT
RLP-101
C115
100NF-0402SMT
PROGRAMN
C114
100NF-0402SMT
0R-0402SMT
0R-0402SMT
0R-0402SMT
C249
20pF-0603SMT
DNI
R129
R130
R134
3_3V
C77
100NF-0402SMT
R53
10K-0402SMT
R136
4_7K-0603SMT
RLP-101
PTS645SM43SMTR92 LFS
2
1
SW2
PTS645SM43SMTR92 LFS
2
1
R51
10K-0402SMT
3_3V
USB Download
SKT_MINIUSB_B_RA
PROGRAMN
& GSRN
Pushbuttons
L5
1
2
3
4
5
1UH-1206SMT
8
9
9
7
7
6
6
J2
VCC
DD+
ID
GND
Y
GSRN
R37
15K-0603SMT-DNI
DNI
C81
2
FB5
MPZ1608Y600B +
DI
PROGRAMN Y
D
100NF-0402SMT
1
R61
LED_GREEN_0603
10
100NF-0402SMT
3_3V
220R-0603SMT
G
3
2
12
37
64
VCORE
VCORE
VCORE
3
4_7K-0603SMT
4
10NF-0402SMT
INITN
100NF-0603SMT
FPGA_CS1N
4
9
VPHY
VPLL
AGND
100NF-0402SMT
R31
LED_GREEN_0603
20
31
42
56
DONE
10NF-0402SMT
R30
LED_GREEN_0603
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
GND
GND
GND
GND
1
5
11
15
25
35
47
51
220R-0603SMT
G
UART_ACT
220R-0603SMT
G
JTAG_ACT
100NF-0402SMT
FPGA_CSN
19
FPGA_WRITEN
C78
5
B
B
A
B
C
D
ECP5 Versa Development Board
Figure 12. Programming
20
A
B
C
C90
VCCHTX0
SMA
2
3
4
5
SMA
1
J8
1
HDTXP0_D0CH1
1
SMA
2
3
4
5
J7
HDRXP0_D0CH1
SMA
1
J5
HDTXN0_D0CH1
HDRXN0_D0CH1
REFCLKP_D1
REFCLKN_D1
5
4
100NFX5R-0402SMT
REFCLKP_D1
REFCLKN_D1
[9]
[9]
HDRXP0_D1CH1 [6]
HDRXN0_D1CH1 [6]
HDRXP0_D1CH0 [5]
HDRXN0_D1CH0 [5]
HDTXP0_D1CH0 [5]
HDTXN0_D1CH0[5]
HDTXP0_D1CH1 [6]
HDTXN0_D1CH1[6]
[9]
[9]
[3]
C86
C87
PCIE_PERSTN
PHY 1 & 2
SGMII
100NFX5R-0402SMT
REFCLKP_D0
REFCLKN_D0
SMA
SMA
All Nets to SMAs are 100-ohm differential pairs.
The P and N traces shall be <20mil matched in length
2
3
4
5
2
3
4
5
C112
C113
C111
C105
VCCA1
C110
VCCHTX1
C106
J6
C93
VCCA0
Y19
W20
HDRXP0_D1CH1
HDRXN0_D1CH1
HDRXP0_D1CH0
HDRXN0_D1CH0
Y14
Y15
Y16
Y17
HDTXP0_D1CH0
HDTXN0_D1CH0
W13
W14
100NF-0402SMT
100NF-0402SMT
C92
REFCLKP_D1
REFCLKN_D1
HDRXP0_D1CH1
HDRXN0_D1CH1
HDRXP0_D1CH0
HDRXN0_D1CH0
HDTXP0_D1CH0
HDTXN0_D1CH0
HDTXP0_D1CH1
HDTXN0_D1CH1
HDTXP0_D1CH1
HDTXN0_D1CH1
REFCLKP_D0
REFCLKN_D0
Y11
Y12
W17
W18
HDRXP0_D0CH1
HDRXN0_D0CH1
x1_PETp0
x1_PETn0
HDTXP0_D0CH1
HDTXN0_D0CH1
HDTXP0_D0CH0
HDTXN0_D0CH0
4
Y7
Y8
10NF-0402SMT
10NF-0402SMT
C91
LFE5UM-45F-BG381
Schematic symbols rev 4.1
SERDES
VCCHRX1_D0CH1
VCCHRX1_D1CH1
VCCHRX0_D0CH0
VCCHRX0_D1CH0
REFCLKP_D0
REFCLKN_D0
HDRXP0_D0CH1
HDRXN0_D0CH1
Y5
Y6
W8
W9
W4
W5
1NF-0402SMT
C89
T9
T13
T8
T12
VCCHTX1_D0CH1
VCCHTX1_D1CH1
HDRXP0_D0CH0
HDRXN0_D0CH0
HDTXP0_D0CH1
HDTXN0_D0CH1
HDTXP0_D0CH0
HDTXN0_D0CH0
100NF-0402SMT
C88
VCCA1
VCCA0
VCCHTX1
T10
T14
1NF-0402SMT
10NF-0402SMT
D
VCCHTX0_D0CH0
VCCHTX0_D1CH0
U1H
100NF-0402SMT
T7
T11
10NF-0402SMT
VCCHTX0
1NF-0402SMT
1NF-0402SMT
3_3V
x1_PERn0
x1_PERp0
3
3
[9]
[9]
R72
4_7K-0603SMT
5
PCIE_CLKP
PCIE_CLKN
R178 OPEN-0603SMT
PRSNT1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V
PERST#
GND
REFCLK+
REFCLKGND
PERp0
PERn0
GND
CN1
+12V
+12V
RSVD_B3
GND
SMCLK
SMDAT
GND
+3.3V
JTAG1
3.3Vaux
WAKE#
RSVD_B12
GND
PETp0
PETn0
GND
PRSNT3#
GND
PCI Express x1 Edge Finger Conn.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
1
3
5
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
[9]
PRSNT3#
x1_PETp0
x1_PETn0
PCIE_3V3 1
PRSNT
X1 PCIe Board Fingers
PRSNT1#
J4
HEADER 3X2
2
4
6
TP6
Testpoint
1
2
Date:
B
Size
Friday, August 21, 2015
ECP5 VERSA Eval Board
Project
SERDES
Title
1
Sheet
Lattice Semiconductor Applications
Email: [email protected]
All Nets are 85-ohm differential pairs.
The P and N traces shall be <20mil matched in length
B side = Primary Component Side(TOP)
A side = Secondary Component Side(BOTTOM)
x1_PERp0
x1_PERn0
PCIE_CLKP
PCIE_CLKN
PCIE_3V3
12_0VIN
PRSNT1#
PRSNT3#
2
4
Schematic Rev
Board Rev
of 11
B
B
A
B
C
D
ECP5 Versa Development Board
Figure 13. SERDES
A
B
C
1
3_3V
2_5V
2
Phy1_Avdd3-3
FB16
Z-600 ohm / 7427926
C250
5
10uF-6.3V-0805SMT
RLP-133
Phy1_RXCTRL
Phy1_RXD0
Phy1_RXD1
Phy1_RXCLK
Phy1_RXD2
Phy1_RXD3
Phy1_Vddo2-5
Phy1_TXD0
Phy1_TXD1
Phy1_Vddo2-5
Phy1_TXCLK
Phy1_TXD2
Phy1_TXD3
Phy1_TXCTRL
R88
R83
R84
R85
R86
R87
C256
100NFX5R-0402SMT
RLP-130-A
C258
100NFX5R-0402SMT
RLP-130-A
C255
0R-0402SMT
0R-0402SMT
R126
R125
Phy1_Mdc
Phy1_Mdio
R292
3
25MHZ
G1 G2
1
DNI
3
4
Phy1_CLK125
Phy1_CLK125PII
2
R90
4_7K-0402SMT
ETH1_MD0_P
ETH1_MD0_N
Phy1_Avdd1-8
Phy1_Avdd3-3
ETH1_MD1_P
ETH1_MD1_N
ETH1_MD2_P
ETH1_MD2_N
Phy1_Avdd3-3
Phy1_Avdd1-8
ETH1_MD3_P
ETH1_MD3_N
Phy1_Resetn
Phy1_Config
3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C254
27pF-0603SMT
RLP-132
4
100NFX5R-0402SMT
100NFX5R-0402SMT
R92
R91
DNI
2_5V
R298
0R-0402SMT
Phy1_Xtal_OUT
Phy1_Avdd1-8
Phy1_CLK125 = L18/GR_PCLK3_1 (Default)
Phy1_CLK125Pll = U16/LRC_GPLL0T_IN
R52
0R-0402SMT
R0_1-3
R89
0R-0402SMT
U44
1
MDIP[0]
MDIN[0]
AVDD18
AVDD33
MDIP[1]
MDIN[1]
MDIP[2]
MDIN[2]
AVDD33
AVDD18
MDIP[3]
MDIN[3]
RESETn
CONFIG
TP10
R294
4.99k
R291
50R-0402SMT
2
1
Y2
100NFX5R-0402SMT
3
100NFX5R-0402SMT
C257
C264
C265
C266
C267
C263
C262
C261
C260
4.7uF-16-0805SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
RLP-133
RLP-130-A RLP-130-A RLP-130-A RLP-130-A
RLP-130-A RLP-130-A RLP-130-A RLP-130-A
R274
4_7K-0402SMT
0R-0402SMT
0R-0402SMT
Phy1_Dvdd
RLP-130-A
C253
27pF-0603SMT
RLP-132
220NF-0402SMT
R128
R127
Place SERDES 0 ohm
resistors near PHY
[4] HDRXP0_D1CH0
[4] HDRXN0_D1CH0
[4] HDTXP0_D1CH0
[4] HDTXN0_D1CH0
VSS
RX_CTRL
RXD[0]
RXD[1]
RX_CLK
RXD[2]
RXD[3]
VDDO
TXD[0]
TXD[1]
VDDO
TX_CLK
TXD[2]
TXD[3]
TX_CTRL
U14
88E1512_56QFN
57
0R-0402SMT43
0R-0402SMT44
0R-0402SMT45
46
20
0R-0402SMT47
0R-0402SMT48
49
50
51
52
53
54
55
56
Phy1_TXD0
Phy1_TXD1
Phy1_TXCLK
Phy1_TXD2
Phy1_TXD3
Phy1_TXCTRL
Place termination
resistors RX_D0-3,
RX_CLK, TX_CLK,
as close to the
G-PHY as possible
using 50 ohm
impedence traces.
Phy1_Xtal_IN
R299
0R-0402SMT-DNI
4_7K-0402SMT-DNI
SEG[0:14] [8]
R124
0R-0402SMT
R113
0R-0402SMT
R114
20
R121
0R-0402SMT
R122
0R-0402SMT
R123
0R-0402SMT
Phy1_RXD0
Phy1_RXD1
Phy1_RXD2
Phy1_RXD3
Phy1_RXCTRL
Phy1_Mdc
Phy1_Mdio
Phy1_Resetn
Phy1_CLK125PII
Phy1_Config
Phy1_RXCLK
SEG0
Phy1_CLK125
SEG2
SEG3
SEG4
SEG1
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
TX and RX traces
are all matched length < 2"
10uF-6.3V-0805SMT
RLP-133
C251
L20
M20
L19
M19
L16
L17
L18
M18
N16
M17
N18
P17
N17
P16
R16
R17
T16
N19
N20
P19
P18
P20
R20
T20
U20
T19
R18
U19
T18
U18
U17
U16
T17
Place termination
resistors TX_D0-3,
TX_CLK as close to
FPGA as possible
using 50 ohm
impedence traces.
Phy1_Vddo2-5
FB17
Z-600 ohm / 7427926
2
C109
1
2_5V
Bank 3
LFE5UM-45F-BG381
Schematic symbols rev 4.1
VCCIO3
VCCIO3
VCCIO3
C108
L14
L15
M15
C107
2_5V
100NF-0603SMT
Phy1_Dvdd
D
PR35A/PCLKT3_1/S3_OUT
PR35B/PCLKC3_1
PR35C/PCLKT3_0/S4_IN
PR35D/PCLKC3_0
PR38A/GR_PCLK3_0
PR38B
PR38C/GR_PCLK3_1
PR38D
PR41A
PR41B
PR41C
PR41D
PR44A/S4_OUT
PR44B/VREF1_3
PR44C/S5_IN
PR44D
PR53A
PR59A/S5_OUT
PR59B/S6_IN
PR59C
PR59D
PR62A/S6_OUT
PR62B/S7_IN
PR62C
PR62D
PR65A
PR65B
PR65C/LRC_GPLL0T_MFGOUT2
PR65D/LRC_GPLL0C_MFGOUT2
PR68A/LRC_GPLL0T_MFGOUT1
PR68B/LRC_GPLL0C_MFGOUT1
PR68C/LRC_GPLL0T_IN
PR68D/LRC_GPLL0C_IN/S7_OUT
10NF-0402SMT
Phy1_Dvdd
Phy1_Avdd1-8
Phy1_Avdd1-8
Phy1_Avdd1-8
U1D
Phy1_Dvdd
100NF-0603SMT
Phy1_Avdd3-3
Phy1_Avdd1-8 50R-0402SMT
Phy1_Xtal_IN
Phy1_Xtal_OUT
42
41
40
39
38
37
36
35
34
33
32
31
30
29
DVDD
REGCAP2
DVDD_OUT
AVDD18_OUT
AVDD18
REGCAP1
REG_IN
AVDDC18
XTAL_IN
XTAL_OUT
HSDACP
HSDACN
RSET
RSTPT
Phy1_Vddo2-5
C395
100NF-0402SMT
C399
100NF-0402SMT
2
2
C402
100NF-0402SMT
C405
100NF-0402SMT
S_INP
S_INN
AVDD18
S_OUTP
S_OUTN
DVDD
MDC
MDIO
CLK125
VDDO_SEL
VDDO
LED[2]/INTn
LED[1]
LED[0]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Phy1_Vddo2-5
PHY1_LED2
PHY1_LED1
PHY1_LED0
C396
10NF-0402SMT
C398
10NF-0402SMT
C401
10NF-0402SMT
C404
10NF-0402SMT
3
28
27
29
23
21
22
24
26
25
31
32
30
J9B
7
8
4
5
3
6
1
2
36
35
34
33
Date:
B
Size
Friday, August 21, 2015
ECP5 VERSA Eval Board
Project
1
Sheet
5
PHY1_LED0
PHY1_LED1
Board Rev
of 11
Schematic Rev
R73
100R-0402SMT
Lattice Semiconductor Applications
Email: [email protected]
0826-1X2T-23-F
Gr/Yel 2_LED2+
2_LED22_LED1+
Yel
2_LED1-
37
38
MH1 and MH2
are 0.100"
diameter plated
through holes
10/100/1000-T PHY#1/RJ45
Title
RJ45
2_MDID+
2_MDDCT 2_SHLD1
2_MDID2_SHLD2
2_MDIC+
2_MDCCT
2_MDIC-
2_MDIB+
2_MDIBCT
2_MDIB-
2_MDIA+
2_MDACT
2_MDIA-
Place caps close
to RJ45 jack
ETH1_MD3_N
ETH1_MD3_P
ETH1_MD2_N
ETH1_MD2_P
ETH1_MD1_N
ETH1_MD1_P
ETH1_MD0_N
ETH1_MD0_P
R74
Ethernet
RJ45
Connector
1
PHY1_LED2
4
4_7K-0402SMT
C397
1000pF-0402SMT
C400
1000pF-0402SMT
C403
1000pF-0402SMT
C406
1000pF-0402SMT
21
B
B
100R-0402SMT
5
A
B
C
D
ECP5 Versa Development Board
Figure 14. 10/100/1000-T PHY #1/RJ45
A
B
C
Bank 2
PR11A/URC_GPLL0T_IN
PR11B/URC_GPLL0C_IN/S0_IN
PR11C/URC_GPLL0T_MFGOUT2
PR11D/URC_GPLL0C_MFGOUT2
PR14A/S0_OUT
PR14B/S1_IN
PR14C
PR14D
PR17A/URC_GPLL0T_MFGOUT1
PR17B/URC_GPLL0C_MFGOUT1
PR17C
PR17D
PR20A
PR20B
PR20C
PR20D
PR23A/S1_OUT
PR23B/S2_IN
PR23C/VREF1_2
PR23D
PR26A
PR26B
PR26C
PR26D
PR29A/GR_PCLK2_1
PR29B
PR29C/GR_PCLK2_0
PR29D
PR32A/PCLKT2_1/S2_OUT
PR32B/PCLKC2_1
PR32C/PCLKT2_0/S3_IN
PR32D/PCLKC2_0
1
3_3V
1
C268
2
Phy2_Avdd3-3
FB20
Z-600 ohm / 7427926
C269
5
10uF-6.3V-0805SMT
RLP-133
Phy2_RXCTRL
Phy2_RXD0
Phy2_RXD1
Phy2_RXCLK
Phy2_RXD2
Phy2_RXD3
Phy2_Vddo2-5
Phy2_TXD0
Phy2_TXD1
Phy2_Vddo2-5
Phy2_TXCLK
Phy2_TXD2
Phy2_TXD3
Phy2_TXCTRL
C274
100NFX5R-0402SMT
RLP-130-A
C275
100NFX5R-0402SMT
RLP-130-A
Phy2_TXD0
Phy2_TXD1
Phy2_TXCLK
Phy2_TXD2
Phy2_TXD3
Phy2_TXCTRL
SWITCH5
SWITCH6
SWITCH7
SWITCH8
LED[0:7] [8]
R102
R94
R98
R99
R100
R101
0R-0402SMT
0R-0402SMT
R112
R109
4
100NFX5R-0402SMT
2
1
R295
100NFX5R-0402SMT
C276
C283
C282
C284
C285
4.7uF-16-0805SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
RLP-133
RLP-130-A RLP-130-A RLP-130-A RLP-130-A
Phy2_Dvdd
R275
4_7K-0402SMT
Phy2_Mdc
Phy2_Mdio
0R-0402SMT
0R-0402SMT
88E1512_56QFN
VSS
RX_CTRL
RXD[0]
RXD[1]
RX_CLK
RXD[2]
RXD[3]
VDDO
TXD[0]
TXD[1]
VDDO
TX_CLK
TXD[2]
TXD[3]
TX_CTRL
R116
R115
Place SERDES 0 ohm
resistors near PHY
[4] HDRXP0_D1CH1
[4] HDRXN0_D1CH1
[4] HDTXP0_D1CH1
[4] HDTXN0_D1CH1
57
0R-0402SMT43
0R-0402SMT44
0R-0402SMT45
46
20
0R-0402SMT47
0R-0402SMT48
49
50
51
52
53
54
55
56
C273
220NF-0402SMT
RLP-130-A
C271
27pF-0603SMT
RLP-132
Phy2_Xtal_IN
SWITCH[1:8] [8]
U15
Place termination
resistors TX_D0-3,
TX_CLK as close to
FPGA as possible
using 50 ohm
impedence traces.
0R-0402SMT
0R-0402SMT
20
0R-0402SMT
0R-0402SMT
0R-0402SMT
PHY2_RXCTRL
Phy2_Resetn
Phy2_Config
Phy2_Mdc
Phy2_Mdio
SWITCH5
SWITCH6
Phy2_RXCLK
SWITCH7
Phy2_Clk125
SWITCH8
Phy2_RXD2
Phy2_RXD3
R120
R110
R111
R117
R118
R119
Phy2_Clk125PII
LED2
LED3
LED6
LED1
LED7
LED0
LED5
LED4
Phy2_RXD0
Phy2_RXD1
TX and RX traces
are all matched length < 2"
10uF-6.3V-0805SMT
RLP-133
FB19
Z-600 ohm / 7427926
C18
D17
E16
F16
D18
E17
E18
F18
F17
G18
G16
H16
H18
H17
J17
J16
C20
D19
D20
E19
E20
F19
F20
G20
G19
H20
J18
K18
J19
K19
J20
K20
Place termination
resistors RX_D0-3,
RX_CLK, TX_CLK,
as close to the
G-PHY as possible
using 50 ohm impedence
traces.
Phy2_Vddo2-5
C147
C146
C145
2
2_5V
LFE5UM-45F-BG381
Schematic symbols rev 4.1
VCCIO2
VCCIO2
VCCIO2
2_5V
H14
H15
J15
2_5V
100NF-0603SMT
Phy2_Dvdd
D
10NF-0402SMT
Phy2_Dvdd
Phy2_Avdd1-8
Phy2_Avdd1-8
Phy2_Avdd1-8
U1C
Phy2_Dvdd
100NF-0603SMT
Phy2_Avdd3-3
Phy2_Avdd1-8 50R-0402SMT
Phy2_Xtal_IN
Phy2_Xtal_OUT
3
3
4
3
DNI
Phy2_Clk125PII
2_5V
Phy2_Avdd1-8
100NFX5R-0402SMT
3
R106
R105
DNI
100NFX5R-0402SMT
C281
C279
C278
100NFX5R-0402SMT
100NFX5R-0402SMT
RLP-130-A RLP-130-A RLP-130-A RLP-130-A
C280
Phy2_Clk125
2
R104
4_7K-0402SMT
ETH2_MD0_P
ETH2_MD0_N
Phy2_Avdd1-8
Phy2_Avdd3-3
ETH2_MD1_P
ETH2_MD1_N
ETH2_MD2_P
ETH2_MD2_N
Phy2_Avdd3-3
Phy2_Avdd1-8
ETH2_MD3_P
ETH2_MD3_N
Phy2_Resetn
Phy2_Config
3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C272
27pF-0603SMT
RLP-132
R300
0R-0402SMT
Phy2_Xtal_OUT
4_7K-0402SMT-DNI
2
2
Phy2_CLK125 = C17/PCLKT0_0 (Default)
Phy2_CLK125Pll = J20/PCLKT2
R93
0R-0402SMT
R0_1-3
R103
0R-0402SMT
U45
1
MDIP[0]
MDIN[0]
AVDD18
AVDD33
MDIP[1]
MDIN[1]
MDIP[2]
MDIN[2]
AVDD33
AVDD18
MDIP[3]
MDIN[3]
RESETn
CONFIG
TP11
R296
4.99k
R293
50R-0402SMT
25MHZ
G1 G2
1
Y3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
DVDD
REGCAP2
DVDD_OUT
AVDD18_OUT
AVDD18
REGCAP1
REG_IN
AVDDC18
XTAL_IN
XTAL_OUT
HSDACP
HSDACN
RSET
RSTPT
S_INP
S_INN
AVDD18
S_OUTP
S_OUTN
DVDD
MDC
MDIO
CLK125
VDDO_SEL
VDDO
LED[2]/INTn
LED[1]
LED[0]
Phy2_Vddo2-5
C407
100NF-0402SMT
C412
100NF-0402SMT
C414
100NF-0402SMT
C416
100NF-0402SMT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Phy2_Vddo2-5
PHY2_LED2
PHY2_LED1
PHY2_LED0
C408
10NF-0402SMT
C410
10NF-0402SMT
C413
10NF-0402SMT
C417
10NF-0402SMT
R301
0R-0402SMT-DNI
Date:
B
Size
0826-1X2T-23-F
Gr/Yel 1_LED2+
1_LED21_LED1+
Yel
1_LED1-
16
15
14
13
19
20
Friday, August 21, 2015
1
Sheet
6
Board Rev
of 11
Schematic Rev
PHY2_LED0
PHY2_LED1
R107
100R-0402SMT
MH1 and MH2
are 0.100"
diameter plated
through holes
Lattice Semiconductor Applications
Email: [email protected]
ECP5 VERSA Eval Board
Project
7
8
4
5
3
6
1
2
1_MDID+
1_MDDCT 1_SHLD1
1_MDID1_SHLD2
1_MDIC+
1_MDCCT
1_MDIC-
1_MDIB+
1_MDIBCT
1_MDIB-
1_MDIA+
1_MDACT
1_MDIA-
J9A
10/100/1000-T PHY#2/RJ45
Title
8
7
9
3
1
2
4
6
5
11
12
10
RJ45
Place caps close
to RJ45 jack
ETH2_MD3_N
ETH2_MD3_P
ETH2_MD2_N
ETH2_MD2_P
ETH2_MD1_N
ETH2_MD1_P
ETH2_MD0_N
ETH2_MD0_P
Ethernet
RJ45
Connector
1
PHY2_LED2
4
4_7K-0402SMT
C409
1000pF-0402SMT
C411
1000pF-0402SMT
C415
1000pF-0402SMT
C418
1000pF-0402SMT
22
R108
B
B
100R-0402SMT
5
A
B
C
D
ECP5 Versa Development Board
Figure 15. 10/100/1000-T PHY #2/RJ45
A
B
C
D
R142
4_7K-0603SMT
C190
C196
10NF-0603SMT
10NF-0603SMT
1_5V
C191
C197
100NF-0603SMT
C172
100NF-0603SMT
L6
L7
M6
1_5V
100NF-0603SMT
C173
5
8
3
100NF-0603SMT
C170
LP2998-SO8
VTT
VSENSE
VDDQ
C174
VREF
SD
5
DDR3_VS
C177 +
100UF-D3POSCAP
Bank 6
C179 +
DDR3_VDD
C178
C175
PL35A/PCLKT6_1
PL35B/PCLKC6_1
PL35C/PCLKT6_0
PL35D/PCLKC6_0
PL38A/GR_PCLK6_0
PL38B
PL38C/GR_PCLK6_1
PL38D
PL41A
PL41B
PL41C
PL41D
PL44A
PL44B/VREF1_6
PL44C
PL44D
PL53A
PL59A
PL59B
PL59C/D15/IO15
PL59D/D14/IO14
PL62A/D13/IO13
PL62B/D12/IO12
PL62C/D11/IO11
PL62D/D10/IO10
PL65A/LLC_GPLL0T_MFGOUT2
PL65B/LLC_GPLL0C_MFGOUT2
PL65C/D9/IO9
PL65D/D8/IO8
PL68A/LLC_GPLL0T_MFGOUT1
PL68B/LLC_GPLL0C_MFGOUT1
PL68C/LLC_GPLL0T_IN
PL68D/LLC_GPLL0C_IN
LFE5UM-45F-BG381
Schematic symbols rev 4.1
VCCIO6
VCCIO6
VCCIO6
U1E
1UF-16V-0805SMT
U12
10NF-0603SMT
10NF-0603SMT
C192
C198
6
7
AVIN
PVIN
1
GND
C193
C199
C194
C200
100NF-0603SMT
100NF-0603SMT
G2
F1
H2
G1
J4
J5
J3
K3
K2
J1
H1
K1
K4
K5
L4
L5
M5
M4
N5
N4
P5
N3
M3
L3
L2
N2
M1
L1
N1
P1
P2
P3
P4
R156
100R-0402SMT
1_5V
1_5V
1_5V
1_5V
4
100MHz_N
1_5V
OPEN-0603SMT
R149
ECP5_VREF
R146
0R-0603SMT
R145
0R-0603SMT
OPEN-0603SMT
R144
MEM_VREF
OPEN-0603SMT
R148
1_5V
FB22
1_5V
BLM41PG600SN1 + C180
OPEN-0603SMT
R143
1_5V
PP1
FB21
BLM41PG600SN1 + C176
Place close to FPGA
100MHz
DDR3_RAS#
DDR3_A0
100MHz
100MHz_N
DDR3_ODT0
DDR3_CE0
DDR3_WE#
DDR3_CAS#
DDR3_K0
DDR3_K0#
DDR3_RST#
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_DQ7
SWITCH2
DDR3_DQS0
DDR3_DQS0#
DDR3_DQ5
DDR3_CS0#
DDR3_DQ2
ECP5_VREF
DDR3_DQ4
DDR3_DQ0
DDR3_DQ6
DDR3_DQ1
SWITCH1
DDR3_DQ3
DDR3_DM0
DDR3_VDDQ
C195
47UF-16V-TANTBSMT
10NF-0603SMT
10NF-0603SMT
100NF-0603SMT
1UF-16V-0805SMT
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
1
2
2
100NF-0603SMT
4
C217
DDR3_VREF
C218
DDR3_SD0
C221
C201
C219
10UF-16V-TANTBSMT
C220
10NF-0603SMT
H6
H7
J6
MEM_VREF
C205
M8
H1
B1
B9
D1
D8
E2
E8
F9
G1
G9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
1_5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
B2
D9
K2
K8
G7
N1
N9
R1
R9
VREFCA
VREFDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Bank 7
U11A
A4
A5
B5
C5
C4
B4
A3
B3
E4
D5
C3
D3
F4
E3
E5
F5
A2
B1
B2
C2
C1
D1
D2
E1
H4
G5
H5
H3
G3
F3
F2
E2
ddr3-96bga
PL11A/ULC_GPLL0T_IN
PL11B/ULC_GPLL0C_IN
PL11C/ULC_GPLL0T_MFGOUT2
PL11D/ULC_GPLL0C_MFGOUT2
PL14A/ULC_GPLL0T_MFGOUT1
PL14B/ULC_GPLL0C_MFGOUT1
PL14C
PL14D
PL17A
PL17B
PL17C
PL17D
PL20A
PL20B
PL20C
PL20D
PL23A
PL23B
PL23C/VREF1_7
PL23D
PL26A
PL26B
PL26C
PL26D
PL29A/GR_PCLK7_1
PL29B
PL29C/GR_PCLK7_0
PL29D
PL32A/PCLKT7_1
PL32B/PCLKC7_1
PL32C/PCLKT7_0
PL32D/PCLKC7_0
10NF-0603SMT
LFE5UM-45F-BG381
Schematic symbols rev 4.1
VCCIO7
VCCIO7
VCCIO7
U1F
C181
DDR3_VDDQ
C171
DDR3_VDD
1UF-16V-0805SMT
1UF-16V-0805SMT
DDR3_VREF
10NF-0603SMT
100NF-0603SMT
SWITCH3
DDR3_DQ12
SWITCH4
DDR3_DQ10
DDR3_DQ14
DDR3_DQS1
DDR3_DQS1#
DDR3_DM1
DDR3_A5
DDR3_A9
DDR3_A2
DDR3_A3
DDR3_DQ13
DDR3_DQ15
ECP5_VREF
DDR3_DQ11
DDR3_DQ9
DDR3_DQ8
DDR3_A4
DDR3_A7
DDR3_A10
DDR3_A12
PCLKT0
PCLKC0
DDR3_A6
DDR3_A8
DDR3_A1
DDR3_A11
ddr3-96bga
3
3
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_CAS#
DDR3_K0
DDR3_K0#
DDR3_CE0
DDR3_CS0#
DDR3_DM0
DDR3_DM1
DDR3_ODT0
DDR3_RAS#
DDR3_RST#
DDR3_WE#
ZQ0
M2
N8
M3
K3
J7
K7
K9
L2
E7
D3
K1
J3
T2
L3
L8
1_5V
1_5V
1_5V
1_5V
[9]
[9]
DDR3_A0
DDR3_A1
DDR3_A2
DDR3_A3
DDR3_A4
DDR3_A5
DDR3_A6
DDR3_A7
DDR3_A8
DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A12
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
J1
L1
J9
L9
T3
T7
M7
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DQ8
DDR3_DQ9
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQS0
DDR3_DQS0#
DDR3_DQS1
DDR3_DQS1#
C242
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
F3
G3
C7
B7
PCLKT0
PCLKC0
NC_J1
NC_L1
NC_J9
NC_L9
NC_T3
NC_T7
NC_M7
ZQ
CAS#
CK
CK#
CKE
CS#
LDM
UDM
ODT
RAS#
RST#
WE#
BA0
BA1
BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDQS#
UDQS
UDQS#
DDR3_VTT
ALL Memory controller
buses, clocks, and contro
traces must be 50 Ohm
Transmission line
s
10NF-0603SMT
2
C185
100NF-0603SMT
A3
B3
C3
D3
E3
F3
G3
H3
J3
10NF-0603SMT
C183
DI
2
DDR3_WE#
DDR3_ODT0
DDR3_CE0
DDR3_CS0#
R1=50 Ohm
C225
DI
C226
DI
10NF-0603SMT
2
2
1
NC
DIS#
R152
50R-0402SMT
Q_N
Q
VTT
R1
R1
RP1
A1
B1
C1
D1
E1
F1
G1
H1
J1
Termination
at end of line
100MHz_N
SWITCH[1..8]
A1
B1
C1
D1
E1
F1
G1
H1
J1
X2
Date:
C
Size
X1
DDR3_BA1
DDR3_A8
DDR3_A11
DDR3_A12
DDR3_RAS#
DDR3_BA2
DDR3_A2
DDR3_A5
DDR3_A3
U1 Pin
[8]
Friday, August 21, 2015
1
Sheet
Board Rev
7
of 11
Schematic Rev
C206
10NF-0402SMT
R155
50R-0402SMT
Lattice Semiconductor Applications
Email: [email protected]
SWITCH[1:8]
R154
50R-0402SMT
C203
10NF-0402SMT
ECP5 VERSA Eval Board
Project
Memory
X1 needs to be matched length
for all traces
DDR3 Memory
Title
100MHz
4
SWITCH4
SWITCH3
SWITCH2
SWITCH1
R153
50R-0402SMT
5
X1
100_00MHz_LVDS
R151
50R-0402SMT
R157
10K-0402SMT
R150
50R-0402SMT
MPZ1608Y600B
FB23
100NF-0603SMT
1
3_3V
DDR3_VTT
1
MEMORY DEVICE TERMINATION for ADDRESS/ CONTROL SIGNALS
CTS-RT1402B7
A3
B3
C3
D3
E3
F3
G3
H3
J3
l
100NF-0603SMT
Place Address/Control Termination Resistors as close as possible to Memory Chip U7
DDR3_A6
DDR3_A4
DDR3_A1
DDR3_A10
DDR3_CAS#
DDR3_A0
DDR3_A9
DDR3_A7
DDR3_BA0
100NF-0603SMT
C184
1_5V
C223
22UF-16V-TANTBSMT
22UF-16V-TANTBSMT
0R-0603SMT
C222
C204
C182
DDR3_VTT
10NF-0603SMT
C202
R141
100NF-0603SMT
100NF-0603SMT
H2
H2
G2
G2
F2
F2
E2
E2
D2
D2
B2
B2
A2
A2
C2
C2
+
C224
U11B
R147
240R-0603SMT
C187
2_5V
100NF-0603SMT
10NF-0402SMT
C188
4
100NF-0603SMT
C186
1
2
10NF-0603SMT
1_5V
C241
100NF-0603SMT
5
10NF-0603SMT
100NF-0603SMT
DDR3_K0
J2
J2
6
VCC
GND
PAD
23
3
7
DDR3_K0#
KOC
C189
PLACE CLOSE TO MEMORY CHIP
2_5V
B
B
A
B
C
D
ECP5 Versa Development Board
Figure 16. DDR3 Memory
14
RN6D
RN6E
RN6F
RN6G
RN6H
RN8A
RN8B
RN8C
RN8D
RN8E
RN8F
RN8G
2
3
4
12
13
15
9
16
8
7
6
11
7
6
5
4
3
2
1
8
7
6
5
4
3
2
8
RN8H
68R
EXB2HV680JV
RN6C
1
10
RN6B
5
24
D24
LED2
LED3
LED4
LED5
LED6
LED7
D17
E16
F17
F18
F16
E17
5
D22
LED1
D18
D28
D29
D27
D26
D25
LED
D21
Signal
LED0
E18
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
EXB2HV680JV
16
U1 Pin
LEDs Signal Map
14-SEGMENT
D23
68R
1
LED[0:7]
RN6A
LED_RED_0603
LED_RED_0603
LED_RED_0603
LED_RED_0603
LED_YELLOW_0603
LED_YELLOW_0603
LED_GREEN_0603
4
USR1_PU
D28
USR0_PU
D29
USR2_PU
D27
USR3_PU
D26
PLL_LK_PU
D25
POLL_PU
D24
L0_PU
D22
DL_UP_PU
D21
2 220R
15
EXB2HV221JV
1 220R
16
EXB2HV221JV
3 220R
14
EXB2HV221JV
4 220R
13
EXB2HV221JV
8 220R
9
EXB2HV221JV
7 220R
10
EXB2HV221JV
6 220R
11
EXB2HV221JV
5 220R
12
EXB2HV221JV
RN7B
RN7A
RN7C
RN7D
RN7H
RN7G
RN7F
RN7E
2_5V
DP
p
n
m
l
k
j
h
g
f
e
d
c
b
a
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
LEDs
Segment
Signal
U1
R17
R16
P16
N17
P17
N18
M17
N16
M18
L17
L16
M19
L18
M20
Character Signal Map
4
U1 pin
LED_GREEN_0603
SEG[0:14]
A
B
C
2_5V
K
J
H
G
F
E
D
C
B
A
D
L
M
N
P
DP
14-SEGMENT DISPLAY
5
3
3
TDA DIP-8
SW3
SWITCH1
SWITCH2
SWITCH3
SWITCH4
SWITCH5
SWITCH6
SWITCH7
SWITCH8
DIP SWITCH
2
SWITCH8
K20
Date:
B
Size
Friday, August 21, 2015
ECP5 VERSA Eval Board
Project
1
Sheet
2_5V
1_5V
Board Rev
of 11
8
Schematic Rev
RN9H
8
Lattice Semiconductor Applications
Email: [email protected]
RN9G
9
SWITCH8 8 4_7K
EXB2HV472JV
RN9F
RN9E
11
SWITCH6 6 4_7K
EXB2HV472JV
RN9D
RN9C
14
SWITCH3 3 4_7K
EXB2HV472JV
12
SWITCH5 5 4_7K
EXB2HV472JV
RN9B
15
SWITCH2 2 4_7K
EXB2HV472JV
13
SWITCH4 4 4_7K
EXB2HV472JV
RN9A
[6] [7]
[3] [5]
[6]
16
SWITCH1 1 4_7K
EXB2HV472JV
SWITCH[1:8]
SEG[0:14]
LED[0:7]
1
7
SWITCH[1..8]
10
SWITCH7 7 4_7K
EXB2HV472JV
6
5
4
3
2
1
SWITCH
LEDs & Switches
Title
SWITCH7
K19
SWITCH6
SWITCH5
J18
K18
SWITCH4
SWITCH3
SWITCH2
SWITCH1
Signal
F2
G3
K3
H2
U1 pin
Switch Signal Map
2
B
B
A
B
C
D
ECP5 Versa Development Board
Figure 17. LEDs and Switches
A
B
C
D
2
C228
DI
2
1
SCL
SDA
FB25
MPZ1608Y600B
TANT
DI
GND
VCC
C231
DI
R169
R170
3
6
5
EN
OUTP
X2
156.25MHz_LVCMOS
3_3V
C235
DI
4
560PF-0603SMT
C234
DI
C236
DI
10NF-0603SMT
VCCO
[4]
[4]
[3] ispCLOCK_TDO
[3]
FTDI_TMS
[3]
FTDI_TCK
[3] ispCLOCK_TDI
PCIE_CLKP
PCIE_CLKN
D30
LED_GREEN_0603
R160
0R-0402SMT
R162
4_7K-0402SMT
R167
470R-0402SMT
DI
J13
R163
3_3V680R-0402SMT
156MHz_EN [3]
156MHz_VREF
HEADER 3(DNP)
1
2
3
10NF-0603SMT
CLK_SCL
CLK_SDA
R181
4_7K-0402SMT
DI
CLK_VCC
C233
DI
PRSNT
CLK_RESETn
100NF-0603SMT
C232
DI
100NF-0603SMT
0R-0603SMT
0R-0603SMT
R180
4_7K-0402SMT
DI
CLK_VCC
[3]
[4]
R166
DI
220R-0402SMT
156MHz
156MHz_EN
4
1
R159
DI
220R-0402SMT
Place bypass caps close to output bank
supply pins.
100NF-0603SMT
C229
6.8UF-TAN-0805SMT
DI
3_3V
[3]
[3]
10NF-0603SMT
C227
DI
100NF-0603SMT
6V
DI
MPZ1608Y600B
FB24
NC1
2
PAD
7
NC2
5
1
3
ispCLOCK_TDO
FTDI_TMS
FTDI_TCK
ispCLOCK_TDI
19
18
17
156MHz
156MHz_VREF
38
39
40
41
22
21
20
16
15
14
24
42
48
47
46
45
PCIE_CLKP
PCIE_CLKN
CLK_RESETn
CLK_LOCK1
CLK_SDA
CLK_SCL
3
TDO
TMS
TCK
TDI
FBKP
FBKN
FBKVTT
REFBP
REFBN
REFBVTT
REFAP
REFAN
REFAVTT
RREF
RESETb
USER0
USER1
USER2
USER3
44
CLK_VCC
U13
DI
ispCLOCK5406D
VCCD
4
GNDD
43
DIE_PAD
49
VCCJ
23
VCCA
37
GNDA
25
13
3_3V
5
VCCO_5
BANK_5P
BANK_5N
GNDO_5
VCCO_4
BANK_4P
BANK_4N
GNDO_4
VCCO_3
BANK_3P
BANK_3N
GNDO_3
VCCO_2
BANK_2P
BANK_2N
GNDO_2
VCCO_1
BANK_1P
BANK_1N
GNDO_1
VCCO_0
BANK_0P
BANK_0N
GNDO_0
4
2
3
1
5
6
7
8
12
10
11
9
25
27
26
28
32
31
30
29
33
35
34
36
2
VCCO
2
Date:
B
Size
Friday, August 21, 2015
ECP5 VERSA Eval Board
Project
REF CLOCK GEN
Title
REFCLKN_D1
10R-0402SMT
[7]
[7]
REFCLKN_D1
REFCLKP_D1
EXPCON_OSC
PCLKC0
PCLKT0
REFCLKN_D0
REFCLKP_D0
1
Sheet
Lattice Semiconductor Applications
Email: [email protected]
REFCLKP_D1
10R-0402SMT
R186
DI
EXPCON_OSC
10R-0402SMT
PCLKC0
10R-0402SMT
PCLKT0
10R-0402SMT
REFCLKN_D0
10R-0402SMT
REFCLKP_D0
10R-0402SMT
R183
DI
R168
DI
R165
DI
R161
DI
R164
DI
R158
DI
1
[4]
[4]
Board Rev
of 11
9
Schematic Rev
[10]
[4]
[4]
B
B
A
B
C
D
ECP5 Versa Development Board
Figure 18. Reference Clock Generator
A
5
F10
F9
3_3V
Bank 0
PT11A
PT11B
PT13A
PT13B
PT15A
PT15B
PT18A
PT18B
PT20A
PT20B
PT27A
PT29A
PT29B
PT31A
PT31B
PT33A/GR_PCLK0_1
PT33B/GR_PCLK0_0
PT36A/PCLKT0_1
PT36B/PCLKC0_1
PT38A/PCLKT0_0
PT38B/PCLKC0_0
PT4A/ULC_GPLL1T_IN
PT4B/ULC_GPLL1C_IN
PT6A
PT6B
PT9A
VCCIO0
PT9B
VCCIO0
U1A
R176
0R-0603SMT
3_3V
EXPCON_IO31
EXPCON_IO11
EXPCON_IO12
EXPCON_IO13
EXPCON_CLKIN
RXD_UART
EXPCON_IO36
TXD_UART
PCIE_PERSTN
EXPCON_IO37
EXPCON_IO32
EXPCON_IO33
EXPCON_IO34
EXPCON_IO35
4
C240
C239
C238
3_3V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
TXD_UART [9]
PCIE_PERSTN [4]
RXD_UART [6]
[9]
EXPCON_IO29
EXPCON_IO31
EXPCON_IO33
EXPCON_IO35
EXPCON_IO37
EXPCON_IO39
EXPCON_IO41
EXPCON_IO43
EXPCON_IO45
3
HDR40
X4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Bank 1
3
D11
E11
B12
C12
D12
E12
A12
A13
B13
C13
D13
E13
A14
C14
D14
E14
A15
B15
C15
D15
E15
A16
B16
C16
D16
B17
C17
A17
B18
A18
B19
A19
B20
EXPCON_IO26
CARDSEL#
EXPCON_IO23
EXPCON_IO20
EXPCON_IO1
EXPCON_IO3
EXPCON_IO5
EXPCON_IO7
EXPCON_IO9
EXPCON_IO11
EXPCON_IO13
EXPCON_IO15
EXPCON_3V3
PT42A/PCLKT1_1
PT42B/PCLKC1_1
PT44A/PCLKT1_0
PT44B/PCLKC1_0
PT47A/GR_PCLK1_0
PT47B/GR_PCLK1_1
PT49A
PT49B
PT51A
PT51B
PT53A
PT53B
PT56A
PT56B
PT58A
PT58B
PT67A
PT69A
PT69B
PT71A
PT71B
PT74A
PT74B
PT76A
PT76B
PT78A
PT78B
PT80A
PT80B
PT83A
PT83B
PT85A/URC_GPLL1T_IN
PT85B/URC_GPLL1C_IN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
LFE5UM-45F-BG381
Schematic symbols rev 4.1
VCCIO1
VCCIO1
U1B
EXPCON_IO16
EXPCON_IO17
EXPCON_IO18
EXPCON_IO19
EXPCON_IO21
EXPCON_IO22
EXPCON_IO24
EXPCON_IO25
EXPCON_IO27
EXPCON_IO28
HPE_RESOUT#
EXPCON_IO0
EXPCON_IO2
EXPCON_IO4
EXPCON_IO6
EXPCON_IO8
EXPCON_IO10
EXPCON_IO12
EXPCON_IO14
F11
F12
3_3V
Pin 2 removed for coding
of expansion board
EXPCON_OSC
HDR40
X3
EXPCON_IO45
EXPCON_IO44
EXPCON_IO43
EXPCON_IO42
EXPCON_IO41
EXPCON_IO40
CARDSEL#
HPE_RESOUT#
EXPCON_IO39
EXPCON_IO38
C237
C6
C7
E8
D8
C8
B8
A7
A8
D9
E9
C9
D10
E10
B9
C10
A9
B10
A10
A11
B11
C11
A6
B6
E6
D6
E7
D7
EXPCON_OSC
LFE5UM-45F-BG381
Schematic symbols rev 4.1
5VIN
TP13
1
3
5
7
9
11
13
15
17
19
21
23
EXPCON_2V5
25
27
29
EXPCON_OSC
EXPCON_CLKIN 31
EXPCON_CLKOUT 33
35
37
39
EXPCON_3V3
EXPCON_2V5
EXPCON_IO30
EXPCON_IO32
EXPCON_IO34
EXPCON_IO36
EXPCON_IO38
EXPCON_IO40
EXPCON_IO42
EXPCON_IO44
10NF-0402SMT
B
TP12
R175
0R-0603SMT
100NF-0603SMT
C
GND
2_5V
4
10NF-0402SMT
26
100NF-0603SMT
D
5
EXPCON_IO16
EXPCON_IO17
EXPCON_IO18
EXPCON_IO19
EXPCON_IO20
EXPCON_IO21
EXPCON_IO22
EXPCON_IO23
EXPCON_IO24
EXPCON_IO25
EXPCON_IO26
EXPCON_IO27
EXPCON_IO28
EXPCON_IO29
EXPCON_IO14
EXPCON_IO15
EXPCON_IO0
EXPCON_IO1
EXPCON_IO2
EXPCON_IO3
EXPCON_IO4
EXPCON_IO5
EXPCON_IO6
EXPCON_IO7
EXPCON_IO8
EXPCON_IO9
2
156MHz_EN
R177
0R-0603SMT- DNI
EXPCON_IO10
EXPCON_CLKOUT
EXPCON_IO30
3_3V
2
Date:
B
Size
Friday, August 21, 2015
ECP5 VERSA Eval Board
Project
1
Sheet
Lattice Semiconductor Applications
Email: [email protected]
Expansion Connector
Title
[9]
1
Schematic Rev
Board Rev
10 of 11
B
B
A
B
C
D
ECP5 Versa Development Board
Figure 19. Expansion Connector
ECP5 Versa Development Board
Appendix B. Bill of Materials
Table 13. ECP5 Versa Development Board Bill of Materials
Item
Quantity
Reference
Part
Manufacturer
Part Number
Description
PCI Express x1 Edge 
Finger Conn.
1
1
CN1
2
31
C1,C2,C3,C4,C5,C20,C21, 10NF-0402SMT
C29,C33,C85,C89,C92,
C95,C108,C110,C113,
C146,C202,C203,C206,
C237,C239,C243,C396,
C398,C401,C404,C408,
C410,C413,C417
Panasonic
ECJ0EB1E103K
CAP .01UF 25V
CERAMIC X7R 0402
3
32
C6,C7,C8,C9,C11,C22,
C23,C28,C30,C34,C66,
C67,C68,C69,C70,C72,
C77,C81,C88,C91,C106,
C111,C114,C115,C395,
C399,C402,C405,C407,
C412,C414,C416
100NF-0402SMT
Panasonic
ECJ-0EB1A104K
CAP .1UF 10V CERAMIC
X5R 0402
4
8
C18,C25,C26,C36,C102,
C104,C176,C180
22UF-16V-TANTBSMT
Kemet
T491B226M016AT
CAPACITOR TANT 22UF
16V 20% SMD
5
12
C19,C24,C27,C35,C101,
C103,C171,C173,C178,
C181,C391,C394
1UF-16V-0805SMT
Panasonic
ECJ-2FB1C105K
CAP 1UF 16V CERAMIC
0805 X5R
6
7
C31,C32,C90,C93,C94,
C105,C112
1NF-0402SMT
TDK Corporation
C1005C0G1E102J
CAP CER 1000PF 25V
C0G 5% 0402
7
2
C37,C51
10uF,25V-1206SMT
TDK Corporation
C3216Y5V1E106Z
CAP CER 10UF 25V Y5V
1206
8
6
C38,C39,C52,C53,C255,
C273
220NF-0402SMT
TDK Corporation
C1005X7R1C224K050BC CAP CER 0.22UF 16V
X7R 10% 0402
9
10
C40,C41,C42,C49,C50,
C54,C55,C58,C63,C64
22uF,6.3V-0805SMT
TDK Corporation
C2012X5R0J226M
CAP CER 22UF 6.3V X5R
20% 0805
10
12
C43,C44,C56,C57,C397,
C400,C403,C406,C409,
C411,C415,C418
1000pF-0402SMT
Panasonic
ECJ-0EB1E102K
CAP 1000PF 25V
CERAMIC X7R 0402
11
4
C45,C48,C59,C62
330pF-0402SMT
TDK Corporation
C1005C0G1H331J
CAP CER 330PF 50V
C0G 5% 0402
12
2
C46,C47,
10pF-0402SMT
TDK Corporation
C1005C0G1H100D
CAP CER 10PF 50V C0G
0402
13
2
C60,C61
10pF-0402SMT
DNI
14
2
C65,C71
4_7UF-10V-SMT
TDK Corporation
C1608X5R1A475K
CAP CER 4.7UF 10V X5R
0603
15
1
C74
3_3UF-10V-SMT
TDK Corporation
C1608X5R1A335K
CAP CER 3.3UF 10V X5R
0603
16
33
C78,C84,C107,C109,C145, 100NF-0603SMT
C147,C172,C174,C175,
C183,C185,C186,C188,
C189,C191,C193,C195,
C197,C199,C201,C205,
C218,C220,C222,C224,
C225,C227,C231,C232,
C233,C238,C240,C242
Panasonic
ECJ-1VF1C104Z
CAP .1UF 16V CERAMIC
Y5V 0603
17
2
C79,C80
TDK Corporation
C1608C0G1H120J
CAP CER 12PF 50V C0G
5% 0603
18
25
C86,C87,C244,C247,C248, 100NFX5R-0402SMT
C256,C258,C260,C261,
C262,C263,C264,C265,
C266,C267,C274,C275,
C278,C279,C280,C281,
C282,C283,C284,C285
Kemet
C0402C104K8PACTU
CAP .10UF 10V
CERAMIC X5R 0402
19
1
C170
47UF-16V-TANTBSMT
Kemet
B45196H2476K209
CAP TANTALUM 47UF
10V 10% SMD
20
1
C177
100UF-D3POSCAP
Sanyo
6TPE100MI
100UF,6.3V ,D2E.
POSCAP
21
1
C179
10UF-16V-TANTBSMT
AVX
TAJB106K016R
CAP TANTALUM 10UF
16V 10% SMD
12PF-0603SMT
27
ECP5 Versa Development Board
Item
Quantity
Reference
Part
Manufacturer
Part Number
Description
22
19
C182,C184,C187,C190,
C192,C194,C196,C198,
C200,C204,C217,C219,
C221,C223,C226,C228,
C234,C236,C241
10NF-0603SMT
Kemet
C0603C103K5RACTU
CAP .01UF 50V
CERAMIC X7R 0603
23
1
C229
6.8UF-TAN-0805SMT
Kemet
T494R685K006AS
CAP TANT 6.8UF 6.3V
10% SMD
24
1
C235
560PF-0603SMT
Kemet
C0603C561K5RACTU
CAP 560PF 50V
CERAMIC X7R 0603
25
2
C245,C246
100pF-0402SMT
Panasonic
ECJ-0EB1E101K
CAP 100PF 25V
CERAMIC X7R 0402
26
3
C249,C286,C287
20pF-0603SMT
TDK Corporation
C1608C0G1H200J
CAP CER 20PF 50V C0G
5% 0603
27
6
C250,C251,C268,C269,
C392,C393
10uF-6.3V-0805SMT
AVX
08056C106KAT2A
CAP CER 10UF 6.3V X7R
10% 0805
28
4
C253,C254,C271,C272
27pF-0603SMT
Kemet
C0603C270J5GACTU
CAP CERAMIC 27PF 50V
NP0 0603
29
2
C257,C276
4.7uF-16-0805SMT
TDK Corporation
C2012Y5V1C475Z/0.85
CAP CER 4.7UF 16V Y5V
0805
30
4
D1,D2,D5,D6
1N4448W
Fairchild
1N4448WT
DIODE 75V 200MA
SOD523F
31
4
D3,D4,D7,D8
DFLS220L
Diodes Inc
DFLS220L
DIODE SCHOTTKY 2A
20V PWRDI 123
32
11
D9,D10,D11,D12,D15,D16, LED_GREEN_0603
D20,D21,D22,D30,D31
Wurth
150060VS75000
LED 1.6X0.8MM 568NM
GRN CLR SMD
33
1
D13
LED_BLUE_0603
Wurth
150060BS75000
LED 1.6X0.8 470NM BL
WTR CLR SMD
34
1
D14
SCHOTTKY/VISHAYV12P10
Vishay
V12P10-M3/86A
DIODE SCHOTTKY 12A
100V SMPC TO-277A
35
7
D17,D18,D19,D26,D27,
D28,D29
LED_RED_0603
Wurth
150060RS75000
LED 1.6X0.8MM 625NM
RED CLR SMD
36
1
D23
14-SEGMENT
Kingbright
ACPSA04-41SRWA
LED Display
37
2
D24,D25
LED_YELLOW_0603
Wurth
150060YS75000
LED 1.6X0.8MM 588NM
YLW CLR SMD
38
7
FB2,FB3,FB4,FB7,FB8,
FB21,FB22
BLM41PG600SN1
Wurth
742792410
FERRITE CHIP 60 OHM
6000MA 1806
39
5
FB5,FB6,FB23,FB24,FB25 MPZ1608Y600B
Wurth
742792602
FERRITE CHIP 60 OHM
2.3A 0603
40
4
FB16,FB17,FB19,FB20
Z-600 ohm / 7427926
Wurth
74279265
FERRITE BEAD 600
OHM .2A 0603
41
1
F1
F1251CT-ND
Littlefuse
0154010.DR
FUSEBLOCK WITH 10A
FUSE SMD
42
1
J2
SKT_MINIUSB_B_RA
NELTRON
5075BMR-05-SM-CR
CONN MINI USB RCPT
RA TYPE B SMD
43
1
J3
HEADER 10
Wurth
61301011121
10x1-0.25 Header
44
2
J4,J50
HEADER 3X2
Wurth
61300621121
3x2-0.25 Header
45
4
J5,J6,J7,J8
SMA
Molex
73391-0060
CONN JACK SMA STR
50 OHM PCB
46
1
J9
0826-1X2T-23-F
Bellfuse
0826-1X2T-23-F
CONN MAGJACK 2PORT
GIGABIT GO/Y
47
1
J11
PJ-002A
Wurth
694106301002
48
1
J13
HEADER 3(DNP)
DNI
TSW-103-07-T-S
3x1-0.25 Header
49
4
L1,L2,L3,L4
4.7uH-SPD62R-472M
API Delavan
SPD62R-472M
6.60mm x 6.20mm x
3.00mm, 4.7uH Power
inductor
50
1
L5
1UH-1206SMT
Murata
LQM31PN1R0M00L
INDUCTOR 1.0UH 1.2A
1206
51
1
PP1
PROBEPOINT
DNI
52
4
Q1,Q2,Q3,Q4
2N2222/SOT23
Diodes Inc
MMBT2222A-7
TRANS NPN 40V 350MW
SMD SOT-23
53
2
RN6,RN8
EXB2HV680JV
Panasonic
EXB2HV680JV
RES ARRAY 68 OHM 5%
8 RES SMD
28
ECP5 Versa Development Board
Item
Quantity
Reference
Part
Manufacturer
Part Number
Description
54
1
RN7
EXB2HV221JV
Panasonic
EXB2HV221JV
RES ARRAY 220 OHM
5% 8 RES SMD
55
1
RN9
EXB2HV472JV
Panasonic
EXB2HV472JV
RES ARRAY 4.7K OHM
5% 8 RES SMD
56
1
RP1
CTS-RT1402B7
CTS Corporation Resistor/Electrocomponents
RT2402B7
RES NET DDR SDRAM
50 OHM 3X9 BGA
57
4
R6,R10,R12,R14
51K-0402SMT
Panasonic
ERJ-2RKF5102X
RES 51.0K OHM 1/10W
1% 0402 SMD
58
1
R7
21_5K-0603SMT
Panasonic
ERJ-3EKF2152V
RES 21.5K OHM 1/10W
1% 0603 SMD
59
1
R8
35_7K-0603SMT
Panasonic
ERJ-3EKF3572V
RES 35.7K OHM 1/10W
1% 0603 SMD
60
6
R9,R21,R27,R28,R29,R65
10K-0603SMT
Panasonic
ERJ-3EKF1002V
RES 10.0K OHM 1/10W
1% 0603 SMD
61
1
R11
34K-0402SMT
Panasonic
ERJ-2RKF3402X
RES 34.0K OHM 1/10W
1% 0402 SMD
62
1
R13
11_5K-0603SMT
Panasonic
ERJ-3EKF1152V
RES 11.5K OHM 1/10W
1% 0603 SMD
63
1
R15
3_83K-0603SMT
Panasonic
ERJ-3EKF3831V
RES 3.83K OHM 1/10W
1% 0603 SMD
64
1
R16
15K-0603SMT
Panasonic
ERJ-3EKF1502V
RES 15.0K OHM 1/10W
1% 0603 SMD
65
1
R17
16_9K-0603SMT
Panasonic
ERJ-3EKF1692V
RES 16.9K OHM 1/10W
1% 0603 SMD
66
1
R18
63_4K-0402SMT
Panasonic
ERJ-2RKF6342X
RES 63.4K OHM 1/10W
1% 0402 SMD
67
1
R19
30_1K-0402SMT
Panasonic
ERJ-2RKF3012X
RES 30.1K OHM 1/10W
1% 0402 SMD
68
1
R20
20K-0402SMT
Panasonic
ERJ-2RKF2002X
RES 20.0K OHM 1/10W
1% 0402 SMD
69
4
R22,R23,R24,R25
1_8K-1206SMT
Panasonic
ERJ-8ENF1801V
RES 1.80K OHM 1/4W
1% 1206 SMD
70
5
R26,R30,R31,R61,R179
220R-0603SMT
Panasonic
ERJ-3EKF2200V
RES 220 OHM 1/10W 1%
0603 SMD
71
11
R32,R33,R36,R38,R141,
R145,R146,R169,R170,
R175,R176
0R-0603SMT
Panasonic
ERJ-3GEY0R00V
RES 0.0 OHM 1/10W
0603 SMD
72
42
R35,R39,R52,R83,R84,
0R-0402SMT
R86,R87,R88,R89,R93,
R94,R98,R100,R101,R102,
R103,R109,R110,R112,
R113,R115,R116,R117,
R118,R119,R120,R121,
R122,R123,R124,R125,
R126,R127,R128,R129,
R130,R131,R133,R134,
R160,R298,R300
Panasonic
ERJ-2GE0R00X
RES 0.0 OHM 1/10W
0402 SMD
73
1
R37
15K-0603SMT-DNI
DNI
74
10
R40,R90,R92,R104,R106,
R162,R180,R181,R274,
R275
4_7K-0402SMT
Panasonic
ERJ-2RKF4701X
RES 4.70K OHM 1/10W
1% 0402 SMD
75
8
R41,R42,R43,R51,R53,
R68,R69,R157
10K-0402SMT
Panasonic
ERJ-2RKF1002X
RES 10.0K OHM 1/10W
1% 0402 SMD
76
1
R44
12K-0603SMT
Panasonic
ERJ-3EKF1202V
RES 12.0K OHM 1/10W
1% 0603 SMD
77
12
R45,R46,R47,R49,R57,
R58,R59,R72,R95,R135,
R136,R142
4_7K-0603SMT
Panasonic
ERJ-3EKF4701V
RES 4.70K OHM 1/10W
1% 0603 SMD
78
1
R48
2_2K-0603SMT
Panasonic
ERJ-3EKF2201V
RES 2.20K OHM 1/10W
1% 0603 SMD
79
1
R50
1M-0603SMT
Panasonic
ERJ-3EKF1004V
RES 1.00M OHM 1/10W
1% 0603 SMD
80
3
R55,R56,R60
680R-0603SMT
Panasonic
ERJ-3EKF6800V
RES 680 OHM 1/10W 1%
0603 SMD
29
ECP5 Versa Development Board
Item
Quantity
Reference
Part
Manufacturer
81
5
R63,R64,R66,R67,R70
0.1
Vishay Dale
82
2
R71,R75
2_2K-0603SMT-DNI
DNI
83
5
R73,R74,R107,R108,R156 100R-0402SMT
Panasonic
84
1
R76
0R-0603SMT-DNI
DNI
85
4
R85,R99,R111,R114
20
Vishay
86
2
R91,R105
4_7K-0402SMT-DNI
DNI
87
4
R96,R190,R191,R192
1K-0603SMT
88
1
R140
89
5
90
Part Number
Description
WSL2010R1000FEA
RES .1 OHM 1/2W 1%
2010 SMD
ERJ-2RKF1000X
RES 100 OHM 1/10W 1%
0402 SMD
CRCW040220R0FKED
RES 20.0 OHM 1/16W 1%
0402 SMD
Panasonic
ERJ-3EKF1001V
RES 1.00K OHM 1/10W
1% 0603 SMD
0.01
Vishay Dale
WSL2512R0100FEA18
RES .01 OHM 2W 1%
2512 SMD
R143,R144,R148,R149,
R178
OPEN-0603SMT
DNI
1
R147
240R-0603SMT
Panasonic
ERJ-3EKF2400V
RES 240 OHM 1/10W 1%
0603 SMD
91
10
R150,R151,R152,R153,
R154,R155,R291,R292,
R293,R295
50R-0402SMT
Vishay
FC0402E50R0FST1
RES 50 OHM 50MW +/1% 0402 SMD
92
7
R158,R161,R164,R165,
R168,R183,R186
10R-0402SMT
Panasonic
ERJ-2RKF10R0X
RES 10.0 OHM 1/10W 1%
0402 SMD
93
2
R159,R166
220R-0402SMT
Panasonic
ERJ-2RKF2200X
RES 200 OHM 1/10W 1%
0402 SMD
94
1
R163
680R-0402SMT
Panasonic
ERJ-2RKF6800X
RES 680 OHM 1/10W 1%
0402 SMD
95
1
R167
470R-0402SMT
Panasonic
ERJ-2RKF4700X
RES 470 OHM 1/10W 1%
0402 SMD
96
1
R177
0R-0603SMT- DNI
DNI
97
1
R184
121K-0603SMT
Panasonic
ERJ-3EKF1213V
RES 121K OHM 1/10W
1% 0603 SMD
98
1
R185
110K-0603SMT
Panasonic
ERJ-3EKF1103V
RES 110K OHM 1/10W
1% 0603 SMD
99
1
R187
50R-0603SMT
Panasonic
ERJ-3EKF49R9V
RES 49.9 OHM 1/10W 1%
0603 SMD
100
2
R294,R296
4.99k
Panasonic
ERJ-2RKF4991X
RES 4.99K OHM 1/10W
1% 0402 SMD
101
2
R299,R301
0R-0402SMT-DNI
DNI
102
2
SW1,SW2
PTS645SM43SMTR92
LFS
Wurth
430483031816
SPST SMD
103
1
SW3
TDA DIP-8
Wurth
416131160808
8-DIP
104
1
SW4
418311170804
Wurth
418311170804
4 poles raised SMT
105
4
TH1,TH2,TH3,TH4
ThruHole
DNI
106
39
TP1,TP2,TP3,TP4,TP5,
TP6,TP7,TP8,TP9,TP10,
TP11,TP12,TP13,TP14,
TP15,TP16,TP17,TP18,
TP19,TP20,TP21,TP22,
TP23,TP24,TP25,TP38,
TP39,TP40,TP41,TP42,
TP43,TP44,TP45,TP46,
TP47,TP48,TP49,TP50,
TP51
TestPoint
DNI
107
1
U1
LFE5UM-45F-BG381
LATTICE SUPPLIED
LFE5UM-45F-8BG381IES
108
2
U3,U4
LT3508EUF
LATTICE SUPPLIED
LT3508EUF#PBF
Dual Monolithic 1.4A
Step-Down Switching
Regulator
109
1
U5
FT2232HL
FTDI
FTD2232HL
USB-UART/JTAG
110
1
U6
93LC56C-I/SN
MicroChip
93LC56C-I/SN
IC EEPROM 2KBIT 3MHZ
8SOIC
111
1
U11
ddr3-96bga
Micron
MT41K64M16TW-107:J
64Mb/x16, 1.5V, 96-ball
FBGA, 667 MHz, DDR31866
30
ECP5 Versa Development Board
Item
Quantity
Reference
Part
Manufacturer
Part Number
Description
112
1
U12
LP2998-SO8
National
LP2998MAX/NOPB
113
1
U13
ispCLOCK5406D
LATTICE SUPPLIED
ISPPAC-CLK5406D01SN48I
114
2
U14,U15
88E1512_56QFN
Marvell
88E1512-A0-NNP2C000
SINGLE-PORT EEE
GIGABIT ETHER
115
2
U44,U45
R0_1-3
Panasonic
ERJ-3GEY0R00V
RES 0.0 OHM 1/10W
0603 SMD
116
1
U52
N25QxxxA13xSF
Micron
N25Q128A13ESF40G
Serial Flash
117
2
U53,U54
LT3085
LATTICE SUPPLIED
LT3085EMS8E#PBF
Adjustable 500mA Single
Resistor Low Dropout
Regulator
118
1
X1
100_00MHz_LVDS
SiTime
SiT9120AC-2D233E100.000
100MHz Low-Jitter LVDS
Clock Osc., 7mm x 5mm,
50ppm
119
1
X2
156.25MHz_LVCMOS
SiTime
SiT8256AI-83-33E156.250T
156.25MHz Single ended
CMOS Clock Osc., 7mm x
5mm
120
2
X3,X4
HDR40
Wurth
61304021121
HEADER 40POS .100"
DL TIN
121
1
Y1
12MHZ
TXC
7M-12.000MAAJ-T
CRYSTAL 12.0000MHZ
18PF SMD
122
2
Y2,Y3
25MHZ
TXC
7M-25.000MAAJ-T
CRYSTAL 25.0000MHZ
18PF SMD
31
Termination regulator
ECP5 Versa Development Board
Appendix C. Demo Board Rev A Information
ECP5 Versa Development Board – Working with Revision A
This document covers the Revision B of ECP5 Versa. To work with Revision A there are several items to be aware
of:
Setting the Configuration Mode
On the Rev A, setting the Configuration Mode requires modifying the resistor population in the CFG[2:0] Setting
Resistor Field (see Figure 3) as described in Table 3. This requires adding and/or removing 0603 size SMT resistors as necessary. Some soldering skill and the correct equipment is necessary to perform this rework.
Figure 20. CFG[2:0] Setting Resistor Field – Revision A
Table 14. CFG[2:0] Selection – Revision A
Rev A
Configuration Mode
1149.1 JTAG only
CFG[2:0]
R190
(1K-4.7 kOhm)
R191
(1K-4.7 kOhm)
R192
(1K-4.7 kOhm)
R182
(0 - 1 kOhm)
R188
(0 - 1 kOhm)
R189
(0 - 1 kOhm)
000
removed
removed
removed
placed
placed
placed
Slave SPI
001
removed
removed
placed
placed
placed
removed
Master SPI
010
removed
placed
removed
placed
removed
placed
SCM (Slave_Serial)
101
placed
removed
placed
removed
placed
removed
SCM (Slave_Parallel)
111
placed
placed
placed
removed
removed
removed
1. Removing all six resistors is equivalent to Slave Parallel mode due to internal weak Pull-up resistors on CFG[2:0] pins.
ECP5 Pin Assignment Changes
The following pins (Table 15) have changed assignment between the Rev A and Rev B board. These functions
would need to be remapped for use between the two boards.
Table 15. Pin Assignment Updates - Rev A vs Rev B
Pin Signal / Function
Rev A ECP5 Ball Location
SEG1 (Character LED)
L19
L18
Switch 3-7
J19
K19
Phy1_CLK125 (Ethernet Phy 1)
L18
L19
Phy2_RxCLK (Ethernet Phy 2)
K19
J19
32
Rev B ECP5 Ball Location
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