Rad Hard and SEE Hard 6A Synchronous Buck Regulator ISL70001ASEH Features The ISL70001ASEH is a radiation hardened and SEE hardened high efficiency monolithic synchronous buck regulator with integrated MOSFETs. This single chip power solution operates over an input voltage range of 3V to 5.5V and provides a tightly regulated output voltage that is externally adjustable from 0.8V to ~85% of the input voltage. Output load current capacity is 6A for TJ < +145°C. • ±1% Reference Voltage Over Line, Load, Temperature and Radiation The ISL70001ASEH utilizes peak current-mode control for excellent output load transient response and features integrated compensation and switches at a fixed frequency of 1MHz to reduce component size and count. In application where two POLs are needed, two ISL70001ASEH devices can be synchronized 180° out-of-phase to reduce the overall input RMS ripple current. The internal synchronous power switches are optimized for high efficiency and good thermal performance. • Highly Efficient: 94% Peak Efficiency The ISL70001ASEH incorporates fault protection for the regulator. The protection circuits include input undervoltage, output undervoltage, and output overcurrent. • Power-Good Output Voltage Monitor High integration and class leading radiation tolerance makes the ISL70001ASEH an ideal choice to power many of today’s small form factor applications. Two devices can be synchronized to provide a complete power solution for large scale digital ICs, like field programmable gate arrays (FPGAs), that require separate core and I/O voltages. Applications • FPGA, CPLD, DSP, CPU Core or I/O Voltages • Low-Voltage, High-Density Distributed Power Systems • Current Mode Control for Excellent Dynamic Response • Full Mil-Temp Range Operation (TA = -55°C to +125°C) • 50% Lower Shutdown Supply Current than the ISL70001SEH • Available in a thermally enhanced heatsink package - R48.B • Operates from 3V to 5.5V Supply • Adjustable Output Voltage - Two External Resistors Set VOUT from 0.8V to ~85% of VIN • Bi-directional SYNC Pin Allows Two Devices to be Synchronized 180° Out-of-Phase • Adjustable Analog Soft-Start • Input Undervoltage, Output Undervoltage and Output Overcurrent Protection • Electrically Screened to DLA SMD 5962-09225 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Hardness - Total Dose [50-300rad(Si)/s] . . . . . . . . . . . . . . 100krad(Si) - Total Dose [<10mrad(Si)/s] . . . . . . . . . . . . . . 100krad(Si)* * Product capability established by initial characterization. The EH version is acceptance tested on a wafer-by-wafer basis to 50krad(Si) at low dose rate. • SEE Hardness - SEL and SEB LETeff . . . . . . . . . . . . 86.4MeV/mg/cm2 min - SEFI X-section (LETeff = 86.4MeV/mg/cm2) 1.4 x 10-6 cm2 max - SET LETeff (< 1 Pulse Perturbation) 86.4MeV/mg/cm2 min Related Literature • ISL70001ASEHEV1Z Evaluation Board, AN1842 100 95 ISL70001ASEH CORE SYNCH ISL75051SEH AUX RAD TOLERANT FPGA EFFICIENCY (%) 5V Supply 90 85 1.5V 1.8V 3.3V 2.5V 80 1.2V ISL70001ASEH I/O 75 SYNCH 70 0 1 2 3 4 5 6 LOAD CURRENT (A) FIGURE 1. TYPICAL APPLICATION May 22, 2013 FN8365.0 1 FIGURE 2. EFFICIENCY 5V INPUT, TA = +25°C CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL70001ASEH EN Functional Block Diagram AVDD POWER-ON RESET (POR) PORSEL DVDD PVINx CURRENT SENSE SLOPE COMPENSATION SOFT START SS EA FB GM PWM CONTROL LOGIC GATE DRIVE LXx COMPENSATION PGNDx UV POWER-GOOD PGOOD REF PWM REFERENCE 0.6V TDI BIT TDO TRIM ZAP SYNC M/S PGNDx PGNDx DGND AGND Ordering Information ORDERING NUMBER (Note 1) PART NUMBER TEMP. RANGE (°C) PACKAGE (Note 3) (RoHS Compliant) PKG. DWG. # 5962R0922503VXC ISL70001ASEHVF (Note 2) -55 to +125 48 Ld CQFP R48.A 5962R0922503VYC ISL70001ASEHVFE (Note 2) -55 to +125 48 Ld CQFP with Heatsink R48.B 5962R0922503V9A ISL70001ASEHVX -55 to +125 Die ISL70001ASEHF/PROTO ISL70001ASEHF/PROTO (Note 2) -55 to +125 48 Ld CQFP R48.A ISL70001ASEHFE/PROTO ISL70001ASEHFE/PROTO (Note 2) -55 to +125 48 Ld CQFP with Heatsink R48.B ISL70001ASEHX/SAMPLE ISL70001SEHX/SAMPLE -55 to +125 Die ISL70001ASEHEV1Z ISL70001ASEHEV1Z Evaluation Board NOTES: 1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the Ordering Information table on page 2 must be used when ordering. 2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL70001ASEH. For more information on MSL, please see Tech Brief TB363. 2 FN8365.0 May 22, 2013 ISL70001ASEH Pin Configuration PVIN3 PVIN2 2 PVIN2 PGND1 3 LX2 LX1 4 PGND2 PVIN1 5 PGND2 PVIN1 6 PGND1 SYNC ISL70001ASEH (48 LD CQFP) TOP VIEW M/S 7 1 48 47 46 45 44 43 42 ZAP 8 41 LX3 TDI 9 40 PGND3 TDO 10 39 PGND3 PGOOD 11 38 PGND4 37 PGND4 36 LX4 PVIN3 13 DVDD 14 35 PVIN4 DGND 15 34 PVIN4 DGND 16 33 PVIN5 AGND 17 32 PVIN5 AGND 31 18 19 20 21 22 23 24 25 26 27 28 29 30 PGND5 PGND6 PGND6 LX6 PVIN6 PVIN6 PORSEL EN FB REF * HEATSINK PGND5 DVDD AVDD SS 12 LX5 * Heatsink available in R48.B package Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1, 2, 27, 28, 29, 30, 37, 38, 39, 40, 47, 48 PGNDx These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins directly to the ground plane. These pins should also connect to the negative terminals of the input and output capacitors. Locate the input and output capacitors as close as possible to the IC. 3, 26, 31, 36, 41, 46 LXx These pins are the outputs of the corresponding internal power blocks and should be connected to the output filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize voltage undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The Schottky diode should be located as close as possible to the IC. 4, 5, 24, 25, 32, 33, 34, 35, 42, 43, 44, 45 PVINx These pins are the power supply inputs to the corresponding internal power blocks. These pins must be connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly to PGNDx with ceramic capacitors located as close as possible to the IC. 6 SYNC This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives the SYNC input of another ISL70001ASEH. When configured as an input (Slave Mode), this pin accepts the SYNC output from another ISL70001ASEH or an external clock. Synchronization of the slave unit is 180° out-of-phase with respect to the master unit. If synchronizing to an external clock, the clock must be SEE hardened and the frequency must be within the range of 1MHz ±20%. 7 M/S This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to DGND. 8 ZAP This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND. 9 TDI This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND. 10 TDO This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND. 11 PGOOD This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin to DGND with a 10nF ceramic capacitor to mitigate SEE. 3 FN8365.0 May 22, 2013 ISL70001ASEH Pin Descriptions (Continued) PIN NUMBER PIN NAME DESCRIPTION 12 SS This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output ramp time in accordance with Equation 1: t SS = C SS ⋅ V REF ⁄ I SS (EQ. 1) where: tSS = Soft-start output ramp time CSS = Soft-start capacitor VREF = Reference voltage (0.6V typical) ISS = Soft-start charging current (23µA typical) Soft-start time is adjustable from approximately 2ms to 200ms. The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive. 13, 14 DVDD These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together at the IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. 15, 16 DGND These pins are the digital ground associated with the internal digital control circuitry. Connect these pins directly to the ground plane. 17, 18 AGND These pins are the analog ground associated with the internal analog control circuitry. Connect these pins directly to the ground plane. 19 AVDD This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. 20 REF This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or sinking) is available from this pin. 21 FB This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and from FB to AGND to adjust the output voltage in accordance with Equation 2: V OUT = V REF ⋅ [ 1 + ( R T ⁄ R B ) ] (EQ. 2) where: VOUT = Output voltage VREF = Reference voltage (0.6V typical) RT = Top divider resistor (Must be 1kΩ) RB = Bottom divider resistor The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate SEE and to improve stability margins. 22 EN This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a 10nF ceramic capacitor to mitigate SEE. 23 PORSEL This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply voltages between 5V and 3.3V, connect this pin to DGND. HEATSINK 4 The heatsink is electrically isolated and should be connected to a thermal chassis of any potential which offers optimal thermal relief. FN8365.0 May 22, 2013 ISL70001ASEH Typical Application Schematic PVIN1 LX1 PVIN2 LX2 PVIN3 LX3 PVIN4 LX4 PVIN5 LX5 5V 100µF 1µF 1µF 1µH LX6 PVIN6 1 1kΩ FB 1µF ISL70001ASEH 0V TO 5.5V AGND 499Ω PGOOD DVDD 10nF 1µF SYNC DGND REF EN 10nF 220nF M/S PORSEL TDI SS TDO 100nF PGND6 PGND5 PGND4 PGND3 PGND2 ZAP PGND1 VSENSE 470µF 20V 3A AVDD 1 1.8V 6A FIGURE 3. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION 5 FN8365.0 May 22, 2013 ISL70001ASEH Typical Application Schematic (Continued) PVIN1 LX1 PVIN2 LX2 PVIN3 LX3 PVIN4 LX4 PVIN5 LX5 3.3V 100µF 1µF 1µF 1µH PVIN6 1 LX6 470µF 20V 3A DVDD 1kΩ 4.7nF FB 1µF ISL70001ASEH 0V TO 5.5V DGND 1 1.8V 6A 499Ω PGOOD AVDD 10nF 1µF VSENSE SYNC AGND REF EN 10nF 220nF M/S PORSEL TDI SS TDO 100nF PGND6 PGND5 PGND4 PGND3 PGND2 PGND1 ZAP FIGURE 4. 3.3V INPUT SUPPLY VOLTAGE WITH SLAVE MODE SYNCHRONIZATION 6 FN8365.0 May 22, 2013 ISL70001ASEH Absolute Maximum Ratings Thermal Information AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND - 0.3V to AGND + 6.5V DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND +6.5V LXx, PVINx . . . . . . . . . . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 6.5V AVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . . PVINx - PGNDx ± 0.3V Signal pins (Note 9) . . . . . . . . . . . . . . . . . . . . . AGND - 0.3V to AVDD + 0.3V Digital control pins (Note 10) . . . . . . . . . . . . . DGND - 0.3V to DVDD + 0.3V PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND - 0.3V to DGND + 6.5V SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND - 0.3V to DGND + 2.5V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 48 Ld CQFP R48.A (Notes 4, 6) . . . . . . . . . 36.5 3 48 Ld CQFP R48.B (Notes 5, 7) . . . . . . . . . 19 1.3 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+145°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Absolute Maximum Ratings (NOTE 8) Recommended Operating Conditions AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND - 0.3V to AGND + 5.7V DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND - 0.3V to DGND + 5.7V LXx, PVINx . . . . . . . . . . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 5.7V AVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . . PVINx - PGNDx ± 0.3V Signal pins (Note 9) . . . . . . . . . . . . . . . . . . . . . AGND - 0.3V to AVDD + 0.3V Digital control pins (Note 10) . . . . . . . . . . . . . DGND - 0.3V to DVDD + 0.3V PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND - 0.3V to DGND + 5.7V SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND - 0.3V to DGND + 2.5V AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND + 3V to 5.5V DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND + 3V to 5.5V PVINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGNDx + 3V to 5.5V AVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . . PVINx - PGNDx ± 0.1V Signal pins (Note 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVDD Digital control pins (Note 10) . . . . . . . . . . . . . . . . . . . . . . . . .DGND to DVDD REF, SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Set GND, TDI, TDO, TPGM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND ILXx (TJ ≤ +145°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.0A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C ESD Rating Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 6. For θJC, the “case temp” location is the center of the package underside. 7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 8. For operation in a heavy ion environment at LET = 86.4 MeV•cm2/mg with +125°C (TC). 9. EN, FB, PORSEL and REF pins. 10. M/S, SYNC, TDI, TDO and ZAP pins Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V; GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V, SYNC = LXx = Open Circuit; PGOOD is pulled up to VIN with a 1k resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 11). Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total iodizing dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total iodizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. V PARAMETER TEST CONDITIONS MIN (Note 12) TYP (Note 11) MAX (Note 12) UNITS POWER SUPPLY Operating Supply Current Shutdown Supply Current VIN = 5.5V 40 65 mA VIN = 3.6V 25 45 mA VIN = 5.5V, EN = GND 2 6 mA VIN = 3.6V, EN = GND 1.5 4.5 mA 0.594 0.6 0.606 V OUTPUT VOLTAGE Reference Voltage Tolerance Output Voltage Tolerance VOUT = 0.8V to 2.5V for VIN = 4.5V to 5.5V, VOUT = 0.8V to 2.5V for VIN = 3V to 3.6V, IOUT = 0A to 6A (Notes 13, 14) -2 0 2 % Feedback (FB) Input Leakage Current VIN = 5.5V, VFB = 0.6V -1 0 1 µA 7 FN8365.0 May 22, 2013 ISL70001ASEH Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V; GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V, SYNC = LXx = Open Circuit; PGOOD is pulled up to VIN with a 1k resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 11). Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total iodizing dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total iodizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) PARAMETER TEST CONDITIONS MIN (Note 12) TYP (Note 11) MAX (Note 12) UNITS 0.85 1 1.15 MHz .8 1 1.2 MHz PWM CONTROL LOGIC Oscillator Accuracy External Oscillator Range Minimum LXx On Time VIN = 5.5V, Test Mode 110 150 ns Minimum LXx Off Time VIN = 5.5V, Test Mode 40 100 ns Minimum LXx On Time VIN = 3V, Test Mode 150 210 ns Minimum LXx Off Time VIN = 3V, Test Mode 50 100 ns Master/Slave (M/S) Input Voltage Input High Threshold VIN - 0.5 Input Low Threshold 1.3 0.5 V 1 µA Master/Slave (M/S) Input Leakage Current VIN = 5.5V, M/S = GND or VIN -1 0 Synchronization (SYNC) Input Voltage Input High Threshold, M/S = GND 2.3 1.7 Input Low Threshold, M/S = GND -1 V 1.2 V 1.5 1 V 0 1 µA Synchronization (SYNC) Input Leakage Current VIN = 5.5V, M/S = GND, SYNC = GND or VIN Synchronization (SYNC) Output Voltage VIN - VOH @ IOH = -1mA 0.15 0.4 V VOL@ IOL = 1mA 0.15 0.4 V POWER BLOCKS Upper Device rDS(ON) VIN = 3V, 0.4A Per Power Block, Test Mode (Note 14) 122 215 346 mΩ Lower Device rDS(ON) VIN = 3V, 0.4A Per Power Block, Test Mode (Note 14) 77 146 236 mΩ LXx Output Leakage VIN = 5.5V, EN = LXx = GND, Single LXx Output -1 0 VIN = 5.5V, EN = GND, LXx = VIN, Single LXx Output Deadtime Within a Single Power Block or between Power Blocks (Note 14) Efficiency 0 1.7 µA 15 µA 5 ns VIN = 3.3V, VOUT = 1.8V, IOUT = 3A 90 % VIN = 5V, VOUT = 2.5V, IOUT = 3A 92 % 1.4 V POWER-ON RESET POR Select (PORSEL) Input High Threshold VIN - 0.5 1.2 0.5 V POR Select (PORSEL) Input Leakage Current VIN = 5.5V, PORSEL = GND or VIN Input Low Threshold -1 0 1 µA VIN POR Rising Threshold, PORSEL = VIN 4.1 4.25 4.45 V Hysteresis, PORSEL = VIN 225 325 425 mV Rising Threshold, PORSEL = GND 2.65 2.8 2.95 V 90 175 260 mV 0.56 0.6 0.64 V Hysteresis, PORSEL = GND Enable (EN) Input Voltage Rising/Falling Threshold Enable (EN) Input Leakage Current VIN = 5.5V, EN = GND or VIN -3 0 3 µA Enable (EN) Sink Current EN = 0.3V 6.4 11 16.6 µA 8 FN8365.0 May 22, 2013 ISL70001ASEH Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V; GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V, SYNC = LXx = Open Circuit; PGOOD is pulled up to VIN with a 1k resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 11). Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total iodizing dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total iodizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) MIN (Note 12) TYP (Note 11) MAX (Note 12) UNITS 20 23 27 µA Soft-Start Discharge ON-Resistance 2.2 4.7 Ω Soft-Start Discharge Time 256 PARAMETER TEST CONDITIONS SOFT-START Soft-Start Source Current SS = GND Clock Cycles POWER-GOOD SIGNAL Rising Threshold VFB as a % of VREF, Test Mode 107 111 115 % Rising Hysteresis VFB as a % of VREF, Test Mode 2 3.5 5 % Falling Threshold VFB as a % of VREF, Test Mode 85 89 93 % Falling Hysteresis VFB as a % of VREF, Test Mode 2 3.5 5 % Power-Good Drive VIN = 3V, PGOOD = 0.4V, EN = GND 7.3 8.2 Power-Good Leakage VIN = PGOOD = 5.5V mA 0.001 1 µA PROTECTION FEATURES Undervoltage Monitor Undervoltage Trip Threshold VIN = 3V, VFB as a % of VREF, Test mode 71 75 79 % Undervoltage Recovery Threshold VIN = 3V, VFB as a % of VREF, Test mode 84 88 92 % Overcurrent Trip Level LX4 Power Block, Test Mode, (Note 15) 1.3 1.9 2.5 A Overcurrent Trip Counts LX4 Power Block, Test Mode (Note 14) Overcurrent or Short-Circuit Duty-Cycle VIN = 3V, SS interval = 200µs, Test Mode, Fault interval divided by hiccup interval 5 % Overcurrent Monitor 2 0.8 NOTES: 11. Typical values shown are not guaranteed. Guaranteed min/max values are provided in the SMD. 12. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 13. Limits do not include tolerance of external feedback resistors. The 0A to 6A output current range may be reduced by Minimum LXx On Time and Minimum LXx Off Time specifications. 14. Limits established by design, characterization or analysis and are not production tested. 15. During an output short-circuit, peak current through the power block(s) can continue to build beyond the overcurrent trip level by up to 3A. With all six power blocks connected, peak current through the power blocks and output inductor could reach (6 x 2.5A) + 3A = 18A.. 9 FN8365.0 May 22, 2013 ISL70001ASEH Typical Operating Performance 100 100 95 95 EFFICIENCY (%) EFFICIENCY (%) Unless otherwise noted, TA = +25°C, VIN = 5V, EN = 5V, L = 1.0µH, CIN = 4x47µF, COUT = 10x100µF, VOUT = 1.8V, IOUT = 0A to 6A. 90 85 1.5V 1.8V 80 1.2V 2.5V 85 1.5V 1.8V 1.2V 0 1 2 3 4 5 70 6 0 1 2 2.0 1.8 1.8 1.6 1.6 POWER DISSIPATION (W) POWER DISSIPATION (W) 2.0 2.5V 1.2 4 5 6 FIGURE 6. EFFICIENCY vs LOAD, VIN = 5.0V FIGURE 5. EFFICIENCY vs LOAD, VIN = 3.3V 1.4 3 ILOAD (A) ILOAD (A) 1.2V 1.8V 1.0 1.5V 0.8 0.6 0.4 2.5V 1.4 1.8V 1.2 1.2V 3.3V 1.0 1.5V 0.8 0.6 0.4 0.2 0.2 0 3.3V 2.5V 80 75 75 70 90 0 1 2 3 4 5 0 6 0 1 2 ILOAD (A) 3 4 5 6 ILOAD (A) FIGURE 7. POWER DISSIPATION vs LOAD, VIN = 3.3V FIGURE 8. POWER DISSIPATION vs LOAD, VIN = 5.0V 0.010 0.005 0.004 0.003 0.005 1.5V 0.001 1.2V 1.2V VOUT (V) VOUT (V) 0.002 0 -0.001 -0.002 -0.005 -0.003 1.8V 1.8V -0.004 -0.005 1.5V 0 2.5V 0 1 2 3 ILOAD (A) 4 5 6 FIGURE 9. VOUT REGULATION vs ILOAD, VIN = 3.3V (NORMALIZED to ILOAD = 0) 10 2.5V 3.3V -0.010 0 1 2 3 4 5 6 ILOAD (A) FIGURE 10. VOUT REGULATION vs ILOAD, VIN = 5.0V (NORMALIZED to ILOAD = 0) FN8365.0 May 22, 2013 ISL70001ASEH Typical Operating Performance Unless otherwise noted, TA = +25°C, VIN = 5V, EN = 5V, L = 1.0µH, CIN = 4x47µF, COUT = 10x100µF, VOUT = 1.8V, IOUT = 0A to 6A. (Continued) EN 2V/DIV EN 2V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 2A/DIV PGOOD 5V/DIV PGOOD 5V/DIV FIGURE 11. SOFT-START WITH NO LOAD LX PULSE 5V/DIV VOUT 20mV/DIV IL 1A/DIV FIGURE 13. STEADY STATE OPERATION WITH NO LOAD VOUT 20mV/DIV FIGURE 12. SOFT-START WITH FULL LOAD LX PULSE 5V/DIV IL 2A/DIV VOUT 20mV/DIV FIGURE 14. STEADY STATE OPERATION WITH FULL LOAD VOUT 50mV/DIV IL 2A/DIV IL 2A/DIV FIGURE 15. LOAD TRANSIENT 50% 11 FIGURE 16. LOAD TRANSIENT 100% FN8365.0 May 22, 2013 ISL70001ASEH Typical Operating Performance Unless otherwise noted, TA = +25°C, VIN = 5V, EN = 5V, L = 1.0µH, CIN = 4x47µF, COUT = 10x100µF, VOUT = 1.8V, IOUT = 0A to 6A. (Continued) EN 2V/DIV EN 2V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 2A/DIV PGOOD 5V/DIV PGOOD 5V/DIV FIGURE 17. SOFT-START WITH PRE-BIASED 0.5V FIGURE 18. SOFT-DISCHARGE SHUTDOWN LX 5V/DIV LX 5V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 5A/DIV IL 5A/DIV PGOOD 5V/DIV PGOOD 5V/DIV FIGURE 19. OUTPUT SHORT CIRCUIT 12 FIGURE 20. OUTPUT SHORT CIRCUIT RECOVERY FN8365.0 May 22, 2013 ISL70001ASEH Functional Description The ISL70001ASEH is a monolithic, fixed frequency, currentmode synchronous buck regulator with user configurable power blocks. Two ISL70001ASEH devices can be used to provide a total DC/DC solution for FPGAs, CPLDs, DSPs and CPUs. The ISL70001ASEH utilizes peak current-mode control with integrated compensation and switches at a fixed frequency of 1MHz. Two ISL70001ASEH devices can be synchronized 180° out-of-phase to reduce input RMS ripple current. These attributes reduce the number and size of external components required, while providing excellent output transient response. The internal synchronous power switches are optimized for high efficiency and good thermal performance. six LXx pins to the output inductor provides a maximum 6A of output current. See the “Typical Application Schematic” on page 5 for pin connection guidance. A scaled pilot device associated with each power block provides current feedback. Power block 4 contains the master pilot device and this is why it must be connected to the output inductor. Main Control Loop During normal operation, the internal top power switch is turned on at the beginning of each clock cycle. Current in the output inductor ramps up until the current comparator trips and turns off the top power MOSFET. The bottom power MOSFET turns on and the inductor current ramps down for the rest of the cycle. The chip features a comparator type enable input that provides flexibility. It can be used for simple digital on/off control or, alternately, can provide undervoltage lockout capability by using two external resistors to precisely sense the level of an external supply voltage. A power-good signal indicates when the output voltage is within ±11% typical of the nominal output voltage. The current comparator compares the output current at the ripple current peak to a current pilot. The error amplifier monitors VOUT and compares it with an internal reference voltage. The output voltage of the error amplifier drives a proportional current to the pilot. If VOUT is low, the current level of the pilot is increased and the trip off current level of the output is increased. The increased output current raises VOUT until it is in agreement with the reference voltage. Regulator start-up is controlled by an analog soft-start circuit, which can be adjusted from approximately 2ms to 200ms by using an external capacitor. Output Voltage Selection The ISL70001ASEH differs from the ISL70001SEH in the fault counts needed to initiate an overcurrent or undervoltage condition. The ISL70001ASEH also has a lower standby supply current. Power Blocks The power output stage of the regulator consists of six 1A capable power blocks that are paralleled to provide full 6A output current capability. The block diagram in Figure 21 shows a top level view of the individual power blocks. The output voltage of the ISL70001ASEH can be adjusted using an external resistor divider as shown in Figure 22. VREF = 0.6V CREF = 220nF RT = 1k CC = 4.7nF POWER BLOCK 1 PVIN2 LX2 PGND2 POWER BLOCK 2 POWER BLOCK 5 PVIN5 LX5 PGND5 PVIN3 LX3 PGND3 POWER BLOCK 3 POWER BLOCK 4 PVIN4 LX4 PGND4 POWER BLOCK 6 PVIN6 LX6 PGND6 FIGURE 21. POWER BLOCK DIAGRAM Each power block has a power supply input pin, PVINx, a phase output pin, LXx, and a power supply ground pin, PGNDx. All PVINx pins must be connected to a common power supply rail and all PGNDx pins must be connected to a common ground. LXx pins should be connected to the output inductor based on the required load current, but must include the LX4 pin. For example, if 3A of output current is needed, any three LXx pins can be connected to the inductor as long as one of them is the LX4 pin. The unused LXx pins should be left unconnected. Connecting all 13 VOUT COUT CC RT ERROR AMPLIFIER FB + PVIN1 LX1 PGND1 L LXx OUT VREF REF RB CREF FIGURE 22. OUTPUT VOLTAGE SELECTION RT should be selected as 1kΩ to mitigate SEE. RT should be shunted by a 4.7nF ceramic capacitor, CC, to mitigate SEE and to improve loop stability margins. The REF pin should be bypassed to AGND with a 220nF ceramic capacitor to mitigate SEE. It should be noted that no current (sourcing or sinking) is available from the REF pin. RB can be determined from Equation 3. The designer can configure the output voltage from 0.8V to 85% of the input voltage. V REF R B = R T ⋅ -------------------------------V –V OUT (EQ. 3) REF Switching Frequency/Synchronization The ISL70001ASEH features an internal oscillator running at a fixed frequency of 1MHz ±15% over recommended operating conditions. The regulator can be configured to run from the internal oscillator or can be synchronized to another ISL70001ASEH or an SEE hardened external clock with a frequency range of 1MHz ±20%. FN8365.0 May 22, 2013 ISL70001ASEH To run the regulator from the internal oscillator, connect the M/S pin to DVDD. In this case, the output of the internal oscillator appears on the SYNC pin. To synchronize the regulator to the SYNC output of another ISL70001ASEH regulator or to an SEE hardened external clock, connect the M/S pin to DGND. In this case, the SYNC pin is an input that accepts an external synchronizing signal. When synchronizing multiple devices, Slave regulators are synchronized 180° out-of-phase with respect to the SYNC output of a Master regulator or to an external clock. VR = 0.6V IEN = 11µA CEN = 10nF VIN1 PVINx VIN2 ENABLE COMPARATOR Operation Initialization The ISL70001ASEH initializes based on the state of the power-on reset (POR) monitor of the PVINx inputs and the state of the EN input. Successful initialization prompts a soft-start interval, and the regulator begins slowly ramping the output voltage. Once the commanded output voltage is within the proper window of operation, the power-good signal changes state from low to high, indicating proper regulator operation. R1 EN + - POR LOGIC CEN VR R2 IEN Power-On Reset FIGURE 23. ENABLE CIRCUIT The POR circuitry prevents the controller from attempting to soft-start before sufficient bias is present at the PVINx pins. The POR threshold of the PVINx pins is controlled by the PORSEL pin. For a nominal 5V supply voltage, PORSEL should be connected to DVDD. For a nominal 3.3V supply voltage, PORSEL should be connected to DGND. For nominal supply voltages between 5V and 3.3V, PORSEL should be connected to DGND. The POR rising and falling thresholds are shown in the “Electrical Specifications” table on page 8. Hysteresis between the rising and falling thresholds ensures that small perturbations on PVINx seen during turn-on/turn-off of the regulator do not cause inadvertent turn-off/turn-on of the regulator. When the PVINx pins are below the POR rising threshold, the internal synchronous power MOSFET switches are turned off, and the LXx pins are held in a high-impedance state. Enable and Disable After the POR input requirement is met, the ISL70001ASEH remains in shutdown until the voltage at the enable input rises above the enable threshold. As shown in Figure 23, the enable circuit features a comparator type input. In addition to simple logic on/off control, the enable circuit allows the level of an external voltage to precisely gate the turn-on/turn-off of the regulator. An internal IEN current sink with a typical value of 11µA is only active when the voltage on the EN pin is below the enable threshold. The current sink pulls the EN pin low. As VIN2 rises, the enable level is not set exclusively by the resistor divider from VIN2. With the current sink active, the enable level is defined by Equation 4. R1 is the resistor from the EN pin to VIN2 and R2 is the resistor from the EN pin to the AGND pin. R1 V ENABLE = V R ⋅ 1 + ------- + I EN ⋅ R1 R2 R1 V DISABLE = V R ⋅ 1 + ------R2 (EQ. 5) The difference between the enable and disable levels provides adjustable hysteresis so that noise on VIN2 does not interfere with the enabling or disabling of the regulator. To mitigate SEE, the EN pin should be bypassed to the AGND pin with a 10nF ceramic capacitor. Soft-Start Once the POR and enable circuits are satisfied, the regulator initiates a soft-start. Figure 24 shows that the soft-start circuit clamps the error amplifier reference voltage to the voltage on an external soft-start capacitor connected to the SS pin. VREF = 0.6V ISS = 23µA RD = 2.2Ω VOUT RT FB RB ERROR AMPLIFIER PWM LOGIC + + SS REF VREF CSS CREF RD ISS (EQ. 4) Once the voltage at the EN pin reaches the enable threshold, the IEN current sink turns off. 14 With the part enabled and the IEN current sink off, the disable level is set by the resistor divider. The disable level is defined by Equation 5. FIGURE 24. SOFT-START CIRCUIT FN8365.0 May 22, 2013 ISL70001ASEH The soft-start capacitor is charged by an internal ISS current source. As the soft-start capacitor is charged, the output voltage slowly ramps to the set point determined by the reference voltage and the feedback network. Once the voltage on the SS pin is equal to the internal reference voltage, the soft-start interval is complete. The controlled ramp of the output voltage reduces the inrush current during start-up. The soft-start output ramp interval is defined in Equation 6 and is adjustable from approximately 2ms to 200ms. The value of the soft-start capacitor, CSS, should range from 8.2nF to 8.2µF, inclusive. The peak inrush current can be computed from Equation 7. The softstart interval should be long enough to ensure that the peak inrush current plus the peak output load current does not exceed the overcurrent trip level of the regulator. V REF t SS = C SS ⋅ ------------I (EQ. 6) SS V OUT I INRUSH = C OUT ⋅ ------------t (EQ. 7) SS The soft-start capacitor is immediately discharged by a 2.2Ω resistor whenever POR conditions are not met or EN is pulled low. The soft-start discharge time is equal to 256 clock cycles. Power-Good The power-good (PGOOD) pin is an open-drain logic output that indicates when the output voltage of the regulator is within regulation limits. The power-good pin pulls low during shutdown and remains low when the controller is enabled. After a successful soft-start, the PGOOD pin releases, and the voltage rises with an external pull-up resistor. The power-good signal transitions low immediately when the EN pin is pulled low. The power-good circuitry monitors the FB pin and compares it to the rising and falling thresholds shown in the “Electrical Specifications” table on page 9. If the feedback voltage exceeds the typical rising limit of 111% of the reference voltage, the PGOOD pin pulls low. The PGOOD pin continues to pull low until the feedback voltage falls to a typical of 107.5% of the reference voltage. If the feedback voltage drops below a typical of 89% of the reference voltage, the PGOOD pin pulls low. The PGOOD pin continues to pull low until the feedback voltage rises to a typical 92.5% of the reference voltage. The PGOOD pin then releases and signals the return of the output voltage to within the power-good window. The PGOOD pin can be pulled up to any voltage from 0V to 5.5V, independently from the supply voltage. The pull-up resistor should have a nominal value from 1kΩ to 10kΩ. The PGOOD pin should be bypassed to DGND, with a 10nF ceramic capacitor to mitigate SEE. Fault Monitoring and Protection The ISL70001ASEH actively monitors output voltage and current to detect fault conditions. Fault conditions trigger protective measures to prevent damage to the regulator and external load device. 15 Undervoltage Protection A hysteretic comparator monitors the FB pin of the regulator. The feedback voltage is compared to an undervoltage threshold that is a fixed percentage of the reference voltage. Once the comparator trips, indicating a valid undervoltage condition, an undervoltage counter increments. The counter is reset if the feedback voltage rises back above the undervoltage threshold, plus a specified amount of hysteresis outlined in the “Electrical Specifications” table on page 9. If the undervoltage condition exists for 3 consecutive counts the counter overflows and the undervoltage protection logic shuts down the regulator. After the regulator shuts down, it enters a delay interval equivalent to the soft-start interval, which allows the device to cool. The undervoltage counter is reset when the device enters the delay interval. The protection logic initiates a normal soft-start once the delay interval ends. If the output successfully soft-starts, the power-good signal goes high, and normal operation continues. If undervoltage conditions continue to exist during the soft-start interval, the undervoltage counter must overflow before the regulator shuts down again. This hiccup mode continues indefinitely until the output soft-starts successfully. Overcurrent Protection A pilot device integrated into the PMOS transistor of Power Block 4 samples current each cycle. This current feedback is scaled and compared to an overcurrent threshold based on the number of power blocks connected. Each additional power block connected beyond Power Block 4 increases the overcurrent limit by 2A. For example, if three power blocks are connected, the typical current limit threshold would be 3 x 2A = 6A. If the sampled current exceeds the overcurrent threshold, an overcurrent counter increments by one. Once the overcurrent counter reaches a count of 3, it overflows and the regulator shuts down. If the sampled current falls below the threshold before the counter overflows, the counter is reset. After the regulator shuts down, it enters a delay interval, equivalent to the soft-start interval, which allows the device to cool. The overcurrent counter is reset when the device enters the delay interval. The protection logic initiates a normal soft-start once the delay interval ends. If the output successfully soft-starts, the power-good signal goes high, and normal operation continues. If overcurrent conditions continue to exist during the soft-start interval, the overcurrent counter must overflow before the regulator shut downs the output again. This hiccup mode continues indefinitely until the output soft-starts successfully. Note: To prevent severe negative ringing that can disturb the overcurrent counter, it is recommended that a Schottky diode of appropriate rating be added from the LXx pins to the PGNDx pins. Feedback Loop Compensation To reduce the number of external components and to simplify the process of determining compensation components, the ISL70001ASEH buck regulator has an internally compensated error amplifier. FN8365.0 May 22, 2013 ISL70001ASEH Due to the current loop feedback in peak current mode control, the modulator has a single pole response with -20dB slope at a frequency determined by the load (Equation 8): 1 F PO = ------------------------------------2π ⋅ R O ⋅ C OUT (EQ. 8) where RO is load resistance and COUT is the output load capacitance. For this type of modulator, a Type 2 compensation circuit is usually sufficient. Figure 25 shows a Type 2 amplifier and its response, along with the responses of the current mode modulator and the converter. C2 R2 C1 CONVERTER R1 EA TYPE 2 EA FZ FPO FIGURE 25. FEEDBACK LOOP COMPENSATION The Type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole (Equations 9 and 10). (EQ. 9) 1 F P = ------------------------------ = 546kHz 2π ⋅ R 1 ⋅ C 2 (EQ. 10) Zero frequency and amplifier high-frequency gain were chosen to satisfy typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. Equation 13 on page 17 approximates the amount of capacitance needed to achieve an optimal pole location depending on the number of LXx pins connected. With this type of compensation, plenty of phase margin is easily achieved due to zero-pole pair phase ‘boost’. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 1.2kHz to 30kHz range gives some additional phase ‘boost’. Some phase boost is also achieved by connecting the recommended capacitor CC in parallel with the upper resistor RT of the divider that sets the output voltage value, as demonstrated in Figure 22. 16 Output Filter Design The output inductor and the output capacitor bank together form a low-pass filter responsible for smoothing the pulsating voltage at the phase node. The filter must also provide the transient energy until the regulator can respond. Since the filter has low bandwidth relative to the switching frequency, it limits the system transient response. The output capacitors must supply or sink current while the current in the output inductor increases or decreases to meet the load demand. The critical load parameters in choosing the output capacitors are the maximum size of the load step (ΔISTEP), the load-current slew rate (di/dt), and the maximum allowable output voltage deviation under transient loading (ΔVMAX). Capacitors are characterized according to their capacitance, ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance). FP FC 1 F Z = ------------------------------ = 8.6kHz 2π ⋅ R 2 ⋅ C 1 This design guide is intended to provide a high-level explanation of the steps necessary to create a power converter. It is assumed the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides a complete evaluation board that includes schematic, BOM, and an example PCB layout (see Ordering Information table on page 2). OUTPUT CAPACITOR SELECTION GEA = 25.1dB MODULATOR Component Selection Guide At the beginning of a load transient, the output capacitors supply all of the transient current. The output voltage initially deviates by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount shown in Equation 11. di ΔV MAX ≈ ESL × ----- + [ ESR × ΔI STEP ] dt (EQ. 11) The filter capacitors selected must have sufficiently low ESL and ESR such that the total output voltage deviation is less than the maximum allowable ripple. Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but larger ESR. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. Ceramic capacitors with X7R dielectric are recommended. Alternately, a combination of low ESR solid tantalum capacitors and ceramic capacitors with X7R dielectric may be used. The ESR of the bulk capacitors is responsible for most of the output voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current, a voltage, VP-P(MAX), develops across the bulk capacitor according to Equation 12. ( V IN – V OUT )V OUT V P-P(MAX) = ESR × ---------------------------------------------L OUT × f s × V IN (EQ. 12) FN8365.0 May 22, 2013 ISL70001ASEH Another consideration in selecting the output capacitors is loop stability. The total output capacitance sets the dominant pole of the PWM. Because the ISL70001ASEH uses integrated compensation techniques, it is necessary to restrict the output capacitance in order to optimize loop stability. The recommended load capacitance can be estimated using Equation 13. 1.8V C OUT = 75μF × NumberofLXxPinsConnected × ------------V OUT (EQ. 13) Another stability requirement on the selection of the output capacitor is that the ‘ESR zero’ (f ZESR) be placed at 60kHz to 90kHz. This range is set by an internal, single compensation zero at 8.6kHz. This ESR zero location contributes to increased phase margin of the control loop; therefore if a capacitor is chosen with an inadequate ESR stability may be compromised. Equation 14 maybe be used to calculate the required ESR to place the ‘ESR zero’ in the recommended range: 1 ESR = ---------------------------------------------2π ( f ZESR ) ( C OUT ) (EQ. 14) 2 ⋅ C OUT L OUT ≤ ------------------------- ΔV MAX – ( ΔI L(P-P) ⋅ ESR ) ⎛ V IN – V OUT⎞ ⎝ ⎠ ( ΔI STEP ) 2 The other concern when selecting an output inductor is to ensure there is adequate slope compensation when the regulator is operated above 50% duty cycle. Since the internal slope compensation is fixed, output inductance should satisfy Equation 18 to ensure this requirement is met. 4.32μH L OUT ≥ ----------------------------------------------------------------------------------NumberofLXxPinsConnected 2. The ESR must be sufficiently low to meet the desired output voltage ripple due to the output inductor current. 3. The ESR zero should be placed, in a rather large range, to provide additional phase margin. OUTPUT INDUCTOR SELECTION Once the output capacitors are selected, the maximum allowable ripple voltage, VP-P(MAX), determines the lower limit on the inductance as shown in Equation 15. ( V IN – V OUT )V OUT L OUT ≥ ESR × -------------------------------------------------f s × V IN × V P-P(MAX) (EQ. 15) Since the output capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductor must be capable of assuming the entire load current before the output voltage decreases more than ΔVMAX. This places an upper limit on inductance. Equation 16 gives the upper limit on output inductance for the case when the trailing edge of the current transient causes a greater output voltage deviation than the leading edge. Equation 17 addresses the leading edge. Normally, the trailing edge dictates the inductance selection because duty cycles are usually <50%. Nevertheless, both inequalities should be evaluated, and inductance should be governed based on the lower of the two results. In each equation, LOUT is the output inductance, COUT is the total output capacitance, and ΔIL(P-P) is the peak-to-peak ripple current in the output inductor. 2 ⋅ C OUT ⋅ V OUT L OUT ≤ --------------------------------------ΔV MAX – ( ΔI L(P-P) ⋅ ESR ) ( ΔI STEP ) 2 17 (EQ. 18) Input Capacitor Selection Input capacitors are responsible for sourcing the AC component of the input current flowing into the switching power devices. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the switching power devices, which is related to duty cycle. The maximum RMS current required by the regulator is closely approximated by Equation 19. I RMS MAX = 2 V OUT ⎛ 2 1 ⎛ V IN – V OUT V OUT⎞ ⎞ ----------------- × ⎜ I + ------ × ⎜ ---------------------------------- × -----------------⎟ ⎟ OUT 12 ⎝ L V V × f ⎝ ⎠ ⎠ MAX IN IN OUT s (EQ. 19) In conclusion, the output capacitors must meet three criteria: 1. They must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient. (EQ. 17) The important parameters to consider when selecting an input capacitor are the voltage rating and the RMS ripple current rating. For reliable operation, select capacitors with voltage ratings at least 1.5x greater than the maximum input voltage. The capacitor RMS ripple current rating should be higher than the largest RMS ripple current required by the circuit. Ceramic capacitors with X7R dielectric are recommended. Alternately, a combination of low ESR solid tantalum capacitors and ceramic capacitors with X7R dielectric may be used. The ISL70001ASEH requires a minimum effective input capacitance of 100µF for stable operation. Derating Current Capability Most space programs issue specific derating guidelines for parts, but these guidelines take the pedigree of the part into account. For instance, a device built to MIL-PRF-38535, such as the ISL70001ASSEH, is already heavily derated from a current density standpoint. However, a mil-temp or commercial IC that is up-screened for use in space applications may need additional current derating to ensure reliable operation because it was not built to the same standards as the ISL70001ASEH. Figure 26 shows the maximum average output current of the ISL70001ASEH with respect to junction temperature. These plots take into account the worst-case current share mismatch in the power blocks and the current density requirement of MIL-PRF38535 (< 2 x 105 A/cm2). The plot clearly shows that the ISL70001ASEH can handle 12.1A at +125°C from a worst-case current density standpoint, but the part is limited to 7.8A (EQ. 16) FN8365.0 May 22, 2013 ISL70001ASEH MAXIMUM AVERAGE CURRENT FOR 0.1% FAILURES AT 100,000 HOURS (A) because that is the lower limit of the current limit threshold with all six power blocks connected. 12 12.14 3A 11 9 MINIMUM OCP LEVEL = 7.8A 8.57 8 6.16 130 135 140 145 + 5.3 6A @ +146°C 125 COUT 150 RT PGNDx CC FB - 6 4 120 ERROR AMPLIFIER 7.25 7 5 RS VOUT CS 10.18 10 LOUT LXx 13 VREF RB REF CREF 155 JUNCTION TEMPERATURE (°C) FIGURE 26. CURRENT vs TEMPERATURE PCB Design PCB design is critical to high-frequency switching regulator performance. Careful component placement and trace routing are necessary to reduce voltage spikes and minimize undesirable voltage drops. Selection of a suitable thermal interface material is also required for optimum heat dissipation and to provide lead strain relief. See Table 1 on page 21 for layout x-y coordinates. FIGURE 27. SCHOTTKY DIODE AND R-C SNUBBER PCB Layout Use a small island of copper to connect the LXx pins of the IC to the output inductor on Layers 1 and 4. To minimize capacitive coupling to the power and ground planes, void the copper on Layers 2 and 3 adjacent to the island. Place most of the island of Layer 4 to minimize the amount of copper that must be voided from the ground plane (Layer 2). Keep all other signal traces as short as possible. For an example layout, see AN1842. PCB Plane Allocation Thermal Management for Ceramic Package Four layers of 2-ounce copper are recommended. Layer 2 should be a dedicated ground plane with all critical component ground connections made with vias to this layer. Layer 3 should be a dedicated power plane split between the input and output power rails. Layers 1 and 4 should be used primarily for signals but can also provide additional power and ground islands, as required. For optimum thermal performance, place a pattern of vias and a thermal land on the top layer of the PCB directly underneath the IC. Connect the vias to the plane which serves as a heat sink. To ensure good thermal contact, thermal interface material such as a Sil-Pad or thermally conductive epoxy should be used to fill the gap between the vias and the bottom of the ceramic package. PCB Component Placement Lead Strain Relief Components should be placed as close as possible to the IC to minimize stray inductance and resistance. Prioritize the placement of bypass capacitors on the pins of the IC in the order shown: REF, SS, AVDD, DVDD, PVINx (high frequency capacitors), EN, PGOOD, PVINx (bulk capacitors). The package leads protrude from the bottom of the package and the leads need forming to provide strain relief. On the ceramic bottom package R48.A, the Sil-pad or epoxy maybe be used to fill the gap left between the PCB board and the bottom of the package when lead forming is completed. On the heat sink option of the package, R48.B, the lead forming should be made so that the bottom of the heat sink and the formed leads are flush. Locate the output voltage resistive divider as close as possible to the FB pin of the IC. The top leg of the divider should connect directly to the POL (Point of Load), and the bottom leg of the divider should connect directly to AGND. The junction of the resistive divider should connect directly to the FB pin. Locate a Schottky clamp diode as close as possible to the LXx and PGNDx pins of the IC. A small series R-C snubber connected from the LXx pins to the PGNDx pins may be used to damp high frequency ringing on the LXx pins, if desired, see Figure 27. 18 Heat Sink Mounting Guidelines The R48.B package option has a heat sink mounted on the underside of the package. The following JESD51-5 guidelines may be used to mount the package: 1. Place a thermal land on the PCB under the heat sink. 2. The land should be approximately the same size as to 1mm larger than the 9x9mm heat sink. FN8365.0 May 22, 2013 ISL70001ASEH 3. Place an array of thermal vias below the thermal land. - Via array size: ~8x8=64 thermal vias - Via diameter: ~0.3mm drill diameter with plated copper on the inside of each via. - Via pitch: ~1.2mm. - Vias should drop to and contact as much buried metal area as feasible to provide the best thermal relief. Heat Sink Electrical Potential The heat sink is electrically isolated and unbiased. The heatsink may be electrically connected to any potential which offers the best thermal relief through conductive mounting materials (conductive epoxy, solder, etc) or may be left unbiased through the use of electrically non-conductive mounting materials (non-conductive epoxy, Sil-pad, kapton film, etc.). 19 FN8365.0 May 22, 2013 ISL70001ASEH Weight Characteristics Weight of Packaged Device 1.602 Grams typical - R48.A Package 2.440 Grams typical - R48.B Package Die Characteristics Die Dimensions 5720µm x 5830µm (225.2 mils x 229.5 mils) Thickness: 483µm ± 25.4µm (19.0 mils ± 1 mil) Interface Materials BACKSIDE FINISH Silicon ASSEMBLY RELATED INFORMATION Substrate Potential Package R48.A and R48.B PGND Metal Lid Potential Electrically Isolated -Package R48.A PGND - Package R48.B ADDITIONAL INFORMATION Worst Case Current Density < 2 x 105 A/cm2 GLASSIVATION Type: Silicon Oxide and Silicon Nitride Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm TOP METALLIZATION Type: AlCu (0.5%) Thickness: 2.7µm ±0.4µm Transistor Count 25030 Layout Characteristics Step and Repeat 5720µm x 5830µm Connect PGND to PGNDx SUBSTRATE Type: Silicon Isolation: Junction 20 FN8365.0 May 22, 2013 ISL70001ASEH Metallization Mask Layout ISL70001ASEH LX1 SYNC PVIN1 PGND1 PGND2 LX2 PVIN2 PVIN3 M/S ZAP LX3 TDI TDO PGND3 PGOOD PGND4 SS LX4 DVDD PVIN4 PVIN5 DGND PGND LX5 AGND AVDD REF FB EN PORSEL PVIN6 LX6 PGND6 PGND5 ORIGIN TABLE 1. LAYOUT X-Y COORDINATES PAD NUMBER X (µm) Y (µm) dX (µm) dY (µm) BOND WIRES PER PAD AVDD 15 478 263 135 135 1 REF 16 865 263 135 135 1 FB 17 1295 263 135 135 1 EN 18 1751 263 135 135 1 PORSEL 19 2151 263 135 135 1 PVIN6 20 2838 188 521 135 3 LX6 21 3449 188 521 135 3 PGND6 22 4060 188 521 135 3 PGND5 23 4845 188 521 135 3 LX5 24 5449 925 135 521 3 PVIN5 25 5449 1651 135 521 3 PVIN4 26 5449 2263 135 521 3 LX4 27 5449 2874 135 521 3 PAD NAME 21 FN8365.0 May 22, 2013 ISL70001ASEH TABLE 1. LAYOUT X-Y COORDINATES (Continued) PAD NUMBER X (µm) Y (µm) dX (µm) dY (µm) BOND WIRES PER PAD PGND4 28 5449 3485 135 521 3 PGND3 29 5449 4096 135 521 3 LX3 30 5449 4745 135 521 3 PVIN3 31 4941 5559 521 135 3 PVIN2 32 4137 5559 521 135 3 LX2 33 3449 5559 521 135 3 PGND2 34 2838 5559 521 135 3 PGND1 1 2227 5559 521 135 3 LX1 2 1578 5559 521 135 3 PVIN1 3 962 5559 521 135 3 SYNC 4 544 5559 135 135 1 M/S 5 226 5280 135 135 1 ZAP 6 226 4910 135 135 1 TDI 7 226 4540 135 135 1 TDO 8 226 4170 135 135 1 PGOOD 9 226 3777 135 135 1 SS 10 226 3425 135 135 1 DVDD 11 226 2566 135 333 2 DGND 12 226 1538 135 333 2 PGND 13 226 1018 135 135 1 AGND 14 226 654 135 135 1 PAD NAME 22 FN8365.0 May 22, 2013 ISL70001ASEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION May 22, 2013 FN8365.0 CHANGE Initial Release About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at http://www.intersil.com/en/support/qualandreliability.html#reliability For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 23 FN8365.0 May 22, 2013 ISL70001ASEH Package Outline Drawing R48.A 48 CERAMIC QUAD FLATPACK PACKAGE (CQFP) Rev 3, 10/12 1.118 (28.40) 1.080 (27.43) 0.572 (14.53) 0.555 (14.10) #1 #48 0.287 (7.29) 0.253 (6.43) 0.040 (1.02) BSC PIN 1 INDEX AREA 0.572 (14.53) 0.555 (14.10) 1.118 (28.40) 1.080 (27.43) 0.007 (0.18) MIN 0.015 (0.38) 0.008 (0.20) 0.015 (0.38) MIN TOP VIEW 0.099 (2.51) 0.076 (1.93) 0.016 (0.41) 0.009 (0.23) SIDE VIEW NOTE: 1. All dimensions are in inches (millimeters). 24 FN8365.0 May 22, 2013 ISL70001ASEH Package Outline Drawing R48.B 48 CERAMIC QUAD FLATPACK PACKAGE (CQFP) WITH BOTTOM HEATSINK Rev 0, 10/12 1.118 (28.40) 1.080 (27.43) 0.572 (14.53) 0.555 (14.10) #1 #48 0.287 (7.29) 0.253 (6.43) 0.040 (1.016) BSC PIN 1 INDEX AREA 1.118 (28.40) 1.080 (27.43) 0.572 (14.53) 0.555 (14.10) 0.012 (0.30) 0.008 (0.20) TOP VIEW 0.131 (3.33) 0.105 (2.67) 0.042 (1.067) REF 0.026 (0.66) MIN. 2 0.013 (0.33) 0.009 (0.23) HEATSINK SIDE VIEW 0.359 (9.12) 0.349 (8.87) HEATSINK 0.359 (9.12) 0.349 (8.87) PIN 1 INDEX AREA NOTES: 1. All dimensions are in inches (millimeters) 2. Dimension shall be measured at point of exit (beyond the meniscus) of the lead from the body. 25 #1 #48 BOTTOM VIEW FN8365.0 May 22, 2013