Dual LDO with Low Noise, High Performance and Low IQ ISL78302 Features ISL78302 is a high performance dual LDO capable of sourcing 300mA current from each output. It has a low standby current and is stable with output capacitance of 1µF to 10µF with ESR of up to 200mΩ. • Integrates Two 300mA High Performance LDOs The device integrates an individual Power-On-Reset (POR) function for each output. The POR delay for VO2 can be externally programmed by connecting a timing capacitor to the CPOR pin. The POR delay for VO1 is internally fixed at approximately 2ms. A reference bypass pin is also provided for connecting a noise filtering capacitor for low noise and high-PSRR applications. The quiescent current is typically only 47µA with both LDOs enabled and active. Separate enable pins control each individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.5µA. The part operates down to 2.3V and up to 6.5V input. The typical output voltage can be as low as 1.2V and as high as 3.3V for each regulator. Please refer to the ordering information section for standard options. Other voltage selections are available upon request. • Excellent Transient Response to Large Current Steps • ±1.8% Accuracy Over All Operating Conditions • Excellent Load Regulation: < 0.1% Voltage Change Across Full Range of Load Current • Extremely Low Quiescent Current: 47µA (Both LDOs Active) • Wide Input Voltage Capability: 2.3V to 6.5V • Low Dropout Voltage: Typically 300mV @ 300mA • Low Output Noise: Typically 37µVRMS @ 100µA (1.5V) • Stable with 1µF to 10µF Ceramic Capacitors • Separate Enable and POR Pins for Each LDO • Soft-start and Staged Turn-on to Limit Input Current Surge During Enable • Current Limit and Over-temperature Protection • Tiny 10 Lead 3mm x 3mm DFN Package • TS16949 Compliant • AEC - Q100 Tested The ISL78302 is both AEC - Q100 rated and fully TS16949 compliant. The ISL78302 is rated for the automotive temperature range (-40°C to +105°C). • Pb-free (RoHS Compliant) Applications • Radio Receivers • Camera Modules • GPS/Navigation • Infotainment Systems Typical Application ISL78302 VIN (2.3 TO 6.5V) 1 ON 2 ENABLE1 OFF ON ENABLE2 OFF 3 4 5 C1 C2 VIN EN1 VO1 VO2 EN2 POR2 CBYP POR1 CPOR GND 10 VOUT1 9 VOUT2 OK 8 7 VOUT2 TOO LOW VOUT1 OK 6 C3 C4 C5 VOUT1 TOO LOW VOUT2 RESET2 (200ms DELAY, C3 = 0.01µF) RESET1 (2ms DELAY) C1, C4, C5: 1µF X5R CERAMIC CAPACITOR C2: 0.01µF X7R CERAMIC CAPACITOR C3: 0.01µF X7R CERAMIC CAPACITOR January 28, 2011 FN7696.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL78302 Block Diagram VIN VO1 VO2 LDO ERROR AMPLIFIER VO1 ~1.0V VREF TRIM IS1 VO2 POR COMPARATOR QEN1 VOK1 1V POR1 LDO-1 POR2 QEN2 VO1 100k QEN1 IS2 LDO-2 IS1 VOK2 EN1 CONTROL LOGIC EN2 POR2 POR2 DELAY VOK2 CBYP VO2 BANDGAP AND TEMPERATURE SENSOR VOLTAGE REFERENCE GENERATOR 100k UVLO 1.00V POR1 DELAY VOK1 0.94V POR1 0.90V GND CPOR Pin Configuration ISL78302 (10 LD 3X3 DFN) TOP VIEW 2 VIN 1 10 VO1 EN1 2 9 VO2 EN2 3 8 POR2 CBYP 4 7 POR1 CPOR 5 6 GND FN7696.0 January 28, 2011 ISL78302 Pin Descriptions PIN NUMBER PIN NAME 1 VIN Analog I/O Supply Voltage/LDO Input. Connect a 1µF capacitor to GND. 2 EN1 Low Voltage Compatible CMOS Input LDO-1 Enable. ENABLE = HIGH 3 EN2 Low Voltage Compatible CMOS Input LDO-2 Enable. ENABLE = HIGH 4 CBYP Analog I/O Reference Bypass Capacitor Pin. Recommended to connect capacitor of value 0.01µF between this pin and GND for optimum noise and PSRR performance. 5 CPOR Analog I/O POR2 Delay Setting Capacitor Pin. Connect a capacitor between this pin and GND to delay the POR2 output release after LDO-2 output reaches 94% of its specified voltage level. (200ms delay per 0.01µF). 6 GND Ground GND is the connection to system ground. Connect to PCB Ground plane. 7 POR1 Open Drain Output (1mA) Open-drain POR Output for LDO-1 (active-low). Internally connected to VO1 through 100kΩ resistor. 8 POR2 Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low). Internally connected to VO2 through 100kΩ resistor. 9 VO2 Analog I/O LDO-2 Output. Connect capacitor of value 1µF to 10µF to GND (1µF recommended). 10 VO1 Analog I/O LDO-1 Output. Connect capacitor of value 1µF to 10µF to GND (1µF recommended). TYPE DESCRIPTION Ordering Information PART NUMBER (Notes 1, 3, 4) PART MARKING VO1 VOLTAGE (V) (Note 2) VO2 VOLTAGE (V) (Note 2) TEMP RANGE (°C) PACKAGE (Pb-Free) PKG DWG. # ISL78302ARFBZ DNAB 2.5 1.5 -40 to +105 10 Ld 3x3 DFN L10.3x3C Coming Soon ISL78302ARBFZ DNAC 1.5 2.5 -40 to +105 10 Ld 3x3 DFN L10.3x3C Coming Soon ISL78302ARNBZ DNAD 3.3 1.5 -40 to +105 10 Ld 3x3 DFN L10.3x3C Coming Soon ISL78302ARBNZ DNAE 1.5 3.3 -40 to +105 10 Ld 3x3 DFN L10.3x3C Coming Soon ISL78302ARNWZ DNAF 3.3 1.2 -40 to +105 10 Ld 3x3 DFN L10.3x3C Coming Soon ISL78302ARWCZ DNAG 1.2 1.8 -40 to +105 10 Ld 3x3 DFN L10.3x3C Coming Soon ISL78302ARFWZ DNAH 2.5 1.2 -40 to +105 10 Ld 3x3 DFN L10.3x3C Coming Soon ISL78302ARCWZ DANJ 1.8 1.2 -40 to +105 10 Ld 3x3 DFN L10.3x3C NOTES: 1. Add “-T*”suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. For other output voltages, contact Intersil. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL78302. For more information on MSL please see techbrief TB363. 3 FN7696.0 January 28, 2011 ISL78302 Absolute Maximum Ratings Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.1V VO1, VO2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V Thermal Resistance (Notes 5, 6) θJA (°C/W) θJC (°C/W) 10 Ld 3x3 DFN Package . . . . . . . . . . . . . . . 59 18.5 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Operating Temperature Range . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp ESD Ratings Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . 3kV Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . . . 200V Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . . . 2kV Recommended Operating Conditions Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-40°C to +105°C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +105°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF; CPOR = 0.01µF. Boldface limits apply over the operating temperature range, -40°C to +105°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNITS 6.5 V DC CHARACTERISTICS Supply Voltage VIN 2.3 Quiescent condition: IO1 = 0µA; IO2 = 0µA Ground Current IDD1 One LDO active 30 36 µA IDD2 Both LDO active 47 55 µA 0.3 2.1 µA Shutdown Current IDDS UVLO Threshold VUV+ 1.9 2.1 2.3 V VUV- 1.6 1.8 2.0 V Regulation Voltage Accuracy Maximum Output Current IMAX Internal Current Limit ILIM Dropout Voltage (Note 7) VDO Thermal Shutdown Temperature VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = +25°C -0.8 +0.8 % VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = -40°C to +125°C -1.8 +1.8 % Continuous 300 320 mA 475 IO = 300mA 300 IO = 150mA 150 650 mA mV 250 mV TSD+ 145 °C TSD- 110 °C @ 1kHz 64 dB @ 10kHz 51 dB @ 100kHz 38 dB AC CHARACTERISTICS Ripple Rejection IO = 10mA, VIN = 2.8V(min), VO = 1.5V, CBYP = 0.01µF 4 FN7696.0 January 28, 2011 ISL78302 Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +105°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF; CPOR = 0.01µF. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued) PARAMETER SYMBOL MIN (Note 8) TEST CONDITIONS IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.01µF BW = 10Hz to 100kHz Output Noise Voltage TYP MAX (Note 8) 37 UNITS µVRMS DEVICE START-UP CHARACTERISTICS Device Enable Time tEN Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO(nom) 250 500 µs LDO Soft-Start Ramp Rate tSSR Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V EN1, EN2 PIN CHARACTERISTICS Input Low Voltage VIL -0.3 0.5 V Input High Voltage VIH 1.35 VIN + 0.3 V 0.1 µA Input Leakage Current IIL, IIH Pin Capacitance CPIN Informative 5 pF POR1, POR2 PIN CHARACTERISTICS POR1, POR2 Thresholds VPOR+ POR1 Delay As a percentage of nominal output voltage 91 94 97 % VPOR- 87 90 93 % tP1LH 0.5 2.0 3.2 ms 25 tP1HL POR2 Delay tP2LH CPOR = 0.01µF 100 VOL POR1, POR2 Pin Internal Pull-Up Resistance 300 25 tP2HL POR1, POR2 Pin Output Low Voltage 200 µs @ IOL = 1.0mA RPOR 78 100 ms µs 0.2 V 180 kΩ NOTES: 7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V. 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. EN1 EN2 tEN VPOR+ VPOR- VPOR+ VPOR- <tP1HL VO1 VO2 <tP2HL tP1LH tP1HL tP2LH tP2HL POR1 POR2 FIGURE 1. TIMING PARAMETER DEFINITION 5 FN7696.0 January 28, 2011 ISL78302 Typical Performance Curves 0.20 0.4 VO = 2.5V ILOAD = 0mA +25°C 0.2 -40°C +105°C 0.1 0 -0.1 -0.2 -0.3 -0.4 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VIN = 3.3V 0.15 OUTPUT VOLTAGE CHANGE (%) OUTPUT VOLTAGE, VO (%) 0.3 VO = 2.5V 0.10 +25°C 0 -0.05 -0.10 -0.15 -0.20 6.5 0 50 100 INPUT VOLTAGE (V) 200 250 300 400 2.6 0.08 VIN = 3.3V VO = 2.5V 2.4 OUTPUT VOLTAGE, VO (V) 0.06 0.04 0.02 0 -0.02 -0.04 VIN = 3.3V VO = 1.5V -0.06 VO = 2.5V IO = 0mA 2.2 IO = 150mA IO = 300mA 2.0 VO = 1.5V IO = 0mA IO = 150mA IO = 300 mA 1.8 1.6 -0.08 -0.10 -40 -25 -10 5 20 35 50 65 80 95 1.4 1.5 110 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 INPUT VOLTAGE (V) TEMPERATURE (°C) FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.5V and 1.5V OUTPUT) FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE 55 400 +105°C VO = 1.5V +25°C 300 54 -40°C 53 GROUND CURRENT (µA) 350 250 200 150 100 50 0 350 FIGURE 3. LOAD REGULATION 0.10 OUTPUT VOLTAGE CHANGE (%) 150 LOAD CURRENT - IO (mA) FIGURE 2. LINE REGULATION (2.5V OUTPUT) DROPOUT VOLTAGE, VDO (mV) +105°C -40°C 0.05 +105°C +25°C 52 -40°C 51 50 49 48 VO1 = 2.5V VO2= 1.5V IO (BOTH CHANNELS) = 0µA 47 46 0 50 100 150 200 250 300 350 OUTPUT LOAD (mA) FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT 6 400 45 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 INPUT VOLTAGE (V) FIGURE 7. GROUND CURRENT vs INPUT VOLTAGE FN7696.0 January 28, 2011 ISL78302 Typical Performance Curves (Continued) 200 60 VIN = 3.6V VO1= 2.5V VO1= 2.5V +105°C VO2= 1.5V 160 GROUND CURRENT (µA) GROUND CURRENT (µA) 180 VIN = 3.5V 140 120 100 80 -40°C VO2= 1.5V 55 ILOAD = 0µA BOTH OUTPUTS ON 50 45 60 +25°C 40 0 50 100 150 200 250 LOAD CURRENT (mA) 300 350 FIGURE 8. GROUND CURRENT vs LOAD 400 40 -40 -25 -10 80 95 110 VO1 = 2.5V VO2 = 1.5V IL1 = 300mA POR1 IL2 = 300mA VO1 VO1 20 35 50 65 TEMPERATURE (°C) FIGURE 9. GROUND CURRENT vs TEMPERATURE VO1 = 2.5V VO2 = 1.5V IL1 = 300mA VIN 5 VO2 IL2 = 300mA CPOR = 0.01µF POR2 V02 FIGURE 10. POWER-UP/POWER-DOWN VO2 (10mV/DIV) FIGURE 11. POWER-UP/POWER-DOWN WITH POR SIGNALS VO (50mV/DIV) VIN = 3.5V VO = 1.5V VO1 = 2.5V VO2 = 1.5V IL1, IL2 = 300mA CBYP = 0.01uF CL1, CL2 = 1µF ILOAD FIGURE 12. TURN-ON/TURN-OFF RESPONSE 7 FIGURE 13. LOAD TRANSIENT RESPONSE FN7696.0 January 28, 2011 ISL78302 Typical Performance Curves (Continued) 100 10 90 VOUT = 1.5V 80 IO = 10mA CLOAD = 1µF 70 PSRR (dB) SPECTRAL NOISE DENSITY (mV/√Hz) VIN = 3.3V CBYP = 0.01µF 60 50 40 30 20 10 0 10 100 1k 10k 100k VIN = 3.6V VOUT = 2.5V ILOAD = 10mA CIN = 1µF 1 CLOAD = 1µF CBYP = 0.01µF 0.1 0.01 10 1M 100 1k FIGURE 14. PSRR vs FREQUENCY 1M 10 VIN = 3.6V SPECTRAL NOISE DENSITY (mV/√Hz) SPECTRAL NOISE DENSITY (mV/√Hz) 100k FIGURE 15. SPECTRAL NOISE DENSITY vs FREQUENCY (2.5V OUTPUT, 10mA LOAD) 10 VOUT = 2.5V ILOAD = 300mA CIN = 1µF 1 CLOAD = 1µF CBYP = 0.01µF 0.1 0.01 10 10k FREQUENCY (Hz) FREQUENCY (Hz) 100 1k 10k 100k VIN = 3.6V VOUT = 1.5V ILOAD = 10mA CIN = 1µF 1 CLOAD = 1µF CBYP = 0.01µF 0.1 0.01 10 1M 100 1k 10k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 16. SPECTRAL NOISE DENSITY vs FREQUENCY (2.5V OUTPUT, 300mA LOAD) 100k 1M FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY (1.5V OUTPUT, 10mA LOAD) SPECTRAL NOISE DENSITY (mV/√Hz) 10 VIN = 3.6V VOUT = 1.5V ILOAD = 300mA CIN = 1µF 1 COUT = 1µF CBYP = 0.01µF 0.1 0.01 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 18. SPECTRAL NOISE DENSITY vs FREQUENCY (1.5V OUTPUT, 300mA LOAD) 8 FN7696.0 January 28, 2011 ISL78302 Functional Description The ISL78302 contains two high performance LDOs. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL78302 adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, staged turn-on and soft-start. Smart thermal shutdown protects the device against overheating. Staged turn-on and soft-start minimize start-up input current surges without causing excessive device turn-on time. Power Control The ISL78302 has two separate enable pins (EN1 and EN2) to individually control power to each of the LDO outputs. When both EN1 and EN2 are low, the device is in shutdown mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.5µA. When one or both of the enable pins is asserted, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power-up. Once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the CBYP pin) to the proper operating voltage. After the bypass capacitor has been charged, the LDOs power-up in their specified sequence. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30µs/V to minimize current surge. If EN1 is brought high and EN2 goes high before the VO1 output stabilizes, the ISL78302 delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high and EN1 goes high before VO2 starts its output ramp, then VO1 turns on first and, the ISL78302 delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high and EN1 goes high after VO2 starts its output ramp, then the ISL78302 immediately starts to ramp up the VO1 output. If both EN1 and EN2 are brought high at the same time, the VO1 output has priority and is always powered up first. During operation, whenever the VIN voltage drops below 1.8V, the ISL78302 immediately disables both LDO outputs. When VIN rises back above 2.1V, the device re-initiates its start-up sequence, and LDO operation will resume automatically. Reference Generation The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01µF (capacitor connected CBYP) implements a 100Hz lowpass filter and is recommended for most high-performance applications. Capacitor values above 0.01µF are not recommended for the CBYP pin. 9 The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference, POR detection thresholds, and other voltage references required for current generation and over-temperature detection. The current generator provides the references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. LDO Regulation and Programmable Output Divider The LDO regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL78302 provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1µF to 10µF output capacitor that has a tolerance better than 20% and an ESR less than 200mΩ. The design is performance-optimized for a 1µF capacitor. Unless limited by the application, use of an output capacitor value above 4.7µF is not normally needed, as LDO performance improvement is minimal. Each LDO uses an independently trimmed 1V reference. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory to the output voltages of 1.2V, 1.5V, 1.8V, 2.5V and 3.3V. Power-On Reset Generation Each LDO has a separate Power-on Reset signal generation circuit, which outputs to the respective POR pins. The POR signal is generated as follows. A POR comparator continuously monitors the output of each LDO. The LDO enters a power-good state when the output voltage is above 94% of the expected output voltage for a period exceeding the LDO PGOOD entry delay time. In the power-good state, the open-drain PORx output is in a high-impedance state. An internal 100kΩ pull-up resistor pulls the pin up to the respective LDO output voltage. An external resistor can be added between the PORx output and the LDO output for a faster rise time; however, the PORx output should not connect through an external resistor to a supply greater than the associated LDO voltage. The power-good state is exited when the LDO output falls below 90% of the expected output voltage for a period longer than the PGOOD exit delay time. While power-good is false, the ISL78302 pulls the respective POR pin low. For LDO-1, the PGOOD entry delay time is fixed at about 2ms, while the PGOOD exit delay is about 25µs. For LDO-2, the PGOOD entry and exit delays are determined by the value of the external capacitor connected to the CPOR pin. For a 0.01µF capacitor, the entry and exit delays are 200ms and 25µs, respectively. Larger or smaller capacitor values will yield proportionately longer or shorter delay times. The POR exit delay should never be allowed to be less than 10µs to ensure sufficient immunity against transient induced false POR triggering. FN7696.0 January 28, 2011 ISL78302 Over-Temperature Detection The bandgap provides a proportional-to-temperature current that indicates the temperature of the silicon. This current is compared with references to determine whether the device is in danger of damage from overheating. When the die temperature reaches about +145°C, one or both of the LDOs momentarily shuts down until the die cools sufficiently. In the overheat condition, only the LDO sourcing more than 50mA is shut off. This shutoff does not affect the operation of the other LDO. If both LDOs source more than 50mA and an overheat condition occurs, both LDO outputs are disabled. Once the die temperature falls back below about +110°C and disabled LDOs are re-enabled, the soft-start automatically takes place. The ISL78302 provides short-circuit protection by limiting the output current to about 475mA. If short circuited, an output current of 475mA causes die heating. If the short circuit lasts long enough, the overheat detection circuit turns off the output. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION 1/28/11 FN7696.0 CHANGE Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL78302 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/sear For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN7696.0 January 28, 2011 ISL78302 Package Outline Drawing L10.3x3C 10 LEAD DUAL FLAT PACKAGE (DFN) Rev 2, 09/09 3.00 6 PIN #1 INDEX AREA A B 10 6 PIN 1 INDEX AREA 1 2.38 3.00 0.50 2 10 x 0.25 6 (4X) 0.10 C B 1.64 TOP VIEW 10x 0.40 BOTTOM VIEW 5 (4X) PACKAGE OUTLINE 0.10 M C B SEE DETAIL "X" (10 x 0.60) (10x 0.25) 0.90 MAX 0.10 C BASE PLANE 2.38 0.20 C SEATING PLANE 0.08 C SIDE VIEW (8x 0.50) 1.64 TYPICAL RECOMMENDED LAND PATTERN C 0.20 REF 5 0.05 DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 7. COMPLAINT TO JEDEC MO-229-WEED-3 except for E-PAD dimensions. 11 FN7696.0 January 28, 2011