Freescale Semiconductor Advance Information Document Number: MM912_S812 Rev. 2.0, 2/2015 S12XS MCU and Multifunctional Ignition and Injector Driver System In Package (SiP) 912_S812 The MM912_S812 is an engine control SMARTMOS IC combining an MCU (S12XS) and analog control die (MC33812) intended for motorcycle and other single cylinder small engine control applications.The MCU S12XS has 8.0 KB or 12 KB RAM, and flash memory size of 128 KB or 256 KB. The S12XS family retains many of the features of the S12XE family including error correction code (ECC) on flash memory, a separate data-flash module for code or data storage, a frequency modulated locked loop (IPLL) that improves the EMC performance and a fast ATD converter. Features: • Designed to operate over the range of ~4.7 V ≤ VPWR ≤ 36 V • Relay/injector/fuel pump driver – current limit – 4.0 A, typical • Lamp driver – current limit – 1.5 A, typical • All external outputs protected against short to battery and overcurrent • VCC voltage pre-regulator provides +5.0 V power for the MCU • MCU watchdog timer circuit with parallel refresh/time setting line • ISO-9141 K-Line transceiver for communicating diagnostic messages 912_S812 5.0 V VDD VCCSENS VCCREF VBAT VPWR LAMPIN PB3 RIN PP1 RESETB RESETB WDRFSH I/O INJIN I/O INJFLT I/O IGNIN I/O IGNFLT I/O RELFLT I/O MRX RXD MTX TXD EXTAL XTAL LAMPOUT ROUT INJOUT IGNFB IGNSUP IGNOUTH IGNOUTL ISO9141 PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 PAD09 MOSI SCK SSB MISO IRQB PM1/TXCAN PM0/RXCAN TEST1 TM_EN, TEST2 WD_INH PGND VSS DGND SMALL ENGINE CONTROL SIP AF Suffix (Pb Free) 98ASA00371D 100 Pin LQFP-EP VBAT VBAT Relay or other load Injector VPWR ISO9141 Notes 1. Surge Voltage protection recommended on VPWR 2. Not all connections on MCU shown Figure 1. 912_S812 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2013-2015. All rights reserved. VBAT VBAT 1 Orderable Parts This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers. Table 1. Orderable Part Variations Part Number (3) MM912JS812AMAF MCU Temperature (TA) S12XS MM912KS812AMAF Flash Memory RAM 128 k 8.0 k 256 k 12 k -40 to 125 °C Package 100 pin LQFP-EP Notes 3. To Order parts in Tape & Reel, add the R2 suffix to the part number. Table 2. Calibration Tools Part Number Package MC9S12XEP100 (MCU Only) PV912NE812AMAF S12XEP Multiple S12XEP + MC33812 100 pin LQFP-EP Notes: 1)Surge Voltage protection recommended on VPWR 2) Not all connections on MCU shown VBAT +5 V 33812 MIL VBAT VPWR LAMPOUT PNP S12XS VDDF VDD VSS1 *PB3 PAD00 *PT1 PAD01 PAD02 RESET PAD03 PAD04 *PT4 PAD05 *PP2 PAD06 PAD07 *PE6 PAD09 *PP0 MOSI *PA1 SCK *PA5 SS RXD MISO TXD IRQ VDD TXCAN VSS RXCAN VDDPLL EXTAL VSSPLL XTAL VSS +5 V Contact sales for availability and quantity VCCREF VCCSENS LAMPIN RIN RESET WDRFSH INJIN INJFLT IGNIN IGNFLT RELFLT MRX MTX TM_EN, TEST2 WD_INH PGND1,2,1A,2A DGND VBAT RELAY OR OTHER LOAD ROUT INJECTOR INJOUT VBAT IGNSUP IGNFB VBAT VPWR IGNOUTH IGNOUTL ISO9141 ISO9141 EP * I/O pins indicated are examples only and not necessarily recommendations Figure 2. 912_S812 Detailed Application Diagram 912_S812 2 Analog Integrated Circuit Device Data Freescale Semiconductor 2 Part Identification This section provides an explanation of the part numbers and their alpha numeric breakdown. 2.1 Description Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to determine the specific part you have received. 2.2 Format and Examples Part numbers for a given device have the following format, followed by a device example: Table 3 - Part Numbering - Analog EMBEDDED MCU + POWER: MM 9 cc f xxx r v PPP RR - MM912JS812AMAF 2.3 Fields These tables list the possible values for each field in the part number (not all combinations are valid). Table 3. Part Numbering - Analog EMBEDDED MCU + POWER FIELD DESCRIPTION MM Product Category 9 Memory Type cc Micro Core f Memory Size xxx Analog Core/Target r Revision t Temperature Range v Variation PPP Package Designator RR Tape and Reel Indicator VALUES • MM- Qualified Device • SM- Custom Device • PM- Prototype Device • 9 = Flash, OTP • 12 = HC12 • J 128 k • K 256 k • 812 - MC33812 • (default A) • M = -40 °C to 125 °C • (default blank) • AF - 100 lead LQFP with exposed pad • R2 912_S812 Analog Integrated Circuit Device Data Freescale Semiconductor 3 Internal Block Diagram 4K … 8K bytes Data Flash VDDR VDD VDDF VDDPLL Voltage Regulator AN[15:0] TIM 16-bit 8 channel Timer CPU12X Debug Module Single-wire Background 4 address breakpoints Debug Module 2 data breakpoints 512 Byte Trace Buffer BKGD Amplitude Controlled Low Power Pierce or Full drive Pierce Oscillator EXTAL XTAL PLL with Frequency Modulation option RESETB Reset Generation and Test Entry TEST XIRQB IRQB PE2 PE3 PE4 PTE PE[1,0] Clock Monitor COP Watchdog Periodic Interrupt Async. Periodic Int. PWM 8-bit 8 channel Pulse Width Modulator PIT 4ch 24-bit Timer Multilevel Interrupt Module CAN0 msCAN 2.0B SPI0 Synchronous Serial IF ECLK IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RXCAN TXCAN MISO SSB MOSI SCK PTAD 8/10/12-bit 16-channel Analog-Digital Converter PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PK[7:0] PTS PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PTH (Wake-up Int) RXD TXD RXD TXD PTB SCI0 Asynchronous Serial IF SCI1 Asynchronous Serial IF PTK PB0, PB2,6 (PB 7:1 not included) PM0 PM1 PM2 PM3 PM4 PM5 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PTJ (Wake-up Int) PTA XCLKSB/ECLKX2 PA[5,1] (PA 7:6, 4:2, 0 not included) PP4 PP5 PP6 PP7 PM6 PM7 PE5 PE6 PE7 VDDA VSSA VRH VRL VSS1 VSS2 PAD[ 07:00] (AD 15:8 not included) PTT 4K … 12K bytes RAM ATD PTP (Wake-Up Int) 128/256K bytes Flash PTM 3 PJ0 PJ1 PJ2 PJ6 PJ7 Figure 3. MC9S12XS Family Block Diagram 912_S812 4 Analog Integrated Circuit Device Data Freescale Semiconductor VPWR VCC TM_EN LOGIC CONTROL TEST1 TEST2 VCCREF VCCSENS VPWR, VCC V10.0 Analog V2.5 Logic POR, overvoltage, undervoltage IGNSUP Ignition Band Gap Oscillator Bias TEST3 IGNFB Predriver IGNOUTH Short Protection IGNOUTL Relay and Injector Output INJIN PGND1 VCC Gate Control INJFLT IGNIN INJOUT VCC VCC PARALLEL CONTROL VClamp Current Limit Temperature Limit Short Protection Open det. on Injector ~75µA ROUT PGND2 + – RS lLimit IGNFLT RIN RELFLT Lamp Output LAMPIN LAMPOUT Gate Control RESETB WATCHDOG (Open Drain) Current Limit Temperature Limit Short Protection VClamp + – WDRFSH VCC RS lLimit GND MTX ISO9141 CONTROLLER MRX VCC ISO9141 WD_INH DGND Notes 4. Pull-up and pull-down current sources are ~50 µA, unless otherwise noted Figure 4. 33812 Simplified Internal Block Diagram 912_S812 Analog Integrated Circuit Device Data Freescale Semiconductor 5 4 Pin Connections 4.1 Pinout Diagram VSS2 PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 VDDA VRH VRL VSSA PS0/RXD PS1/TXD TEST SCK/PM5 RESETB INJFLT RELFLT IGNFLT INJIN RIN LAMPIN IGNIN Transparent Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 N.C. N.C. MTX MRX WDRFSH TM_EN N.C. N.C. ROUT PGND2 N.C. LAMPOUT N.C. DGND PGND1 PGND1 INJOUT N.C. N.C. N.C. WD_INH TEST1 TEST2 TEST3 N.C. EP GND 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD PA5 PA1 XIRQB PE1/IRQB VDDPLL XTAL EXTAL VSSPLL VSS3 VDDR RESETB VDDX2 VSSX2 PE4 PE6 PE7 PB6 PB5 PB4 PB3 PB2 PB0 BKGD PT7 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PT6 PT5 PT4 VSS1 VDDF PT3 PP0 PP1 PP2 PP3 VDDX1 VSSX1 PM0/RXCAN PM1/TXCAN PM2/MISO PM/3SSB PM4/MOSI VPWR VCCREF VCCSENS ISO9141 IGNFB IGNSUP IGNOUTH IGNOUTL Notes 5. EP, PGND1, PGND2, and DGND, must all be connected to the ground plane. 6. Compared to the MC33812 in the 32 pin SOICW package, there are no pins missing. 7. Compared to the S12XS in the 80 pin QFP package, 22 pins are missing in the SiP. These pins are: PB1, PB7, PE5, PJ2, PE2, PE3, PA0, PA2, PA3, PA4, PA6, PA7, PAD08, PAD09, PS2, PS3, PJ7, PJ6, PP7, PP6, PP5, and PP4. Figure 5. 33812_S812 Pin Connections 912_S812 6 Analog Integrated Circuit Device Data Freescale Semiconductor 4.2 Pin definitions Table 4. 912_S812 Pin Definitions Analog or MCU Pin Pin Name Pin Function Formal Name - 1 N.C. Unused ------- Unused pin, leave open - 2 N.C. Unused ------- Unused pin, leave open Analog 3 MTX Input ISO9141 Data Input to MCU Input logic level ISO9141 data, from the MCU, to the ISO9141 IN/OUT pin Connect to MCU SCI TXD output (pin 90) if using ISO9141 circuit Analog 4 MRX Output ISO9141 Data Output to MCU Output logic level ISO9141 data to the MCU from the ISO9141 IN/OUT pin Connect to MCU SCI RXD input (pin 89) if using ISO9141 circuit Analog 5 WDRFSH Input Watchdog Refresh Logic Level input from MCU to refresh the watchdog circuit to prevent RESETB Connect to MCU I/O output (e.g. PT4 pin 48) Analog 6 TM_EN Input Test Mode Enable Used by Freescale test engineering, Connect to Ground - 7 N.C. Unused ------- Unused pin, leave open - 8 N.C. Unused ------- Unused pin, leave open Analog 9 ROUT Output Relay Driver Output Analog 10 PGND2 Ground Power Ground 2 - 11 N.C. Unused ------- Analog 12 LAMPOUT Output Warning Lamp Output - 13 N.C. Unused ------- Analog 14 DGND Ground Supply Ground - 7 N.C. Unused ------- Analog 16 PGND1 Ground Power Ground 1 Analog 17 INJOUT Output Injector Driver Output - 7 N.C. Unused ------- Unused pin, leave open - 19 N.C. Unused ------- Unused pin, leave open - 20 N.C. Unused ------- Unused pin, leave open Analog 21 WD_INH Input Watchdog Inhibit Analog 22 TEST1 Input Test 1 MUST be tied to GND. Connect to Ground Analog 23 TEST2 Input Test 2 MUST be tied to GND. Connect to Ground Analog 24 TEST3 Input Test 3 MUST leave OPEN. Leave open - 25 N.C. Unused ------- Unused pin. Leave open Analog 26 IGNOUTL Output Ignition Output Low Low side output to drive the Gate/Base of the IGBT/Bipolar Darlington The network used on this pin is determined by the user requirements. Analog 27 IGNOUTH Output Ignition Output High High side output to drive the Gate/Base of IGBT/Bipolar Darlington The network used on this pin is determined by the user requirements. Analog 28 IGNSUP Input Ignition Output Supply Tie to +5.0 V for Darlington, tie to the VPWR supply for the IGBT output device Analog 29 IGNFB Input Feedback from Source Voltage feedback from the source of the Ignition driver transistor through a 10:1 voltage divider. Use a 10:1 voltage divider (36 k/4.02 k) Description and Recommendations Low side relay driver output driven by parallel input RIN Use ESD capacitor where the signal goes off the PC Board. Ground for the RELAY driver output Connect to Ground Unused pin, leave open Low side driver output for MIL (warning lamp) driven by parallel input LAMPIN. Use an ESD capacitor where the signal goes off the PC Board Unused pin, leave open Used as ground for all low power signals. Connect to Ground Unused pin, leave open Ground for INJOUT injector driver output. Connect to Ground Low side driver output for the Injector driven by parallel input INJIN. Use an ESD capacitor where the signal goes off the PC Board. Normally tied to GND, If tied high through a pull-up, it inhibits RESETB from occurring when a watchdog timeout occurs. Normally connect to Ground. 912_S812 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Table 4. 912_S812 Pin Definitions Analog or MCU Pin Pin Name Pin Function Formal Name Description and Recommendations Analog 30 ISO9141 Input/ Output ISO9141 K-Line Bidirectional Serial Data Signal The ISO9141 pin is a VPWR level IN/OUT signal connected to a external ECU Tester, using ISO9141 Protocol.The Output is Open drain and the Input is a ratiometric VPWR level threshold comparator. Use an ESD capacitor where the signal goes off the PC Board. Analog 31 VCCSENS Input Voltage Sense from VCC Feedback to the internal VCC regulator from a external pass transistor. Must have the minimum of a 2.2 F capacitor Analog 32 VCCREF Output VCC Reference Base drive Base drive voltage for an external PNP pass transistor Analog 33 VPWR Supply Input Main Voltage Supply Input VPWR is the main voltage supply input for the device. It is connected to a +12 volt battery (It should have reverse battery protection and transient suppression.) It also needs a bypass capacitor to ground (100 nF or 0.1 F) MCU 34 PM4/MOSI I/O PM4/ SPI MOSI Port M, I/O pin 4 is a general purpose input or output pin. It can be configured as the master output (during master mode) or slave input pin (during slave mode). MOSI for the serial peripheral interface (SPI). MCU 35 PM3/SSB I/O PM3/ SPI SSB Port M, I/O pin 3 is a general purpose input or output pin. It can be configured as the slave select output pin SSB of the serial peripheral interface (SPI) (during master mode) and chip select input (CSB) (during slave mode). MCU 36 PM2/MISO I/O PM2/ SPI MISO Port M, I/O pin 2 is a general purpose input or output pin. It can be configured as the master input (during master mode) or slave output pin (during slave mode). MISO for the serial peripheral interface (SPI). MCU 37 PM1/TXCAN I/O PM1/ TXCAN Port M, I/O pin 1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controller (CAN). MCU 38 PM0/RXCAN I/O PM0/ RXCAN Port M, I/O pin 0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the scalable controller area network controller (CAN). MCU 39 VSSX1 Ground VSSX1 External ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded. All VSSX pins are connected together internally. Connect to Ground MCU 40 VDDX1 Supply Input VDDX1 External power for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded. All VDDX pins are connected together internally. Connect to VCC and use a 100 nF bypass capacitor to ground. MCU 41 I/O PP3/KWP3/PWM3 Port P, I/O pin 3 is a general purpose input or output pin. It can be configured as a keypad wake-up input. It can be configured as a pulse width modulator (PWM) output channel 3. MCU 42 PP2 PT0(8) I/O PP2/KWP2/PWM2 PT0(8) Port P, I/O pin 3 is a general purpose input or output pin. It can be configured as a keypad wake-up input. It can be configured as a pulse width modulator (PWM) output channel 2.(8) MCU 43 PP1 PT1(8) I/O PP1/KWP1/PWM1 PT1(8) Port P, I/O pin 3 is a general purpose input or output pin. It can be configured as a keypad wake-up input. It can be configured as a pulse width modulator (PWM) output channel 1.(8) MCU 44 PP0 PT2(8) I/O PP0/KWP0/PWM0 PT2(8) Port P, I/O pin 3 is a general purpose input or output pin. It can be configured as a keypad wake-up input. It can be configured as a pulse width modulator (PWM) output channel 0.(8) MCU 45 PT3 I/O PT3/IOC3 Port T, I/O pin 3 is a general purpose input or output pin. It can be configured as a timer (TIM) channel 3. Signals VDDF/VSS are the secondary outputs of VREG_3V3 that provide the power supply for the NVM logic. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic). In Shutdown mode an external supply driving VDDF/VSS can replace the voltage regulator. PP3 MCU 46 VDDF Supply VDDF 3.3 V supply output MCU 47 VSS1 Ground VSS1 See previous description for VDDF/VSS. Notes 8. S12XEP signals noted for reuse of PC board for the calibration device. 912_S812 8 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. 912_S812 Pin Definitions Analog or MCU Pin Pin Name Pin Function Formal Name Description and Recommendations MCU 48 PT4 I/O PT4/IOC4/PWM4 Port T, I/O pin 4 is a general purpose input or output pin. It can be configured as a timer (TIM) channel 4 or pulse width modulator (PWM) output 4. MCU 49 PT5 I/O PT5/IOC5/PWM5/ API_EXTCLK Port T, I/O pin 5 is a general purpose input or output pin. It can be configured as a timer (TIM) channel 5, pulse width modulator (PWM) output 5, or as the output of the API_EXTCLK. MCU 50 PT6 I/O PT6/IOC6 Port T, I/O pin 6 is a general purpose input or output pin. It can be configured as a timer (TIM) channel 6. MCU 51 PT7 I/O PT7/IOC7 Port T, I/O pin 7 is a general purpose input or output pin. It can be configured as a timer (TIM) channel 7. MCU 52 BKGD BDM BKGD/MODC The BKGD/MODC pin is used as a pseudo open-drain pin for the background debug communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESETB. The BKGD pin has an internal pull-up device. MCU 53 PB0 I/O PB0 Port B, I/O pin 0 is a general purpose input or output pin. MCU 54 PB2 I/O PB2 Port B, I/O pin 2 is a general purpose input or output pin. MCU 55 PB3 I/O PB3 Port B, I/O pin 3 is a general purpose input or output pin. MCU 56 PB4 I/O PB4 Port B, I/O pin 4 is a general purpose input or output pin. MCU 57 PB5 I/O PB5 Port B, I/O pin 5 is a general purpose input or output pin. MCU 58 PB6 I/O PB6 Port B, I/O pin 6 is a general purpose input or output pin. MCU 59 PE7 I/O PE7/ECLKX2 MCU 60 PE6 I/O PE6 MCU 61 PE4 I/O PE4/ECLK Port E, I/O pin 4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference. The ECLK output has a programmable prescaler. MCU 62 VSSX2 Ground VSSX2 External ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded. All VSSX pins are connected together internally.Connect to Ground MCU 63 VDDX2 Supply Input VDDX2 External power for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded. All VDDX pins are connected together internally. Connect to VCC and use a 100 nF bypass capacitor to Ground The RESETB pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The RESETB pin has an internal pullup device. Use external pull-up (10 k and 0.1 F capacitor to Ground) connect to the 33812 RESETB pin 93. Port E, I/O pin 7 is a general purpose input or output pin. An internal pull-up is enabled during reset. It can be configured to output ECLKX2. Port E, I/O pin 6 is a general purpose input or output pin. MCU 64 RESETB Input RESETB External Reset Pin MCU 65 VDDR Supply Input VDDR Power supply input to the internal voltage regulator. Connect to VCC and use bypass capacitor, 100 nF to Ground. MCU 66 VSS3 Ground VSS3 Core Ground Pin The voltage supply of nominally 1.8 V is derived from the internal voltage regulator. The return current path is through the VSS3 pin. No static external loading of these pins is permitted. Connect to Ground MCU 67 VSSPLL Ground VSSPLL PLL Ground Pin Provides operating voltage and ground for the phased-locked loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground are generated by the internal regulator. Connect to Ground MCU 68 EXTAL Clock Input EXTAL Oscillator Pin EXTAL is the external clock pin. On reset all the device clocks are derived from the internal reference clock. Connect to external crystal and 18 pf capacitor to Ground MCU 69 XTAL Clock Output XTAL Oscillator Pin XTAL is the crystal driver pin. On reset all the device clocks are derived from the internal reference clock. XTAL is the oscillator output. Connect to external crystal and 18 pf capacitor to Ground 912_S812 Analog Integrated Circuit Device Data Freescale Semiconductor 9 Table 4. 912_S812 Pin Definitions Analog or MCU Pin Pin Name MCU 70 VDDPLL MCU 71 IRQB Pin Function Formal Name PLL Supply Output of 3.3 V regulator I/O PE1/IRQB Description and Recommendations Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors. (100 nF...220 nF, X7R ceramic). In Shutdown mode, an external supply driving VDDPLL/VSSPLL can replace the voltage regulator. Port E, I/O pin 1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake-up the MCU from stop or wait mode. Port E, I/O pin 0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake-up the MCU from stop or wait mode. The XIRQ interrupt is level sensitive and active low. As XIRQ is level sensitive while this pin is low, the MCU will not enter STOP mode. Connect to a 10K pull-up resistor to VCC. MCU 72 XIRQB I/O PE0/XIRQB MCU 73 PA1 I/O PA1 Port A, I/O pin 1 is a general purpose input or output pin. MCU 74 PA5 I/O PA5 Port A, I/O pin 5 is a general purpose input or output pin. Signals VDD/VSS2 are the primary outputs of VREG_3V3 that provide the power supply for the core logic.These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic).In Shutdown mode, an external supply driving VDD/VSS2 can replace the voltage regulator. MCU 75 VDD Supply Output of 3.3 V regulator MCU 76 VSS2 Ground Ground of 3.3 V regulator See previous description on VDD. MCU 77 PAD00 A/D Input PAD00 PAD00 is the general purpose input or output pin and analog input AN0 of the analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD protection capacitor. Use of low pass filter as necessary. MCU 78 PAD01 A/D Input PAD01 PAD01 is the general purpose input or output pin and analog input AN1 of the analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD protection capacitor. Use of low pass filter as necessary. MCU 79 PAD02 PA/D Input PAD02 PAD02 is the general purpose input or output pin and analog input AN2 of the analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD protection capacitor. Use of low pass filter as necessary. MCU 80 PAD03 A/D Input PAD03 PAD03 is the general purpose input or output pin and analog input AN3 of the analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD protection capacitor. Use of low pass filter as necessary. MCU 81 PAD04 A/D Input PAD04 PAD04 is the general purpose input or output pin and analog input AN4 of the analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD protection capacitor. Use of low pass filter as necessary. MCU 82 PAD05 A/D Input PAD05 PAD05 is the general purpose input or output pin and analog input AN5 of the analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD protection capacitor. Use of low pass filter as necessary. MCU 83 PAD06 A/D Input PAD06 PAD06 is the general purpose input or output pin and analog input AN6 of the analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD protection capacitor. Use of low pass filter as necessary. MCU 84 PAD07 A/D Input PAD07 PAD07 is the general purpose input or output pin and analog input AN7 of the analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD protection capacitor. Use of low pass filter as necessary. MCU 85 VDDA Supply Input VDDA This is the power supply input pin for the analog-to-digital converter and the voltage regulator. Connect to VCC and use a bypass capacitor, 100 nF to Ground. MCU 86 VRH Supply Input VRH VRH and VRL are the reference voltage input pins for the analog-to-digital converter.Connect to VCC and use a bypass capacitor, 100 nF to Ground. MCU 87 VRL Supply Input VRL VRH and VRL are the reference voltage input pins for the analog-to-digital converter. Connect to Ground. 912_S812 10 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. 912_S812 Pin Definitions Analog or MCU Pin Pin Name Pin Function Formal Name Description and Recommendations MCU 88 VSSA Ground VSSA This is the ground input pin for the analog-to-digital converter and the voltage regulator. Connect to Ground. MCU 89 PS0/RXD I/O PS0/ SCI RXD Port S, I/O pin 0 is a general purpose input or output pin. It can be configured as the receive pin RXD of serial communication interface (SCI). If used for ISO9141 connect to pin 4, MRX. MCU 90 PS1/TXD I/O PS1/ SCI TXD Port S, I/O pin 1 is a general purpose input or output pin. It can be configured as the receive pin TXD of serial communication interface (SCI). If used for ISO9141 connect to pin 3, MTX. MCU 91 TEST Input Test MCU 92 PM5/SCK I/O PM5/ SPI SCK Port M, I/O pin 5 is a general purpose input or output pin. It can be configured as the serial clock input pin for the serial peripheral interface (SPI) when the SPI is in slave mode and as a serial clock output when the SPI is in master mode. Analog 93 RESETB Output RESETB Output to MCU Logic Level ResetB signal used to reset the MCU when the watchdog circuit times out, during undervoltage condition on VCC, and for initial power up and power down. Provides RESETB to MCU on pin 64. Analog 94 INJFLT Output Injector Fault Analog 95 RELFLT Output Relay Fault Analog 96 IGNFLT Output Ignition Fault Analog 97 INJIN Input Injector Parallel Input Analog 98 RIN Input Relay Parallel Input Logic Level Parallel input to activate RELAY output, ROUT Analog 99 LAMPIN Input LAMP Parallel Input Logic Level Parallel input to activate the malfunction indicator lamp output, LAMP Analog 100 IGNIN Input Ignition Parallel Input Logic Level Parallel Input from MCU controlling the ignition coil current flow and spark. - EP GND Ground Substrate Ground MUST leave OPEN. leave open Logic Level output to MCU indicating any fault in the injector circuit. Logic Level output to MCU indicating any fault in the relay circuit. Logic Level output to MCU indicating any fault in the ignition circuit. Logic Level Parallel Input from the MCU to control the injector driver output Should be tied to the Ground plane. Connect to Ground. 912_S812 Analog Integrated Circuit Device Data Freescale Semiconductor 11 5 Electrical Characteristics 5.1 Maximum Ratings Table 5. 912_S812 Maximum Ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Rating Value Unit Notes V (9) ELECTRICAL RATINGS VESD1 VESD2 VESD3 VESD4 ESD Voltage • Human Body Model • Machine Model • Charge Device Model (Corner pins) • Charge Device Model ±2000 ±200 ±750 ±500 THERMAL RATINGS TA TJ TC TSTG -40 to 125 -40 to 150 -40 to 125 C Storage Temperature -55 to 150 C 1.7 W (12) Note 11 C (10), (11) Power Dissipation (TA 25C) PD TSOLDER RJA RJL RJC Operating Temperature • Ambient • Junction • Case Peak Package Reflow Temperature During Solder Mounting Thermal Resistance • Junction-to-Ambient • Junction- to-Lead • Junction-to-Flag 75 8.0 1.2 C/W Notes 9. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 10. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 11. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. 12. This parameter is guaranteed by design but is not production tested. 5.2 Analog MC33812 Parametrics The detailed MC33812 specifications can be found in the MC33812 data sheet. See MC33812. 5.3 Microcontroller S12XS Parametrics The detailed S12XS specifications can be found in the MC9S12XS128 reference manual. See MC9S12XS128. 912_S812 12 Analog Integrated Circuit Device Data Freescale Semiconductor 6 Packaging 6.1 Package Mechanical Dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Package Suffix 100-Pin LQFP-EP AF Package Outline Drawing Number 98ASA00371D . 912_S812 Analog Integrated Circuit Device Data Freescale Semiconductor 13 912_S812 14 Analog Integrated Circuit Device Data Freescale Semiconductor 912_S812 Analog Integrated Circuit Device Data Freescale Semiconductor 15 7 Revision History REVISION DATE DESCRIPTION OF CHANGES 1.0 2/2013 • Initial release 2.0 2/2015 • Changed ordering part numbers from PM to MM • Updated document status to Advance Information • Update document form and style 912_S812 16 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no on the information in this document. warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2015 Freescale Semiconductor, Inc. Document Number: MM912_S812 Rev. 2.0 2/2015