AK4618VQ

[AK4618]
AK4618
192kHz 24-bit 6ch/12ch Audio CODEC with Microphone Interface
GENERAL DESCRIPTION
The AK4618 is a single chip audio CODEC that includes 6-channel ADC and 12-channel DAC. The
6-channel ADC supports differential/single-ended analog inputs. The high performance 12-channel DAC
integrates full-range digital volume control and achieves 106dB dynamic range. A car audio system can
be easily designed with an audio DSP and the AK4618. The AK4618 is housed in a space saving 48-pin
LQFP package.
FEATURES
 6ch ADC
- Sampling Frequency: 8KHz~48KHz
- ADC S/N: 98dB, S/ (N+D): 87dB
- I/F format: MSB justified, I2S or TDM
 12ch DAC
- Sampling Frequency: 8KHz~192KHz
- DAC S/N: 106dB, S/ (N+D): 92dB
- I/F format: MSB justified, LSB justified (16bit, 24bit), I2S or TDM
- Channel Independent Digital Attenuator (Linear 256 steps)
 Microphone Interface
- Single-ended/Differential Input Select
- Programmable Gain (+33dB ~ +15dB and 0dB, 3dB step)
- Low Noise Microphone Bias
 Master / Slave mode
 Master clock
- Slave mode: 256fs, 384fs or 512fs (Normal Speed Mode: fs=8kHz  48kHz)
256fs
(Double Speed Mode: fs=64kHz  96kHz)
128fs
(Quad Speed Mode: fs=128kHz  192kHz)
- Master mode: 256fs, 384fs or 512fs (Normal Speed Mode: fs=8kHz  48kHz)
256fs
(Double Speed Mode: fs=64kHz  96kHz)
128fs
(Quad Speed Mode: fs=128kHz  192kHz)
 μP I/F: I2C
 Power supply
- Analog Power Supply: 3.0V ~ 3.6V (typ.3.3V)
- Digital I/O Power Supply: 3.0V ~ 3.6V (typ.3.3V)
 Operating temperature range: -40C ~ 105C
 Package: 48pin LQFP
015000617-E-00
2015/01
-1-
[AK4618]
■ Block Diagram
MICBIAS
MIC Power
Supply
IN1/IN1P
IN1N
IN2/IN2P
IN2N
Audio
I/F
ADC
HPF
ADC
HPF
ADC
HPF
ADC
HPF
SDOUT1
SDOUT2
ADC
HPF
SDOUT3
ADC
HPF
PDN
IN3/IN3P
IN3N
IN4/IN4P
IN4N
IN5/IN5P
IN5N
IN6/IN6P
IN6N
LOUT1
LPF
SCF
SCF
DAC
DATT
ROUT1
LPF
SCF
DAC
DATT
LOUT2
LPF
SCF
DAC
DATT
ROUT2
LOUT3
LPF
LPF
SCF
SCF
DAC
DAC
DATT
DATT
ROUT3
LPF
SCF
DAC
DATT
LOUT4
LPF
SCF
DAC
DATT
ROUT4
LPF
SCF
DAC
DATT
LOUT5
LPF
SCF
SCF
DAC
DATT
ROUT5
LPF
SCF
DAC
DATT
LOUT6
LPF
SCF
DAC
DATT
ROUT6
LPF
SCF
DAC
DATT
SDTO1
SDTO2
SDTO3
MCLK
MCLK
LRCK
BICK
LRCK
BICK
SDIN1
SDTI1
SDIN2
SDTI2
SDIN3
SDTI3
SDIN4
SDTI4
SDIN5
SDTI5
SDIN6
SDTI6
Reg
REGO
uP I/F
(I2C)
SCL
SDA
VCOM
AVDD1 VSS1 AVDD2 VSS2
TVDD VSS3
Figure 1. Block Diagram
015000617-E-00
2015/01
-2-
[AK4618]
■ Ordering Guide
AK4618VQ
AKD4618
40  +105C
48pin LQFP (0.5mm pitch)
Evaluation Board for AK4618
LOUT1
ROUT1
LOUT2
ROUT2
LOUT3
ROUT3
LOUT4
ROUT4
LOUT5
ROUT5
LOUT6
ROUT6
36
35
34
33
32
31
30
29
28
27
26
25
■ Pin Layout
AVDD2
37
24
IN6/IN6P
VSS2
38
23
IN6N
TVDD
39
22
IN5/IN5P
VSS3
40
21
IN5N
REGO
41
20
VCOM
SDTO1
42
19
VSS1
SDTO2
43
18
AVDD1
17
MICBIAS
AK4618VQ
Top View
10
11
12
IN1/IN1P
IN2N
IN2/IN2P
9
IN1N
IN3N
8
13
PDN
48
7
BICK
SCL
SDTI1
IN3/IN3P
6
14
SDTI2
47
5
MCLK
SDTI3
IN4N
4
15
SDTI4
46
3
SCL
SDTI5
IN4/IN4P
2
16
SDTI6/TDMI
45
1
44
LRCK
SDTO3
11
SDA
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Pin Name
IN1/IN1P, IN1N, IN2/IN2P, IN2N, IN3/IN3P, IN3N,
IN4/IN4P, IN4N, IN5/IN5P, IN5N, IN6/IN6P, IN6N
Analog
MICBIAS
LOUT1-6, ROUT1-6
SDTI1-6
Digital
SDTO1-3
015000617-E-00
Setting
Open
Open
Open
Connect to VSS3
Open
2015/01
-3-
[AK4618]
PIN/FUNCTION
No.
1
Pin Name
LRCK
SDTI6
2
TDMI
I/O
I/O
I
I
3
4
5
6
7
SDTI5
SDTI4
SDTI3
SDTI2
SDTI1
I
I
I
I
I
8
PDN
I
9
IN1N
I
IN1
I
IN1P
I
IN2N
I
IN2
I
IN2P
I
IN3N
I
IN3
I
IN3P
I
IN4N
I
IN4
I
IN4P
I
17
18
19
MICBIAS
AVDD1
VSS1
O
-
20
VCOM
O
21
IN5N
I
IN5
I
IN5P
I
IN6N
I
IN6
I
IN6P
I
ROUT6
LOUT6
O
O
10
11
12
13
14
15
16
22
23
24
25
26
Function
Input Channel Clock Pin
(TDM1-0 bits = “00”)
Audio Serial Data Input 6 Pin
(TDM1-0 bits = “01” or “10”)
TDM Data Input Pin
Audio Serial Data Input 5 Pin
Audio Serial Data Input 4 Pin
Audio Serial Data Input 3 Pin
Audio Serial Data Input 2 Pin
Audio Serial Data Input 1 Pin
Power-Down & Reset Pin
When “L”, the AK4618 is powered-down and the control registers are reset to default state.
(MDIE1 bit = “1”)
Differential Analog Negative input 1 pin
(MDIE1 bit = “0”)
Single-ended Analog Input 1 pin
(MDIE1 bit = “1”)
Differential Analog Positive input 1 pin
(MDIE2 bit = “1”)
Differential Analog Negative input 2 pin
(MDIE2 bit = “0”)
Single-ended Analog Input 2 pin
(MDIE2 bit = “1”)
Differential Analog Positive input 2 pin
(MDIE3 bit = “1”)
Differential Analog Negative input 1 pin
(MDIE3 bit = “0”)
Single-ended Analog Input 1 pin
(MDIE3 bit = “1”)
Differential Analog Positive input 1 pin
(MDIE4 bit = “1”)
Differential Analog Negative input 2 pin
(MDIE4 bit = “0”)
Single-ended Analog Input 2 pin
(MDIE4 bit = “1”)
Differential Analog Positive input 2 pin
Microphone bias pin.
Analog Power Supply Pin, 3.0V3.6V
Ground Pin, 0V
Common Voltage Output Pin, AVDD1x1/2
Large external capacitor around 1µF is used to reduce power-supply noise.
(MDIE5 bit = “1”)
Differential Analog Negative input 1 pin
(MDIE5 bit = “0”)
Single-ended Analog Input 1 pin
(MDIE5 bit = “1”)
Differential Analog Positive input 1 pin
(MDIE6 bit = “1”)
Differential Analog Negative input 2 pin
(MDIE6 bit = “0”)
Single-ended Analog Input 2 pin
(MDIE6 bit = “1”)
Differential Analog Positive input 2 pin
Rch Analog Output 6 Pin
Lch Analog Output 6 Pin
015000617-E-00
2015/01
-4-
[AK4618]
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ROUT5
LOUT5
ROUT4
LOUT4
ROUT3
LOUT3
ROUT2
LOUT2
ROUT1
LOUT1
AVDD2
VSS2
TVDD
VSS3
O
O
O
O
O
O
O
O
O
O
-
Rch Analog Output 5 Pin
Lch Analog Output 5 Pin
Rch Analog Output 4 Pin
Lch Analog Output 4 Pin
Rch Analog Output 3 Pin
Lch Analog Output 3 Pin
Rch Analog Output 2 Pin
Lch Analog Output 2 Pin
Rch Analog Output 1 Pin
Lch Analog Output 1 Pin
Analog Power Supply Pin, 3.0V3.6V
Ground Pin, 0V
Digital Power Supply Pin, 3.0V3.6V
Ground Pin, 0V
Regulator Output Pin
41 REGO
O
This pin should be connected to ground with 1.0uF.
42 SDTO1
O Audio Serial Data Output Pin1
43 SDTO2
O Audio Serial Data Output Pin2
44 SDTO3
O Audio Serial Data Output Pin3
45 SDA
I/O Control Data Input Pin in I2C Bus Serial control mode
46 SCL
I
Control Data Clock Pin in I2C Bus serial control mode
47 MCLK
I
External Master Clock Input Pin
48 BICK
I/O Audio Serial Data Clock Pin
Note 1. All digital input pins must not be allowed to float.
015000617-E-00
2015/01
-5-
[AK4618]
ABSOLUTE MAXIMUM RATINGS
(VSS1 ~ 3 = 0V; Note 2)
Parameter
Symbol
Min.
Max.
Power Supplies
Analog1
AVDD1
-0.3
6.0
Analog2
AVDD2
-0.3
6.0
Digital1
TVDD
-0.3
6.0
Input Current (any pins except for supplies)
IIN
10
Analog Input Voltage
VINA
-0.3
AVDD1+0.3
Digital Input Voltage (MCLK, LRCK, BICK,
SDTI1-6/TDMI, SCL, SDA, PDN pins)
VIND
-0.3
TVDD+0.3
Ambient Temperature (power applied)(Note 3)
Ta
-40
105
Storage Temperature
Tstg
-65
150
Note 2. All voltages with respect to ground. VSS1 ~ 3 must be connected to the same analog ground plane.
Note 3. In case that PCB wiring density is 100%.
Unit
V
V
V
mA
V
V
C
C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1 ~ 3 = 0V; Note 2)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supplies Analog
AVDD1, AVDD2
3.0
3.3
3.6
V
(Note 4)
Digital
TVDD
3.0
3.3
3.6
V
Difference
AVDD1, AVDD2 – TVDD
-0.1
0
+0.1
V
Note 4. The power up sequence between AVDD1, AVDD2 and TVDD is not critical. Each power supplies should be
powered up during the PDN pin = “L”. The PDN pin should be “H” after all power supplies are powered up. All
power supplies should be powered on, only a part of these power supplies cannot be powered off. (Power off
means power supplies equal to ground or power supplies are floating.) Do not turn off only the AK4618 under the
condition that a surrounding device is powered on and the I2C bus is in use. AVDD1 and AVDD2 must be
connected with the same power supply.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
015000617-E-00
2015/01
-6-
[AK4618]
ANALOG CHARACTERISTICS
(Ta=25ºC; AVDD1, AVDD2=TVDD=3.3V, VSS1 ~ 3 =0V, BICK=64fs; Signal frequency 1kHz; Measurement
frequency = 20Hz~20kHz @fs=48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz; Unless otherwise
specified.)
Parameter
MIC AMP
Input Resistance
Gain
Min.
Max.
40
MGAIN[2:0]bits=0h
MGAIN[2:0]bits=1h
MGAIN[2:0]bits=2h
MGAIN[2:0]bits=3h
MGAIN[2:0]bits=4h
MGAIN[2:0]bits=5h
MGAIN[2:0]bits=6h
MGAIN[2:0]bits=7h
MIC BIAS
Bias Output Voltage
Load current = 0mA
Load current = 6mA
2.40
2.40
DR (-60dBFS with A-weighted)
(A-weighted)
MGAIN[2:0]bits=3h(+21dB)
MGAIN[2:0]bits=0h(0dB)
MGAIN[2:0]bits=3h(+21dB)
MGAIN[2:0]bits=0h(0dB)
MGAIN[2:0]bits=3h(+21dB)
0.4
30
24
77
88
88
Interchannel Isolation
Interchannel Gain Mismatch
Gain Drift
Input Voltage
Single-ended (AIN=0.81x AVDD1)
Differential (AIN=±0.81x AVDD1)
Power Supply Rejection Ratio
(Note 5)
DAC Analog Output Characteristics
Resolution
S/(N+D)
(0dBFS) fs=48kHz
BW=20kHz
82
fs=96kHz
BW=40kHz
fs=192kHz
BW=40kHz
DR
(-60dBFS with A-weighted)
100
S/N
(A-weighted)
100
Interchannel Isolation
Interchannel Gain Mismatch (Note 6)
Gain Drift
Output Voltage
AOUT=0.86x AVDD2
2.54
Load Resistance
(AC Load)
5
Load Capacitance
Power Supply Rejection (Note 5)
Note 5. PSRR is applied to AVDD1, AVDD2 and TVDD with 1kHz, 50mVpp.
Note 6. Channel gain mismatch between all output channels (LOUT1-6, ROUT1-6).
015000617-E-00
87
80
98
85
98
85
110
0
20
2.67
±2.67
60
0.5
24
92
90
90
106
106
100
0
20
2.83
0.7
3.12
30
60
Unit
k
dB
dB
dB
dB
dB
dB
dB
dB
0
15
18
21
24
27
30
33
Load Resistance
Load Capacitance
ADC Analog Input Characteristics(Differential inputs)
Resolution
MGAIN[2:0]bits=0h(0dB)
S/(N+D)
(-1dBFS)
S/N
Typ.
V
V
k
pF
Bits
dB
dB
dB
dB
dB
dB
dB
dB
ppm/C
Vpp
Vpp
dB
Bits
dB
dB
dB
dB
dB
dB
dB
ppm/C
Vpp
k
pF
dB
2015/01
-7-
[AK4618]
Parameter
Min.
Typ.
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
AVDD1+AVDD2
fs=48kHz
55
AVDD1+AVDD2
fs=96kHz, 192kHz
40
TVDD
fs=48kHz
8
TVDD
fs=96kHz
7
TVDD
fs=192kHz
10
Power-down mode
(PDN pin = “L”) (Note 7)
AVDD1+AVDD2+TVDD
10
Note 7. In the power-down mode, all digital input pins including clock pins are held VSS3.
015000617-E-00
Max.
Unit
77
12
mA
mA
mA
mA
mA
200
µA
2015/01
-8-
[AK4618]
FILTER CHARACTERISTICS (fs=48kHz)
(Ta= -40  +105C; AVDD1, AVDD2= TVDD=3.0 3.6V)
Parameter
Symbol
ADC Digital Filter (Decimation LPF): Sharp roll-off mode
(SD_AD bit = “0”)
Passband (Note 8)
±0.16dB
PB
0.28dB
3.0dB
Min.
Typ.
Max.
Unit
0
-
18.8
kHz
20.0
22.8
0
15.5
-
kHz
kHz
kHz
dB
1/fs
1/fs
20.0
22.8
5.5
18.8
2.4
-
kHz
kHz
kHz
1/fs
1/fs
3.7
10.9
24.0
-
Hz
Hz
Hz
Stopband (Note 8)
SB
28.4
Stopband Attenuation
SA
71
Group Delay Distortion 0 ~ 20.0kHz
GD
Group Delay (Note 10)
GD
ADC Digital Filter (Decimation LPF): Short delay Sharp roll-off mode
(SD_AD bit = “1”)
Passband (Note 8)
±0.16dB
PB
0
0.28dB
3.0dB
Stopband (Note 8)
SB
28.4
Stopband Attenuation
SA
72
Group Delay Distortion 0 ~ 20.0kHz
GD
Group Delay (Note 10)
GD
ADC Digital Filter (HPF):
Frequency Response
FR
3.0dB
(Note 8)
0.5dB
0.1dB
015000617-E-00
2015/01
-9-
[AK4618]
FILTER CHARACTERISTICS (fs=48kHz)
(Ta= -40  +105C; AVDD1, AVDD2= TVDD=3.0 3.6V)
Parameter
Symbol
DAC Digital Filter (LPF): Sharp roll-off mode
(DEM=OFF; SD_DA bit=“0” ; SLOW bit=“0”)
±0.06dB
PB
Passband
(Note 8)
6.0dB
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay Distortion 0 ~ 20.0kHz
GD
Group Delay
(Note 10)
GD
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 20.0kHz (Note 11)
FR
DAC Digital Filter (LPF): Slow roll-off mode
(DEM=OFF; SD_DA bit=“0” ; SLOW bit=“1”)
Passband
(Note 9)
±0.06dB
6.0dB
PB
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay Distortion 0 ~ 20.0kHz
GD
Group Delay
(Note 10)
GD
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 20.0kHz (Note 11)
FR
DAC Digital Filter (LPF): Short delay Sharp roll-off mode
(DEM=OFF; SD_DA bit=“1”; SLOW bit=“0”)
±0.06dB
Passband
(Note 8)
PB
6.0dB
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay Distortion 0 ~ 20.0kHz
GD
Group Delay
(Note 10)
GD
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 20.0kHz (Note 11)
FR
DAC Digital Filter (LPF): Short delay Slow roll-off mode
(DEM=OFF; SD_DA bit=“1” ; SLOW bit=“1”)
±0.06dB
Passband
(Note 9)
PB
6.0dB
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay Distortion 0 ~ 20.0kHz
GD
Group Delay
(Note 10)
GD
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 20.0kHz (Note 11)
FR
015000617-E-00
Min.
Typ.
Max.
Unit
0
26.2
-0.06
52
-
24.0
0
19.3
21.8
+0.06
-
kHz
kHz
kHz
dB
dB
1/fs
1/fs
-
-0.1
-
dB
22.5
9.8
-
kHz
kHz
0
40.1
-4.0
50
0
26.2
-0.06
52
-
0
6.8
kHz
dB
dB
1/fs
1/fs
-4.0
dB
+0.06
24.0
6.2
21.8
+0.06
1.7
-
-0.1
0
40.1
-4.0
50
-
22.5
-
-
kHz
kHz
kHz
dB
dB
1/fs
1/fs
dB
5.8
9.8
+0.06
0.5
-
kHz
kHz
kHz
dB
dB
1/fs
1/fs
-4.0
-
dB
2015/01
- 10 -
[AK4618]
FILTER CHARACTERISTICS (fs=96kHz)
(Ta= -40  +105C; AVDD1, AVDD2= TVDD=3.0 3.6V)
Parameter
Symbol
DAC Digital Filter (LPF): Sharp roll-off mode
(DEM=OFF; SD_DA bit=“0” ; SLOW bit=“0”)
±0.06dB
PB
Passband
(Note 8)
6.0dB
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay Distortion 0 ~ 40.0kHz
GD
Group Delay
(Note 10)
GD
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 40.0kHz (Note 11)
FR
DAC Digital Filter (LPF): Slow roll-off mode
(DEM=OFF; SD_DA bit=“0” ; SLOW bit=“1”)
Passband
(Note 9)
±0.06dB
6.0dB
PB
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay Distortion 0 ~ 40.0kHz
GD
Group Delay
(Note 10)
GD
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 40.0kHz (Note 11)
FR
DAC Digital Filter (LPF): Short delay Sharp roll-off mode
(DEM=OFF; SD_DA bit=“1”; SLOW bit=“0”)
±0.06dB
Passband
(Note 8)
PB
6.0dB
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay Distortion 0 ~ 40.0kHz
GD
Group Delay
(Note 10)
GD
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 40.0kHz (Note 11)
FR
DAC Digital Filter (LPF): Short delay Slow roll-off mode
(DEM=OFF; SD_DA bit=“1” ; SLOW bit=“1”)
±0.06dB
Passband
(Note 9)
PB
6.0dB
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay Distortion 0 ~ 40.0kHz
GD
Group Delay
(Note 10)
GD
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 40.0kHz (Note 11)
FR
015000617-E-00
Min.
Typ.
Max.
Unit
0
52.4
-0.06
52
-
48.0
0
19.3
43.6
+0.06
-
kHz
kHz
kHz
dB
dB
1/fs
1/fs
-
-0.3
-
dB
45.0
19.6
-
kHz
kHz
0
80.2
-4.0
50
0
52.4
-0.06
52
-
0
6.8
kHz
dB
dB
1/fs
1/fs
-4.2
dB
+0.06
48.0
6.2
43.6
+0.06
1.7
-
-0.3
0
80.2
-4.0
50
-
45.0
-
-
kHz
kHz
kHz
dB
dB
1/fs
1/fs
dB
5.8
19.6
+0.06
0.5
-
kHz
kHz
kHz
dB
dB
1/fs
1/fs
-4.2
-
dB
2015/01
- 11 -
[AK4618]
FILTER CHARACTERISTICS (fs=192kHz)
(Ta= -40  +105C; AVDD1, AVDD2= TVDD=3.0 3.6V)
Parameter
Symbol
Min.
Typ.
Max.
DAC Digital Filter (LPF): Sharp roll-off mode (DEM=OFF; SD_DA bit=“0” ; SLOW bit=“0”)
±0.06dB
PB
0
87.2
Passband
(Note 8)
96.0
6.0dB
Stopband
SB
104.8
Passband Ripple
PR
-0.06
+0.06
Stopband Attenuation
SA
52
Group Delay Distortion 0 ~ 80.0kHz
0
GD
Group Delay
(Note 10)
GD
19.3
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 80.0kHz (Note 11)
FR
-1.0
DAC Digital Filter (LPF): Slow roll-off mode (DEM=OFF; SD_DA bit=“0” ; SLOW bit=“1”)
Passband
(Note 9)
±0.06dB
6.0dB
0
160.4
-4.0
50
PB
90.0
39.2
-
Unit
kHz
kHz
kHz
dB
dB
1/fs
1/fs
dB
kHz
kHz
Stopband
SB
kHz
Passband Ripple
PR
dB
+0.06
Stopband Attenuation
SA
dB
Group Delay Distortion 0 ~ 80.0kHz
0
1/fs
GD
Group Delay
(Note 10)
GD
6.8
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 80.0kHz (Note 11)
FR
-5.0
dB
DAC Digital Filter (LPF): Short delay Sharp roll-off mode (DEM=OFF; SD_DA bit=“1”; SLOW bit=“0”)
±0.06dB
Passband
(Note 8)
PB
0
87.2
kHz
96.0
kHz
6.0dB
Stopband
SB
104.8
kHz
Passband Ripple
PR
dB
-0.06
+0.06
Stopband Attenuation
SA
52
dB
Group Delay Distortion 0 ~ 80.0kHz
1.7
1/fs
GD
Group Delay
(Note 10)
GD
6.2
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 80.0kHz (Note 11)
FR
-1.0
dB
DAC Digital Filter (LPF): Short delay Slow roll-off mode (DEM=OFF; SD_DA bit=“1” ; SLOW bit=“1”)
±0.06dB
Passband
(Note 9)
PB
0
39.2
kHz
90.0
kHz
6.0dB
Stopband
SB
160.4
kHz
Passband Ripple
PR
dB
-4.0
+0.06
Stopband Attenuation
SA
50
dB
Group Delay Distortion 0 ~ 80.0kHz
0.5
1/fs
GD
Group Delay
(Note 10)
GD
5.8
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 80.0kHz (Note 11)
FR
-5.0
dB
Note 8. The passband and stopband frequencies scale with fs (sampling frequency). For example, ADC: Passband
(0.1dB) = 0.375 x fs, DAC: Passband (0.06dB) = 0.454 x fs (@ fs=48kHz).
Note 9. The passband and stopband frequencies scale with fs (sampling frequency). For example, DAC: Passband
(0.06dB) = 0.204 x fs (@ fs=48kHz).
Note 10. The calculated delay time is resulting from digital filtering. For the ADC, this time is from the input of an analog
signal to the setting of 24bit data for both channels to the ADC output register. For the DAC, this time is from
setting the 24 bit data both channels at the input register to the output of an analog signal.
Note 11. The reference frequency is 1kHz.
015000617-E-00
2015/01
- 12 -
[AK4618]
DC CHARACTERISTICS
(Ta=-40C+105C; AVDD1, AVDD2= TVDD=3.0 3.6V)
Parameter
Symbol
High-Level Input Voltage
VIH
(MCLK, LRCK, BICK, SDTI1-6/TDMI,
SCL, SDA, PDN pins)
Low-Level Input Voltage
VIL
(MCLK, LRCK, BICK, SDTI1-6/TDMI,
SCL, SDA, PDN pins)
High-Level Output Voltage
(LRCK, BICK, SDTO1-3 pins: Iout=-100µA)
VOH
Low-Level Output Voltage
(LRCK, BICK, SDTO1-3 pins: Iout= 100µA)
VOL
(SDA pin:
Iout= 3mA)
VOL
Input Leakage Current
Iin
015000617-E-00
Min.
70% TVDD
Typ.
-
Max.
-
Unit
V
-
-
30% TVDD
V
TVDD-0.5
-
-
V
-
-
0.5
0.4
10
V
V
µA
2015/01
- 13 -
[AK4618]
SWITCHING CHARACTERISTICS
(Ta=-40+105C; AVDD1, AVDD2= TVDD=3.0 3.6V; CL=20pF; unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Master Clock Timing
External Clock
256fsn:
fCLK
2.048
Pulse Width Low
tCLKL
32
Pulse Width High
tCLKH
32
384fsn:
fCLK
3.072
Pulse Width Low
tCLKL
22
Pulse Width High
tCLKH
22
512fsn:
fCLK
4.096
Pulse Width Low
tCLKL
16
Pulse Width High
tCLKH
16
256fsd, 128fsq:
fCLK
16.384
Pulse Width Low
tCLKL
16
Pulse Width High
tCLKH
16
LRCK Timing (Slave mode)
Stereo mode
(TDM1-0 bits = “00”)
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
64
Quad Speed Mode
fsq
128
Duty Cycle
Duty
45
TDM512 mode
(Note 12)
(TDM1-0 bits = “01”)
LRCK frequency
fsn
8
“H” time
tLRH
1/512fs
“L” time
tLRL
1/512fs
TDM256 mode
(Note 13)
(TDM1-0 bits = “10”)
LRCK frequency
fsn
8
fsd
64
“H” time
tLRH
1/256fs
“L” time
tLRL
1/256fs
TDM128 mode
(Note 14)
(TDM1-0 bits = “11”)
LRCK frequency
fsq
128
“H” time
tLRH
1/128fs
“L” time
tLRL
1/128fs
LRCK Timing (Master Mode)
Stereo mode
(TDM1-0 bits = “00”)
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
64
Quad Speed Mode
fsq
128
Duty Cycle
Duty
50
TDM512 mode
(Note 12)
(TDM1-0 bits = “01”)
LRCK frequency
fsn
8
“H” time
(Note 15)
tLRH
1/16fs
TDM256 mode
(Note 13)
(TDM1-0 bits = “10”)
LRCK frequency
fsn
8
fsd
64
“H” time
(Note 15)
tLRH
1/8fs
015000617-E-00
Max.
Unit
12.288
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
18.432
24.576
24.576
48
96
192
55
kHz
kHz
kHz
%
48
kHz
ns
ns
48
96
kHz
kHz
ns
ns
192
kHz
ns
ns
48
96
192
-
kHz
kHz
kHz
%
48
kHz
ns
48
96
kHz
kHz
ns
2015/01
- 14 -
[AK4618]
TDM128 mode
(Note 14)
(TDM1-0 bits = “11”)
LRCK frequency
fsq
128
192
kHz
“H” time
(Note 15)
tLRH
1/4fs
ns
Note 12. Please use for Normal Speed mode. Master clock should be input the 512fs in Master mode.
Note 13. Please use for Normal Speed mode, Double Speed mode. Master clock should be input the 256fs or 512fs in
Master mode.
Note 14. Please use for Quad Speed mode. Master clock should be input the 128fs in Master mode.
Note 15. If the format is I2S, it is “L” time.
Parameter
Audio Interface Timing (Slave mode)
Stereo mode (TDM1-0 bits = “00”)
for Normal Speed mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 16)
BICK “” to LRCK Edge
(Note 16)
LRCK to SDTO(MSB) (Except I2S mode)
BICK “” to SDTO
SDTI Hold Time
SDTI Setup Time
Stereo mode (TDM1-0 bits = “00”)
for Double and Quad Speed mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 16)
BICK “” to LRCK Edge
(Note 16)
SDTI Hold Time
SDTI Setup Time
TDM512 mode (TDM1-0 bits = “01”)
(Note 12)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 16)
BICK “” to LRCK Edge
(Note 16)
SDTO Setup time BICK “”
SDTO Hold time BICK “”
SDTI/TDMI Hold Time
SDTI/TDMI Setup Time
TDM256 mode (TDM1-0 bits = “10”)
(Note 13)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 16)
BICK “” to LRCK Edge
(Note 16)
SDTO Setup time BICK “”
SDTO Hold time BICK “”
SDTI/TDMI Hold Time
SDTI/TDMI Setup Time
Symbol
015000617-E-00
Min.
Typ.
Max.
Unit
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
324
130
130
20
20
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
81
33
33
23
23
10
10
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSS
tBSH
tSDH
tSDS
40
16
16
10
10
6
5
5
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSS
tBSH
tSDH
tSDS
40
16
16
10
10
6
5
5
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
80
80
2015/01
- 15 -
[AK4618]
TDM128 mode (TDM1-0 bits = “11”)
(Note 14)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 16)
BICK “” to LRCK Edge
(Note 16)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
Parameter
Symbol
Audio Interface Timing (Master mode)
Stereo mode (TDM1-0 bits = “00”)
for Normal Speed mode
BICK Frequency
fBCK
BICK Duty
dBCK
BICK “” to LRCK
tMBLR
tBSD
BICK “” to SDTO
tSDH
SDTI Hold Time
tSDS
SDTI Setup Time
Stereo mode (TDM1-0 bits = “00”)
for Double and Quad Speed mode
BICK Frequency
fBCK
BICK Duty
(Note 17)
dBCK
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
TDM512 mode (TDM1-0 bits = “01”)
(Note 12)
BICK Frequency
fBCK
BICK Duty
(Note 17)
dBCK
BICK “” to LRCK
tMBLR
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold time BICK “”
tSDH
SDTI/TDMI Hold Time
tSDS
SDTI/TDMI Setup Time
TDM256 mode (TDM1-0 bits = “10”)
(Note 13)
BICK Frequency
fBCK
BICK Duty
(Note 17)
dBCK
BICK “” to LRCK
tMBLR
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold time BICK “”
tSDH
SDTI/TDMI Hold Time
tSDS
SDTI/TDMI Setup Time
TDM128 mode (TDM1-0 bits = “11”)
(Note 14)
BICK Frequency
fBCK
BICK Duty
(Note 17)
dBCK
tMBLR
BICK “” to LRCK
tSDH
SDTI Hold Time
tSDS
SDTI Setup Time
Note 16. BICK rising edge must not occur at the same time as LRCK edge.
Note 17. The case that duty of MCLK is 50%.
015000617-E-00
40
16
16
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
Min.
Typ.
Max.
Unit
80
80
50
50
64fs
50
-
80
80
-
Hz
%
ns
ns
ns
ns
10
10
64fs
50
-
-
Hz
%
ns
ns
-10
6
5
5
6
512fs
50
10
-
Hz
%
ns
ns
ns
ns
ns
10
6
5
5
6
256fs
50
-
10
--
Hz
%
ns
ns
ns
ns
ns
10
10
10
128fs
50
-
10
-
Hz
%
ns
ns
ns
-
2015/01
- 16 -
[AK4618]
Parameter
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 18)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
Power-down & Reset Timing
PDN Pulse Width
(Note 19)
PDN “” to SDTO valid
(Note 20)
Symbol
Min.
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
tPD
tPDV
150
Typ.
Max.
Unit
400
1.0
0.3
50
400
kHz
s
s
s
s
s
s
s
s
s
s
ns
pF
ns
32768/MCLK
1/fs
+1059/fs
Note 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 19. The AK4618 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L” for more
than 150ns for a certain reset. The AK4618 is not reset by the “L” pulse less than 30ns.
Note 20. These cycles are the numbers of MCLK and LRCK rising from the PDN pin rising.
Note 21. I2C-bus is a trademark of NXP B.V.
015000617-E-00
2015/01
- 17 -
[AK4618]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
LRCK
VIL
tdLRKH
tdLRKL
Duty
= tdLRKH (or tdLRKL) x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 2. Clock Timing (TDM1-0 bits = “00” & Slave mode)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 3. Clock Timing (Except TDM1-0 bits = “00” & Slave mode)
015000617-E-00
2015/01
- 18 -
[AK4618]
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
LRCK
50%TVDD
tdLRKH
tdLRKL
dLRK
= tdLRKH (or tdLRKL) x fs x 100
1/fBCK
50%TVDD
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x fs x 100
Figure 4. Clock Timing (TDM1-0 bits = “00” & Master mode)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
LRCK
50%TVDD
tLRH
1/fBCK
50%TVDD
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x fs x 100
Figure 5. Clock Timing (Except TDM1-0 bits = “00” & Master mode)
015000617-E-00
2015/01
- 19 -
[AK4618]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (TDM1-0 bits = “00” & Slave mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSH
tBSS
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 7. Audio Interface Timing (Except TDM1-0 bits = “00” & Slave mode)
015000617-E-00
2015/01
- 20 -
[AK4618]
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSD
50%TVDD
SDTO
tSDS
tSDH
VIH
SDTI
VIL
Figure 8. Audio Interface Timing (TDM1-0 bits = “00” & Master mode)
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSS
tBSH
50%TVDD
SDTO
tSDS
tSDH
VIH
SDTI
VIL
Figure 9. Audio Interface Timing (Except TDM1-0 bits = “00” & Master mode)
015000617-E-00
2015/01
- 21 -
[AK4618]
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
Figure 10. I2C Bus mode Timing
tPD
VIH
PDN
VIL
tPDV
SDTO
50%TVDD
Figure 11. Power-down & Reset Timing
015000617-E-00
2015/01
- 22 -
[AK4618]
OPERATION OVERVIEW
■ System Clock
The external clocks which are required to operate the AK4618 in slave mode are MCLK, LRCK and BICK. MCLK
should be synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In
Manual Setting Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of
MCLK at each sampling speed is set automatically. (Table 3, Table 4, Table 5). In Auto Setting Mode (ACKS bit= “1”),
as MCLK frequency is detected automatically (Table 6) and the internal master clock attains the appropriate frequency
(Table 7), so it is not necessary to set DFS.
In master mode, only MCLK is required. Master Clock Input Frequency should be set with the CKS1-0 bits, and the
sampling speed should be set by the DFS1-0 bits. The frequencies and the duties of the clocks (LRCK, BICK) are not
stabile immediately after setting CKS1-0 bits and DFS1-0 bits up.
After exiting reset at power-up in slave mode, the AK4618 is in power-down mode until MCLK and LRCK are input.
If the clock is stopped, click noise occurs when restarting the clock. Mute the digital output externally if the click noise
influences system applications.
Note: ADC is automatically powered-down in Doble Speed Mode and Quad Speed Mode.
DFS1
0
0
1
1
DFS0
0
1
0
1
Sampling Speed Mode (fs)
(default)
Normal Speed Mode
8kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
128kHz~192kHz
N/A
(N/A: Not available)
Table 1. Sampling Speed (Manual Setting Mode)
CKS1
CKS0
0
0
1
1
0
1
0
1
Normal Speed
Mode
256fs
384fs
512fs
512fs
Double Speed
Mode
256fs
256fs
256fs
256fs
Quad Speed
Mode
128fs
128fs
128fs
128fs
(default)
Table 2. Master Clock Input Frequency Select (Master Mode)
Note: In Normal Speed Mode, TDM mode (TDM1-0 bits =”01) can be used when CKS1 bit = “1”.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK (MHz)
384fs
12.2880
16.9344
18.4320
512fs
16.3840
22.5792
24.5760
BICK (MHz)
64fs
2.0480
2.8224
3.0720
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
015000617-E-00
2015/01
- 23 -
[AK4618]
LRCK
fs
88.2kHz
96.0kHz
MCLK (MHz)
256fs
22.5792
24.5760
BICK (MHz)
64fs
5.6448
6.1440
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
fs
176.4kHz
192.0kHz
MCLK (MHz)
128fs
22.5792
24.5760
BICK (MHz)
64fs
11.2896
12.2880
Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
512fs
256fs
128fs
Sampling Speed Mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Table 6. Sampling Speed (Auto Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
MCLK (MHz)
256fs
22.5792
24.5760
-
512fs
16.3840
22.5792
24.5760
-
Sampling
Speed Mode
Normal Speed
Mode
Double Speed
Mode
Quad Speed
Mode
Table 7. System Clock Example (Auto Setting Mode)
015000617-E-00
2015/01
- 24 -
[AK4618]
■ De-emphasis Filter
The AK4618 has a digital de-emphasis filter (tc=50/15µs) by an IIR filter. The de-emphasis filter supports only Normal
Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC
can be set individually by registers, DAC1(SDTI1), DAC2(SDTI2), DAC3(SDTI3), DAC4(SDTI4), DAC5(SDTI5),
DAC6(SDTI6).
Mode
Sampling Speed Mode
0
1
2
3
Normal Speed Mode
Normal Speed Mode
Normal Speed Mode
Normal Speed Mode
DEM11
(DEM61-21)
0
0
1
1
DEM10
(DEM60-20)
0
1
0
1
DEM
44.1kHz
OFF
48kHz
32kHz
(default)
Table 8. De-emphasis Control
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 3.7Hz at fs=48kHz
and scales with the sampling rate (fs).
■ Master Mode and Slave Mode
Master Mode and Slave Mode are selected by setting the MS bit.
LRCK and BICK pins are outputs in Master Mode (MS bit= “1”)
LRCK and BICK pins are inputs in Slave Mode (MS bit= “0”)
The BICK and LRCK pins are in Hi-z state before an internal power up and MS bit = "1".
When a problem is occurred by this, pulldown BICK and LRCK pins by external resistance(ex. 100kohm).
PDN
L
H
MS bit
0
1
0
1
LRCK pin
Input
Hi-z
Input
Output
BICK pin
Input
Hi-z
Input
Output
Table 9. LRCK and BICK pins
015000617-E-00
2015/01
- 25 -
[AK4618]
■ Audio Serial Interface Format
(1) Stereo Mode
When TDM1-0 bits = “00”, ten modes can be selected by the DIF2-0 bits as shown in Table 10. In all modes the serial data
is MSB-first, 2’s compliment format. The data SDTO is clocked out on the falling edge of BICK and the SDTI1-6 is
latched on the rising edge of BICK.
Mode3/4/8/9/13/14/18/19/23/24/28/29/33/34/38/39 in SDTI input formats can be used for 16-20bit data by zeroing the
unused LSBs.
Mode
M/S
TDM1
TDM0
DIF2
DIF1
DIF0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
0
0
0
1
0
0
SDTO1-3
SDTI1-6
24bit, Left
justified (*)
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
24bit, I2S
LRCK
I/O
H/L
I
H/L
I
H/L
I
H/L
I
L/H
I
BICK
I/O
32fs
I
64fs
48fs
I
64fs
48fs
I
64fs
48fs
I
64fs
48fs
I
64fs
(default)
24bit, Left 16bit, Right
H/L O
64fs
O
justified
justified
24bit, Left 20bit, Right
6
1
0
0
0
0
1
H/L O
64fs
O
justified
justified
24bit, Left 24bit, Right
7
1
0
0
0
1
0
H/L O
64fs
O
justified
justified
24bit, Left
24bit, Left
8
1
0
0
0
1
1
H/L O
64fs
O
justified
justified
2
2
9
1
0
0
1
0
0
24bit, I S
24bit, I S
L/H O
64fs
O
Table 10. Audio Data Formats (Stereo mode)
(*)When the BICK is less than 48fs, the output data length from SDTO is limited to the clock number of BICK in the half
LRCK period.
5
1
0
0
0
0
0
015000617-E-00
2015/01
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[AK4618]
(2) TDM Mode
The audio serial interface format is set in TDM mode by the TDM1-0 bits = “01”. Five modes can be selected by the
DIF2-0 bits as shown in Table 11. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked
out on the rising edge of BICK and the SDTI1/2/3 are latched on the rising edge of BICK.
TDM512 mode can be set by TDM1-0 bits as show in Table 11. In the TDM512 mode (fs = 48kHz), the serial data of all
ADC (six channels) is output to the SDTO1 pin, SDTO2/3 pin = “L”. And the serial data of all DAC (twelve channels) is
input to the SDTI1 pin. The input data to SDTI2-6 pins are ignored and the SDTI6 pin is used as the TDMI pin in TDM
cascade Mode(Figure 32). BICK should be fixed to 512fs. “H” time and “L” time of LRCK should be 1/512fs at least.
TDM256 mode can be set by TDM1-0 bits as show in Table 12. In the TDM256 mode (fs =48, 96kHz), the serial data of
all ADC (six channels) is output to the SDTO1 pin, SDTO2/3 pin = “L”. And the serial data of DAC (eight channels; L1,
R1, L2, R2, L3, R3, L4, R4) is input to the SDTI1 pin. Other four data (L5, R5, L6, R6) are input to the SDTI2 pin. The
input data to SDTI3-6 pins are ignored and the SDTI6 pin is used as the TDMI pin in TDM cascade Mode(Figure 32).
BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be 1/256fs at least. TDM128 mode can be set by
TDM1-0 bits as show in Table 13.
TDM128 mode can be set by TDM1-0 bits as show in Table 13. In TDM128 mode (fs=192kHz), SDTO1/2/3 pin = “L”.
And the serial data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin and the serial data of DAC (four
channels; L3, R3, L4, R4) is input to the SDTI2 pin, the serial data of DAC (four channels; L5, R5, L6, R6) is input to the
SDTI3 pin. The input data to SDTI4-6 pins are ignored. BICK should be fixed to 128fs. “H” time and “L” time of LRCK
should be 1/128fs at least.
Mode
M/S
TDM1
TDM0
10
0
0
1
11
0
0
1
12
0
0
1
13
0
0
1
14
0
0
1
15
1
0
1
16
1
0
1
17
1
0
1
18
1
0
1
19
1
0
1
DIF2
DIF1
DIF0
SDTO1
SDTI1
24bit, Left
16bit, Right
0
0
0
justified
justified
24bit, Left
20bit, Right
0
0
1
justified
justified
24bit, Left
24bit, Right
0
1
0
justified
justified
24bit, Left
24bit, Left
0
1
1
justified
justified
1
0
0
24bit, I2S
24bit, I2S
24bit, Left
16bit, Right
0
0
0
justified
justified
24bit, Left
20bit, Right
0
0
1
justified
justified
24bit, Left
24bit, Right
0
1
0
justified
justified
24bit, Left
24bit, Left
0
1
1
justified
justified
2
1
0
0
24bit, I S
24bit, I2S
Table 11. Audio Data Formats (TDM512 mode)
015000617-E-00
LRCK
I/O
BICK
I/O

I
512fs
I

I
512fs
I

I
512fs
I

I
512fs
I

I
512fs
I

O
512fs
O

O
512fs
O

O
512fs
O

O
512fs
O

O
512fs
O
2015/01
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[AK4618]
Mode
M/S
TDM1
TDM0
20
0
1
0
21
0
1
0
22
0
1
0
23
0
1
0
24
0
1
0
25
1
1
0
26
1
1
0
27
1
1
0
28
1
1
0
29
1
1
0
Mode
M/S
TDM1
TDM0
DIF2
DIF1
DIF0
SDTO1
SDTI1-2
24bit, Left
16bit, Right
justified
justified
24bit, Left
20bit, Right
0
0
1
justified
justified
24bit, Left
24bit, Right
0
1
0
justified
justified
24bit, Left
24bit, Left
0
1
1
justified
justified
2
1
0
0
24bit, I S
24bit, I2S
24bit, Left
16bit, Right
0
0
0
justified
justified
24bit, Left
20bit, Right
0
0
1
justified
justified
24bit, Left
24bit, Right
0
1
0
justified
justified
24bit, Left
24bit, Left
0
1
1
justified
justified
1
0
0
24bit, I2S
24bit, I2S
Table 12. Audio Data Formats (TDM256 mode)
0
DIF2
0
DIF1
0
DIF0
SDTO1-3
30
0
1
1
0
0
0
L
31
0
1
1
0
0
1
L
32
0
1
1
0
1
0
L
33
0
1
1
0
1
1
L
34
0
1
1
1
0
0
L
35
1
1
1
0
0
0
L
36
1
1
1
0
0
1
L
37
1
1
1
0
1
0
L
38
1
1
1
0
1
1
L
39
1
1
1
1
0
0
L
SDTI1-3
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
LRCK
I/O
BICK
I/O

I
256fs
I

I
256fs
I

I
256fs
I

I
256fs
I

I
256fs
I

O
256fs
O

O
256fs
O

O
256fs
O

O
256fs
O

O
256fs
O
LRCK
I/O
BICK
I/O

I
128fs
I

I
128fs
I

I
128fs
I

I
128fs
I

I
128fs
I

O
128fs
O

O
128fs
O

O
128fs
O

O
128fs
O

O
128fs
O
Table 13. Audio Data Formats (TDM128 mode)
015000617-E-00
2015/01
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[AK4618]
LRCK
0
1
2
16
17
18
24
25
31
0
1
2
16
17
18
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
8
7
Don’t Care
6
0
15 14
8
23 22
7
1
8
7
Don’t Care
0
6
0
15 14
SDTO-23:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 12. Mode 0/5 Timing (Stereo Mode)
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
12 11 10
0
19 18
8
Don’t Care
23 22
7
1
12
11 10
Don’t Care
0
0
19 18
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 13. Mode 1/6 Timing (Stereo Mode)
LRCK
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
16 15 14
Don’t Care
0
23 22
23:MSB, 0:LSB
23 22
8
7
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
8
7
1
0
Rch Data
Figure 14. Mode 2/7 Timing (Stereo Mode)
LRCK
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
2
1
0
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
23
Don’t Care
23
Rch Data
Figure 15. Mode 3/8 Timing (Stereo Mode)
015000617-E-00
2015/01
- 29 -
[AK4618]
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
2
1
0
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
Don’t Care
Rch Data
Figure 16. Mode 4/9 Timing (Stereo Mode)
512BICK
LRCK(Mode15)
LRCK(Mode10)
BICK(512fs)
*
SDTO1(o)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
SDTI1(i)
15 14
0
15 14
0
15 14
R1
L1
15 14
0
0
15 14
R2
L2
0
15 14
0
15 14
R3
L3
15 14
0
15 14
0
R4
L4
0
15 14
0
15 14
R5
L5
15 14
0
0
15
R6
L6
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
TDMI(i)
*
23 22
0
23 22
0
23 22
0
23 22
23 22
0
0
23 22
0
23 22
0
23 22
23 22
0
0
23 22
0
23
Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
(*: Optional)
Figure 17. Mode 10/15 Timing (TDM512 Mode)
512BICK
LRCK(Mode16)
LRCK(Mode11)
BICK(512fs)
*
SDTO1(o)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
23 22
0
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
SDTI1(i)
19 18
0
L1
19 18
0
R1
19 18
0
L2
19 18
0
R2
19 18
0
19 18
0
R3
L3
19 18
0
19 18
0
R4
L4
19 18
0
19 18
0
R5
L5
19 18
L6
0
19 18
0
19
R6
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
TDMI(i)
*
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23
Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
(*: Optional)
Figure 18. Mode 11/16 Timing (TDM512 Mode)
015000617-E-00
2015/01
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[AK4618]
512BICK
LRCK(Mode17)
LRCK(Mode12)
BICK(512fs)
SDTO1(o)
*
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
23 22
0
0
23 22
0
23 22
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
SDTI1(i)
23 22
0
23 22
0
23 22
R1
L1
23 22
0
0
23 22
R2
L2
0
23 22
0
23 22
R3
L3
23 22
0
23 22
0
R4
L4
0
23 22
0
23 22
R5
L5
23 22
0
0
23
R6
L6
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
TDMI(i)
*
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23
Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
(*: Optional)
Figure 19. Mode 12/17 Timing (TDM512 Mode)
512BICK
LRCK(Mode18)
LRCK(Mode13)
BICK(512fs)
*
SDTO1(o)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
23 22
0
0
23 22
0
23 22
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
SDTI1(i)
23 22
0
23 22
0
23 22
R1
L1
0
23 22
0
23 22
R2
L2
0
23 22
0
23 22
R3
L3
0
23 22
0
23 22
R4
L4
0
23 22
0
23 22
R5
L5
0
23 22
0
23 22
R6
L6
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
TDMI(i)
*
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23
Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
(*: Optional)
Figure 20. Mode 13/18 Timing (TDM512 Mode)
512BICK
LRCK(Mode19)
LRCK(Mode14)
BICK(512fs)
SDTO1(o)
*
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
SDTI1(i)
23
0
L1
23
0
R1
23
0
L2
23
0
23
R2
0
L3
23
0
23
R3
0
L4
23
0
R4
23
0
L5
23
0
R5
23
0
L6
23
0
23
R6
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
TDMI(i)
*
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
(*: Optional)
Figure 21. Mode 14/19 Timing (TDM512 Mode)
015000617-E-00
2015/01
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[AK4618]
256 BICK
LRCK (Mode25)
LRCK (Mode20)
BICK(256fs)
*
SDTO1(o)
23
0
TDMI (i) *
0
23
0
23
0
23
0
23
0
23
0
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0
15 14
0
15 14
0
15 14
0
15 14
0
15 14
0
15 14
0
15 14
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
15 14
23
23
Data 1
4
SDTI2(i)
0
32 BICK
15 14
SDTI1(i)
23
0
15 14
0
15 14
0
15 14
R5
L6
R6
32 BICK
32 BICK
32 BICK
32 BICK
23
0
19
0
Data 7
Data 8
32 BICK
32 BICK
15
0
L5
0
23
23
(*: Optional)
Figure 22. Mode 20/25 Timing (TDM256 Mode)
256 BICK
LRCK (Mode26)
LRCK (Mode21)
BICK(256fs)
*
SDTO1 (o)
23
23
0
23
0
23
0
23
0
23
0
23
0
23
0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
19 18
SDTI2(i)
23
32 BICK
19 18
SDTI1(i)
TDMI (i) *
0
0
19 18
0
19 18
0
19 18
L5
R5
L6
R6
32 BICK
32 BICK
32 BICK
32 BICK
0
23
Data 7
Data 8
32 BICK
0
19
0
0
32 BICK
23
19
23
(*: Optional)
Figure 23. Mode 21/26 Timing (TDM256 Mode)
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2015/01
- 32 -
[AK4618]
256 BICK
LRCK (Mode27)
LRCK (Mode22)
BICK(256fs)
SDTO1 (o)
*
23 22
0
23
0
23
0
23
0
23
0
23
0
23
0
23
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
SDTI2(i)
23 22
32 BICK
23 22
SDTI1(i)
TDMI (i) *
0
0
23 22
0
23 22
0
23 22
0
L5
R5
L6
R6
32 BICK
32 BICK
32 BICK
32 BICK
23
0
23
23
23
0
23
Data 7
Data 8
32 BICK
32 BICK
(*: Optional)
Figure 24. Mode 22/27 Timing (TDM256 Mode)
256 BICK
LRCK (Mode28)
LRCK (Mode23)
BICK(256fs)
*
SDTO1 (o)
SDTI1(i)
SDTI2(i)
TDMI (i) *
23
0
0
23
0
23
0
23
0
23
0
23
0
23
0
23
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
23
23
0
23 22
0
23 22
0
23 22
0
L5
R5
L6
R6
32 BICK
32 BICK
32 BICK
32 BICK
0
23
0
Data 7
Data 8
32 BICK
32 BICK
23 22
23 22
23
(*: Optional)
Figure 25. Mode 23/28 Timing (TDM256 Mode)
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[AK4618]
256 BICK
LRCK (Mode29)
LRCK (Mode24)
BICK(256fs)
*
SDTO1 (o)
SDTI1(i)
SDTI2(i)
TDMI (i) *
23
0
23
0
23
0
23
0
23
0
23
23
0
0
23
0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
0
23
0
23
0
23
23
L5
L6
R6
32 BICK
32 BICK
32 BICK
32 BICK
0
23
23
0
R5
23
23
0
Data 7
Data 8
32 BICK
32 BICK
23
(*: Optional)
Figure 26. Mode 24/29 Timing (TDM256 Mode)
128 BICK
LRCK (Mode35)
LRCK (Mode30)
BICK(128fs)
SDTI1(i)
SDTI2(i)
SDTI3(i)
15 14
0
0
15 14
15 14
0
15 14
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
15 14
0
15 14
0
15 14
0
15 14
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
15 14
0
15 14
15 14
0
15 14
L5
R5
L6
R6
32 BICK
32 BICK
32 BICK
32 BICK
0
15
0
15
0
15
Figure 27. Mode 30/35 Timing (TDM128 Mode)
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- 34 -
[AK4618]
128 BICK
LRCK (Mode36)
LRCK (Mode31)
BICK(128fs)
SDTI1(i)
SDTI2(i)
SDTI3(i)
19 18
0
0
19 18
19 18
0
19 18
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
19 18
0
19 18
0
19 18
0
19 18
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
19 18
0
19 18
19 18
0
19 18
L5
R5
L6
R6
32 BICK
32 BICK
32 BICK
32 BICK
0
19
0
19
0
19
0
23
0
23
0
23
Figure 28. Mode 31/36 Timing (TDM128 Mode)
128 BICK
LRCK (Mode37)
LRCK (Mode32)
BICK(128fs)
SDTI1(i)
SDTI2(i)
SDTI3(i)
23 22
0
0
23 22
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
23 22
0
23 22
L5
R5
L6
R6
32 BICK
32 BICK
32 BICK
32 BICK
Figure 29. Mode 32/37 Timing (TDM128 Mode)
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[AK4618]
128 BICK
LRCK (Mode38)
LRCK (Mode33)
BICK(128fs)
SDTI1(i)
SDTI2(i)
SDTI3(i)
23 22
0
0
23 22
23 22
0
L1
R1
L2
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
23 22
0
23 22
R2
32 BICK
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
23 22
0
23 22
L5
R5
L6
R6
32 BICK
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
0
23 22
0
23
0
23
0
23
Figure 30. Mode 33/38 Timing (TDM128 Mode)
128 BICK
LRCK (Mode39)
LRCK (Mode34)
BICK(128fs)
SDTI1(i)
SDTI2(i)
SDTI3(i)
23
0
23
0
0
23
23
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
0
23
0
23
0
23
23
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
23
0
23
0
23
23
L5
R5
L6
R6
32 BICK
32 BICK
32 BICK
32 BICK
Figure 31. Mode 34/39 Timing (TDM128 Mode)
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[AK4618]
■ TDM Cascade Mode
The AK4618 can be connected with other ADCs or CODECs in cascades in TDM mode. In Figure 32, the SDTO pin of
ADC or CODEC is connected with the TDMI pin of the AK4618. TDMI data is added after the 6channel ADC data of
SDTO1.It is possible to output 8channel TDM data from the SDTO1 pin of the AK4618 as shown in Figure 22 ~ Figure
26 in TDM256 mode, and it is possible to output 16channel TDM data as shown Figure 17 ~ Figure 21 in TDM512 mode.
ADC or CODEC
256fs or 512fs
MCLK
48kHz
LRCK
256fs or 512fs
BICK
SDTO
AK4618
MCLK
TDMI
LRCK
BICK
SDTO1
8ch or 16ch TDM
Figure 32. Cascade TDM Connection Diagram
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[AK4618]
■ Digital Attenuator
AK4618 has a channel-independent digital attenuator (256 levels, 0.5dB steps). Attenuation level of each DAC1-6 can be
set by DAATL1/R1 7-0 bits, DAATL2/R2 7-0 bit, DAATL3/R3 7-0 bit, DAATL4/R4 7-0 bit, DAATL5/R5 7-0 bit,
DAATL6/R6 7-0 bit, respectively (Table 14).
DAATL1/R1 7-0bits
DAATL2/R2 7-0 bits
DAATL3/R3 7-0 bits
Attenuation Level
DAATL4/R4 7-0 bits
DAATL5/R5 7-0 bits
DAATL6/R6 7-0 bits
00H
+0dB
(default)
01H
-0.5dB
02H
-1.0dB
:
:
7DH
-62.5dB
7EH
-63.0dB
7FH
-63.5dB
:
:
FEH
-127.0dB
FFH
MUTE (-∞)
Table 14. Attenuation level of DAC Digital Attenuator
Transition time between set values of DAATL1/R1 7-0, DAATL2/R2 7-0, DAATL3/R3 7-0, DAATL4/R4 7-0,
DAATL5/R5 7-0, DAATL6/R6 7-0 bits can be selected by the DAATS1-0 bits (Table 15). Transition between set values
is the soft transition in Mode1/2/3 eliminating switching noise in the transition.
Mode
0
1
2
3
DAATS1
0
0
1
1
DAATS0
0
1
0
1
ATT speed
4080/fs
2040/fs
510/fs
255/fs
(default)
Table 15. Transition Time between Set Values of DAATL1/R1 7-0, DAATL2/R2 7-0, DAATL3/R3 7-0,
DAATL4/R4 7-0, DAATL5/R5 7-0, DAATL6/R6 7-0 bits
The transition between set values is a soft transition of 4080 levels in mode 0. It takes 4080/fs ([email protected]=48kHz) from
00H to FFH. If the PDN pin goes to “L”, DAATL1/R1 7-0, DAATL2/R2 7-0, DAATL3/R3 7-0, DAATL4/R4 7-0,
DAATL5/R5 7-0, DAATL6/R6 7-0 bits are initialized to 00H. These bits are also set to 00H respectively when RSTN bit
= “0”, and fade to their current value when RSTN bit returns to “1”.
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[AK4618]
■ MIC Gain Amplifier
The AK4618 has a gain amplifier which supports both single-ended and differential inputs. When MDIE 6-1bit is set to
“1”, differential inputs are supported by the IN6-1P IN6-1N, pins and the maximum input voltage is dependent on
AVDD1. If the AVDD= 3.3V, the maximum input voltage for single-ended input is 2.67Vpp and ±2.67Vpp for
differential inputs. The typical input impedance is 60k (typ). MGAIN1 2-0, MGAIN2 2-0, MGAIN3 2-0, MGAIN4 2-0,
MGAIN5 2-0, MGAIN6 2-0 bits control the input gain of the microphone amplifier (Table 16). A pop nose may occur if
the input gain is changed during an operation.
Mode
0
1
2
3
4
5
6
7
MGAIN12
MGAIN22
MGAIN32
MGAIN42
MGAIN52
MGAIN62
0
0
0
0
1
1
1
1
MGAIN11
MGAIN10
MGAIN21
MGAIN20
MGAIN31
MGAIN30
MGAIN41
MGAIN40
MGAIN51
MGAIN50
MGAIN61
MGAIN60
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Table 16. MIC Input Gain (typ.)
015000617-E-00
Input Gain
0dB
15dB
18dB
21dB
24dB
27dB
30dB
33dB
(default)
2015/01
- 39 -
[AK4618]
■ MIC Bias
The AK4618 integrates power supply for microphone. When PMMB bit = “1”, the MICBIAS pin supplies power for the
microphone. This output voltage is typically 2.40V and the load resistance is minimum 0.3 k. (Figure 33, Figure 34)
Maximum interchannel isolation of microphone inputs is 70dB. The isolation depends on MICBIAS common impedance.
The microphone impedance and the microphone bias resistance is 2k ohm and MIC-Amp input voltage is ±500mVpp
(500mVpp). At this time, internal MICBIAS common impedance is 600m ohms or less, and external MICBIAS common
impedance should be 200m ohms or less.
PMMB bit
0
1
MICBIAS pin
Hi-Z
Output
Table 17. MICBIAS pin
(default)
AK4618
MICBIAS pin
PMMB bit
2k
MIC-Amp
Microphone
IN6-1 pin
IN6-1 pin
2k
Figure 33. MIC Input Block Circuit (differential input)
AK4618
PMMB bit
MICBIAS pin
MIC-Amp
Microphone
IN6-1 pin
Figure 34. MIC Input Block Circuit (single-ended input)
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[AK4618]
■ Soft Mute Operation
Soft mute operation is performed in the digital domain. When the SMUTEN bit is set “0”, the output signal is attenuated
to - in the cycle set by ATS bits (Table 15) from the current ATT level. When the SMUTEN bit is returned to “0”, the
mute is cancelled and the output attenuation gradually changes to the ATT level in the cycle set by ATS bits. If the soft
mute is cancelled before attenuating to - after starting the operation, attenuation is discontinued and it is returned to ATT
level by the same cycle. Soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTEN bit
ATT Level
(1)
(2)
(4)
Attenuation
-
GD
(3)
GD
AOUT
Notes:
(1) The time for input data attenuation to - (Table 15). For example, this time is 4080LRCK cycles (4080/fs) at
ATT_DATA=00H. ATT transition of the soft-mute is from 00H to FFH
(2) The time for input data recovery to ATT level (Table 15). For example, this time is 4080LRCK cycles (4080/fs) at
ATT-DATA=FFH. ATT transition of soft-mute is from FFH to 00H.
(3) The analog output corresponding to the digital input has group delay, GD.
(4) If the soft mute is cancelled before attenuating to -, the attenuation is discontinued and returned to ATT level by
the same cycle.
Figure 35. Soft Mute
■ System Reset
The AK4618 should be reset once by bringing the PDN pin = “L” upon power-up. The AK4618 is powered up and the
internal timing starts clocking by MCLK or LRCK “” after exiting the power down state of reference voltage (such as
VCOM) by the PDN pin. The AK4618 is in power-down mode until MCLK and LRCK, BICK are input.
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[AK4618]
■ Power-Down
All ADCs and DACs of the AK4618 are placed in power-down mode by bringing the PDN pin “L” which resets both
digital filters at the same time. The PDN pin “L” also resets the control registers to their default values. In power-down
mode, the SDTO goes to “L”, and the analog outputs go to Hi-Z. This reset should always be executed after power-up. For
the ADC, an analog initialization cycle (1056/fs) starts 3~4/fs after exiting power-down mode. The output data, SDTO is
available after 1059~1060 cycles of the LRCK clock. For the DAC, an analog initialization cycle (516/fs) starts 3~4/fs
after exiting power-down mode. The analog outputs go to Hi-Z during the initialization. Figure 36 shows the power-down
and power-up sequences.
AVDD1/AVD
D2/DVDD
(11)
PDN
VCOM
150ns
REGO
3~4/fs
Internal PDN
(9)
(10)
1056/fs
ADC Internal
State
(1)
Init Cycle
Normal Operation
Power-down
Normal Operation
Power-down
516/fs (2)
DAC Internal
State
Init Cycle
GD (3)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
“0”data
(6)
(4)
“0”data
“0”data
GD(3)
DAC Out
(Analog)
(5)
(7)
GD
(7)
(7)
Clock In
Don’t care
Don’t care
MCLK,LRCK,BICK
External
Mute
Mute ON
Mute ON
(8)
Notes:
(1) The analog part of ADC is initialized after exiting internal power-down state.
When start-up the AK4618, ADC input voltage should be operating common voltage.
It is necessary to wait for the charge up time of HPF which consists of analog inputs.
When the external capacitor is 1uF and the input impedance is 60kΩ(typ), τ = 0.06 sec.
(2) The analog part of DAC is initialized after exiting internal power-down state.
(3) Digital output corresponds to analog input and analog output corresponds to digital input have group delay (GD).
(4) ADC output is “0” data at power-down state.
(5) The analog outputs go to Hi-Z in power-down mode.
(6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise
influences system applications.
(7) Click noise occurs at the falling edge of PDN and at 519~520/fs after exiting internal power-down state.
(8) Mute the analog output externally if the click noise (7) influences system applications.
(9) There is a delay, 3~4/fs from internal power up to the start of initial cycle.
(10) The PDN pin must be “L” when power up the AK4618 and set to “H” after all poweres are supplied.
(11) The internal power-down state is released when MCLK counter rise.Do not write to the registers for
32768/MCLK([email protected]=12.288MHz, until internal power down is released after the PDN pin = “H”.
Figure 36. Pin power-down/Pin power-up sequence example
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[AK4618]
All ADCs and all DACs can be powered-down individually through the PMADC bits and PMDAC bits. DAC1-6 can be
power-down individually by PMDA6-1 bits. In this case, the internal register values are not initialized. When PMADC bit
= “0”, SDTO goes to “L”. When PMDAC bit = “0”, the analog outputs go to Hi-Z. As some click noise occurs, the analog
output should be muted externally if the click noise influences system applications. Figure 37 shows the power-down and
power-up sequences.
4~5/fs (9)
3~4/fs (10)
PMADC/PMDAC bit
ADC Internal
State
(1)
Normal Operation
Power-down
Init Cycle
516/fs
DAC Internal
State
Normal Operation
Power-down
Normal Operation
(2)
Init Cycle
Normal Operation
GD (3)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
“0”data
GD
Clock In
GD
(5)
(7)
Don’t care
MCLK,LRCK,BICK
External
Mute
(6)
(3)
(7)
DAC Out
(Analog)
(4)
(8)
Mute ON
Notes:
(1) The analog section of ADC is initialized after exiting power-down state.
(2) The analog section of DAC is initialized after exiting power-down state.
(3) Digital output corresponding to the analog inputs and analog outputs corresponding to the digital inputs have group
delay (GD).
(4) ADC output is “0” data at power-down state.
(5) DAC output is Hi-Z in power-down state.
(6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise
influences system application.
(7) Click noise occurs at 45/fs after PMDAC bit becomes “0”, and occurs at 519520/fs after PMDAC bit becomes
“1”.
(8) Mute the analog output externally if the click noise (7) influences system application.
(9) There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable ADC power-down.
There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable DAC power-down.
(10) There is a delay, 3~4/fs from PMADC and PMDAC bits become “1” to the start of initial cycle.
Figure 37. Bit power-down/Bit power-up sequence example
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[AK4618]
■ Reset Function
When RSTN bit= “0”, the analog and digital part of ADC and DACs are powered-down, but the internal register are not
initialized. The analog outputs go to Hi-Z, the SDTO pin goes to “L”. As some click noise occurs, the analog output
should be muted externally if the click noise influences system application. Figure 38 shows the power-up sequence.
RSTN bit
4~5/fs (8)
3~4/fs (9)
Internal
RSTN bit
(1)
ADC Internal
State
Normal Operation
DAC Internal
State
Normal Operation
Power-down
Normal Operation
Init Cycle
(2)
Digital Block Power-down
Init Cycle
Normal Operation
GD (3)
GD
ADC In
(Analog)
ADC Out
(Digital)
(4)
“0”data
DAC In
(Digital)
(5)
“0”data
(3)
GD
DAC Out
(Analog)
Clock In
MCLK,LRCK,BICK
GD
(7)
(7)
(6)
(7)
Don’t care
Notes:
(1) The analog section of the ADC is initialized after exiting reset state.
The initializing cycle is 1056fs. When start-up the AK4618, ADC input voltage should be operating common
voltage.
(2) The analog section of DAC is initialized after exiting exiting reset state.
(3) Digital output corresponding to the analog inputs, and analog outputs corresponding to the digital inputs have group
delay (GD).
(4) ADC output is “0” data at power-down state.
(5) Click noise occurs when the initializing cycle is finished. Mute the digital output externally if the click noise
influences system application.
(6) The analog outputs go to Hi-Z when RSTN bit becomes “0”.
(7) Click noise occurs at 45/fs after RSTN bit becomes “0”, and it occurs at 34/fs after RSTN bit becomes “1”.
(8) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
(9) There is a delay, 3~4/fs from RSTN bit “1” to the start of initial cycle.
Figure 38. Reset Sequence Example
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[AK4618]
■ DAC Partial Power-Down Function
All of the DACs can be powered-down individually by PMDA6-1 bits. The analog section and the digital section of the
DAC are placed in power-down mode when the PMDA6-1 bits = “0”. The analog output of the powered-down channels,
which are set by PMDA6-1 bits, go to Hi-Z. Some click noise occurs in both set-up and release of power-down. Mute the
analog output externally or set PMDA6-1 bits when PMDAC bit = “0” or RSTN bit = “0”, if click noise aversely affects
system performance. Figure 39 shows the sequence of the power-down and the power-up by PMDA6-1 bits.
PMDA6-1 bit
4~5/fs (4)
Power Down Channel
DAC Digital
Internal State
Normal Operation
2~3/fs (5)
Power-down
2~3/fs (5)
4~5/fs (4)
Power-down
Normal Operation
516/fs (6)
DAC Analog
Internal State
Normal Operation
Power-down
DAC In
(Digital)
Normal Operation
516/fs (6)
Normal Operation Power-down
Init Cycle
Init Cycle
Normal Operation
“0”data
(1)
GD
GD
(3) (2)
DAC Out
(Analog)
(3)
(3)
(2)
(3)
Normal Operation Channel
DAC In
(Digital)
“0”data
GD
GD
DAC Out
(Analog)
Notes:
(1) Analog outputs corresponding to the digital inputs have group delay (GD).
(2) Analog output of the DAC is powered down by PMDA6-1 = “0” and goes to Hi-Z.
(3) Click noise occurs in 45/fs after PMDA6-1 bits are set to “0”, and it occurs in 518519/fs after PMDA6-1 bits are
set to “1”.
(4) The DACs will be powered-down 4~5fs after PMDA6-1 bits = “0”
(5) The initialization stars 2~3fs after PMDA6-1 bits are set to “1”.
(6) The analog parts of DACs are initialized after exiting power down mode.
Figure 39. DAC Partial Power-down Example
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[AK4618]
■ Serial Control Interface
I2C-bus Control Mode
The AK4618 supports the fast-mode I2C-bus (max: 400kHz).
1. WRITE Operations
Figure 40 shows the data transfer sequence of the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 46). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant seven bits of the slave address are fixed as “0010000” (Figure 41). If the slave address
matches that of the AK4618, the AK4618 generates an acknowledge and the operation is executed. The master must
generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
(Figure 47). R/W bit = “1” indicates that the read operation is to be executed. “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4618. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 42). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 43). The AK4618 generates an acknowledge after each byte is received. Data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH
defines STOP condition (Figure 46).
The AK4618 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4618
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 16H prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 48) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 40. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
0
0
R/W
A2
A1
A0
D2
D1
D0
Figure 41. The First Byte
0
0
0
A4
A3
Figure 42. The Second Byte
D7
D6
D5
D4
D3
Figure 43. Byte Structure after the second byte
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[AK4618]
2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4618. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 16H prior to generating stop condition, the address
counter will “roll over” to 00H and the data of 16H will be read out.
The AK4618 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
2-1. CURRENT ADDRESS READ
The AK4618 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4618 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4618
ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 44. CURRENT ADDRESS READ
2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing a slave address
with the R/W bit =“1”, the master must execute a “dummy” write operation first. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit =“1”. The AK4618 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but generates a stop condition instead, the AK4618 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
Slave
S Address
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 45. RANDOM ADDRESS READ
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[AK4618]
SDA
SCL
S
P
start condition
stop condition
Figure 46. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 47. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 48. Bit Transfer on the I2C-Bus
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[AK4618]
■ Register Map
Add
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
Register Name
Power Management 1
Power Management 2
System Clock
Filter setting1
Filter setting2
Audio Interface Format
Soft Mute
DAC1L Volume
DAC1R Volume
DAC2L Volume
DAC2R Volume
DAC3L Volume
DAC3R Volume
DAC4L Volume
DAC4R Volume
DAC5L Volume
DAC5R Volume
DAC6L Volume
DAC6R Volume
Input Control
Microphone Gain
Microphone Gain
Microphone Gain
D7
MS
0
D6
PMMB
0
D5
PMADC
PMDA6
D4
PMDAC
PMDA5
D3
PMADC56
PMDA4
0
D2
PMADC34
PMDA3
0
D1
PMADC12
PMDA2
0
D0
RSTN
PMDA1
ACKS
CKS1
DEM41
SLOW
CKS0
DEM40
SD_DA
DFS1
DEM31
0
DFS0
DEM30
SD_AD
DEM21
DEM61
DEM20
DEM60
DEM11
DEM51
DEM10
DEM50
0
0
0
0
TDM1
DAATS1
TDM0
DAATS0
0
0
DIF2
0
DIF1
0
DIF0
SMUTEN
DAATL17
DAATR17
DAATL27
DAATR27
DAATL37
DAATR37
DAATL47
DAATR47
DAATL57
DAATR67
DAATL67
DAATR67
DAATL16
DAATR16
DAATL26
DAATR26
DAATL36
DAATR36
DAATL46
DAATR56
DAATL56
DAATR66
DAATL66
DAATR66
DAATL15
DAATR15
DAATL25
DAATR25
DAATL35
DAATR35
DAATL45
DAATR45
DAATL55
DAATR55
DAATL65
DAATR65
DAATL14
DAATR14
DAATL24
DAATR24
DAATL34
DAATR34
DAATL44
DAATR44
DAATL54
DAATR54
DAATL64
DAATR64
DAATL13
DAATR13
DAATL23
DAATR23
DAATL33
DAATR33
DAATL43
DAATR43
DAATL53
DAATR53
DAATL63
DAATR63
DAATL12
DAATR12
DAATL22
DAATR22
DAATL32
DAATR32
DAATL42
DAATR42
DAATL52
DAATR52
DAATL62
DAATR62
DAATL11
DAATR11
DAATL21
DAATR21
DAATL31
DAATR31
DAATL41
DAATR41
DAATL51
DAATR51
DAATL61
DAATR61
DAATL10
DAATR10
DAATL20
DAATR20
DAATL30
DAATR30
DAATL40
DAATR40
DAATL50
DAATR50
DAATL60
DAATR60
0
0
0
0
0
0
0
0
DIE6
MGAIN22
MGAIN42
MGAIN62
DIE5
MGAIN21
MGAIN41
MGAIN61
DIE4
MGAIN20
MGAIN40
MGAIN60
DIE3
MGAIN12
MGAIN32
MGAIN52
DIE2
MGAIN11
MGAIN31
MGAIN51
DIE1
MGAIN10
MGAIN30
MGAIN50
Note: For addresses from 14H to 1FH, data must not be written. The bits defined as 0 must contain a “0” value.
When the PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timing is reset, but registers are not initialized to their default values.
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[AK4618]
■ Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
MS
PMMB
PMADC
PMDAC
PMAD56
PMAD34
PMAD12
RSTN
RD
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
RSTN: Internal timing reset
0: Reset.
1: Normal operation (default)
PMAD12/34/56: Power management of ADC1-6 (0: Power-down, 1: Normal operation)
PMAD12: Power management control of ADC1 and ADC2
PMAD34: Power management control of ADC3 and ADC4
PMAD56: Power management control of ADC5 and ADC6
PMDAC: Power management of DAC1-6
0: All DAC’s Power-down. PMDA1-6 bits are invalid.
1: Normal operation. (default) PMDA1-6 bits are valid.
PMADC: Power management of mono-stereo
0: All ADC’s Power-down.
1: Normal operation. (default)
PMMB: Power management of microphone bias
0: Power-down
1: Normal operation (default)
MS : Master Mode Select
0: Slave Mode (default)
1: Master Mode
Addr
01H
Register Name
Power Management 3
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
D4
D3
D2
D1
D0
PMDA6
PMDA5
PMDA4
PMDA3
PMDA2
PMDA1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
D2
0
RD
0
D1
0
RD
0
D0
ACKS
R/W
0
PMDA6-1: Power management of DAC1-6 (0: Power-down, 1: Normal operation)
PMDA1: Power management control of DAC1
PMDA2: Power management control of DAC2
PMDA3: Power management control of DAC3
PMDA4: Power management control of DAC4
PMDA5: Power management control of DAC5
PMDA6: Power management control of DAC6
Addr
02H
Register Name
System Clock
R/W
Default
D7
CKS1
R/W
1
D6
CKS0
R/W
0
D5
DFS1
R/W
0
D4
DFS0
R/W
0
D3
0
RD
0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS are
ignored. When this bit is “0”, DFS0, 1 set the sampling speed mode.
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[AK4618]
DFS1-0: Sampling speed mode (Table 1)
The setting of DFS is ignored at ACKS bit =“1”.
CKS1-0: Master Clock Input Frequency Select (Table 2)
Addr
03H
Register Name
Filter setting1
R/W
Default
D7
DEM41
R/W
0
D6
DEM40
R/W
1
D5
DEM31
R/W
0
D4
DEM30
R/W
1
D3
DEM21
R/W
0
D2
DEM20
R/W
1
D1
DEM11
R/W
0
D0
DEM10
R/W
1
D1
DEM51
R/W
0
D0
DEM50
R/W
1
DEM11-10: De-emphasis response control for DAC1 data on SDTI1 (Table 8)
Initial: “01”, OFF
DEM21-20: De-emphasis response control for DAC2 data on SDTI2 (Table 8)
Initial: “01”, OFF
DEM31-30: De-emphasis response control for DAC3 data on SDTI3 (Table 8)
Initial: “01”, OFF
DEM41-40: De-emphasis response control for DAC4 data on SDTI4 (Table 8)
Initial: “01”, OFF
Addr
04H
Register Name
Filter setting2
R/W
Default
D7
SLOW
R/W
0
D6
SD_DA
R/W
1
D5
0
RD
0
D4
SD_AD
R/W
1
D3
DEM61
R/W
0
D2
DEM60
R/W
1
DEM51-50: De-emphasis response control for DAC5 data on SDTI5 (Table 8)
Initial: “01”, OFF
DEM61-60: De-emphasis response control for DAC6 data on SDTI6 (Table 8)
Initial: “01”, OFF
SD_AD: Digital filter Setting for ADC
0: Sharp roll off filter
1: Short delay Sharp roll off filter (default)
SD_DA: Digital filter Setting for DAC
0: Sharp roll off filter or Slow roll off filter
1: Short delay Sharp roll off filter or Short delay Slow roll off filter (default)
SLOW: Slow Roll-off Filter Enable for DAC
0: Sharp Roll-off Filter (default)
1: Slow Roll-off Filter
SD_DA bit
0
0
1
1
SLOW bit
Mode
0
Sharp roll-off filter
1
Slow roll-off filter
0
Short delay Sharp roll-off filter
1
Short delay Slow roll-off filter
Table 18 Digital Filter setting for DAC
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[AK4618]
Addr
05H
Register Name
Audio Interface Format
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
TDM1
R/W
0
D4
TDM0
R/W
0
D3
0
RD
0
D2
DIF2
R/W
1
D1
DIF1
R/W
0
D0
DIF0
R/W
0
DIF2-0: Audio Data Interface Modes (Table 10, Table 11, Table 12, Table 13)
Initial: “100”, mode 4
TDM1-0: TDM Format Select (Table 10, Table 11, Table 12, Table 13)
Mode
0
1
2
3
Addr
06H
TDM1 TDM0
0
0
0
1
1
0
1
1
Register Name
Soft Mute
R/W
Default
D7
0
RD
0
SDTI
1-6
1
1-2
1-3
D6
0
RD
0
Sampling Speed
Stereo mode (Normal, Double, Quad Speed Mode)
TDM512 mode (Normal Speed Mode)
TDM256 mode (Normal, Double Speed Mode)
TDM128 mode (Quad Speed Mode)
D5
DAATS1
R/W
0
D4
DAATS0
R/W
0
D3
0
RD
0
D2
0
RD
0
D1
0
RD
0
D0
SMUTEN
R/W
1
SMUTEN: Soft Mute Enable
0: Mute
1: Unmute (default)
DAATS1-0: DAC Digital attenuator transition time setting (Table 15)
Initial: “00”, mode 0
Add
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
Register Name
DAC1L Volume
DAC1R Volume
DAC2L Volume
DAC2R Volume
DAC3L Volume
DAC3R Volume
DAC4L Volume
DAC4R Volume
DAC5L Volume
DAC5R Volume
DAC6L Volume
DAC6R Volume
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
DAATL17
DAATR17
DAATL27
DAATR27
DAATL37
DAATR37
DAATL47
DAATR47
DAATL57
DAATR67
DAATL67
DAATR67
DAATL16
DAATR16
DAATL26
DAATR26
DAATL36
DAATR36
DAATL46
DAATR56
DAATL56
DAATR66
DAATL66
DAATR66
DAATL15
DAATR15
DAATL25
DAATR25
DAATL35
DAATR35
DAATL45
DAATR45
DAATL55
DAATR55
DAATL65
DAATR65
DAATL14
DAATR14
DAATL24
DAATR24
DAATL34
DAATR34
DAATL44
DAATR44
DAATL54
DAATR54
DAATL64
DAATR64
DAATL13
DAATR13
DAATL23
DAATR23
DAATL33
DAATR33
DAATL43
DAATR43
DAATL53
DAATR53
DAATL63
DAATR63
DAATL12
DAATR12
DAATL22
DAATR22
DAATL32
DAATR32
DAATL42
DAATR42
DAATL52
DAATR52
DAATL62
DAATR62
DAATL11
DAATR11
DAATL21
DAATR21
DAATL31
DAATR31
DAATL41
DAATR41
DAATL51
DAATR51
DAATL61
DAATR61
DAATL10
DAATR10
DAATL20
DAATR20
DAATL30
DAATR30
DAATL40
DAATR40
DAATL50
DAATR50
DAATL60
DAATR60
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DAATL1/R1 7-0, DAATL2/R2 7-0, DAATL3/R3 7-0, DAATL4/R4 7-0, DAATL5/R5 7-0, DAATL6/R6 7-0:
Attenuation Level (Table 14)
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[AK4618]
Addr
13H
Register Name
Input Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
RD
0
0
RD
0
DIE6
R/W
0
DIE5
R/W
0
DIE4
R/W
0
DIE3
R/W
0
DIE2
R/W
0
DIE1
R/W
0
DIE6-1: Single-ended/Differential Input Select
0: Single-ended input to the IN1-6 pins. Leave the IN1-6N pins open. (default)
1: Differential input (IN1-6P and IN1-6N pins)
Addr
14H
15H
16H
Register Name
Microphone Gain
Microphone Gain
Microphone Gain
R/W
Default
D7
0
0
0
RD
0
D6
0
0
0
RD
0
D5
D4
D3
D2
D1
D0
MGAIN22
MGAIN42
MGAIN62
MGAIN21
MGAIN41
MGAIN61
MGAIN20
MGAIN40
MGAIN60
MGAIN12
MGAIN32
MGAIN52
MGAIN11
MGAIN31
MGAIN51
MGAIN10
MGAIN30
MGAIN50
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MGAIN6-1 2-0: Microphone-Amp Gain Control (Table 16)
MGAIN6-1 2-0: “000” (0dB) (default)
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[AK4618]
SYSTEM DESIGN
Figure 49 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
 Differential Input Mode (DIE6-1 bits = “111111”)
+
3.3V Digital
1u
+
0.1u
0.1u
1u
LOUT6 26
37 AVDD2
ROUT6 25
ROUT5 27
LOUT5 28
LOUT4 30
ROUT4 29
ROUT3 31
LOUT3 32
LOUT2 34
ROUT2 33
1u
ROUT1 35
3.3V Analog
LOUT1 36
*1
*2
IN6/IN6P 24
38 VSS2
IN6N 23
39 TVDD
IN5/IN5P 22
40 VSS3
IN5N 21
VCOM 20
41 REGO
AK4618
42 SDTO1
1u
VSS1 19
43 SDTO2
AVDD1 18
44 SDTO3
MICBIAS 17
45 SDA
IN4/IN4P 16
46 SCL
0.1u
+
1u
3.3V Analog
IN4N 15
SDTI4
SDTI3
SDTI2
SDTI1
PDN
IN1N
4
5
6
7
8
9
12 IN2/IN2P
SDTI5
3
11 IN2N
SDTI6/TDMI
2
48 BICK
10 IN1/IN1P
LRCK
IN3/IN3P 14
1
47 MCLK
IN3N 13
*2
*2
µP
DSP
Digital Ground
Analog Ground
Figure 49. Typical Connection Diagram1
*1: Refer to Figure 52
*2: Refer to Figure 50, Figure 51
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[AK4618]
1. Grounding and Power Supply Decoupling
The AK4618 requires careful attention to power supply and grounding arrangements. AVDD1, AVDD2 and TVDD are
usually supplied from analog supply in system. VSS1 ~ 3 of the AK4618 must be connected to analog ground plane.
System analog ground and digital ground should be wired separately and connected together as close as possible to where
the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4618 as
possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
VCOM is a signal ground of this chip and output the voltage AVDD1x1/2. A ceramic capacitor 1µF attached to the
VCOM pin eliminates the effects of high frequency noise. This capacitor should be as close to the pin as possible. No load
current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in
order to avoid unwanted coupling into the AK4618.
3. Analog Inputs
The AK4618 supports single-ended and differential analog input. The single-ended input signal range scales with the
supply voltage and nominally 0.81xAVDD1 Vpp (typ). The differential input signal range between IN+ and IN scales
with the supply voltage and nominally ±0.81xAVDD1 Vpp (typ). The power supply voltage range of the AK4618 is from
VSS2 to AVDD1. The ADC output data format is 2’s complement. The internal HPF removes the DC offset.
The AK4618 samples the analog inputs at 64fs (@ fs=48kHz). The digital filter removes noise above the stop band except
for multiples of the sampling frequency of analog inputs. The AK4618 includes an anti-aliasing filter (RC filter) to
attenuate a noise around the sampling frequency of analog inputs.
4. Analog Outputs
The single-ended output signal range is nominally 0.86 x AVDD2 Vpp centered around the VCOM voltage. The DAC
input data format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full
scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). The internal analog filters remove
most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband, in single-ended input
mode. There are no internal analog filters for differential output mode, therefore this noise should be removed by the
external analog filters.
The DAC outputs have DC offsets of a few millivolts to VCOM voltage.
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[AK4618]
5. External Analog Inputs Circuit
Analog In
2.67Vpp
INP
1
AK4618
Analog In
2.67Vpp
INN

Figure 50. Input Buffer Circuit Example 1 (AC coupled differential input)
(IN1-6P/IN1-6N pins)
Analog In
2.67Vpp
IN
AK4618

Figure 51. Input Buffer Circuit Example 2 (AC coupled single-ended input)
(IN1-6 pins)
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[AK4618]
6. External Analog Outputs Circuit
AK4618
AOUT
Analog Out
C=1F
R=100k
2.83Vpp (typ)
Figure 52. External Circuit Example (LOUT1-6, ROUT1-6 pins)
Note: The cut-offfrequency (fc) of HPF is determined by following equation.
fc= 1/(2 × π × R × C) [Hz]
Where the C is the external AC coupling capacitor and the R is load resistance.
When C = 1μF and R = 100kΩ, then fs = 1.6Hz.
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[AK4618]
PACKAGE
48-pin LQFP(Unit: mm)
1.70Max
9.0
0.13 0.13
7.0
36
1.40 0.05
24
48
13
7.0
37
1
9.0
25
12
0.09 0.20
0.5
0.22 0.08
0.10 M
0° 10°
S
0.10 S
0.30 ~ 0.75
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy resin, Halogen (Br, Cl) free
Cu
Solder (Pb free) plate
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[AK4618]
MARKING
AK4618VQ
XXXXXXX
1
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK4618VQ
REVISION HISTORY
Date (Y/M/D)
15/01/23
Revision
00
Reason
First Edition
Page
Contents
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[AK4618]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application of
AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM
or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants any
license to any intellectual property rights or any other rights of AKM or any third party with respect
to the information in this document. You are fully responsible for use of such information contained
in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR
ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF
SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including
but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry,
medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic
signaling equipment, equipment used to control combustions or explosions, safety devices, elevators
and escalators, devices related to electric power, and equipment used in finance-related fields. Do not
use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible
for complying with safety standards and for providing adequate designs and safeguards for your
hardware, software and systems which minimize risk and avoid situations in which a malfunction or
failure of the Product could cause loss of human life, bodily injury or damage to property, including
data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and regulations.
The Products and related technology may not be used for or incorporated into any products or
systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation,
the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth
in this document shall immediately void any warranty granted by AKM for the Product and shall not
create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
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