Data Sheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5668X
Rev. 6, 03/2011
MPC5668x
MAPBGA–208
17 mm x 17 mm
MPC5668x Microcontroller
Data Sheet
MPC5668x features:
• 32-bit CPU core complex (e200z650)
– Compliant with Power Architecture embedded category
– 32 KB unified cache with line locking and eight-entry
store buffer16
– Execution speed static to 116 MHz
• 32-bit I/O processor (e200z0)
– Execution speed static to 1/2 CPU core speed (58 MHz)
• 2 MB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 512 KB + 80 KB (592 KB) on-chip ECC SRAM
(MPC5668G)
• 128 KB on-chip ECC SRAM (MPC5668E)
• 16-entry Memory Protection Unit (MPC5668E only)
• Direct memory access controller
– 16-channel on MPC5668G
– 32-channel on MPC5668E
• Fast ethernet controller
– Supports 10-Mbps and 100-Mbps IEEE 802.3 MII,
10-Mbps 7-wire interface
– IEEE 802.3 MAC (compliant with IEEE 802.3 1998
edition)
• Media Local Bus (MLB) interface (MPC5668G only)
– Supports 16 logical channels, max speed 1024 Fs
• Interrupt controller (INTC) supports 316 external interrupt
vectors (22 are reserved)
• System clocks
– Frequency-modulated phase-locked loop (FMPLL)
– 4 – 40 MHz crystal oscillator (XTAL)
– 32 kHz crystal oscillator (XTAL)
– Dedicated 16 MHz and 128 kHz internal RC oscillators
• Analog to Digital Converter (ADC) module
– 10-bit A/D resolution
– 32 external channels
– 36 internal channels (MPC5668G)
– 64 internal channels (MPC5668E)
MAPBGA–256
17 mm x 17 mm
• Cross-Triggering Unit (MPC5668E only)
– Internal conversion triggering for ADC
– Triggerable by internal timers or eMIOS200
• Deserial Serial Peripheral Interface (DSPI)
– Four individual DSPI modules
– Full duplex, synchronous transfers
– Master or slave operation
• Inter-IC communication (I2C) interface
– Four individual I2C modules
– Multi-master operation
• Serial Communication Interface (eSCI) module
– Two-channel DMA interface
– Configurable as LIN bus master
• eMIOS200 timed input/output
– 24 channels, 16-bit timers (MPC5668G)
– 32 channels, 16-bit timers (MPC5668E)
• Controller Area Network (FlexCAN) module
– Compliant with CAN protocol specification, Version
2.0B active
– 64 mailboxes, each configurable as transmit or receive
• Dual-channel FlexRay controller
– Full implementation of FlexRay Protocol Specification
2.1, RevA
– 128 message buffers
• JTAG controller (MPC5668G only)
– Compliant with the IEEE 1149.1-2001
• Nexus Development Interface (NDI)
– Available in 256 MAPBGA package only
– Compliant with IEEE-ISTO 5001-2003
– Nexus class 3 development support on e200z650
– Nexus class 2+ development support on e200z0
• Internal voltage regulator allows operation from single
3.3 V or 5 V supply
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2010, 2011. All rights reserved.
Table of Contents
1
2
3
4
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
MPC5668x Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1 208-ball MAPBGA Pin Assignments . . . . . . . . . . . . . . . .6
3.2 256-ball MAPBGA Pin Assignments . . . . . . . . . . . . . . . .7
3.3 Pin Muxing and Reset States . . . . . . . . . . . . . . . . . . . . .8
3.3.1 Power and Ground Supply Summary . . . . . . . .25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .27
4.2.1 General Notes for Specifications at Maximum
Junction Temperature . . . . . . . . . . . . . . . . . . . .27
4.3 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.4 VRC Electrical Specifications . . . . . . . . . . . . . . . . . . . .30
4.5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30
4.6 Operating Current Specifications
. . . . . . . . . . . . . .32
4.7 I/O Pad Current Specifications . . . . . . . . . . . . . . . . . . .34
4.7.1 I/O Pad VDD33 Current Specifications . . . . . . . .35
4.8
4.9
4.10
4.11
4.12
4.13
4.14
5
6
Low Voltage Characteristics . . . . . . . . . . . . . . . . . . . .
Oscillators Electrical Characteristics . . . . . . . . . . . . . .
FMPLL Electrical Characteristics. . . . . . . . . . . . . . . . .
ADC Electrical Characteristics. . . . . . . . . . . . . . . . . . .
Flash Memory Electrical Characteristics . . . . . . . . . . .
Pad AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.1 Reset and Boot Configuration Pins . . . . . . . . .
4.14.2 External Interrupt (IRQ) and Non-Maskable
Interrupt (NMI) Pins . . . . . . . . . . . . . . . . . . . . .
4.14.3 JTAG (IEEE 1149.1) Interface . . . . . . . . . . . . .
4.14.4 Nexus Debug Interface. . . . . . . . . . . . . . . . . . .
4.14.5 Enhanced Modular I/O Subsystem (eMIOS) . .
4.14.6 Deserial Serial Peripheral Interface (DSPI) . . .
4.14.7 MLB Interface . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.8 Fast Ethernet Interface . . . . . . . . . . . . . . . . . .
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
36
38
39
39
40
43
43
43
44
47
49
50
55
57
61
61
65
Table 1. MPC5668G/MPC5668E Comparison
Feature
Package
RAM with ECC
MPU
DMA
Ethernet (FEC)
MediaLB (MLB-DIM)
FlexRay
ADC (10-bit)
Total Timer I/O (eMIOS200)
Cross Trigger Unit (CTU)
SCI (eSCI)
SPI (DSPI)
CAN (FlexCAN)
I2C
Nexus3 Debug (e200Z6)
Nexus2+ Debug (e200Z0)
MPC5668G
208 MAPBGA
256 MAPBGA
592 KB
No
16-channel
Yes
Yes
Yes (128 Message Buffers)
36 internal channels
Supports 32 external channels
24 channels, 16-bit
No
6
4
6
4
Supported on 256BGA
—
emulation package
MPC5668E
208 MAPBGA
256 MAPBGA
128 KB
16 entry
32-channel
No
No
No
64 internal channels
Supports 32 external channels
32 channels, 16-bit
Yes
12
4
5
4
Supported on 256BGA
—
emulation package
MPC5668x Microcontroller Data Sheet, Rev. 6
2
Freescale Semiconductor
Ordering Information
1
Ordering Information
1.1
Orderable Parts
S PC 5668G F 0A V MG R
Qualification status
Core code
Device number
Fabrication Site
Revision
Temperature range
Package identifier
Tape and reel status
Qualification Status
P = Prototype
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Core Code PC = Power Architecture
Fabrication Site
F = Freescale
Temperature Range
V = –40 °C to 105 °C
M = –40 °C to 125 °C
Package Identifier
MG = 208 MAPBGA Pb-free
MJ = 256 MAPBGA Pb-free
Tape and Reel Status
R = Tape and reel
(blank) = Trays
Note: Not all options are available on all devices. Refer to Table 1.
Table 1 shows the orderable part numbers for the MPC5668x.
Table 1. Orderable Part Numbers
Freescale Part Number1
Speed (MHz)
Package Description
Operating Temperature2
Max3 (fMAX)
Min (TL)
Max (TH)
PPC5668GF1AVMJ4
MPC5668G 256 MAPBGA package
Lead-free (PbFree)
116
–40 °C
105 °C
SPC5668GF1AMMG
MPC5668G 208 MAPBGA package
Lead-free (PbFree)
116
–40 °C
125 °C
SPC5668EF1AVMG
MPC5668G 208 MAPBGA package
Lead-free (PbFree)
116
–40 °C
105 °C
SPC5668EF1AVMGR
MPC5668G 208 MAPBGA package
Lead-free (PbFree)
116
–40 °C
105 °C
SPC5668GF1AMMGR
MPC5668G 208 MAPBGA package
Lead-free (PbFree)
116
–40 °C
125 °C
SPC5668GF1AVMG
MPC5668G 208 MAPBGA package
Lead-free (PbFree)
116
–40 °C
105 °C
SPC5668GF1AVMGR
MPC5668G 208 MAPBGA package
Lead-free (PbFree)
116
–40 °C
105 °C
1
All packaged devices are PPC5668x, rather than MPC5668x or SPC5668x, until product qualifications are complete. The
unpackaged device prefix is PCC, rather than SCC, until product qualification is complete.
Not all configurations are available in the PPC parts.
2
The lowest ambient operating temperature (TA) is referenced by TL; the highest ambient operating temperature is referenced
by TH.
3 Maximum speed is the maximum frequency allowed including frequency modulation (FM).
4
The 256 MAPBGA package for the MPC5668x is not intended for full production qualification, and is supplied for
development use only.
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
3
MPC5668x Block Diagrams
2
MPC5668x Block Diagrams
Figure 1 shows a top-level block diagram of the MPC5668G device.
DEBUG
MPC5668G
JTAG
NDI
Nexus3(Z6)
NDI
Nexus2+(Z0)
MASTERS
e200z650 Core
32 kHz
XTAL
4–40 MHz
XTAL
128 kHz
IRC
FMPLL
16 MHz
IRC
VREG
Controller
RTC/API
SWT
VLE
STM
MMU(32TLB)
INTC
Semaphores
e200z0 Core
FPU/SPE
VLE
32K Cache
4/8 Way
16ChDMA
Mux
PIT
FEC
MLB-DIM
FlexRay
BAM
SIU
SPP Crossbar Switch (XBAR)
AIPS(0) Bridge B
AIPS(1) Bridge A
6 x eSCI
2 x I2C
2 x DSPI
Flash
(ECC)
36 x ADC
2 x DSPI
2 x I2C
ECSM
24 x eMIOS
6 x FlexCAN
2 MB
512 KB
80 KB
SRAM
(ECC)
SRAM
(ECC)
Standby RAM
ECSM
ECSM
LEGEND
ADC
– Analog to Digital Converter
BAM
– Boot Assist Module
DSPI
– Serial Peripherals Interface
ECC
– Error Correction Code
ECSM
– Error Correction Status Module
eMIOS
– Timed Input Output
eDMA
– Enhanced Direct Memory Access controller
eSCI
– Serial Communications Interface
FEC
– Fast Ethernet Controller
FlexCAN – Controller Area Network controller
FlexRay™ – FlexRay Bus Controller
FMPLL
– Frequency Modulated Phase Locked Loop
I2 C
INTC
JTAG
MLB-DIM
NDI
PIT
RTC
SIU
STM
SWT
VREG
– Inter IC Controller
– Interrupt Controller
– Joint Test Action Group interface
– Media Local Bus Device Interface Module
– Nexus Debug Interface
– Periodic Interrupt Timer
– Real Time Clock
– System Integration
– System Timer Module
– Software Watchdog Timer
– Voltage Regulator
Figure 1. MPC5668G Block Diagram
MPC5668x Microcontroller Data Sheet, Rev. 6
4
Freescale Semiconductor
MPC5668x Block Diagrams
Figure 2 shows a top level block diagram for the MPC5668E device.
DEBUG
JTAG
NDI
Nexus3(Z6)
NDI
Nexus2+(Z0)
MPC5668E
MASTERS
e200z650 Core
32 kHz
XTAL
4–40 MHz
XTAL
128 kHz
IRC
FMPLL
16 MHz
IRC
VREG
Controller
RTC/API
SWT
VLE
STM
MMU(32TLB)
e200z0 Core
FPU/SPE
VLE
32K Cache
4/8 Way
INTC
Semaphores
PIT
32ChDMA
BAM
Mux
SIU
SPP Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
AIPS(1) Bridge A
AIPS(0) Bridge B
64 x ADC
5 x FlexCAN
4 x eSCI
128 KB
32 x eMIOS
2 x DSPI
2 x DSPI
SRAM
(ECC)
8 x eSCI
2 x I2C
2 x I2C
2 MB
Flash
(ECC)
ECSM
Standby RAM
ECSM
CTU
LEGEND
ADC
BAM
CTU
DSPI
ECC
ECSM
eDMA
eMIOS200
eSCI
FlexCAN
FMPLL
– Analog to Digital Converter
– Boot Assist Module
– Cross Triggering Unit
– Serial Peripherals Interface controller
– Error Correction Code
– Error Correction Status Module
– Enhanced Direct Memory Access controller
– Timed Input Output
– Serial Communications Interface
– Controller Area Network controller
– Frequency Modulated Phase Locked Loop
I2 C
INTC
JTAG
MPU
NDI
PIT
RTC
SIU
STM
SWT
VREG
– Inter IC Controller
– Interrupt Controller
– Joint Test Action Group interface
– Memory Protection Unit
– Nexus Debug Interface
– Periodic Interrupt Timer
– Real Time Clock
– System Integration
– System Timer Module
– Software Watchdog Timer
– Voltage Regulator
Figure 2. MPC5668E Block Diagram
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
5
Pin Assignments
3
Pin Assignments
3.1
208-ball MAPBGA Pin Assignments
Figure 3 shows the 208-ball MAPBGA pin assignments.
1
2
3
4
5
6
7
8
9
10
11
12
A
VSS
PD0
PG1
PC12
PC9
PC7
PC2
PB13
PB10
PB8
RESET VDDSYN XTAL EXTAL VSSSYN
B
PD2
PD1
PG0
PC11
PC10
PC8
PC3
PB14
PB11
VRC
VRCCTL
PB9
PB2
PB0
C
PD3
PD4
PD14
PC14
PC13
PC5
PC6
PC1
PB15
PB12
PB6
PB4
PB3
D
PD5
PD6
PD15
VDD
PC15
VDDE1
VSS
PC4
PC0
VDD
PB7
PB5
E
PD7
PD8
PE0
PE1
14
15
F
PD9
PD10
PE3
PE2
G
PD11
PD12
PE4
VSS
VSS
VSS
VSS
H
PD13
PF0
PE5
VDD
VSS
VSS
J
PF1
PF2
TDI
PE8
VSS
K
PK1
PK2
VSS
L
PK0
PE7
TMS
VDDE2
M
PF4
PE6
TDO
PE9
N
PF6
PF3
PE10
PE11
VDD
PE15
PE14
PH9
PH11
VDDE4
PH15
P
PF8
PF5
TCK
PE12
PE13
PK10
PH8
PH10
PH12
PH13
R
PF10
PF7
PF11
PK4
PK6
PK8
PJ0
PJ2
PJ4
T
VSS
PF9
PK3
PK5
PK7
PK9
PJ1
PJ3
1
2
3
4
5
6
7
8
16
VSS
A
VDDA
VRH
B
PB1
VSSA
VRL
C
PA10
PA12
PA0
PA14
D
PA11
PA9
PA1
PA15
E
PA13
PA8
PA3
PA2
F
VSS
VDD
PA7
PA5
PA4
G
VSS
VSS
VRCSEL
PG2
PG6
PA6
H
VSS
VSS
VSS
VDDE3
PG3
PG7
PG11
J
VSS
VSS
VSS
VDD
PG4
PG8
PG12
K
VDD33
PG5
PG9
PG13
L
TEST
PF13
PG10
PG14
M
PJ10
VSS
PF12
PH3
PG15
N
PH14
PJ11
PF15
PF14
PH4
PH1
P
PJ6
PJ9
PJ12
PJ14
PH5
PH6
PH2
R
PJ5
PJ7
PJ8
PJ13
PJ15
PH0
PH7
VSS
T
9
10
11
12
13
14
15
16
208 MAPBGA Ball Map
(as viewed from top through the package)
JCOMP VDDEMLB
13
Note: This ballmap is preliminary and
should not be used for board
design.
Figure 3. MPC5668x 208-ball MAPBGA (full diagram)
MPC5668x Microcontroller Data Sheet, Rev. 6
6
Freescale Semiconductor
Pin Assignments
3.2
256-ball MAPBGA Pin Assignments
Figure 4 shows the 256-ball MAPBGA pin assignments.
256 MAPBGA Ball Map
(as viewed from top through the package)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
VSS
PD0
PG1
PC12
PC9
PC7
PC2
PB13
PB10
PB8
RESET VDDSYN XTAL
B
PD2
PD1
PG0
PC11
PC10
PC8
PC3
PB14
PB11
VRC
VRCCTL
PB9
PB2
PB0
C
PD3
PD4
PD14
PC14
PC13
PC5
PC6
PC1
PB15
PB12
PB6
PB4
PB3
D
PD5
PD6
PD15
VDD
PC15
VDDE1
VSS
PC4
PC0
VDD
PB7
PB5
E
PD7
PD8
PE0
PE1
MDO0 VDDENEX
VSS
VSS
VSS
VSS
VSS
F
PD9
PD10
PE3
PE2
MDO1
VSS
VSS
VSS
VSS
VSS
G
PD11
PD12
PE4
VSS
MDO2
VSS
VSS
VSS
VSS
H
PD13
PF0
PE5
VDD
MDO3 MDO4
VSS
VSS
J
PF1
PF2
TDI
PE8
MDO6 MDO5
VSS
K
PK1
PK2
L
PK0
PE7
TMS
M
PF4
PE6
TDO
PE9
N
PF6
PF3
PE10
PE11
VDD
P
PF8
PF5
TCK
PE12
PE13
R
PF10
PF7
PF11
PK4
PK6
PK8
PJ0
PJ2
PJ4
PJ6
T
VSS
PF9
PK3
PK5
PK7
PK9
PJ1
PJ3
PJ5
1
2
3
4
5
6
7
8
9
15
EXTAL VSSSYN
16
VSS
A
VDDA
VRH
B
PB1
VSSA
VRL
C
PA10
PA12
PA0
PA14
D
VSS
PA11
PA9
PA1
PA15
E
VSS
VSS
PA13
PA8
PA3
PA2
F
VSS
VSS
VSS
VDD
PA7
PA5
PA4
G
VSS
VSS
VSS
VSS
VRCSEL
PG2
PG6
PA6
H
VSS
VSS
VSS
VSS
VSS
VDDE3
PG3
PG7
PG11
J
JCOMP VDDEMLB MDO7
VSS
VSS
VSS
VSS
VSS VDDENEX
VSS
VDD
PG4
PG8
PG12
K
VDDE2 MDO8
VSS
VDDENEX
VSS
VSS
VSS
VSS
VSS
VDD33
PG5
PG9
PG13
L
EVTI
EVTO
TEST
PF13
PG10
PG14
M
PH15
PJ10
VSS
PF12
PH3
PG15
N
PJ11
PF15
PF14
PH4
PH1
P
PJ9
PJ12
PJ14
PH5
PH6
PH2
R
PJ7
PJ8
PJ13
PJ15
PH0
PH7
VSS
T
10
11
12
13
14
15
16
MDO9 MDO10 MDO11 MSEO1 MSEO0 MCKO
PE15
PE14
PH9
PH11
VDDE4
Note: ThisPH8
ballmap
is preliminary and
PH10 PH12 PH13 PH14
PK10
should not be used for board
design.
Figure 4. MPC5668x 256-ball MAPBGA (full diagram)
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
7
Pin Assignments
3.3
Pin Muxing and Reset States
Table 2 shows the signals properties for each pin on MPC5668x. For all port pins that have an associated SIU_PCRn register
to control pin properties, the supported functions column lists the functions associated with the programming of the
SIU_PCRn[PA] bit in the order: general-purpose input/output (GPIO), function 1, function 2, and function 3 (see Figure 5).
When an alternate function is not implemented for a value of SIU_PCRn[PA], a dash is shown in the Description column and
the respective value in the PA bit field is reserved.
GPIO
Supported
2 (PCR)
Functions
Num3
PA[0]
AN[0]
0
PA4
00
01
10
11
Description
GPIO
Port A GPI
ADC Analog Input
—
—
Function 1
Functions 2 and 3
not implemented
Figure 5. Supported Functions Example
Table 2. MPC5668x Signal Properties
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
3
Num
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
Port A (16)
PA0
PA[0]
AN[0]
0
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
D15
D15
PA1
PA[1]
AN[1]
1
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
E15
E15
PA2
PA[2]
AN[2]
2
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
F16
F16
PA3
PA[3]
AN[3]
3
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
F15
F15
PA4
PA[4]
AN[4]
4
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
G16
G16
PA5
PA[5]
AN[5]
5
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
G15
G15
MPC5668x Microcontroller Data Sheet, Rev. 6
8
Freescale Semiconductor
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PA6
PA[6]
AN[6]
6
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
H16
H16
PA7
PA[7]
AN[7]
7
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
G14
G14
PA8
PA[8]
AN[8]
8
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
F14
F14
PA9
PA[9]
AN[9]
9
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
E14
E14
PA10
PA[10]
AN[10]
10
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
D13
D13
PA11
PA[11]
AN[11]
11
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
E13
E13
PA12
PA[12]
AN[12]
12
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
D14
D14
PA13
PA[13]
AN[13]
13
00
01
10
11
Port A GPI
ADC Analog Input
—
—
I
I
—
—
VDDA
IHA
—
—
F13
F13
PA14
PA[14]
AN[14]
EXTAL32
14
00
01
10
11
Port A GPI
ADC Analog Input
External 32 kHz Crystal In
—
I
I
I
—
VDDA
IHA
—
—
D16
D16
PA15
PA[15]
AN[15]
XTAL32
15
00
01
10
11
Port A GPI
ADC Analog Input
External 32 kHz Crystal Out
—
I
I
O
—
VDDA
IHA
—
—
E16
E16
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
9
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
Port B (16)
PB0
PB[0]
16
AN[16]/ANW
00
01
10
11
Port B GPIO
ADC Analog Input/Mux In
—
—
I/O
I
—
—
VDDE1
SHA
—
—
B14
B14
PB1
PB[1]
AN[17]/ANX
17
00
01
10
11
Port B GPIO
ADC Analog Input/Mux In
—
—
I/O
I
—
—
VDDE1
SHA
—
—
C14
C14
PB2
PB[2]
AN[18]/ANY
18
00
01
10
11
Port B GPIO
ADC Analog Input/Mux In
—
—
I/O
I
—
—
VDDE1
SHA
—
—
B13
B13
PB3
PB[3]
AN[19]/ANZ
19
00
01
10
11
Port B GPIO
ADC Analog Input/Mux In
—
—
I/O
I
—
—
VDDE1
SHA
—
—
C13
C13
PB4
PB[4]
AN[20]
20
00
01
10
11
Port B GPIO
ADC Analog Input
—
—
I/O
I
—
—
VDDE1
SHA
—
—
C12
C12
PB5
PB[5]
AN[21]
21
00
01
10
11
Port B GPIO
ADC Analog Input
—
—
I/O
I
—
—
VDDE1
SHA
—
—
D12
D12
PB6
PB[6]
AN[22]
22
00
01
10
11
Port B GPIO
ADC Analog Input
—
—
I/O
I
—
—
VDDE1
SHA
—
—
C11
C11
PB7
PB[7]
AN[23]
23
00
01
10
11
Port B GPIO
ADC Analog Input
—
—
I/O
I
—
—
VDDE1
SHA
—
—
D11
D11
PB8
PB[8]
AN[24]
PCS_A[2]
24
00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_A Peripheral Chip Select
—
I/O
I
O
—
VDDE1
SHA
—
—
A10
A10
PB9
PB[9]
AN[25]
PCS_A[3]
25
00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_A Peripheral Chip Select
—
I/O
I
O
—
VDDE1
SHA
—
—
B12
B12
MPC5668x Microcontroller Data Sheet, Rev. 6
10
Freescale Semiconductor
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PB10
PB[10]
AN[26]
PCS_B[4]
26
00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_B Peripheral Chip Select
—
I/O
I
O
—
VDDE1
SHA
—
—
A9
A9
PB11
PB[11]
AN[27]
PCS_B[5]
27
00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_B Peripheral Chip Select
—
I/O
I
O
—
VDDE1
SHA
—
—
B9
B9
PB12
PB[12]
AN[28]
PCS_C[1]
28
00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_C Peripheral Chip Select
—
I/O
I
O
—
VDDE1
SHA
—
—
C10
C10
PB13
PB[13]
AN[29]
PCS_C[2]
29
00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_C Peripheral Chip Select
—
I/O
I
O
—
VDDE1
SHA
—
—
A8
A8
PB14
PB[14]
AN[30]
PCS_D[3]
30
00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_D Peripheral Chip Select
—
I/O
I
O
—
VDDE1
SHA
—
—
B8
B8
PB15
PB[15]
AN[31]
PCS_D[4]
31
00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_D Peripheral Chip Select
—
I/O
I
O
—
VDDE1
SHA
—
—
C9
C9
Port C (16)
PC0
PC[0]
AN[32]
32
00
01
10
11
Port C GPIO
ADC Analog Input
—
—
I/O
I
—
—
VDDE1
SHA
—
—
D9
D9
PC1
PC[1]
AN[33]
33
00
01
10
11
Port C GPIO
ADC Analog Input
—
—
I/O
I
—
—
VDDE1
SHA
—
—
C8
C8
PC2
PC[2]
AN[34]
EVTI
34
00
01
10
11
Port C GPIO
ADC Analog Input
Nexus Event In
—
I/O
I
I
—
VDDE1
SHA
—
—
A7
A7
PC3
PC[3]
AN[35]
EVTO
35
00
01
10
11
Port C GPIO
ADC Analog Input
Nexus Event Out
—
I/O
I
O
—
VDDE1
SHA
—
—
B7
B7
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
11
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PC4
PC[4]
AN[36]
36
00
01
10
11
Port C GPIO
ADC Analog Input
—
—
I/O
I
—
—
VDDE1
SHA
—
—
D8
D8
PC5
PC[5]
AN[37]
Z6NMI
37
00
01
10
11
Port C GPIO
ADC Analog Input
Z6 Core Non-Maskable Interrupt
—
I/O
I
I
—
VDDE1
SHA
—
—
C6
C6
PC6
PC[6]
AN[38]
Z0NMI
38
00
01
10
11
Port C GPIO
ADC Analog Input
Z0 Core Non-Maskable Interrupt
—
I/O
I
I
—
VDDE1
SHA
—
—
C7
C7
PC7
PC[7]
AN[39]
FR_DBG3
39
00
01
10
11
Port C GPIO
ADC Analog Input
FlexRay Debug
—
I/O
I
O
—
VDDE1
SHA
—
—
A6
A6
PC8
PC[8]
AN[40]
FR_DBG2
40
00
01
10
11
Port C GPIO
ADC Analog Input
FlexRay Debug
—
I/O
I
O
—
VDDE1
SHA
—
—
B6
B6
PC9
PC[9]
AN[41]
FR_DBG1
41
00
01
10
11
Port C GPIO
ADC Analog Input
FlexRay Debug
—
I/O
I
O
—
VDDE1
SHA
—
—
A5
A5
PC10
PC[10]
AN[42]
FR_DBG0
42
00
01
10
11
Port C GPIO
ADC Analog Input
FlexRay Debug
—
I/O
I
O
—
VDDE1
SHA
—
—
B5
B5
PC11
PC[11]
AN[43]
SCL_C
—
43
00
01
10
11
Port C GPIO
ADC Analog Input
I2C_C Serial Clock
—
I/O
I
I/O
—
VDDE1
SHA
—
—
B4
B4
PC12
PC[12]
AN[44]
SDA_C
—
44
00
01
10
11
Port C GPIO
ADC Analog Input
I2C_C Serial Data
—
I/O
I
I/O
—
VDDE1
SHA
—
—
A4
A4
PC13
PC[13]
AN[45]
—
MA[0]
45
00
01
10
11
Port C GPIO
ADC Analog Input
—
ADC Ext. Mux Address Select
I/O
I
—
O
VDDE1
SHA
—
—
C5
C5
PC14
PC[14]
AN[46]
MA[1]
—
46
00
01
10
11
Port C GPIO
ADC Analog Input
ADC Ext. Mux Address Select
—
I/O
I
—
O
VDDE1
SHA
—
—
C4
C4
MPC5668x Microcontroller Data Sheet, Rev. 6
12
Freescale Semiconductor
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
PC15
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
PC[15]
AN[47]
MA[2]
—
47
00
01
10
11
Status
Description
Port C GPIO
ADC Analog Input
ADC Ext. Mux Address Select
—
I/O
Type
Voltage
Pad
Type5
I/O
I
O
—
VDDE1
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
SHA
—
—
D5
D5
Port D (16)
PD0
PD[0]
CNTX_A
48
00
01
10
11
Port D GPIO
FlexCAN_A Transmit
—
—
I/O
O
—
—
VDDE2
SH
—
—
A2
A2
PD1
PD[1]
CNRX_A
49
00
01
10
11
Port D GPIO
FlexCAN_A Receive
—
—
I/O
I
—
—
VDDE2
SH
—
—
B2
B2
PD2
PD[2]
CNTX_B
50
00
01
10
11
Port D GPIO
FlexCAN_B Transmit
—
—
I/O
O
—
—
VDDE2
SH
—
—
B1
B1
PD3
PD[3]
CNRX_B
51
00
01
10
11
Port D GPIO
FlexCAN_B Receive
—
—
I/O
I
—
—
VDDE2
SH
—
—
C1
C1
PD4
PD[4]
CNTX_C
52
00
01
10
11
Port D GPIO
FlexCAN_C Transmit
—
—
I/O
O
—
—
VDDE2
SH
—
—
C2
C2
PD5
PD[5]
CNRX_C
53
00
01
10
11
Port D GPIO
FlexCAN_C Receive
—
—
I/O
I
—
—
VDDE2
SH
—
—
D1
D1
PD6
PD[6]
CNTX_D
TXD_K
SCL_B
54
00
01
10
11
Port D GPIO
FlexCAN_D Transmit
SCI_K Transmit
I2C_B Serial Clock
I/O
O
O
I/O
VDDE2
SH
—
—
D2
D2
PD7
PD[7]
CNRX_D
RXD_K
SDA_B
55
00
01
10
11
Port D GPIO
FlexCAN_D Receive
SCI_K Receive
I2C_B Serial Data
I/O
I
I
I/O
VDDE2
SH
—
—
E1
E1
PD8
PD[8]
CNTX_E
TXD_L
SCL_C
56
00
01
10
11
Port D GPIO
FlexCAN_E Transmit
SCI_L Transmit
I2C_C Serial Clock
I/O
O
O
I/O
VDDE2
SH
—
—
E2
E2
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
13
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PD9
PD[9]
CNRX_E
RXD_L
SDA_C
57
00
01
10
11
Port D GPIO
FlexCAN_E Receive
SCI_L Receive
I2C_C Serial Data
I/O
I
I
I/O
VDDE2
SH
—
—
F1
F1
PD10
PD[10]
CNTX_F
TXD_M
SCL_D
58
00
01
10
11
Port D GPIO
FlexCAN_F Transmit
SCI_M Transmit
I2C_D Serial Clock
I/O
O
O
I/O
VDDE2
SH
—
—
F2
F2
PD11
PD[11]
CNRX_F
RXD_M
SDA_D
59
00
01
10
11
Port D GPIO
FlexCAN_F Receive
SCI_M Receive
I2C_D Serial Data
I/O
I
I
I/O
VDDE2
SH
—
—
G1
G1
PD12
PD[12]
TXD_A
60
00
01
10
11
Port D GPIO
eSCI_A Transmit
—
—
I/O
O
—
—
VDDE2
SH
—
—
G2
G2
PD13
PD[13]
RXD_A
61
00
01
10
11
Port D GPIO
eSCI_A Receive
—
—
I/O
I
—
—
VDDE2
SH
—
—
H1
H1
PD14
PD[14]
TXD_B
62
00
01
10
11
Port D GPIO
eSCI_B Transmit
—
—
I/O
O
—
—
VDDE2
SH
—
—
C3
C3
PD15
PD[15]
RXD_B
63
00
01
10
11
Port D GPIO
eSCI_B Receive
—
—
I/O
I
—
—
VDDE2
SH
—
—
D3
D3
Port E (16)
PE0
PE[0]
TXD_C
eMIOS[31]
64
00
01
10
11
Port E GPIO
eSCI_C Transmit
eMIOS Channel
—
I/O
O
I/O
—
VDDE2
SH
—
—
E3
E3
PE1
PE[1]
RXD_C
eMIOS[30]
65
00
01
10
11
Port E GPIO
eSCI_C Receive
eMIOS Channel
—
I/O
I
I/O
VDDE2
SH
—
—
E4
E4
PE2
PE[2]
TXD_D
eMIOS[29]
66
00
01
10
11
Port E GPIO
eSCI_D Transmit
eMIOS Channel
—
I/O
O
I/O
VDDE2
SH
—
—
F4
F4
MPC5668x Microcontroller Data Sheet, Rev. 6
14
Freescale Semiconductor
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PE3
PE[3]
RXD_D
eMIOS[28]
67
00
01
10
11
Port E GPIO
eSCI_D Receive
eMIOS Channel
—
I/O
I
I/O
VDDE2
SH
—
—
F3
F3
PE4
PE[4]
TXD_E
eMIOS[27]
68
00
01
10
11
Port E GPIO
eSCI_E Transmit
eMIOS Channel
—
I/O
O
I/O
VDDE2
SH
—
—
G3
G3
PE5
PE[5]
RXD_E
eMIOS[26]
69
00
01
10
11
Port E GPIO
eSCI_E Receive
eMIOS Channel
—
I/O
I
I/O
VDDE2
SH
—
—
H3
H3
PE6
PE[6]
TXD_F
eMIOS[25]
70
00
01
10
11
Port E GPIO
eSCI_F Transmit
eMIOS Channel
—
I/O
O
I/O
VDDE2
SH
—
—
M2
M2
PE7
PE[7]
RXD_F
eMIOS[24]
71
00
01
10
11
Port E GPIO
eSCI_F Receive
eMIOS Channel
—
I/O
I
I/O
VDDE2
SH
—
—
L2
L2
PE8
PE[8]
TXD_G
PCS_A[1]
72
00
01
10
11
Port E GPIO
eSCI_G Transmit
DSPI_A Peripheral Chip Select
—
I/O
O
O
VDDE2
SH
—
—
J4
J4
PE9
PE[9]
RXD_G
PCS_A[4]
73
00
01
10
11
Port E GPIO
eSCI_G Receive
DSPI_A Peripheral Chip Select
—
I/O
I
O
VDDE2
SH
—
—
M4
M4
PE10
PE[10]
TXD_H
PCS_B[3]
74
00
01
10
11
Port E GPIO
eSCI_H Transmit
DSPI_B Peripheral Chip Select
—
I/O
O
O
VDDE2
SH
—
—
N3
N3
PE11
PE[11]
RXD_H
PCS_B[2]
75
00
01
10
11
Port E GPIO
eSCI_H Receive
DSPI_B Peripheral Chip Select
—
I/O
I
O
VDDE2
SH
—
—
N4
N4
PE12
PE[12]
TXD_J
PCS_C[5]
76
00
01
10
11
Port E GPIO
eSCI_J Transmit
DSPI_C Peripheral Chip Select
—
I/O
O
O
VDDE2
SH
—
—
P4
P4
PE13
PE[13]
RXD_J
PCS_C[3]
77
00
01
10
11
Port E GPIO
eSCI_J Receive
DSPI_C Peripheral Chip Select
—
I/O
I
O
VDDE2
SH
—
—
P5
P5
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
15
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PE14
PE[14]
SCL_A
PCS_D[2]
78
00
01
10
11
Port E GPIO
I2C_A Serial Clock
DSPI_D Peripheral Chip Select
—
I/O
I/O
O
—
VDDE2
SH
—
—
N7
N7
PE15
PE[15]
SDA_A
PCS_D[5]
79
00
01
10
11
Port E GPIO
I2C_A Serial Data
DSPI_D Peripheral Chip Select
—
I/O
I/O
O
—
VDDE2
SH
—
—
N6
N6
Port F (16)
PF0
PF[0]
SCK_A
80
00
01
10
11
Port F GPIO
DSPI_A Serial Clock
—
—
I/O
I/O
—
—
VDDE2
MH
—
—
H2
H2
PF1
PF[1]
SOUT_A
81
00
01
10
11
Port F GPIO
DSPI_A Serial Data Out
—
—
I/O
O
—
—
VDDE2
MH
—
—
J1
J1
PF2
PF[2]
SIN_A
82
00
01
10
11
Port F GPIO
DSPI_A Serial Data In
—
—
I/O
I
—
—
VDDE2
SH
—
—
J2
J2
PF3
PF[3]
PCS_A[0]
PCS_B[5]
PCS_C[4]
83
00
01
10
11
Port F GPIO
DSPI_A Peripheral Chip Select
DSPI_B Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
I/O
O
O
VDDE2
SH
—
—
N2
N2
PF4
PF[4]
SCK_B
PCS_A[1]
PCS_C[2]
84
00
01
10
11
Port F GPIO
DSPI_B Serial Clock
DSPI_A Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
I/O
O
O
VDDE2
MH
—
—
M1
M1
PF5
PF[5]
SOUT_B
PCS_A[2]
PCS_C[3]
85
00
01
10
11
Port F GPIO
DSPI_B Serial Data Out
DSPI_A Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
O
O
O
VDDE2
MH
—
—
P2
P2
PF6
PF[6]
SIN_B
PCS_A[3]
PCS_C[5]
86
00
01
10
11
Port F GPIO
DSPI_B Serial Data In
DSPI_A Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
I
O
O
VDDE2
SH
—
—
N1
N1
PF7
PF[7]
PCS_B[0]
PCS_C[5]
PCS_D[4]
87
00
01
10
11
Port F GPIO
DSPI_B Peripheral Chip Select
DSPI_C Peripheral Chip Select
DSPI_D Peripheral Chip Select
I/O
I/O
O
O
VDDE2
SH
—
—
R2
R2
MPC5668x Microcontroller Data Sheet, Rev. 6
16
Freescale Semiconductor
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PF8
PF[8]
SCK_C
88
00
01
10
11
Port F GPIO
DSPI_C Serial Clock
—
—
I/O
I/O
—
—
VDDE2
MH
—
—
P1
P1
PF9
PF[9]
SOUT_C
89
00
01
10
11
Port F GPIO
DSPI_C Serial Data Out
—
—
I/O
O
—
—
VDDE2
MH
—
—
T2
T2
PF10
PF[10]
SIN_C
90
00
01
10
11
Port F GPIO
DSPI_C Serial Data In
—
—
I/O
I
—
—
VDDE2
SH
—
—
R1
R1
PF11
PF[11]
PCS_C[0]
PCS_D[5]
PCS_A[4]
91
00
01
10
11
Port F GPIO
DSPI_C Peripheral Chip Select
DSPI_D Peripheral Chip Select
DSPI_A Peripheral Chip Select
I/O
I/O
O
O
VDDE2
SH
—
—
R3
R3
PF12
PF[12]
SCK_D
92
00
01
10
11
Port F GPIO
DSPI_D Serial Clock
—
—
I/O
I/O
—
—
VDDE3
MH
—
—
N14
N14
PF13
PF[13]
SOUT_D
93
00
01
10
11
Port F GPIO
DSPI_D Serial Data Out
—
—
I/O
O
—
—
VDDE3
MH
—
—
M14
M14
PF14
PF[14]
SIN_D
94
00
01
10
11
Port F GPIO
DSPI_D Serial Data In
—
—
I/O
I
—
—
VDDE3
SH
—
—
P14
P14
PF15
PF[15]
PCS_D[0]
PCS_A[5]
PCS_B[4]
95
00
01
10
11
Port F GPIO
DSPI_D Peripheral Chip Select
DSPI_A Peripheral Chip Select
DSPI_B Peripheral Chip Select
I/O
I/O
O
O
VDDE3
SH
—
—
P13
P13
Port G (16)
PG0
PG[0]
PCS_A[4]
PCS_B[3]
AN[48]
96
00
01
10
11
Port G GPIO
DSPI_A Peripheral Chip Select
DSPI_B Peripheral Chip Select
ADC Analog Input
I/O
O
O
I
VDDE2
SHA
—
—
B3
B3
PG1
PG[1]
PCS_A[5]
PCS_B[4]
AN[49]
97
00
01
10
11
Port G GPIO
DSPI_A Peripheral Chip Select
DSPI_B Peripheral Chip Select
ADC Analog Input
I/O
O
O
I
VDDE2
SHA
—
—
A3
A3
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
17
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PG2
PG[2]
PCS_D[1]
SCL_C
AN[50]
98
00
01
10
11
Port G GPIO
DSPI_D Peripheral Chip Select
I2C_C Serial Clock
ADC Analog Input
I/O
O
I/O
I
VDDE3
SHA
—
—
H14
H14
PG3
PG[3]
PCS_D[2]
SDA_C
AN[51]
99
00
01
10
11
Port G GPIO
DSPI_D Peripheral Chip Select
I2C_C Serial Data
ADC Analog Input
I/O
O
I/O
I
VDDE3
SHA
—
—
J14
J14
PG4
PG[4]
PCS_D[3]
SCL_B
AN[52]
100
00
01
10
11
Port G GPIO
DSPI_D Peripheral Chip Select
I2C_B Serial Clock
ADC Analog Input
I/O
O
I/O
I
VDDE3
SHA
—
—
K14
K14
PG5
PG[5]
PCS_D[4]
SDA_B
AN[53]
101
00
01
10
11
Port G GPIO
DSPI_D Peripheral Chip Select
I2C_B Serial Data
ADC Analog Input
I/O
O
I/O
I
VDDE3
SHA
—
—
L14
L14
PG6
PG[6]
PCS_C[1]
FEC_MDC
AN[54]
102
00
01
10
11
Port G GPIO
DSPI_C Peripheral Chip Select
Ethernet Mgmt. Data Clock
ADC Analog Input
I/O
O
O
I
VDDE3
MHA
—
—
H15
H15
PG7
PG[7]
PCS_C[2]
FEC_MDIO
AN[55]
103
00
01
10
11
Port G GPIO
DSPI_C Peripheral Chip Select
Ethernet Mgmt. Data I/O
ADC Analog Input
I/O
O
I/O
I
VDDE3
MHA
—
—
J15
J15
PG8
PG[8]
104
eMIOS[7]
FEC_TX_CLK
AN[56]
00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Transmit Clock
ADC Analog Input
I/O
I/O
I
I
VDDE3
SHA
—
—
K15
K15
PG9
PG[9]
eMIOS[6]
FEC_CRS
AN[57]
105
00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Carrier Sense
ADC Analog Input
I/O
I/O
I
I
VDDE3
SHA
—
—
L15
L15
PG10
PG[10]
106
eMIOS[5]
FEC_TX_ER
AN[58]
00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Transmit Error
ADC Analog Input
I/O
I/O
O
I
VDDE3
MHA
—
—
M15
M15
PG11
PG[11]
107
eMIOS[4]
FEC_RX_CLK
AN[59]
00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Receive Clock
ADC Analog Input
I/O
I/O
I
I
VDDE3
SHA
—
—
J16
J16
PG12
PG[12]
108
eMIOS[3]
FEC_TXD[0]
AN[60]
00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Transmit Data
ADC Analog Input
I/O
I/O
O
I
VDDE3
MHA
—
—
K16
K16
MPC5668x Microcontroller Data Sheet, Rev. 6
18
Freescale Semiconductor
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PG13
PG[13]
109
eMIOS[2]
FEC_TXD[1]
AN[61]
00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Transmit Data
ADC Analog Input
I/O
I/O
O
I
VDDE3
MHA
—
—
L16
L16
PG14
PG[14]
110
eMIOS[1]
FEC_TXD[2]
AN[62]
00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Transmit Data
ADC Analog Input
I/O
I/O
O
I
VDDE3
MHA
—
—
M16
M16
PG15
PG[15]
111
eMIOS[0]
FEC_TXD[3]
AN[63]
00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Transmit Data
ADC Analog Input
I/O
I/O
O
I
VDDE3
MHA
—
—
N16
N16
Port H (16)
PH0
PH[0]
eMIOS[31]
FEC_COL
112
00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Collision
—
I/O
I/O
I
—
VDDE3
SH
—
—
T14
T14
PH1
PH[1]
113
eMIOS[30]
FEC_RX_DV
00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Receive Data Valid
—
I/O
I/O
I
—
VDDE3
SH
—
—
P16
P16
PH2
114
PH[2]
eMIOS[29]
FEC_TX_EN
00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Transmit Enable
—
I/O
I/O
O
—
VDDE3
MH
—
—
R16
R16
PH3
PH[3]
115
eMIOS[28]
FEC_RX_ER
00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Receive Error
—
I/O
I/O
I
—
VDDE3
SH
—
—
N15
N15
PH4
PH[4]
116
eMIOS[27]
FEC_RXD[0]
00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Receive Data
—
I/O
I/O
I
—
VDDE3
SH
—
—
P15
P15
PH5
PH[5]
117
eMIOS[26]
FEC_RXD[1]
00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Receive Data
—
I/O
I/O
I
—
VDDE3
SH
—
—
R14
R14
PH6
PH[6]
118
eMIOS[25]
FEC_RXD[2]
00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Receive Data
—
I/O
I/O
I
—
VDDE3
SH
—
—
R15
R15
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
19
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PH7
PH[7]
119
eMIOS[24]
FEC_RXD[3]
00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Receive Data
—
I/O
I/O
I
—
VDDE3
SH
—
—
T15
T15
PH8
PH[8]
eMIOS[23]
120
00
01
10
11
Port H GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
P7
P7
PH9
PH[9]
eMIOS[22]
121
00
01
10
11
Port H GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
N8
N8
PH10
PH[10]
eMIOS[21]
122
00
01
10
11
Port H GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
P8
P8
PH11
PH[11]
eMIOS[20]
123
00
01
10
11
Port H GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
N9
N9
PH12
PH[12]
eMIOS[19]
124
00
01
10
11
Port H GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
P9
P9
PH13
PH[13]
eMIOS[18]
125
00
01
10
11
Port H GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
P10
P10
PH14
PH[14]
eMIOS[17]
126
00
01
10
11
Port H GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
P11
P11
PH15
PH[15]
eMIOS[16]
127
00
01
10
11
Port H GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
N11
N11
I/O
I/O
O
—
VDDE4
SH
—
—
R7
R7
Port J (16)
PJ0
PJ[0]
eMIOS[15]
PCS_A[4]
128
00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_A Peripheral Chip Select
—
MPC5668x Microcontroller Data Sheet, Rev. 6
20
Freescale Semiconductor
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PJ1
PJ[1]
eMIOS[14]
PCS_A[5]
129
00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_A Peripheral Chip Select
—
I/O
I/O
O
—
VDDE4
SH
—
—
T7
T7
PJ2
PJ[2]
eMIOS[13]
PCS_B[1]
130
00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_B Peripheral Chip Select
—
I/O
I/O
O
—
VDDE4
SH
—
—
R8
R8
PJ3
PJ[3]
eMIOS[12]
PCS_B[2]
131
00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_B Peripheral Chip Select
—
I/O
I/O
O
—
VDDE4
SH
—
—
T8
T8
PJ4
PJ[4]
eMIOS[11]
PCS_C[3]
132
00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_C Peripheral Chip Select
—
I/O
I/O
O
—
VDDE4
SH
—
—
R9
R9
PJ5
PJ[5]
eMIOS[10]
PCS_C[4]
133
00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_C Peripheral Chip Select
—
I/O
I/O
O
—
VDDE4
SH
—
—
T9
T9
PJ6
PJ[6]
eMIOS[09]
PCS_D[5]
134
00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_D Peripheral Chip Select
—
I/O
I/O
O
—
VDDE4
SH
—
—
R10
R10
PJ7
PJ[7]
eMIOS[08]
PCS_D[1]
135
00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_D Peripheral Chip Select
—
I/O
I/O
O
—
VDDE4
SH
—
—
T10
T10
PJ8
PJ[8]
eMIOS[07]
136
00
01
10
11
Port J GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
T11
T11
PJ9
PJ[9]
eMIOS[06]
137
00
01
10
11
Port J GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
R11
R11
PJ10
PJ[10]
eMIOS[05]
138
00
01
10
11
Port J GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
N12
N12
PJ11
PJ[11]
eMIOS[04]
139
00
01
10
11
Port J GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
P12
P12
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
21
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PJ12
PJ[12]
eMIOS[03]
140
00
01
10
11
Port J GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
R12
R12
PJ13
PJ[13]
eMIOS[02]
141
00
01
10
11
Port J GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
T12
T12
PJ14
PJ[14]
eMIOS[01]
142
00
01
10
11
Port J GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
R13
R13
PJ15
PJ[15]
eMIOS[00]
143
00
01
10
11
Port J GPIO
eMIOS Channel
—
—
I/O
I/O
—
—
VDDE4
SH
—
—
T13
T13
Port K (11)
PK0
PK[0]
MLBCLK
SCK_B
CLKOUT
144
00
01
10
11
Port K GPIO
Media Local Bus Clock
DSPI_B Serial Clock
CLKOUT (Test Only)
I/O
I
I/O
O
VDDEMLB
F
—
—
L1
L1
PK1
PK[1]
MLBSIG
SOUT_B
PCS_D[4]
145
00
01
10
11
Port K GPIO
Media Local Bus Signal
DSPI_B Serial Data Out
DSPI_D Peripheral Chip Select
I/O
I/O
O
O
VDDEMLB
F
—
—
K1
K1
PK2
PK[2]
MLBDAT
SIN_B
PCS_D[5]
146
00
01
10
11
Port K GPIO
Media Local Bus Data
DSPI_B Serial Data In
DSPI_D Peripheral Chip Select
I/O
I/O
I
O
VDDEMLB
F
—
—
K2
K2
PK3
PK[3]
FR_A_RX
MA[0]
PCS_C[1]
147
00
01
10
11
Port K GPIO
FlexRay A Receive Data
ADC Ext. Mux Address Select
DSPI_C Peripheral Chip Select
I/O
I
O
O
VDDE2
SH
—
—
T3
T3
PK4
PK[4]
FR_A_TX
MA[1]
PCS_C[2]
148
00
01
10
11
Port K GPIO
FlexRay A Transmit Data
ADC Ext. Mux Address Select
DSPI_C Peripheral Chip Select
I/O
O
O
O
VDDE2
MH
—
—
R4
R4
PK5
PK[5]
149
FR_A_TX_EN
MA[2]
PCS_C[3]
00
01
10
11
Port K GPIO
FlexRay A Transmit Enable
ADC Ext. Mux Address Select
DSPI_C Peripheral Chip Select
I/O
O
O
O
VDDE2
MH
—
—
T4
T4
MPC5668x Microcontroller Data Sheet, Rev. 6
22
Freescale Semiconductor
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
Status
Description
I/O
Type
Voltage
Pad
Type5
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
PK6
PK[6]
FR_B_RX
PCS_B[1]
PCS_C[4]
150
00
01
10
11
Port K GPIO
FlexRay B Receive Data
DSPI_B Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
I
O
O
VDDE2
SH
—
—
R5
R5
PK7
PK[7]
FR_B_TX
PCS_B[2]
PCS_C[5]
151
00
01
10
11
Port K GPIO
FlexRay B Transmit Data
DSPI_B Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
O
O
O
VDDE2
MH
—
—
T5
T5
PK8
PK[8]
152
FR_B_TX_EN
PCS_B[3]
PCS_A[1]
00
01
10
11
Port K GPIO
FlexRay B Transmit Enable
DSPI_B Peripheral Chip Select
DSPI_A Peripheral Chip Select
I/O
O
O
O
VDDE2
MH
—
—
R6
R6
PK9
PK[9]
CLKOUT
PCS_D[1]
PCS_A[2]
BOOTCFG
153
00
01
10
11
Port K GPIO
CLKOUT (User mode)
DSPI_D Peripheral Chip Select
DSPI_A Peripheral Chip Select
Boot Configuration
I/O
O
O
O
I
VDDE2
MH
BOOT GPIO
CFG
(Pulldown)
T6
T6
PK10
PK[10]
PCS_B[5]
PCS_D[2]
PCS_A[3]
154
00
01
10
11
Port K GPIO
DSPI_B Peripheral Chip Select
DSPI_D Peripheral Chip Select
DSPI_A Peripheral Chip Select
I/O
O
O
O
VDDE2
SH
—
—
P6
P6
Nexus Pins (17)
EVTI
EVTI
—
— Nexus Event In
I
VDDENEX
F
—
—
—
M11
EVTO
EVTO
—
— Nexus Event Out
O
VDDENEX
F
—
—
—
M12
MSEO0 MSEO[0]
—
— Nexus Message Start/End Out
O
VDDENEX
F
—
—
—
M9
MSEO1 MSEO[1]
—
— Nexus Message Start/End Out
O
VDDENEX
F
—
—
—
M8
MCKO
MCKO
—
— Nexus Message Clock Out
O
VDDENEX
F
—
—
—
M10
MDO0
MDO[0]
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
E5
MDO1
MDO[1]
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
F5
MDO2
MDO[2]
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
G5
MDO3
MDO[3]
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
H5
MDO4
MDO[4]
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
H6
MDO5
MDO[5]
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
J6
MDO6
MDO[6]
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
J5
MDO7
MDO[7]
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
K5
MDO8
MDO[8]
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
L5
MDO9
MDO[9]
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
M5
—
— Nexus Message Data Out
O
VDDENEX
F
—
—
—
M6
MDO10 MDO[10]
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
23
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1
GPIO
Supported
4
2 (PCR) PA
Functions
Num3
MDO11 MDO[11]
—
Status
Description
— Nexus Message Data Out
I/O
Type
Voltage
Pad
Type5
O
VDDENEX
F
Package Pin
Locations
During
Reset6
After
Reset7
208
BGA
256
BGA
—
—
—
M7
Miscellaneous Pins (9)
EXTAL
EXTAL
EXTCLK
—
— Main Crystal Oscillator Input
External Clock Input
I
I
VDDSYN
A
EXTAL
A14
A14
XTAL
XTAL
—
— Main Crystal Oscillator Output
O
VDDSYN
A
XTAL
A13
A13
TDI
TDI
—
— JTAG Test Data Input
I
VDDE2
SH
TDI (Pull Up)
J3
J3
TDO
TDO
—
— JTAG Test Data Output
O
VDDE2
MH
TDO (Pull Up8)
M3
M3
TMS
TMS
—
— JTAG Test Mode Select Input
I
VDDE2
MH
TMS (Pull Up)
L3
L3
TCK
TCK
—
— JTAG Test Clock Input
I
VDDE2
SH
TCK (Pull Down)
P3
P3
JCOMP JCOMP
—
— JTAG Compliancy
I
VDDE2
SH
JCOMP (Pull Down)
K3
K3
TEST
—
— Test Mode Select
I
VDDE3
IH
TEST9
M13
M13
—
— External Reset
I/O
VDDE1
MH
RESET (Pull Up)
A11
A11
TEST
RESET RESET
1
2
3
4
5
6
7
8
9
The primary signal name is used as the pin label on the BGA map for identification purposes.
Each line in the Signal Name column corresponds to a separate signal function on the pin. For all device I/O pins, the primary,
alternate, or GPIO signal functions are designated in the PA field of the System Integration Unit (SIU) PCR registers except
where explicitly noted.
The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number.
The PA bitfield in the SIU_PCRn register selects the signal function for the pin. A dash in the Description field of this table
indicates that this value for PC is reserved on this pin, and should not be used.
The pad type is indicated by one or more of the following abbreviations: A–analog, F—fast speed, H–high voltage, I—input-only,
M–medium speed, S–slow speed. For example, pad type SH designates a slow high-voltage pad.
The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high
impedance. The terminology used in this column is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown
enabled, Low – output driven low, High – output driven high. A dash on the left side of the slash denotes that both the input and
output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on
the pin. The signal name to the left or right of the slash indicates the pin is enabled.
The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the
input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down
enabled on the pin.
Pullup is enabled only when JCOMP is negated.
Tie to VSS for normal operation.
MPC5668x Microcontroller Data Sheet, Rev. 6
24
Freescale Semiconductor
Pin Assignments
3.3.1
Power and Ground Supply Summary
Table 3. MPC5668x Power/Ground
Pin
Name
Function Description
VDD
Internal Logic Power
VDDE1
External I/O Power
Package Pin Locations
Voltage1
208
256
1.2 V
D4, D10, H4, G13, K13, N5
D4, D10, H4, G13, K13, N5
3.3–5.0 V
D6
D6
VDDE2
L4
L4
VDDE3
J13
J13
VDDE4
N10
N10
VDDA
Analog Power
3.3–5.0 V
B15
B15
VDD33
3.3 V I/O Power
3.3 V
L13
L13
VDDEMLB
Media Local Bus Power
2.5 or 3.3 V
K4
K4
VDDENEX2
Nexus Power
3.3 V
—
E6, K11, L7
VRCSEL
Voltage Regulator Select
VSSA / VDDA
H13
H13
VRC
Voltage Regulator Control Voltage
3.3–5.0 V
B10
B10
B11
B11
A12
A12
3
VRCCTL
Voltage Regulator Control Output
VDDSYN
Clock Synthesizer Power
3.3 V
VRH
Analog High Voltage Reference
3.3–5.0 V
B16
B16
VRL
Analog Low Voltage Reference
0V
C16
C16
VSS
Ground
0V
VSSA
Analog Ground
0V
C15
C15
VSSSYN
Clock Synthesizer Ground
0V
A15
A15
—
A1, A16, D7, G4, G[7:10],
A1, A16, D7, E[7:12], F[7:12],
H[7:10], J[7:10], K[7:10], N13, G4, G[6:12], H[7:12], J[7:12],
T1, T16
K[6:10], K12, L[8:10], L12,
N13, T1, T16
1
Nominal voltages.
Dedicated Nexus power pin on 256-pin package only. On the 208-pin package, VDDENEX is tied to VSS internal to the
package substrate and is not available externally.
3 Base current to external NPN power transistor. Voltage may vary.
2
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
25
Electrical Characteristics
4
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC5668x.
4.1
Maximum Ratings
Table 4. Absolute Maximum Ratings1
Spec
1
2
4
5
6
Voltage2, 4
3.3 V Clock Synthesizer
3
3.3 V I/O Buffer Voltage 2, 4
4
3.3–5.0 V Voltage Regulator Control Voltage 2, 5, 6
5
3.3–5.0 V Analog Supply Voltage (reference to VSSA)
6
3.3–5.0 V External I/O Supply Voltage 2, 5, 7
7
2.5–3.3 V External I/O Supply Voltage (MLB) 2, 4
9
3
1.2 V Core Supply Voltage2
2
8
1
Characteristic
3.3 V External I/O Supply Voltage (Nexus)
2, 5
2, 4
Voltage9
Symbol
Min
Max
Unit
VDD
–0.3
1.323
V
VDDSYN
–0.3
3.6
V
VDD33
–0.3
3.6
V
VRC
–0.3
5.5
V
VDDA
–0.3
5.5
V
VDDE18
VDDE28
VDDE38
VDDE48
–0.3
–0.3
–0.3
–0.3
5.5
5.5
5.5
5.5
V
VDDEMLB8
–0.3
3.6
V
VDDENEX8
–0.3
3.6
V
–1.010
–1.09
VDDEx + 0.3 V11
VDDEx + 0.3 V10
DC Input
VDDE1, VDDE2, VDDE3, VDDE4
VDDEMLB, VDDENEX
VIN
10
Analog Reference High Voltage
VRH
–0.3
Minimum of
5.5
or
VDDA + 0.3
V
11
Analog Reference Low Voltage
VRL
–0.3
5.5
V
12
VSS to VSSA Differential Voltage
VSS – VSSA
–100
100
mV
13
VSS to VSSSYN Differential Voltage
VSS – VSSSYN
–100
100
mV
12
V
14
Maximum DC Digital Input Current
digital F, MH, SH, and IH pins)
(per pin, applies to all
IMAXD
–2
2
mA
15
Maximum DC Analog Input Current13 (per pin, applies to all
analog AE and A pins)
IMAXA
–3
3
mA
16
Storage Temperature Range
TSTG
–55.0
150.0
oC
17
Maximum Solder Temperature14
TSDR
—
235.0
oC
18
Moisture Sensitivity Level15
MSL
—
3
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability
or cause permanent damage to the device.
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.
5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining.
6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.
VRC cannot be 100mV higher than VDDA. VDDSYN and VDD33 cannot be 100mV higher than VRC.
MPC5668x Microcontroller Data Sheet, Rev. 6
26
Freescale Semiconductor
Electrical Characteristics
7
All functional non-supply I/O pins are clamped to VSS and VDDEx.
VDDEx are separate power segments and may be powered independently with no differential voltage constraints between
the power segments.
9
AC signal over and undershoot of the input voltages of up to ±2.0 V is permitted for a cumulative duration of 60 hours over
the complete lifetime of the device (injection current does not need to be limited for this duration).
10 Internal structures will hold the input voltage above –1.0 V if the injection current limit of 2 mA is met.
11
Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the
maximum injection current specification is met (25 mA for all pins) and VDDE is within Operating Voltage specifications.
12
Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
13
Total injection current for all analog input pins must not exceed 15 mA.
14
Solder profile per CDF-AEC-Q100.
15
Moisture sensitivity per JEDEC test method A112.
8
4.2
Thermal Characteristics
Table 5. Thermal Characteristics
Value
Spec
1
2
3
4
5
6
Characteristic
Symbol
Unit
208 MAPBGA
256 MAPBGA
1
Junction to Ambient1, 2
Natural Convection
(Single layer board)
RJA
°C/W
39
39
2
Junction to Ambient1, 3
Natural Convection
(Four layer board 2s2p)
RJA
°C/W
24
24
3
Junction to Ambient1, 3
(@200 ft./min., Single layer board)
RJMA
°C/W
31
31
4
Junction to Ambient1, 3
(@200 ft./min., Four layer board 2s2p)
RJMA
°C/W
20
20
5
Junction to Board4
RJB
°C/W
13
13
RJC
°C/W
6
6
JT
°C/W
2
2
Case5
6
Junction to
7
Junction to Package Top6
Natural Convection
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
4.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
27
Electrical Characteristics
TJ = TA + (RJA  PD)
Eqn. 1
where:
TA = ambient temperature for the package (oC)
RJA = junction to ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer
board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of
the component is not a constant. It depends on the construction of the application board (number of planes), the effective size
of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the
power being dissipated by adjacent components.
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value
obtained on the board with the internal planes is usually appropriate if the application board has one oz. (35 micron nominal
thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02
W/cm2.
The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition,
the ambient temperature varies widely within the application. For many natural convection and especially closed box
applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature
near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description
of the local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RJB  PD)
Eqn. 2
where:
TJ = junction temperature (oC)
TB = board temperature at the package perimeter (oC/W)
RJB = junction to board thermal resistance (oC/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
The application board should be similar to the thermal test condition, with the component soldered to a board with internal
planes.
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case
to ambient thermal resistance:
RJA = RJC + RCA
Eqn. 3
where:
RJA = junction to ambient thermal resistance (oC/W)
RJC = junction to case thermal resistance (oC/W)
RCA = case to ambient thermal resistance (oC/W)
MPC5668x Microcontroller Data Sheet, Rev. 6
28
Freescale Semiconductor
Electrical Characteristics
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RCA. For instance, the user can change the air flow around the device, add a heat sink, change the
mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the
device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the
heat sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction
to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount
of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance
when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a
computational fluid dynamics (CFD) thermal model.
To determine the junction temperature of the device in the application after prototypes are available, the Thermal
Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using the following equation:
TJ = TT + (JT  PD)
Eqn. 4
where:
TT = thermocouple temperature on top of the package (oC)
JT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1.
2.
3.
C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53–58, March 1998.
B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
29
Electrical Characteristics
4.3
ESD Characteristics
Table 6. ESD Ratings1, 2
Characteristic
Symbol
Value
Unit
2000
V
R1
1500
Ohm
C
100
pF
ESD for Human Body Model (HBM)
HBM Circuit Description
ESD for Field Induced Charge Model (FDCM)
750 (corner pins)
V
250 (all other pins)
Number of Pulses per pin:
Positive Pulses (HBM)
Negative Pulses (HBM)
—
—
1
1
—
—
Interval of Pulses
—
1
second
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room
temperature followed by hot temperature, unless specified otherwise in the device specification.
2
4.4
VRC Electrical Specifications
Table 7. VRC Electrical Specifications
Characteristic
Spec
1
1
Current which can be sourced by VRCCTL
2
Minimum Required Gain from external circuit:
IDD / I_VRCCTL (@VDD = 1.32 V)1
–40C
25C
150C
Symbol
Min
Max
Units
I_VRCCTL
6.25 µA
20 mA
—
BETA
50
50
50
500
Assumes “typical usage” currents which will vary with application.
4.5
DC Electrical Specifications
Table 8. DC Electrical Specifications
Spec
Characteristic
Symbol
Min
Max
Unit
1
Maximum Operating Temperature Range — Die Junction Temperature
TJ
–40.0
150.0
oC
2
3.3 V Clock Synthesizer Voltage1
VDDSYN
3.0
3.6
V
VDD33
3.0
3.6
V
3.0
4.5
3.6
5.5
maximum of
3.0 V or
VVRC – 0.1
5.5
Voltage1
3
3.3 V I/O Buffer
4
3.3–5.0 V Voltage Regulator Reference Voltage1
VRCSEL = VSSA
VRCSEL = VDDA
VVRC
3.3–5.0 V Analog Supply Voltage
VDDA
5
V
V
MPC5668x Microcontroller Data Sheet, Rev. 6
30
Freescale Semiconductor
Electrical Characteristics
Table 8. DC Electrical Specifications
Spec
6
Symbol
Min
Max
VDDE1
VDDE2
VDDE3
VDDE4
3.0
3.0
3.0
3.0
5.5
5.5
5.5
5.5
3.3–5.0 V External I/O Supply Voltage2
Unit
V
7
2.5 V – 3.3 V External I/O Supply Voltage (MLB)
VDDEMLB3
2.375
3.6
V
8
3.3 V External I/O Supply Voltage (Nexus)
VDDENEX
3.0
3.6
V
9
Pad Input High Voltage
Hysteresis enabled
Hysteresis disabled (IHA/SH/SHA/MH/MHA)4, 5
Hysteresis disabled (F)
VIH
VDDE + 0.3
V
Pad Input Low Voltage
Hysteresis enabled
Hysteresis disabled (IHA/SH/SHA/MH/MHA)4, 5
Hysteresis disabled (F)
VIL
10
1
Characteristic
0.65  VDDE
0.55  VDDE
0.55  VDDE
VSS – 0.3
V
0.35  VDDE
0.40  VDDE
0.40  VDDE
0.1  VDDE
V
11
Pad Input Hysteresis
VHYS
12
Analog (IHA) Input Voltage
VINDC
VSSA – 0.3
VDDA + 0.3
V
13
Pad Output High Voltage6, 7, 8
VOH
0.8  VDDE
—
V
14
Pad Output Low Voltage8
VOL
—
0.2  VDDE
V
15
Input Capacitance (Digital Pins: Pad type F, MH, SH)4
CIN
—
7
pF
16
Input Capacitance (Analog Pins: Pad type IHA)4, 5
CIN_A
—
10
pF
17
Input Capacitance (Shared digital/analog pins: MHA, SHA)4
CIN_M
—
12
pF
18
I/O Weak Pull Up/Down Absolute Current4, 9
Pad F: 2.375 V – 3.6 V
Pad SH/MH/IHA: 3.0 V – 3.6 V
Pad SH/MH/IHA: 4.5 V – 5.5 V
25
10
35
180
95
200
IINACT_D
–2.5
2.5
A
IIC
–1.0
1.0
mA
IINACT_A
–150
150
nA
A
IACT
19
I/O Input Leakage Current10
20
DC Injection Current (per pin)
21
Analog Input Current, Channel Off11 (Analog pins IHA)4, 5
22
Analog Reference High Voltage
VRH
VDDA – 500
VDDA
mV
23
Analog Reference Low Voltage
VRL
VSSA
VSSA + 500
mV
24
VSS to VSSA Differential Voltage
VSS – VSSA
–100
100
mV
25
VSSSYN to VSS Differential Voltage
VSSSYN – VSS
–100
100
mV
26
Slew rate on VDDA, VDDEx, VDDSYN, VDD33, and VRC power supply
pins
VRamp
—
100
V/ms
27
Capacitive Supply Load (VDD)
VLoad
8
—
µF
28
Capacitive Supply Load (VDD33, VDDSYN)
VLoad
1
—
µF
When VRCSEL = VSSA (low), VDDSYN and VDD33 are externally supplied. When VRCSEL = VDDA (high), VDDSYN and VDD33 are
generated by internal voltage regulators. When VRCSEL = VSSA (low), VDDSYN and VDD33 cannot be 100 mV higher than VRC.
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
31
Electrical Characteristics
2
VDDE1 – VDDE4 are separate power segments and may be powered independently with no differential voltage constraints
between the power segments. VDDE1 – VDDE3 pad power segments contain ADC analog input channels and thus the input
analog signal level may be clamped to the VDDE level, resulting in inaccurate ADC results if the VDDE voltage level is less than
VDDA.
3
When VRCSEL = VDDA (high), the internally generated VDD33 voltage may be used to power VDDEMLB as long as the PK[0:2]
pads remain in the disabled default state with their output buffers, input buffers, and pull devices disabled.
4 The pad type is indicated by one or more of the following abbreviations: A–analog, F—fast speed, H–high voltage, I—input-only,
M–medium speed, S–slow speed. For example, pad type SH designates a slow high-voltage pad.
5
The IHA pads are related to VDDA.
6
Characterization Based Capability:
IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE = 3.0 V;
IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE = 2.25 V;
IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE = 1.62 V.
7
Characterization Based Capability:
IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH = 4.5 V;
IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH = 3.0 V
8 All V /V
OL OH values 100% tested with ±2 mA load.
9 Absolute value of current, measured at V and V .
IL
IH
10 Weak pull up/down inactive. Measured at V
=
DDE 5.25 V. Applies to pad types: SH and MH. Leakage specification guaranteed
only when power supplies are within specified operating conditions.
11 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each
8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
4.6
Operating Current Specifications
Table 9. Operating Currents
Spec
Characteristic
Equations ITOTAL = IDDE + IDDA + IRH + IDD33 + IDDSYN + IRC + IDD
IDDE = IDDE1 + IDDE2 + IDDE3 + IDDE4 + IDDEMLB
1
2
3
4
Typ1
Symbol
25 C
Ambient
—
VDDE Current
VDDE(1,2,3,4) @ 3.0 V – 5.5 V
VDDEMLB @ 2.375 V – 3.6 V
Static2
Dynamic3
IDDE
VDDA Current
VDDA @ 3.0 V – 5.5 V
Run mode
Sleep mode
– Optional 32 kHz osc enabled
IDDA
VRH Current
VRH @ 3.0 V – 5.5 V
Run mode
Sleep mode
IRH
VDD33 Current
VDD33 @ 3.0 V – 3.6 V
Run mode
Sleep mode
Max1
–40–150 C
Junction
Unit
—
—
—
0
Note 3
30
25
A
mA
1
20
+5
30
50
+15
mA
A
A
300
1
700
30
A
A
10
10
20
20
mA
A
IDD33
MPC5668x Microcontroller Data Sheet, Rev. 6
32
Freescale Semiconductor
Electrical Characteristics
Table 9. Operating Currents (continued)
Spec
5
6
7
1
2
3
4
5
6
Characteristic
VDDSYN Current
VDD33 @ 3.0 V – 3.6 V
Run mode
Sleep mode
– Optional4 4–40 MHz osc enabled w/ no clock
– Optional4 4–40 MHz osc enabled w/ clock
Typ1
Symbol
25 C
Ambient
Max1
–40–150 C
Junction
Unit
5
1
+150
+300
10
20
+350
+400
mA
A
A
A
1
0
+40
10
10
+60
mA
A
A
200
100
+5
+200
+5
+5
+150
+10
+20
+40
340
900
+10
+220
+20
+20
+200
+150
+300
+600
mA
A
A
A
A
A
A
A
A
A
IDDSYN
VRC Current (excluding IDD, IDD33, IDDSYN)5
VRC @ 3.135 V – 5.5 V
Run mode
Sleep mode
– Optional4 16MIRC enabled
IRC
VDD Current
VDD @ 1.08 V – 1.32 V
Run mode (Maximum @ 116 MHz)6
Sleep mode
– Optional4 128KIRC enabled
– Optional4 16MIRC enabled
– Optional4 32 kHz osc enabled
– Optional4 4–40 MHz osc enabled w/ no clock
– Optional4 4–40 MHz osc enabled w/ clock
– Optional4 32 KB RAM
– Optional4 64 KB RAM
– Optional4 128 KB RAM
IDD
Typ – Nominal voltage levels and functional activity. Max – Maximum voltage levels and functional activity.
Static state of pins is when input pins are disabled or not being toggled and driven to a valid input level, output pins are not
toggling or driving against any current loads, and internal pull devices are disabled or not pulling against any current loads.
Dynamic current from pins is application-specific and depends on active pull devices, switching outputs, output capacitive and
current loads, and switching inputs. Refer to Table 10 for more information.
Optional currents are values that should be added to their respective current specifications to obtain the actual value for that
specification when the optional function is active. The plus sign (+) in the Typ and Max columns indicates these optional
currents. For example, VDDSYN in Sleep mode draws 1 .A (typ). With the optional 4–40 MHz osc enabled w/ no clock, add
150 .A for a total of 151 .A (typ).
VRC Current excluding the current supply to VDD33, VDDSYN and VDD from VRC.
Maximum supply current transition: 50mA per 20S observation window.
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
33
Electrical Characteristics
4.7
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption
is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 10 based on
the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load
parameters that fall outside the values given in Table 10.
Table 10. I/O Pad Average IDDE Specifications1
Period
(ns)
Load3
(pF)
VDDE
(V)
Drive/Slew
Rate Select
IDDE Avg
(mA)
37
50
5.5
11
14
130
50
5.5
01
5.3
650
50
5.5
00
1.1
4
840
200
5.5
00
3
6
24
50
5.5
11
9
62
50
5.5
01
2.5
317
50
5.5
00
0.5
9
425
200
5.5
00
1.5
11
10
50
3.6
11
50.4
101.6
12
10
30
3.6
10
14.2
57.3
13
10
20
3.6
01
16.4
43.6
10
10
3.6
00
9.8
15.9
10
50
2.75
11
22.9
45.3
16
10
30
2.75
10
6.7
25.3
17
10
20
2.75
01
4.5
17.3
18
10
10
2.75
00
3
9.6
7
0.5
5.5
N/A
N/A
N/A
Spec
Pad
Type2
Symbol
1
2
Slow
3
IDRV_SSR_HV
7
Medium
8
IDRV_MSR_HV
14
Fast
15
19
Input
IDRV_FC
IDRV_I_HV
IDDE RMS
(mA)
1
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2.
3 All loads are lumped.
2
MPC5668x Microcontroller Data Sheet, Rev. 6
34
Freescale Semiconductor
Electrical Characteristics
4.7.1
I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption
is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from
Table 11 based on the voltage, frequency, and load on all Pad F pins. The input pin VDD33 current can be calculated from
Table 11 based on the voltage, frequency, and load on all Pad MH pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table 11.
Table 11. I/O Pad Average IDD33 Specifications1
Period
(ns)
Load3
(pF)
Drive
Select
IDD33 Avg
(µA)
IDD33 RMS
(µA)
100
50
11
0.8
235.7
200
50
01
0.04
87.4
800
50
00
0.06
47.4
4
800
200
00
0.009
47
5
40
50
11
100
50
01
0.11
76.5
500
50
00
0.02
56.2
500
200
00
0.01
56.2
7
0.5
N/A
Spec
Pad
Type2
Symbol
1
2
Slow
3
IDRV_SSR_HV
6
Medium
7
IDRV_MSR_HV
8
9
Input
IDRV_I_HV
1
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2.
3 All loads are lumped.
2
Table 12. IDD33 Pad Average DC Current1
Period
(ns)
Load3
(pF)
VDD33
(V)
VDDE
(V)
Drive
Select
IDD33 Avg
(µA)
IDD33 RMS
(µA)
1
10
50
3.6
3.6
11
3.32
11.77
2
10
30
3.6
3.6
10
2.28
7.07
3
10
20
3.6
3.6
01
1.73
5.75
10
10
3.6
3.6
00
1.39
4.77
10
50
3.6
2.75
11
2.3
7.81
6
10
30
3.6
2.75
10
1.64
4.96
7
10
20
3.6
2.75
01
1.37
4.31
8
10
10
3.6
2.75
00
1.06
4.09
Spec
Pad
Type2
Symbol
4
Fast
5
IDRV_FC
1
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2.
3 All loads are lumped.
2
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
35
Electrical Characteristics
4.8
Low Voltage Characteristics
Table 13. Low Voltage Monitors
Spec
Characteristic
1
Power-on-Reset Assert Level1
2
Low Voltage Monitor 3.3 V2
Assert Level
De-assert Level
Low Voltage Monitor 3.0 V Low Threshold1
VRCSEL = VSSA
Assert Level
De-assert Level
VRCSEL = VDDA
Assert Level
De-assert Level
4
5
6
Min
Typical
Max
Unit
VPOR
1.5
—
2.8
V
VLVI33A
VLVI33D
3.00
3.04
3.05
3.12
3.10
3.19
VLVISYNA
VLVISYND
3.00
3.04
3.05
3.12
3.10
3.19
V
Low Voltage Monitor Synthesizer3
Assert Level
De-assert Level
3
Symbol
V
V
VLVI_VDDA_LOA
VLVI_VDDA_LOD
3.00
3.04
3.05
3.12
3.10
3.19
VLVI_VDDA_LOA
VLVI_VDDA_LOD
3.25
3.35
3.35
3.45
3.48
3.55
Low Voltage Monitor 5.0 V1, 4
Assert Level
De-assert Level
VLVI_VDDA_A
VLVI_VDDA_D
4.35
4.45
4.475
4.575
4.55
4.65
Low Voltage Monitor 5.0 V High Threshold1, 5
Assert Level
De-assert Level
VLVI_VDDA_HA
VLVI_VDDA_HD
4.50
4.50
4.675
4.675
4.80
4.80
V
V
1
Monitors VDDA.
Monitors VDD33.
3 Monitors V
DDSYN.
4 Disabled when V
RCSEL = VSSA.
2
4.9
Oscillators Electrical Characteristics
Table 14. 3.3 V High Frequency External Oscillator
Spec
Characteristic
Symbol
Min
Max
Unit
40
MHz
%
1
Frequency Range
fref
41
2
Duty Cycle of reference
tDC
40
60
3
EXTAL Input High Voltage
External crystal mode2
External clock mode
VIHEXT
VXTAL + 0.4
0.65  VDDSYN
VDDSYN + 0.3
VDDSYN + 0.3
EXTAL Input Low Voltage
External crystal mode3
External clock mode
VILEXT
VDDSYN – 0.3
VDDSYN – 0.3
VXTAL – 0.4
0.35  VDDSYN
IXTAL
1
3
mA
4
V
V
5
XTAL Current4
6
Total On-chip stray capacitance on XTAL
CS_XTAL
—
3
pF
7
Total On-chip stray capacitance on EXTAL
CS_EXTAL
—
3
pF
MPC5668x Microcontroller Data Sheet, Rev. 6
36
Freescale Semiconductor
Electrical Characteristics
Table 14. 3.3 V High Frequency External Oscillator (continued)
Spec
2
3
4
5
Symbol
Min
Max
Unit
CL
See crystal
specification
See crystal
specification
pF
8
Crystal manufacturer’s recommended
capacitive load
9
Discrete load capacitance to be connected
to EXTAL
CL_EXTAL
—
2CL – CS_EXTAL –
CPCB_EXTAL5
pF
10
Discrete load capacitance to be connected
to XTAL
CL_XTAL
—
2CL – CS_XTAL – C
pF
11
1
Characteristic
Startup Time
PCB_XTAL
tstartup
—
5
10
ms
When PLL frequency modulation is active, reference frequencies less than 8 MHz will distort the modulated waveform and the
effects of this on emissions is not characterized.
This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal
mode. In that case, Vextal – Vxtal  400 mV criteria has to be met for oscillator’s comparator to produce output clock.
This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal
mode. In that case, Vxtal – Vextal  400 mV criteria has to be met for oscillator’s comparator to produce output clock.
Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
Table 15. 5 V Low Frequency (32 kHz) External Oscillator
Spec
1
Characteristic
Symbol
Min
Max
Unit
1
Frequency Range
fref32
32
40
kHz
2
Duty Cycle of reference
tdc32
40
60
%
IXTAL32
—
3
A
CL32
See crystal
specification
See crystal
specification
pF
tStartup
—
2
s
Current1
3
XTAL32
4
Crystal manufacturer’s recommended
capacitive load
5
Startup Time
Ixtal32 is the oscillator bias current out of the XTAL32 pin with both EXTAL32 and XTAL32 pins grounded.
Table 16. 5 V High Frequency (16 MHz) Internal RC Oscillator
Spec
1
2
3
Characteristic
Frequency before trim1
Frequency after loading factory
Application trim
trim2
resolution3
4
Application frequency trim
5
Startup Time
step3
Symbol
Range
Min
Typ
Max
Unit
fut
35%
10.4
16
21.6
MHz
ft
7%
14.9
16
17.1
MHz
ts
—
—
—
05
%
fs
—
—
300
—
kHz
tStartup
—
—
—
500
ns
1
Across process, voltage, and temperature.
Across voltage and temperature.
3 Fixed voltage and temperature.
2
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
37
Electrical Characteristics
Table 17. 5V Low Frequency (128 kHz) Internal RC Oscillator
Spec
Characteristic
1
1
2
3
Frequency before trim
Frequency after loading factory
Application trim
trim2
resolution3
3
Symbol
Range
Min
Typ
Max
Unit
Fut128
35%
83.2
128
172.8
kHz
Ft128
7%
119.0
128
137.0
kHz
Ts128
—
—
—
2
%
4
Application frequency trim step
Fs128
—
—
4
—
kHz
5
Startup Time
St128
—
—
—
100
s
1
Across process, voltage, and temperature.
Across voltage and temperature.
3
Fixed voltage and temperature.
2
4.10
FMPLL Electrical Characteristics
Table 18. FMPLL Electrical Specifications1
Spec
1
Characteristic
Symbol
Min
Max
Unit
1
System Frequency2
fSYS
—
116
MHz
2
PLL Reference Frequency Range
fREF
4
40
MHz
3
PLL Frequency
fPLL
f vco  min 
---------------------------- ERFD + 1 
4
Loss of Reference Frequency 3
fLOR
100
2000
kHz
5
Self Clocked Mode Frequency
fSCM
16
64
MHz
6
PLL Lock Time4
tLPLL
—
400
s
7
Duty Cycle of Reference
tDC
40
60
%
8
Frequency un-LOCK Range
fUL
–4.0
4.0
% fSYS
9
Frequency LOCK Range
fLCK
–2.0
2.0
% fSYS
10
CLKOUT Period Jitter,5 Measured at fSYS Max
Cycle-to-cycle Jitter
CJitter
–5
5
%fSYS
11
CLKOUT Jitter at  50 µs period
CJitter
–250
250
ns
12
Peak-to-Peak Frequency Modulation Range Limit 6,7
(fSYSMax must not be exceeded)
Cmod
0
4
%fSYS
13
FM Depth Tolerance8
Cmod_err
–0.50
0.50
%fSYS
14
VCO Frequency9
fVCO
192
600
MHz
15
Modulation Rate Limits10
fMOD
0.400
1
MHz
MHz
VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH.
MPC5668x Microcontroller Data Sheet, Rev. 6
38
Freescale Semiconductor
Electrical Characteristics
2
The maximum frequency value is with frequency modulation disabled. If frequency modulation is enabled, the maximum
frequency value should be de-rated by the percentage of modulation enabled so that the maximum frequency is not exceeded.
3
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
4
This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal
startup time.
5
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter + Cmod.
6
Modulation depth selected must not result in fPLL value greater than the fPLL maximum specified value.
7
Maximum and minimum variations from programmed modulation depth are 2%, 3%, and 4% peak-to-peak. Use only these
settings.
8
Depth tolerance is the programmed modulation depth ±0.25% of fSYS.
9
See the Block Guide for VCO frequency synthesis equations.
10
Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than
1 MHz will result in reduced calibration accuracy.
4.11
ADC Electrical Characteristics
Table 19. ADC Conversion Specifications (Operating)
Spec
Characteristic
Min
Max
Unit
1
Analog High Reference Voltage
VRH
VDDA – 0.5
VDDA
V
2
Analog Low Reference Voltage
VRL
0
0.5
V
3
Analog Input Voltage
AVIN
VRL
VRH
V
4
Sampling Frequency
FS
—
1.53
MHz
5
Maximum ADC Clock Frequency
FMAX
—
60
MHz
6
Sampling Time
VDDA = 3.0 V – 3.6 V
VDDA > 3.6 V – 5.5 V
tS
—
ns
7
Differential Non Linearity
DNL
–1.0
1.0
LSB
8
Integral Non Linearity
INL
–1.5
1.5
LSB
9
Offset Error
OFS
–1.0
1.0
LSB
10
Gain Error
GNE
–2.0
2.0
LSB
TUE
–2.0
2.0
LSB
11
1
Symbol
Total Unadjusted Error
250
125
1
TUE assumes no pin activity on pins adjacent to analog channel or output driver activity on corresponding VDDE segment.
4.12
Flash Memory Electrical Characteristics
Table 20. Flash Program and Erase Specifications1
Spec
1
Symbol
Min
Initial
Max2
Max3
Unit
tdwprogram
—
—
500
s
tpprogram
—
160
500
s
Characteristic
Double Word (64 bits) Program Time4
Time4
2
Page (128 bits and 256 bits) Program
3
16 KB Block Pre-program and Erase Time
t16kpperase
—
1000
5000
ms
4
64 KB Block Pre-program and Erase Time
t64kpperase
—
1800
5000
ms
5
128 KB Block Pre-program and Erase Time
t128kpperase —
2600
7500
ms
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
39
Electrical Characteristics
Table 20. Flash Program and Erase Specifications1 (continued)
Spec
Characteristic
6
256 KB Block Pre-program and Erase Time
7
Frequency5
8
Symbol
Initial
Max2
Max3
Unit
5200
15,000
ms
—
—
—
—
—
—
—
—
30
60
90
fSYS max
—
—
45
Min
t256kpperase —
Wait States Relative to System
PFCRPn[RWSC] = PFCRPn[APC] = 0b000; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = PFCRPn[APC] = 0b001; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = PFCRPn[APC] = 0b010; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = PFCRPn[APC] = 0b011 – 0b111; PFCRPn[WWSC] = 0b01
trwsc
Recovery Time
tRecover
MHz
s
1
Typical program and erase times assume nominal supply values and operation at 25 oC.
Initial factory condition:  100program/erase cycles, nominal supply values and operation at 25 oC.
3
The maximum time is at worst case conditions after the specified number of program/erase cycles. This maximum value is
characterized but not guaranteed.
4 Actual hardware programming time. This does not include software overhead.
5 Wait state timing is based on the system clock frequency and thus is same for all masters.
2
Table 21. Flash EEPROM Module Life (Full Temperature Range)
Spec
Characteristic
Symbol
Min
Typical1
Unit
—
cycles
1
Number of Program/Erase cycles per block for 16 KB and 64 KB blocks
over the operating temperature range (TJ)
P/E
100,000
2
Number of Program/Erase cycles per block for 128 KB blocks over the
operating temperature range (TJ)
P/E
1,000
3
Minimum Data Retention at 85 °C ambient temperature2
Blocks with 0–1,000 P/E cycles
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
100,000 cycles
—
Retention
years
20
10
1–5
1
Typical endurance is evaluated at 25 oC. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance
for Nonvolatile Memory.
2 Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
4.13
Pad AC Specifications
Table 22. Pad AC Specifications (5.0 V, 2.5 V)1
Spec
Pad Type2
SRC/DSC3
00
1
Slow7
01
11
Output Delay4,4 (ns)
Rise/Fall5,6
(ns)
Load Drive
(pF)
318/343
155/173
50
408/431
188/204
200
61/67
30/34
50
80/90
38/44
200
18/18
10/11
50
27/28
15/17
200
MPC5668x Microcontroller Data Sheet, Rev. 6
40
Freescale Semiconductor
Electrical Characteristics
Table 22. Pad AC Specifications (5.0 V, 2.5 V)1 (continued)
Spec
Pad Type2
SRC/DSC3
Output Delay4,4 (ns)
00
2
01
Medium
11
Rise/Fall5,6
(ns)
142/186
65/89
50
195/253
91/122
200
20/35
8.7/16.6
50
41/64
24/35
200
12/11
5.3/5.9
50
32/34
21/23
200
00
3
10
01
Fast8
2.7
10
1.5
11
4
1
2
3
4
5
6
7
8
Input
Load Drive
(pF)
20
30
50
N/A
1.9/1.9
1.5/1.5
0.5
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 116 MHz, VDD = 1.08 – 1.32 V, VDDE = 1.62 – 1.98 V, VDDEH = 4.5 – 5.5 V, VRC33 and VDDPLL = 3.0 – 3.6 V, TA = TL to
TH.
Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2.
SRC/DSC are bit fields in the Pad Configuration Registers. SRC—Slew Rate Control (slow and medium pad types only),
DSC—Drive Strength Control (fast pad type only).
This parameter is supplied for reference and is not guaranteed by design and not tested.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
Add a maximum of one system clock to the output delay for delay with respect to system clock.
Output delay is shown in. Add a maximum of one system clock to the output delay for delay with respect to system clock.
Table 23. De-rated Pad AC Specifications (3.3 V, 3.3 V)1
Spec
Pad Type2
SRC/DSC3
Out Delay4,5
(ns)
Rise/Fall6,
(ns)
Load Drive
(pF)
408/431
188/204
50
533/592
250/288
200
80/90
38/44
50
146/167
82/96
200
27/28
15/17
50
81/92
57/67
200
184/240
79/107
50
253/330
114/153
200
28/47
11.8/21.8
50
58/88
34/49
200
18/17
7.6/8.9
50
46/51
30/35
200
00
1
Slow7
01
11
00
2
Medium
01
11
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
41
Electrical Characteristics
Table 23. De-rated Pad AC Specifications (3.3 V, 3.3 V)1 (continued)
Pad Type2
Spec
Rise/Fall6,
(ns)
Load Drive
(pF)
1.2
10
1.2
20
10
1.2
30
11
1.2
50
1.5/1.5
0.5
SRC/DSC3
Out Delay4,5
(ns)
00
4
1
2
3
4
5
6
7
8
01
Fast8
3
2.5
Input
N/A
3/3
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 116 MHz, VDD = 1.08 – 1.32 V, VDDE = 3.0 – 3.6 V, VDDEH = 3.0 – 3.6 V, VRC33 and VDDPLL = 3.0 – 3.6 V, TA = TL to
TH.
Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2.
SRC/DSC are bit fields in the Pad Configuration Registers. SRC—Slew Rate Control (slow and medium pad types only),
DSC—Drive Strength Control (fast pad type only).
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Add a maximum of one system clock to the output delay for delay with respect to system clock.
Output delay is shown in Figure 6. Add a maximum of one system clock to the output delay for delay with respect to system
clock.
VDD/2
Pad
Internal Data Input Signal
Rising
Edge
Out
Delay
Falling
Edge
Out
Delay
VOH
Pad
Output
VOL
Figure 6. Pad Output Delay
MPC5668x Microcontroller Data Sheet, Rev. 6
42
Freescale Semiconductor
Electrical Characteristics
4.14
AC Timing
4.14.1
Reset and Boot Configuration Pins
Table 24. Reset and Boot Configuration Timing
Spec
Characteristic
Symbol
Min
Max
Unit
1
RESET Pulse Width
tRPW
150
—
ns
2
BOOTCFG Setup Time after RESET Valid
tRCSU
—
100
s
3
BOOTCFG Hold Time from RESET Valid
tRCH
0
—
s
RESET
1
2
BOOTCFG
3
Figure 7. Reset and Boot Configuration Timing
4.14.2
External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Pins
Table 25. IRQ/NMI Timing
Spec
Symbol
Min
Max
Unit
1
IRQ/NMI Pulse Width Low
tIPWL
3
—
tSYS
2
IRQ/NMI Pulse Width High
TIPWH
3
—
tSYS
tICYC
6
—
tSYS
3
1
Characteristic
IRQ/NMI Edge to Edge
Time1
Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
IRQ/NMI
1,2
1,2
3
Figure 8. IRQ and NMI Timing
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
43
Electrical Characteristics
4.14.3
JTAG (IEEE 1149.1) Interface
Table 26. JTAG Interface Timing1
Spec
1
Characteristic
Symbol
Min
Max
Unit
1
TCK Cycle Time
tJCYC
100
—
ns
2
TCK Clock Pulse Width (Measured at VDDE/2)
tJDC
40
60
ns
3
TCK Rise and Fall Times (40% – 70%)
tTCKRISE
—
3
ns
4
TMS, TDI Data Setup Time
tTMSS, tTDIS
5
—
ns
5
TMS, TDI Data Hold Time
tTMSH, tTDIH
25
—
ns
6
TCK Low to TDO Data Valid
tTDOV
—
25
ns
7
TCK Low to TDO Data Invalid
tTDOI
0
—
ns
8
TCK Low to TDO High Impedance
tTDOHZ
—
20
ns
9
JCOMP Assertion Time
tJCMPPW
100
—
ns
10
JCOMP Setup Time to TCK Low
tJCMPS
40
—
ns
11
TCK Falling Edge to Output Valid
tBSDV
—
50
ns
12
TCK Falling Edge to Output Valid out of High Impedance
tBSDVZ
—
50
ns
13
TCK Falling Edge to Output High Impedance
tBSDHZ
—
50
ns
14
Boundary Scan Input Valid to TCK Rising Edge
tBSDST
50
—
ns
15
TCK Rising Edge to Boundary Scan Input Invalid
tBSDHT
50
—
ns
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDDE = 3.0 – 5.5 V, TA = TL to TH, and
CL = 30 pF with SRC = 0b11.
TCK
2
3
2
1
3
Figure 9. JTAG Test Clock Input Timing
MPC5668x Microcontroller Data Sheet, Rev. 6
44
Freescale Semiconductor
Electrical Characteristics
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 10. JTAG Test Access Port Timing
TCK
10
JCOMP
9
Figure 11. JTAG JCOMP Timing
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
45
Electrical Characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 12. JTAG Boundary Scan Timing
MPC5668x Microcontroller Data Sheet, Rev. 6
46
Freescale Semiconductor
Electrical Characteristics
4.14.4
Nexus Debug Interface
Table 27. Nexus Debug Port Timing1
Spec
Characteristic
1
MCKO Cycle Time
2
MCKO Duty Cycle
2
Symbol
Min
Max
Unit
tMCYC
15.6
—
ns
tMDC
40
60
%
tMDOV
–0.1
0.25
tMCYC
—
tTCYC
3
MCKO Low to MDO, MSEO, EVTO Data Valid
4
EVTI Pulse Width
tEVTIPW
4.0
5
EVTO Pulse Width
tEVTOPW
1
tTCYC
40
—
ns
tTDC
40
60
%
3
tMCYC
6
TCK Cycle Time
7
TCK Duty Cycle
8
TDI, TMS Data Setup Time
tNTDIS, tNTMSS
8
—
ns
9
TDI, TMS Data Hold Time
tNTDIH, tNTMSH
5
—
ns
10
TCK Low to TDO Data Valid
tJOV
0
25
ns
1
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from
50% of MCKO and 50% of the respective signal. Nexus timing specified at VDDE = 3.0 – 5.5 V, TA = TL to TH, and CL = 30 pF
with SRC = 0b11.
2
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
3 The system clock frequency needs to be three times faster than the TCK frequency.
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
EVTI
4
Figure 13. Nexus Output Timing
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
47
Electrical Characteristics
6
7
TCK
8
9
TMS, TDI
10
TDO
Figure 14. Nexus TDI, TMS, TDO Timing
MPC5668x Microcontroller Data Sheet, Rev. 6
48
Freescale Semiconductor
Electrical Characteristics
4.14.5
Enhanced Modular I/O Subsystem (eMIOS)
Table 28. eMIOS Timing1
Spec
1
2
Characteristic
Symbol
Min
Max
Unit
1
eMIOS Input Pulse Width
tMIPW
4
—
tCYC
2
eMIOS Output Pulse Width
tMOPW
12
—
tCYC
eMIOS timing specified at VDDE = 3.0 – 5.5 V, TA = TL to TH, and CL = 30 pF with SRC = 0b11.
This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
Figure 15. eMIOS Timing
D_CLKOUT
2
eMIOS output
eMIOS input
1
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
49
Electrical Characteristics
4.14.6
Deserial Serial Peripheral Interface (DSPI)
Table 29. DSPI Timing
116 MHz1
Spec
1
Characteristic
Symbol
Unit
Min. Value
Max. Value
100
100
50
50
—
—
—
—
ns
ns
ns
ns
DSPI Cycle Time
Master (MTFE = 0)
Slave (MTFE = 0)
Master (MTFE = 1)
Slave (MTFE = 1)
tSCK
2
PCS to SCK Delay2
tCSC
7
—
ns
3
After SCK Delay3
tASC
14
—
ns
4
SCK Duty Cycle
tSDC
0.4  tSCK
0.6  tSCK
ns
5
Slave Access Time
(SS active to SOUT valid)
tA
—
25
ns
6
Slave SOUT Disable Time
(SS inactive to SOUT High-Z or invalid)
tDIS
—
25
ns
7
PCSx to PCSS time
tPCSC
0
—
ns
8
PCSS to PCSx time
tPASC
0
—
ns
9
Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)4
Master (MTFE = 1, CPHA = 1)
tSUI
25
5
10
25
—
—
—
—
ns
ns
ns
ns
Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)4
Master (MTFE = 1, CPHA = 1)
tHI
–4
7
12
–4
—
—
—
—
ns
ns
ns
ns
Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tSUO
—
—
—
—
8
28
15
8
ns
ns
ns
ns
Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO
–7
2
1
–7
—
—
—
—
ns
ns
ns
ns
10
11
12
1
116 MHz timing specified at CL = 50 pF with SRC = 0b11.
The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
3 The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
4 This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
2
MPC5668x Microcontroller Data Sheet, Rev. 6
50
Freescale Semiconductor
Electrical Characteristics
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Figure 16. DSPI Classic SPI Timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
SIN
Data
First Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Figure 17. DSPI Classic SPI Timing — Master, CPHA = 1
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
51
Electrical Characteristics
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
First Data
SOUT
9
6
Data
Last Data
Data
Last Data
10
First Data
SIN
11
12
Figure 18. DSPI Classic SPI Timing — Slave, CPHA = 0
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Figure 19. DSPI Classic SPI Timing — Slave, CPHA = 1
MPC5668x Microcontroller Data Sheet, Rev. 6
52
Freescale Semiconductor
Electrical Characteristics
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
11
First Data
Last Data
Data
Figure 20. DSPI Modified Transfer Format Timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Data
Last Data
11
Last Data
Figure 21. DSPI Modified Transfer Format Timing — Master, CPHA = 1
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
53
Electrical Characteristics
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
12
11
5
First Data
SOUT
Data
Last Data
10
9
Data
First Data
SIN
6
Last Data
Figure 22. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Figure 23. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
7
8
PCSS
PCSx
Figure 24. DSPI PCS Strobe (PCSS) Timing
MPC5668x Microcontroller Data Sheet, Rev. 6
54
Freescale Semiconductor
Electrical Characteristics
4.14.7
4.14.7.1
MLB Interface
Media Local Bus DC Electrical Characteristics
Table 30 provides the DC electrical characteristics for the Media Local Bus interface.
Table 30. Media Local Bus DC Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Maximum Input Voltage
—
—
—
3.6
V
Low Level Input Threshold
VIL
—
—
0.7
V
1
Comments
High Level Input Threshold
VIH
1.8
—
—
V
Low Level Output Threshold
VOL
—
—
0.4
V
IOL = 6 mA
High Level Output Threshold
VOH
2.0
—
—
V
IOH = –6 mA
IL
—
—
±1
µA
0 < Vin < VDDE4
Input Leakage Current
1
Higher VIH thresholds can be used; however, the risks associated with less noise margin in the system must be evaluated and
assumed by the customer.
4.14.7.2
Media Local Bus (MLB) AC Electrical Characteristics
Table 31 and Table 32 provide the AC electrical characteristics for the Media Local Bus interface.
Table 31. MLB Timing for MLB Speed 256 Fs or 512 Fs
Spec
Parameter
1
Symbol
Min
Typ
Max
fmck
11.264
—
—
—
—
12.288
24.576
—
—
—
—
—
24.6272
25.600
Unit
Comments
1
MLBCLK Operating Frequency
2
MLBCLK rise time
tmckr
—
—
3
ns
VIL to VIH
3
MLBCLK fall time
tmckf
—
—
3
ns
VIH to VIL
4
MLBCLK cycle time
tmckc
—
81
40
—
ns
256 Fs
512 Fs
5
MLBCLK low time
tmckl
31.5
30
37
35.5
—
ns
256 Fs
256 Fs PLL unlocked
14.5
14
17
16.5
—
ns
512 Fs
512 Fs PLL unlocked
31.5
30
38
36.5
—
ns
256xFs
256 Fs PLL unlocked
14.5
14
17
16.5
—
ns
512 Fs
512 Fs PLL unlocked
6
MLBCLK high time
tmckh
256 Fs at 44.0 kHz
256 Fs at 48.0 kHz
MHz 512 Fs at 48.0 kHz
512 Fs at 48.1 kHz
512 Fs PLL unlocked
7
MLBCLK pulse width variation2
tmpwv
—
—
2
ns p-p
8
MLBSIG/MLBDAT input valid to
MLBCLK falling
tdsmcf
1
—
—
ns
9
MLBSIG/MLBDAT input hold from
MLBCLK low
tdhmcf
0
—
—
ns
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
55
Electrical Characteristics
Table 31. MLB Timing for MLB Speed 256 Fs or 512 Fs (continued)
Spec
Parameter
Symbol
Min
Typ
Max
Unit
10
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0
—
tmckl
ns
11
Bus Hold time3
tmdzh
4
—
—
ns
12
MLBSIG/MLBDAT output valid from
MLBCLK rising
tmcrdv
—
—
8
ns
Comments
• Ground = 0.0V
• Load Capacitance = 60 pF, SIU_PCR144–SIU_PCR146[DSC] = 0b11.
• MLB speed of 256 Fs or 512 Fs (Fs = 48 kHz)
Unless otherwise noted, all timing parameters are specified from the valid voltage threshold in Table 30.
1
The Controller can shut off MLBCLK to place MLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (ns p-p).
3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
2
Table 32. MLB Timing for MLB Speed 1024 Fs
Spec
•
•
•
•
Parameter
Symbol
Min
Typ
Max
Unit
Comments
1
MLBCLK Operating Frequency1
fmck
45.056
—
—
—
—
49.152
—
—
—
—
49.2544
51.200
2
MLBCLK rise time
tmckr
—
—
1
ns
VIL to VIH
3
MLBCLK fall time
tmckf
—
—
1
ns
VIH to VIL
4
MLBCLK cycle time
tmckc
—
20.3
—
ns
VIL to VIH
5
MLBCLK low time
tmckl
6.5
6.1
7.7
7.3
—
ns
1024 Fs
PLL unlocked
6
MLBCLK high time
tmckh
9.7
9.3
10.6
10.2
—
ns
1024 Fs
PLL unclocked
7
MLBCLK pulse width variation2
tmpwv
—
—
0.7
ns p-p
8
MLBSIG/MLBDAT input valid to
MLBCLK falling
tdsmcf
1
—
—
ns
9
MLBSIG/MLBDAT input hold from
MLBCLK low
tdhmcf
0
—
—
ns
10
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0
—
tmckl
ns
11
Bus Hold time3
tmdzh
2
—
—
ns
12
MLBSIG/MLBDAT output valid from
MLBCLK rising
tmcrdv
—
—
7
ns
1024 Fs at 44.0 kHz
1024 Fs at 48.0 kHz
MHz 1024 Fs at 48.1 kHz
1024 Fs PLL unlocked
Ground = 0.0V
Load Capacitance = 40 pF, SIU_PCR144–SIU_PCR146[DSC] = 0b00.
MLB speed = 1024Fs (Fs = 48 kHz)
Unless otherwise noted, timing parameters are specified from the valid voltage threshold in Table 30.
MPC5668x Microcontroller Data Sheet, Rev. 6
56
Freescale Semiconductor
Electrical Characteristics
1
The Controller can shut off MLBCLK to place MLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (ns p-p).
3
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
2
MLBSIG/
MLBDAT
(input)
valid data
9
8
3
6
2
5
MLBCLK
4
10
12
MLBSIG/
MLBDAT
(output)
11
valid data
Figure 25. Media Local Bus (MLB) Timing
4.14.8
Fast Ethernet Interface
MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible.
They follow the CMOS electrical characteristics.
4.14.8.1
MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency.
Table 33. MII Receive Signal Timing
Spec
Characteristic
Min
Max
Unit
M1
RXD[3:0], RX_DV, RX_ER to RX_CLK setup
5
—
ns
M2
RX_CLK to RXD[3:0], RX_DV, RX_ER hold
5
—
ns
M3
RX_CLK pulse width high
35%
65%
RX_CLK period
M4
RX_CLK pulse width low
35%
65%
RX_CLK period
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
57
Electrical Characteristics
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
M2
Figure 26. MII Receive Signal Timing Diagram
4.14.8.2
MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Table 34. MII Transmit Signal Timing1
Spec
1
Characteristic
Min
Max
Unit
M5
TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
5
—
ns
M6
TX_CLK to TXD[3:0], TX_EN, TX_ER valid
—
25
ns
M7
TX_CLK pulse width high
35%
65%
TX_CLK period
M8
TX_CLK pulse width low
35%
65%
TX_CLK period
Output pads configured with SRC = 0b11.
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
Figure 27. MII Transmit Signal Timing Diagram
MPC5668x Microcontroller Data Sheet, Rev. 6
58
Freescale Semiconductor
Electrical Characteristics
4.14.8.3
MII Async Inputs Signal Timing (CRS and COL)
Table 35. MII Async Inputs Signal Timing1
Spec
M9
1
Characteristic
CRS, COL minimum pulse width
Min
Max
Unit
1.5
—
TX_CLK period
Output pads configured with SRC = 0b11.
CRS, COL
M9
Figure 28. MII Async Inputs Timing Diagram
4.14.8.4
MII Serial Management Channel Timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 36. MII Serial Management Channel Timing1
Spec
1
Characteristic
Min
Max
Unit
M10
MDC falling edge to MDIO output invalid (minimum propagation delay)
0
—
ns
M11
MDC falling edge to MDIO output valid (max prop delay)
—
25
ns
M12
MDIO (input) to MDC rising edge setup
10
—
ns
M13
MDIO (input) to MDC rising edge hold
0
—
ns
M14
MDC pulse width high
40%
60%
MDC period
M15
MDC pulse width low
40%
60%
MDC period
Output pads configured with SRC = 0b11.
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
59
Electrical Characteristics
M14
M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
Figure 29. MII Serial Management Channel Timing Diagram
MPC5668x Microcontroller Data Sheet, Rev. 6
60
Freescale Semiconductor
Package Characteristics
5
Package Characteristics
5.1
Package Mechanical Data
Figure 30. 208 MAPBGA Package Mechanical Drawing
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
61
Package Characteristics
Figure 31. 208 MAPBGA Package Detail
MPC5668x Microcontroller Data Sheet, Rev. 6
62
Freescale Semiconductor
Package Characteristics
Figure 32. 256 MAPBGA Package Mechanical Drawing
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
63
Package Characteristics
Figure 33. 256 MAPBGA Package Detail
MPC5668x Microcontroller Data Sheet, Rev. 6
64
Freescale Semiconductor
Revision History
6
Revision History
Table 37 describes the changes made to this document between revisions.
Table 37. Revision History
Revision
Date
0
April 2008
Preliminary release.
1
June 2008
Initial release: Advance Information.
2
Jan 2009
Release: Advance Information.
3
Description
September 2009 Release: Advance Information, interim updates.
4
January 2011
Release: Technical Data, interim updates.
5
January 2011
Release: Technical Data, interim updates.
6
March 2011
Release: Technical Data, interim updates.
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
65
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Document Number: MPC5668X
Rev. 6
2010, 2011
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