Data Sheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCIMX35SR2CEC
Rev. 10, 06/2012
IMX35
i.MX35 Applications
Processors for
Industrial and
Consumer Products
1
Introduction
The i.MX353 and the i.MX357 multimedia applications
processors represent the next generation of ARM11
products with the right performance and integration to
address applications within the industrial and consumer
markets for applications such as HMI and display
controllers. Unless otherwise specified, the material in
this data sheet is applicable to both the i.MX353 and
i.MX357 devices and referred to singularly throughout
this document as i.MX35 or MCIMX35. The i.MX353
devices do not include a graphics processing unit
(GPU). For information on i.MX35 devices for
automotive applications, please refer to document
number, MCIMX35SR2AEC.
The i.MX35 processor takes advantage of the
ARM1136JF-S™ core running at 532 MHz that is
boosted by a multi-level cache system and integrated
features such as LCD controller, Ethernet, and graphics
acceleration for creating rich user interfaces.
The i.MX35 supports connections to various types of
external memories, such as SDRAM, mobile DDR, and
DDR2, SLC and MCL NAND Flash, NOR Flash and
© Freescale Semiconductor, Inc., 2010. All rights reserved.
Package Information
Plastic Package
Case 5284 17 x 17 mm, 0.8 mm Pitch
Ordering Information
See Table 1 on page 3 for ordering information.
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Functional Description and Application Information. . . . . . 4
2.1. Application Processor Domain Overview . . . . . . . . . 5
2.2. Shared Domain Overview . . . . . . . . . . . . . . . . . . . . 6
2.3. Advanced Power Management Overview . . . . . . . . 6
2.4. ARM11 Microprocessor Core. . . . . . . . . . . . . . . . . . 6
2.5. Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Signal Descriptions: Special Function Related Pins . . . . 12
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1. i.MX35 Chip-Level Conditions . . . . . . . . . . . . . . . . 12
4.2. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . 18
4.6. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . 19
4.7. I/O Pin DC Electrical Characteristics . . . . . . . . . . . 20
4.8. I/O Pin AC Electrical Characteristics . . . . . . . . . . . 23
4.9. Module-Level AC Electrical Specifications . . . . . . . 29
5. Package Information and Pinout . . . . . . . . . . . . . . . . . . 130
5.1. MAPBGA Production Package 1568-01, 17 × 17 mm,
0.8 Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.2. MAPBGA Signal Assignments . . . . . . . . . . . . . . . 132
6. Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . 144
7. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SRAM. The devices can be connected to a variety of external devices such as USB 2.0 OTG, ATA,
MMC/SDIO, and Compact Flash.
1.1
Features
It provides low-power solutions for applications demanding high-performance multimedia and graphics.
The i.MX35 is based on the ARM1136 platform, which has the following features:
• ARM1136JF-S processor, version r1p3
• 16-Kbyte L1 instruction cache
• 16-Kbyte L1 data cache
• 128-Kbyte L2 cache, version r0p4
• 128 Kbytes of internal SRAM
• Vector floating point unit (VFP11)
To boost multimedia performance, the following hardware accelerators are integrated:
• Image processing unit (IPU)
• OpenVG 1.1 graphics processing unit (GPU) (not available for the MCIMX351)
The MCIMX35 provides the following interfaces to external devices (some of these interfaces are muxed
and not available simultaneously):
• 2 controller area network (CAN) interfaces
• 2 SDIO/MMC interfaces, 1 SDIO/CE-ATA interface (CE-ATA is not available for the MCIMX351)
• 32-bit mobile DDR, DDR2 (4-bank architecture), and SDRAM (up to 133 MHz)
• 2 configurable serial peripheral interfaces (CSPI) (up to 52 Mbps each)
• Enhanced serial audio interface (ESAI)
• 2 synchronous serial interfaces (SSI)
• Ethernet MAC 10/100 Mbps
• 1 USB 2.0 host with ULPI interface or internal full-speed PHY. Up to 480 Mbps if external HS
PHY is used.
• 1 USB 2.0 OTG (up to 480 Mbps) controller with internal high-speed OTG PHY
• Flash controller—MLC/SLC NAND and NOR
• GPIO with interrupt capabilities
• 3 I2C modules (up to 400 Kbytes each)
• JTAG
• Key pin port
• Asynchronous sample rate converter (ASRC)
• 1-Wire
• Parallel camera sensor (4/8/10/16-bit data port for video color models: YCC, YUV, 30 Mpixels/s)
• Parallel display (primary up to 24-bit, 1024 x 1024)
• Parallel ATA (up to 66 Mbytes) (not available for the MCIMX351)
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•
•
•
PWM
SPDIF transceiver
3 UART (up to 4.0 Mbps each)
1.2
Ordering Information
Table 1 provides the ordering information for the i.MX35 processors for consumer and industrial
applications.
Table 1. Ordering Information
1
Description
Part Number
Silicon
Revision
Package1
Speed
Operating
Temperature
Range (°C)
Signal Ball
Map
Locations
Ball Map
i.MX353
MCIMX353CVM5B
2.0
5284
532 MHz
–40 to 85
Table 94
Table 96
i.MX353
MCIMX353DVM5B
2.0
5284
532 MHz
–20 to 70
Table 94
Table 96
i.MX357
MCIMX357CVM5B
2.0
5284
532 MHz
–40 to 85
Table 94
Table 96
i.MX357
MCIMX357DVM5B
2.0
5284
532 MHz
–20 to 70
Table 94
Table 96
i.MX353
MCIMX353CJQ5C
2.1
5284
532MHz
-40 to 85
Table 95
Table 97
i.MX353
MCIMX353DJQ5C
2.1
5284
532MHz
-20 to 70
Table 95
Table 97
i.MX357
MCIMX357CJQ5C
2.1
5284
532MHz
-40 to 85
Table 95
Table 97
i.MX357
MCIMX357DJQ5C
2.1
5284
532MHz
-20 to 70
Table 95
Table 97
Case 5284 is RoHS-compliant, lead-free, MSL = 3, 1.
The ball map for silicon revision 2.1 is different than the ballmap for silicon revision 2.0. The layout for
each revision is not compatible, so it is important that the correct ballmap be used to implement the layout.
See Section 5, “Package Information and Pinout.”
Table 2 shows the functional differences between the different parts in the i.MX35 family.
Table 2. Functional Differences in the i.MX35 Parts
Module
MCIMX351
MCIMX353
MCIMX355
MCIMX356
MCIMX357
I2C (3)
Yes
Yes
Yes
Yes
Yes
CSPI (2)
Yes
Yes
Yes
Yes
Yes
SSI/I2S (2)
Yes
Yes
Yes
Yes
Yes
ESAI
Yes
Yes
Yes
Yes
Yes
SPDIF I/O
Yes
Yes
Yes
Yes
Yes
USB HS Host
Yes
Yes
Yes
Yes
Yes
USB OTG
Yes
Yes
Yes
Yes
Yes
FlexCAN (2)
Yes
Yes
Yes
Yes
Yes
MLB
Yes
Yes
Yes
Yes
Yes
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Table 2. Functional Differences in the i.MX35 Parts (continued)
Module
MCIMX351
MCIMX353
MCIMX355
MCIMX356
MCIMX357
Ethernet
Yes
Yes
Yes
Yes
Yes
1-Wire
Yes
Yes
Yes
Yes
Yes
KPP
Yes
Yes
Yes
Yes
Yes
SDIO/MMC (2)
Yes
Yes
Yes
Yes
Yes
SDIO/Memory Stick
Yes
Yes
Yes
Yes
Yes
External Memory Controller (EMC)
Yes
Yes
Yes
Yes
Yes
JTAG
Yes
Yes
Yes
Yes
Yes
PATA
—
Yes
Yes
Yes
Yes
CE-ATA
—
Yes
Yes
Yes
Yes
Image Processing Unit (IPU) (inversion
and rotation, pre- and post-processing,
camera interface, blending, display
controller)
—
Yes
Yes
Yes
Yes
Open VG graphics acceleration (GPU)
—
Yes
—
Yes
Yes
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1.3
Block Diagram
Figure 1 is the i.MX35 simplified interface block diagram.
NOR
Flash/
PSRAM
DDR2/SDDR
RAM
NAND
Flash
Camera
Sensor
External Memory
Interface (EMI)
Smart
DMA
Image
Processing Unit
(IPU)
ARM11
Platform
ARM1136JF-S
SPBA
LCD Display 1 External Graphics
Accelerator
LCD Display 2
VFP
ARM1136 Platform Peripherals
SSI
HS USBOTG
HS USBOTGPHY
AUDMUX
HS USBHost
FS USBPHY
L1 I/D cache
Peripherals
ESAI
MSHC
SPDIF
SSI
ASRC
L2 cache
I2C(3)
AVIC
UART(2)
MAX
CSPI
AIPS (2)
ATA
eSDHC(3)
ETM
CAN(2)
UART
CSPI
GPU 2D
Internal
Memory
FEC
ECT
IOMUX
IIM
RTICv3
GPIO(3)
RNGC
EPIT
SCC
PWM
Timers
RTC
WDOG
OWIRE
GPT
KPP
3 FuseBox
Audio/Power
Management
JTAG
Bluetooth
MMC/SDIO
or WLAN
Keypin
Connectivity
Access
Figure 1. i.MX35 Simplified Interface Block Diagram
2
Functional Description and Application Information
The i.MX35 consists of the following major subsystems:
• ARM1136 Platform—AP domain
• SDMA Platform and EMI—Shared domain
2.1
Application Processor Domain Overview
The applications processor (AP) and its domain are responsible for running the operating system and
applications software, providing the user interface, and supplying access to integrated and external
peripherals. The AP domain is built around an ARM1136JF-S core with 16-Kbyte instruction and data L1
caches, an MMU, a 128-Kbyte L2 cache, a multiported crossbar switch, and advanced debug and trace
interfaces.
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The i.MX35 core is intended to operate at a maximum frequency of 532 MHz to support the required
multimedia use cases. Furthermore, an image processing unit (IPU) is integrated into the AP domain to
offload the ARM11 core from performing functions such as color space conversion, image rotation and
scaling, graphics overlay, and pre- and post-processing.
The functionality of AP Domain peripherals includes the user interface; the connectivity, display, security,
and memory interfaces; and 128 Kbytes of multipurpose SRAM.
2.2
Shared Domain Overview
The shared domain is composed of the shared peripherals, a smart DMA engine (SDMA) and a number of
miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the SDMA
engine.
The i.MX35 has a hierarchical memory architecture including L1 caches and a unified L2 cache. This
reduces the bandwidth demands for the external bus and external memory. The external memory
subsystem supports a flexible external memory system, including support for SDRAM (SDR, DDR2 and
mobile DDR) and NAND Flash.
2.3
Advanced Power Management Overview
To address the continuing need to reduce power consumption, the following techniques are incorporated
in the i.MX35:
• Clock gating
• Power gating
• Power-optimized synthesis
• Well biasing
The insertion of gating into the clock paths allows unused portions of the chip to be disabled. Because
static CMOS logic consumes only leakage power, significant power savings can be realized.
“Well biasing” is applying a voltage that is greater than VDD to the nwells, and one that is lower than VSS
to the pwells. The effect of applying this well back bias voltage reduces the subthreshold channel leakage.
For the 90-nm digital process, it is estimated that the subthreshold leakage is reduced by a factor of ten
over the nominal leakage. Additionally, the supply voltage for internal logic can be reduced from 1.4 V to
1.22 V.
2.4
ARM11 Microprocessor Core
The CPU of the i.MX35 is the ARM1136JF-S core, based on the ARM v6 architecture. This core supports
the ARM Thumb® instruction sets, features Jazelle® technology (which enables direct execution of Java
byte codes) and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit
registers.
The ARM1136JF-S processor core features are as follows:
• Integer unit with integral EmbeddedICE™ logic
• Eight-stage pipeline
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•
•
•
•
•
•
•
•
•
•
Branch prediction with return stack
Low-interrupt latency
Instruction and data memory management units (MMUs), managed using micro TLB structures
backed by a unified main TLB
Instruction and data L1 caches, including a non-blocking data cache with hit-under-miss
Virtually indexed/physically addressed L1 caches
64-bit interface to both L1 caches
Write buffer (bypassable)
High-speed Advanced Micro Bus Architecture (AMBA)™ L2 interface
Vector floating point co-processor (VFP) for 3D graphics and hardware acceleration of other
floating-point applications
ETM™ and JTAG-based debug support
Table 3 summarizes information about the i.MX35 core.
Table 3. i.MX35 Core
Core
Acronym
ARM11 or
ARM1136
2.5
Core
Name
ARM1136
Platform
Brief Description
Integrated Memory
Features
The ARM1136™ platform consists of the ARM1136JF-S core, the ETM
real-time debug modules, a 6 × 5 multi-layer AHB crossbar switch (MAX), and
a vector floating processor (VFP).
The i.MX35 provides a high-performance ARM11 microprocessor core and
highly integrated system functions. The ARM Application Processor (AP) and
other subsystems address the needs of the personal, wireless, and portable
product market with integrated peripherals, advanced processor core, and
power management capabilities.
• 16-Kbyte
instruction cache
• 16-Kbyte data
cache
• 128-Kbyte L2
cache
• 32-Kbyte ROM
• 128-Kbyte RAM
Module Inventory
Table 4 shows an alphabetical listing of the modules in the MCIMX35. For extended descriptions of the
modules, see the MCIMX35 reference manual.
Table 4. Digital and Analog Modules
Block
Mnemonic
1-WIRE
ASRC
Block Name
Domain1
Subsystem
Brief Description
1-Wire
interface
ARM
ARM1136
platform
peripherals
1-Wire provides the communication line to a 1-Kbit add-only
memory. the interface can send or receive 1 bit at a time.
Asynchronous
sample rate
converter
SDMA
Connectivity
peripherals
The ASRC is designed to convert the sampling rate of a signal
associated to an input clock into a signal associated to a different
output clock. It supports a concurrent sample rate conversion of
about –120 dB THD+N. The sample rate conversion of each
channel is associated to a pair of incoming and outgoing sampling
rates.
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Table 4. Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Domain1
Subsystem
Brief Description
ATA
ATA module
SDMA
Connectivity
peripherals
The ATA block is an AT attachment host interface. Its main use is to
interface with IDE hard disk drives and ATAPI optical disk drives. It
interfaces with the ATA device over a number of ATA signals.
AUDMUX
Digital audio
mux
ARM
Multimedia
peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (SSIs) and
peripheral serial interfaces (audio codecs). The AUDMUX has two
sets of interfaces: internal ports to on-chip peripherals and external
ports to off-chip audio devices. Data is routed by configuring the
appropriate internal and external ports.
CAN(2)
CAN module
ARM
Connectivity
peripherals
The CAN protocol is primarily designed to be used as a vehicle
serial data bus running at 1 Mbps.
CCM
Clock control
module
ARM
Clocks
This block generates all clocks for the peripherals in the SDMA
platform. The CCM also manages ARM1136 platform low-power
modes (WAIT, STOP), disabling peripheral clocks appropriately for
power conservation, and provides alternate clock sources for the
ARM1136 and SDMA platforms.
CSPI(2)
Configurable
serial
peripheral
interface
SDMA,
ARM
Connectivity
peripherals
This module is a serial interface equipped with data FIFOs; each
master/slave-configurable SPI module is capable of interfacing to
both serial port interface master and slave devices. The CSPI ready
(SPI_RDY) and slave select (SS) control signals enable fast data
communication with fewer software interrupts.
ECT
Embedded
cross trigger
SDMA,
ARM
Debug
ECT (embedded cross trigger) is an IP for real-time debug
purposes. It is a programmable matrix allowing several subsystems
to interact with each other. ECT receives signals required for
debugging purposes (from cores, peripherals, buses, external
inputs, and so on) and propagates them (propagation programmed
through software) to the different debug resources available within
the SoC.
EMI
External
memory
interface
SDMA
External
memory
interface
The EMI module provides access to external memory for the ARM
and other masters. It is composed of the following main
submodules:
M3IF—provides arbitration between multiple masters requesting
access to the external memory.
SDRAM CTRL—interfaces to mDDR, DDR2 (4-bank architecture
type), and SDR interfaces.
NANDFC—provides an interface to NAND Flash memories.
WEIM—interfaces to NOR Flash and PSRAM.
Enhanced
periodic
interrupt timer
ARM
Timer
peripherals
Each EPIT is a 32-bit “set-and-forget” timer that starts counting after
the EPIT is enabled by software. It is capable of providing precise
interrupts at regular intervals with minimal processor intervention. It
has a 12-bit prescaler to adjust the input clock frequency to the
required time setting for the interrupts, and the counter value can be
programmed on the fly.
EPIT(2)
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Table 4. Digital and Analog Modules (continued)
Block
Mnemonic
ESAI
eSDHCv2
(3)
FEC
GPIO(3)
Block Name
Domain1
Subsystem
Brief Description
Enhanced
serial audio
interface
SDMA
Connectivity
peripherals
The enhanced serial audio interface (ESAI) provides a full-duplex
serial port for serial communication with a variety of serial devices,
including industry-standard codecs, SPDIF transceivers, and other
DSPs. The ESAI consists of independent transmitter and receiver
sections, each section with its own clock generator.
Enhanced
secure digital
host controller
ARM
Connectivity
peripherals
The eSDHCv2 consists of four main modules: CE-ATA, MMC, SD
and SDIO. CE-ATA is a hard drive interface that is optimized for
embedded applications of storage. The MultiMediaCard (MMC) is a
universal, low-cost, data storage and communication media to
applications such as electronic toys, organizers, PDAs, and smart
phones. The secure digital (SD) card is an evolution of MMC and is
specifically designed to meet the security, capacity, performance,
and environment requirements inherent in emerging audio and
video consumer electronic devices. SD cards are categorized into
Memory and I/O. A memory card enables a copyright protection
mechanism that complies with the SDMI security standard. SDIO
cards provide high-speed data I/O (such as wireless LAN via SDIO
interface) with low power consumption.
Note: CE-ATA is not available for the MCIMX351.
Ethernet
SDMA
Connectivity
peripherals
The Ethernet media access controller (MAC) is designed to support
both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to
complete the interface to the media
General
purpose I/O
modules
ARM
Pins
Used for general purpose input/output to external ICs. Each GPIO
module supports 32 bits of I/O.
GPT
General
ARM
purpose timers
Timer
peripherals
Each GPT is a 32-bit free-running or set-and-forget mode timer with
a programmable prescaler and compare and capture registers. A
timer counter value can be captured using an external event and can
be configured to trigger a capture event on either the leading or
trailing edges of an input pulse. When the timer is configured to
operate in set-and-forget mode, it is capable of providing precise
interrupts at regular intervals with minimal processor intervention.
The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either
on an external clock or on an internal clock.
GPU2D
Graphics
ARM
processing unit
2Dv1
Multimedia
peripherals
This module accelerates OpenVG and GDI graphics.
Note: Not available for the MCIMX351.
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Table 4. Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Domain1
Subsystem
Brief Description
I2C(3)
I2C module
ARM
ARM1136
platform
peripherals
Inter-integrated circuit (I2C) is an industry-standard, bidirectional
serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. I2C is suitable for
applications requiring occasional communications over a short
distance among many devices. The interface operates at up to
100 kbps with maximum bus loading and timing. The I2C system is
a true multiple-master bus, with arbitration and collision detection
that prevent data corruption if multiple devices attempt to control the
bus simultaneously. This feature supports complex applications with
multiprocessor control and can be used for rapid testing and
alignment of end products through external connections to an
assembly-line computer.
IIM
IC
identification
module
ARM
Security
modules
The IIM provides the primary user-visible mechanism for interfacing
with on-chip fuse elements. Among the uses for the fuses are
unique chip identifiers, mask revision numbers, cryptographic keys,
and various control signals requiring a fixed value.
IOMUX
External
ARM
signals and pin
multiplexing
Pins
Each I/O multiplexer provides a flexible, scalable multiplexing
solution with the following features:
• Up to eight output sources multiplexed per pin
• Up to four destinations for each input pin
• Unselected input paths held at constant levels for reduced power
consumption
IPUv1
Image
ARM
processing unit
Multimedia
peripherals
The IPU supports video and graphics processing functions. It also
provides the interface for image sensors and displays. The IPU
performs the following main functions:
• Preprocessing of data from the sensor or from the external
system memory
• Postprocessing of data from the external system memory
• Post-filtering of data from the system memory with support of the
MPEG-4 (both deblocking and deringing) and H.264 post-filtering
algorithms
• Displaying video and graphics on a synchronous (dumb or
memory-less) display
• Displaying video and graphics on an asynchronous (smart)
display
• Transferring data between IPU sub-modules and to/from the
system memory with flexible pixel reformatting
KPP
Keypin port
ARM
Connectivity
peripherals
Can be used for either keypin matrix scanning or general purpose
I/O.
OSCAUD
OSC audio
reference
oscillator
Analog
Clock
The OSCAUDIO oscillator provides a stable frequency reference for
the PLLs. This oscillator is designed to work in conjunction with an
external 24.576-MHz crystal.
OSC24M
OSC24M
24-MHz
reference
oscillator
Analog
Clock
The signal from the external 24-MHz crystal is the source of the
CLK24M signal fed into USB PHY as the reference clock and to the
real time clock (RTC).
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Table 4. Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Domain1
Subsystem
Brief Description
MPLL
PPLL
Digital
phase-locked
loops
SDMA
Clocks
DPLLs are used to generate the clocks:
MCU PLL (MPLL)—programmable
Peripheral PLL (PPLL)—programmable
PWM
Pulse-width
modulator
ARM
ARM1136
platform
peripherals
The pulse-width modulator (PWM) is optimized to generate sound
from stored sample audio images; it can also generate tones.
RTC
Real-time
clock
ARM
Clocks
Provides the ARM1136 platform with a clock function (days, hours,
minutes, seconds) and includes alarm, sampling timer, and minute
stopwatch capabilities.
Smart DMA
engine
SDMA
System
controls
The SDMA provides DMA capabilities inside the processor. It is a
shared module that implements 32 DMA channels and has an
interface to connect to the ARM1136 platform subsystem, EMI
interface, and the peripherals.
SJC
Secure JTAG
controller
ARM
Pins
The secure JTAG controller (SJC) provides debug and test control
with maximum security.
SPBA
SDMA
peripheral bus
arbiter
SDMA
System
controls
The SPBA controls access to the SDMA peripherals. It supports
shared peripheral ownership and access rights to an owned
peripheral.
S/PDIF
Serial audio
interface
SDMA
Connectivity
peripherals
Sony/Philips digital transceiver interface
SSI(2)
Synchronous
SDMA,
serial interface ARM(2)
Connectivity
peripherals
The SSI is a full-duplex serial port that allows the processor
connected to it to communicate with a variety of serial protocols,
including the Freescale Semiconductor SPI standard and the I2C
sound (I2S) bus standard. The SSIs interface to the AUDMUX for
flexible audio routing.
SDMA
UART(3)
Universal
asynchronous
receiver/trans
mitters
ARM
Connectivity
(UART1,2) peripherals
SDMA
(UART3)
USBOH
High-speed
SDMA
USB on-the-go
Connectivity
peripherals
The USB module provides high performance USB on-the-go (OTG)
functionality (up to 480 Mbps), compliant with the USB 2.0
specification, the OTG supplement, and the ULPI 1.0 low pin count
specification. The module has DMA capabilities handling data
transfer between internal buffers and system memory.
WDOG
Watchdog
modules
Timer
peripherals
Each module protects against system failures by providing a method
of escaping from unexpected events or programming errors. Once
activated, the timer must be serviced by software on a periodic
basis. If servicing does not take place, the watchdog times out and
then either asserts a system reset signal or an interrupt request
signal, depending on the software configuration.
ARM
Each UART provides serial communication capability with external
devices through an RS-232 cable using the standard RS-232
non-return-to-zero (NRZ) encoding format. Each module transmits
and receives characters containing either 7 or 8 bits
(program-selectable). Each UART can also provide low-speed IrDA
compatibility through the use of external circuitry that converts
infrared signals to electrical signals (for reception) or transforms
electrical signals to signals that drive an infrared LED (for
transmission).
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
11
1
ARM = ARM1136 platform, SDMA = SDMA platform
3
Signal Descriptions: Special Function Related Pins
Some special functional requirements are supported in the device. The details about these special functions
and the corresponding pin names are listed in Table 5.
Table 5. Special Function Related Pins
Function Name
Pin Name
Mux Mode
EXT_ARMCLK
ALT0
External clock input for ARM clock.
External Peripheral Clock
I2C1_CLK
ALT6
External peripheral clock source.
External 32-kHz Clock
CAPTURE
ALT4
CSPI1_SS1
ALT2
External clock input of 32 kHz, used when the internal
24M Oscillator is powered off, which could be
configured either from CAPTURE or CSPI1_SS1.
CLKO
ALT0
Clock-out pin from CCM, clock source is controllable
and can also be used for debug.
GPIO1_0
ALT1
TX1
ALT1
PMIC power-ready signal, which can be configured
either from GPIO1_0 or TX1.
GPIO1_1
ALT6
External ARM Clock
Clock Out
Power Ready
Tamper Detect
4
Detailed Description
Tamper-detect logic is used to issue a security
violation. This logic is activated if the tamper-detect
input is asserted. Tamper-detect logic is enabled by the
bit of IOMUXC_GPRA[2]. After enabling the logic, it is
impossible to disable it until the next reset.
Electrical Characteristics
The following sections provide the device-level and module-level electrical characteristics for the i.MX35
processor.
4.1
i.MX35 Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
Table 6. i.MX35 Chip-Level Conditions
Characteristics
Table/Location
Absolute Maximum Ratings
Table 7 on page 13
i.MX35 Operating Ranges
Table 8 on page 13
Interface Frequency
Table 9 on page 14
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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Freescale Semiconductor
CAUTION
Stresses beyond those listed in Table 7 may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at
these or any other conditions beyond those indicated in Table 8 is not
implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
Table 7. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Supply voltage (core)
VDDmax1
–0.5
1.47
V
Supply voltage (I/O)
NVCCmax
–0.5
3.6
V
Input voltage range
VImax
–0.5
3.6
V
Tstorage
–40
125
oC
Storage temperature
ESD damage immunity:
Vesd
V
2
Human Body Model (HBM)
—
2000
Charge Device Model (CDM)
—
5003
1
VDD is also known as QVCC.
HBM ESD classification level according to the AEC-Q100-002 standard
3
Corner pins max. 750 V
2
4.1.1
i.MX35 Operating Ranges
Table 8 provides the recommended operating ranges. The term NVCC in this section refers to the
associated supply rail of an input or output.
Table 8. i.MX35 Operating Ranges
Parameter
Min.
Typical
Max.
Units
1.22
—
1.47
V
Core Operating Voltage
0 < fARM < 532 MHz
1.33
—
1.47
V
State Retention Voltage
1
—
—
V
Core Operating Voltage
0 < fARM < 400 MHz
Symbol
VDD
EMI1
NVCC_EMI1,2,3
1.7
—
3.6
V
WTDG, Timer, CCM, CSPI1
NVCC_CRM
1.75
—
3.6
V
NANDF
NVCC_NANDF
1.75
—
3.6
V
ATA, USB generic
NVCC_ATA
1.75
—
3.6
V
eSDHC1
NVCC_SDIO
1.75
—
3.6
V
CSI, SDIO2
NVCC_CSI
1.75
—
3.6
V
JTAG
NVCC_JTAG
1.75
—
3.6
V
LCDC, TTM, I2C1
NVCC_LCDC
1.75
—
3.6
V
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
13
Table 8. i.MX35 Operating Ranges (continued)
Parameter
Symbol
Min.
Typical
Max.
Units
NVCC_MISC
1.75
—
3.6
V
MLB
2
NVCC_MLB
1.75
—
3.6
V
USB OTG PHY
PHY1_VDDA
3.17
3.3
3.43
V
USB OTG PHY
USBPHY1_VDDA_BIAS
3.17
3.3
3.43
V
USB OTG PHY
USBPHY1_UPLLVDD
3.17
3.3
3.43
V
USB HOST PHY
PHY2_VDD
3.0
3.3
3.6
V
OSC24M
OSC24M_VDD
3.0
3.3
3.6
V
OSC_AUDIO
OSC_AUDIO_VDD
3.0
3.3
3.6
V
MPLL
MVDD
1.4
—
1.65
V
PPLL
PVDD
1.4
—
1.65
V
Fusebox program supply voltage
FUSE_VDD3
3.0
3.6
3.6
V
I2Sx2,ESAI, I2C2, UART2, UART1, FEC
Operating Ambient Temperature Range
TA
–20
—
70
oC
Operating Ambient Temperature Range
TA
–40
—
85
oC
1
EMI I/O interface power supply should be set up according to external memory. For example, if using SDRAM then
NVCC_EMI1,2,3 should all be set at 3.3 V (typ.). If using MDDR or DDR2, NVC_EMI1,2,3 must be set at 1.8 V (typ.).
2 MLB Interface I/O pins can be programmed to function as GPIO for the consumer and industrial parts by setting NVCC_MLB
to 1.8 or 3.3 V. NVCC_MLB can be left floating.
3 The Fusebox read supply is connected to supply of the full speed USB PHY. FUSE_VDD is only used for programming. It is
recommended that FUSE_VDD be connected to ground when not being used for programming. FUSE_VDD should be
supplied by following the power up sequence given in Section 4.3.1, “Powering Up.”
4.1.2
Interface Frequency Limits
Table 9 provides information on interface frequency limits.
Table 9. Interface Frequency
ID
1
Parameter
JTAG TCK Frequency
Symbol
Min.
Typ.
Max.
Units
fJTAG
DC
5
10
MHz
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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Freescale Semiconductor
4.2
Power Modes
Table 10 provides descriptions of the power modes of the i.MX35 processor.
Table 10. i.MX35 Power Modes
Power
Mode
Wait
Doze
Stop
Description
QVCC (ARM/L2
Peripheral)
MVDD/PVDD
OSC24M_VDD
OSC_AUDO_VDD
Typ.
Max.
Typ.
Max.
Typ.
Max.
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is active.
L2 cache is kept powered.
MCU PLL is on (400 MHz)
PER PLL is off (can be configured)
(default: 300 MHz)
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured).
RNGC internal osc is off.
16 mA
—
7.2 mA
—
1.2 mA
—
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted.
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is on(400 MHz)
PER PLL is off (can be configured).
(300 Mhz).
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured)
RNGC internal osc is off
12.4 mA
—
7.2 mA
—
1.2 mA
—
1.1 mA
—
400 µA
—
1.2 mA
—
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24 MHz is on
OSC audio is off
RNGC internal osc is off
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
15
Table 10. i.MX35 Power Modes (continued)
Power
Mode
Static
Description
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24MHz is on
OSC audio is off
RNGC internal osc is off
QVCC (ARM/L2
Peripheral)
OSC24M_VDD
OSC_AUDO_VDD
MVDD/PVDD
Typ.
Max.
Typ.
Max.
Typ.
Max.
820 µA
—
50 µA
—
24 µA
—
Note: Typical column: TA = 25 °C
4.3
Supply Power-Up/Power-Down Requirements and Restrictions
This section provides power-up and power-down sequence guidelines for the i.MX35 processor.
CAUTION
Any i.MX35 board design must comply with the power-up and power-down
sequence guidelines as described in this section to guarantee reliable
operation of the device. Any deviation from these sequences can result in
irreversible damage to the i.MX35 processor (worst-case scenario).
NOTE
Deviation from these sequences may also result in one or more of the
following:
•
•
•
4.3.1
Excessive current during power-up phase
Prevent the device from booting
Programming of unprogrammed fuses
Powering Up
The power-up sequence should be completed as follows:
1. Assert Power on Reset (POR).
2. Turn on digital logic domain and IO power supply: VDDn, NVCCx
3. Wait until VDDn and NVCCx power supplies are stable + 32 μs.
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4. Turn on all other power supplies: PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD,
USBPHY1_UPLLVDD, OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, FUSEVDD.
(Always FUSE_VDD should be connected to ground, except when eFuses are to be
programmed.)
5. Wait until PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD, USBPHY1_UPLLVDD,
OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, (FUSEVDD, optional). Power supplies
are stable + 100 μs.
6. Deassert the POR signal.
Figure 2 shows the power-up sequence and timing.
Figure 2. i.MX35 Power-Up Sequence and Timing
4.3.2
Powering Down
The power-up sequence in reverse order is recommended for powering down. However, all power supplies
can be shut down at the same time.
4.4
Reset Timing
There are two ways of resetting the i.MX35 using external pins:
• Power On Reset (using the POR_B pin)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
17
•
4.4.1
System Reset (using the RESET_IN_B pin)
Power On Reset
POR_B is normally connected to a power management integrated circuit (PMIC). The PMIC asserts
POR_B while the power supplies are turned on and negates POR_B after the power up sequence is
finished. See Figure 2.
Assuming the i.MX35 chip is already fully powered; it is still possible to reset all of the modules to their
default reset by asserting POR_B for at least 4 CKIL cycles and later de-asserting POR_B. This method
of resetting the i.MX35 can also be supported by tying the POR_B and RESET_IN_B pins together.
POR_B
At least 4 CKIL cycles
CKIL
Figure 3. Timing Between POR_B and CKIL for Complete Reset of i.MX35
4.4.2
System Reset
System reset can be achieved by asserting RESET_IN_B for at least 4 CKIL cycles and later negating
RESET_IN_B. The following modules are not reset upon system reset: RTC, PLLs, CCM, and IIM.
POR_B pin must be deasserted all the time.
RESET_IN_B
At least 4 CKIL cycles
CKIL
Figure 4. Timing Between RESET_IN_B and CKIL for i.MX35 System Reboot
4.5
Power Characteristics
The table shows values representing maximum current numbers for the i.MX35 under worst case voltage
and temperature conditions. These values are derived from the i.MX35 with core clock speeds up to
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
18
Freescale Semiconductor
532 MHz. Common supplies have been bundled according to the i.MX35 power-up sequence
requirements. Peak numbers are provided for system designers so that the i.MX35 power supply
requirements will be satisfied during startup and transient conditions. Freescale recommends that system
current measurements be taken with customer-specific use-cases to reflect normal operating conditions in
the end system.
Table 11. Power Consumption
Power Supply
Voltage (V)
Max Current (mA)
QVCC
1.47
400
MVDD, PVDD
1.65
20
NVCC_EMI1, NVCC_EMI2, NVCC_EMI3, NVCC_LCDC, NVCC_NFC
1.9
90
FUSE_VDD1
3.6
62
NVCC_MISC, NVCC_CSI, NVCC_SDIO, NVCC_CRM, NVCC_ATA, NVCC_MLB,
NVCC_JTAG
3.6
60
OSC24M_VDD, OSC_AUDIO_VDD, PHY1_VDDA, PHY2_VDD,
USBPHY1_UPLLVDD, USBPHY1_VDDA_BIAS
3.6
25
1
This rail is connected to ground; it only needs a voltage if eFuses are to be programmed. FUSE_VDD should be supplied by
following the power up sequence given in Section 4.3.1, “Powering Up.”
The method for obtaining max current is as follows:
1. Measure worst case power consumption on individual rails using directed test on i.MX35.
2. Correlate worst case power consumption power measurements with worst case power
consumption simulations.
3. Combine common voltage rails based on power supply sequencing requirements
4. Guard band worst case numbers for temperature and process variation. Guard band is based on
process data and correlated with actual data measured on i.MX35.
5. The sum of individual rails is greater than real world power consumption, as a real system does
not typically maximize power consumption on all peripherals simultaneously.
4.6
Thermal Characteristics
The thermal resistance characteristics for the device are given in Table 12. These values were measured
under the following conditions:
• Two-layer substrate
• Substrate solder mask thickness: 0.025 mm
• Substrate metal thicknesses: 0.016 mm
• Substrate core thickness: 0.200 mm
• Core via I.D: 0.168 mm, Core via plating 0.016 mm.
• Full array map design, but nearly all balls under die are power or ground.
• Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K
• Mold compound: k = 0.9 W/m K
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
19
Table 12. Thermal Resistance Data
Rating
Condition
Symbol
Value
Unit
Junction to ambient1 natural convection
Single layer board (1s)
ReJA
53
ºC/W
Junction to ambient1 natural convection
Four layer board (2s2p)
ReJA
30
ºC/W
Junction to ambient1 (at 200 ft/min)
Single layer board (1s)
ReJMA
44
ºC/W
Junction to ambient1 (at 200 ft/min)
Four layer board (2s2p)
ReJMA
27
ºC/W
Junction to boards2
—
ReJB
19
ºC/W
Junction to case (top)3
—
ReJCtop
10
ºC/W
Natural convection
ΨJT
2
ºC/W
Junction to package top4
1
Junction-to-ambient thermal resistance determined per JEDC JESD51-3 and JESD51-6. Thermal test board meets JEDEC
specification for this package.
2 Junction-to-board thermal resistance determined per JEDC JESD51-8. Thermal test board meets JEDEC specification for this
package.
3 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used
for the case temperature. Reported value includes the thermal resistance of the interface layer.
4
Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, this thermal characterization parameter is written
as Psi-JT.
4.7
I/O Pin DC Electrical Characteristics
I/O pins are of two types: GPIO and DDR. DDR pins can be configured in three different drive strength
modes: mobile DDR, SDRAM, and DDR2. The SDRAM and mobile DDR modes can be further
customized at three drive strength levels: normal, high, and max.
Table 13 shows currents for the different DDR pin drive strength modes.
Table 13. DDR Pin Drive Strength Mode Current Levels
Drive Mode
Normal
High
Max.
3.6 mA
7.2 mA
10.8 mA
SDRAM (1.8 V)
—
—
6.5 mA
SDRAM (3.3 V)
4 mA
8 mA
12 mA
—
—
13.4 mA
Mobile DDR (1.8 V)
DDR2 (1.8 V)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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Freescale Semiconductor
Table 14 shows the DC electrical characteristics for GPIO, DDR2, mobile DDR, and SDRAM pins. The
term NVCC refers to the power supply voltage that feeds the I/O of the module in question. For example,
NVCC for the SD/MMC interface refers to NVCC_SDIO.
Table 14. I/O Pin DC Electrical Characteristics
Pin
GPIO
DC Electrical Characteristics Symbol
Test Condition
Min.
Typ.
Max.
Unit
High-level output voltage
Voh
Ioh = –1 mA
Ioh = specified drive
NVCC – 0.15
0.8 × NVCC
—
—
V
Low-level output voltage
Vol
Iol = 1 mA
Iol = specified drive
—
—
0.15
0.2 × NVCC
V
High-level output current for
slow mode
(Voh = 0.8 × NVCC)
Ioh
Standard drive
High drive
Max. drive
–2.0
–4.0
–8.0
—
—
mA
High-level output current
for fast mode
(Voh = 0.8 × NVCC)
Ioh
Standard drive
High drive
Max. drive
–4.0
–6.0
–8.0
—
—
mA
Low-level output current
for slow mode
(Voh = 0.2 × NVCC)
Iol
Standard drive
High drive
Max. drive
2.0
4.0
8.0
—
—
mA
Low-level output current
for fast mode
(Voh = 0.2 × NVCC)
Iol
Standard drive
High drive
Max. drive
4.0
6.0
8.0
—
—
mA
High-level DC Input
Voltage with 1.8 V,
3.3 V NVCC (for digital
cells in input mode)
VIH
—
0.7 × NVCC
—
NVCC
V
Low-level DC Input
Voltage with 1.8 V,
3.3 V NVCC (for digital
cells in input mode
VIL
—
–0.3 V
—
0.3 × NVCC
V
VHYS
OVDD = 3.3 V
OVDD = 1.8 V
—
410
330
—
mV
Schmitt trigger VT+
VT+
—
0.5 × NVCC
—
Schmitt trigger VT–
VT–
—
—
—
0.5 × NVCC
V
Pull-up resistor
(22 kΩ PU)
Rpu
Vi = 0
—
22
—
kΩ
Pull-up resistor
(47 kΩ PU)
Rpu
Vi = 0
—
47
—
kΩ
Pull-up resistor
(100 kΩ PU)
Rpu
Vi = 0
—
100
—
kΩ
Pull-down resistor (100 kΩ PD)
Rpd
Vi = NVCC
—
100
—
kΩ
External resistance to pull
keeper up when enabled
Rkpu
Ipu > 620 μA
@ min Vddio = 3.0 V
—
—
4.8
kΩ
External resistance to pull
keeper down when enabled
Rkpd
Ipu > 510 μA
@min Vddio = 3.0 V
—
—
5.9
kΩ
Input Hysteresis
V
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
21
Table 14. I/O Pin DC Electrical Characteristics (continued)
Pin
DDR2
DC Electrical Characteristics Symbol
Min.
Typ.
Max.
Unit
NVCC – 0.28
—
—
V
—
0.28
V
High-level output voltage
Voh
—
Low-level output voltage
Vol
—
Output min. source current
Ioh
—
–13.4
—
—
mA
Output min. sink current
Iol
—
13.4
—
—
mA
DC input logic high
VIH(dc)
—
NVCC ÷ 2 +
0.125
—
NVCC + 0.3
V
DC input logic low
VIL(dc)
—
–0.3 V
—
NVCC ÷ 2 –
0.125
V
DC input signal voltage
(for differential signal)
Vin(dc)
—
–0.3
—
NVCC + 0.3
V
DC differential input voltage
Vid(dc)
—
0.25
—
NVCC + 0.6
V
Termination voltage
Vtt
—
NVCC ÷ 2 –
0.04
NV
CC
÷2
NVCC ÷ 2 +
0.04
V
Input current (no
pull-up/down)
IIN
—
—
—
±1
μA
Icc – N
VCC
—
—
—
±1
μA
High-level output voltage
—
IOH = –1mA
IOH = specified drive
NVCC – 0.08
0.8 × NVCC
—
—
V
Low-level output voltage
—
IOL = 1mA
IOL = specified drive
—
—
0.08
0.2 × NVCC
V
High-level output current
(Voh = 0.8 × NVCCV)
—
Standard drive
High drive
Max. drive
–3.6
–7.2
–10.8
—
—
mA
Low-level output current
(Vol = 0.2 × NVCCV)
—
Standard Drive
High Drive
Max. Drive
3.6
7.2
10.8
—
—
mA
High-Level DC CMOS
input voltage
VIH
—
0.7 × NVCC
—
NVCC + 0.3
V
Low-Level DC CMOS
input voltage
VIL
—
–0.3
—
0.2 × NVCC
V
Differential receiver VTH+
VTH+
—
—
—
100
mV
Differential receiver VTH–
VTH–
—
–100
—
IIN
VI = 0
VI = NVCC
—
—
±1
μA
Icc – N
VCC
VI = NVCC or 0
—
—
±1
μA
Tri-state I/O supply current
Mobile
DDR
Test Condition
Input current (no
pull-up/down)
Tri-state I/O supply current
mV
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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Freescale Semiconductor
Table 14. I/O Pin DC Electrical Characteristics (continued)
Pin
DC Electrical Characteristics Symbol
Test Condition
Min.
Typ.
Max.
Unit
SDR High-level output voltage
(1.8 V)
Low-level output voltage
Voh
loh = 5.7 mA
OVDD – 0.28
—
—
V
Vol
loh = 5.7 mA
—
—
0.4
V
High-level output current
Ioh
Max. drive
5.7
—
—
mA
Low-level output current
Iol
Max. drive
7.3
—
—
mA
High-level DC Input Voltage
VIH
—
1.4
—
1.98
V
Low-level DC Input Voltage
VIL
—
–0.3
—
0.8
V
Input current (no
pull-up/down)
IIN
VI = 0
VI=NVCC
—
—
150
80
μA
Tri-state I/O supply current
Icc
(NVCC)
VI = OVDD or 0
—
—
1180
μA
Tri-state core supply current
Icc
(NVCC)
VI = VDD or 0
—
—
1220
μA
SDR High-level output voltage
(3.3 V)
Voh
Ioh=specified drive
(Ioh = –4, –8, –12,
–16 mA)
2.4
—
—
V
Low-level output voltage
Vol
Ioh=specified drive (Ioh = 4,
8, 12, 16 mA)
—
—
0.4
V
High-level output current
Ioh
Standard drive
High drive
Max. drive
–4.0
–8.0
–12.0
—
—
mA
Low-level output current
Iol
Standard drive
High drive
Max. drive
4.0
8.0
12.0
—
—
mA
High-level DC Input Voltage
VIH
—
2.0
—
3.6
V
Low-level DC Input Voltage
VIL
—
–0.3V
—
0.8
V
Input current (no
pull-up/down)
IIN
VI = 0
—
—
±1
μA
—
—
±1
μA
VI = NVCC
Tri-state I/O supply current
4.8
Icc
(NVCC)
VI = NVCC or 0
I/O Pin AC Electrical Characteristics
Figure 5 shows the load circuit for output pins.
From Output
Under Test
Test Point
CL
CL includes package, probe and jig capacitance
Figure 5. Load Circuit for Output Pin
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
23
Figure 6 shows the output pin transition time waveform.
NVCC
80%
80%
20%
0V
20%
Output (at pin)
PA1
PA1
Figure 6. Output Pin Transition Time Waveform
4.8.1
AC Electrical Test Parameter Definitions
AC electrical characteristics in Table 16 through Table 21 are not applicable for the output open drain
pull-down driver.
The dI/dt parameters are measured with the following methodology:
• The zero voltage source is connected between pin and load capacitance.
• The current (through this source) derivative is calculated during output transitions.
Table 15. AC Requirements of I/O Pins
Parameter
Symbol
Min.
Max.
Units
AC input logic high
VIH(ac)
NVCC ÷ 2 + 0.25
NVCC + 0.3
V
AC input logic low
VIL(ac)
–0.3
NVCC ÷ 2 – 0.25
V
Table 16. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode
[NVCC = 3.0 V–3.6 V]
Symbol
Test
Condition
Min.
Rise/Fall
Typ. Rise/Fall
Max.
Rise/Fall
Units
Fduty
—
40
—
60
%
Output pin slew rate (max. drive)
tps
25 pF
50 pF
0.79/1.12
0.49/0.73
1.30/1.77
0.84/1.23
2.02/2.58
1.19/1.58
V/ns
Output pin slew rate (high drive)
tps
25 pF
50 pF
0.48/0.72
0.27/0.42
0.76/1.10
0.41/0.62
1.17/1.56
0.63/0.86
V/ns
Output pin slew rate (standard
drive)
tps
25 pF
50 pF
0.25/0.40
0.14/0.21
0.40/0.59
0.21/0.32
0.60/0.83
0.32/0.44
V/ns
Output pin di/dt (max. drive)
tdit
25 pF
50 pF
15
16
36
38
76
80
mA/ns
Output pin di/dt (high drive)
tdit
25 pF
50 pF
8
9
20
21
45
47
mA/ns
Output pin di/dt (standard
drive)
tdit
25 pF
50 pF
4
4
10
10
22
23
mA/ns
Parameter
Duty cycle
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
24
Freescale Semiconductor
Table 17. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode
[NVCC = 1.65 V–1.95 V]
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
—
60
%
Output pin slew rate (max. drive)
tps
25 pF
50 pF
0.30/0.42
0.20/0.29
0.54/0.73
0.35/0.50
0.91/1.20
0.60/0.80
V/ns
Output pin slew rate (high drive)
tps
25 pF
50 pF
0.19/0.28
0.12/0.18
0.34/0.49
0.34/0.49
0.58/0/79
0.36/0.49
V/ns
Output pin slew rate (standard drive)
tps
25 pF
50 pF
0.12/0.18
0.07/0.11
0.20/0.30
0.11/0.17
0.34/0.47
0.20/0.27
V/ns
Output pin di/dt (max. drive)
tdit
25 pF
50 pF
7
7
21
22
56
58
mA/ns
Output pin di/dt (high drive)
tdit
25 pF
50 pF
5
5
14
15
38
40
mA/ns
Output pin di/dt (standard
drive)
tdit
25 pF
50 pF
2
2
7
7
18
19
mA/ns
Parameter
Duty cycle
Table 18. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode for
[NVCC = 3.0 V–3.6 V]
Symbol
Test Condition
Min.
rise/fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
—
60
%
Output pin slew rate (max. drive)
tps
25 pF
50 pF
0.96/1.40
0.54/0.83
1.54/2.10
0.85/1.24
2.30/3.00
1.26/1.70
V/ns
Output pin slew rate (high drive)
tps
25 pF
50 pF
0.76/1.10
0.41/0.64
1.19/1.71
0.63/0.95
1.78/2.39
0.95/1.30
V/ns
Output pin slew rate (standard drive)
tps
25 pF
50 pF
0.52/0.78
0.28/0.44
0.80/1.19
0.43/0.64
1.20/1.60
0.63/0.87
V/ns
Output pin di/dt (max. drive)
tdit
25 pF
50 pF
46
49
108
113
250
262
mA/ns
Output pin di/dt (high drive)
tdit
25 pF
50 pF
35
37
82
86
197
207
mA/ns
Output pin di/dt (standard
drive)
tdit
25 pF
50 pF
22
23
52
55
116
121
mA/ns
Parameter
Duty cycle
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
25
Table 19. AC Electrical Characteristics, GPIO Pins in Fast Slew Rate Mode
[NVCC = 1.65 V–1.95 V]
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
—
60
%
Output pin slew rate (max. drive)
tps
25 pF
50 pF
0.40/0.57
0.25/0.36
0.72/0.97
0.43/0.61
1.2/1.5
0.72/0.95
V/ns
Output pin slew rate (high drive)
tps
25 pF
50 pF
0.38/0.48
0.20/0.30
0.59/0.81
0.34/0.50
0.98/1.27
0.56/0.72
V/ns
Output pin slew rate (standard drive)
tps
25 pF
50 pF
0.23/0.32
0.13/0.20
0.40/0.55
0.23/0.34
0.66/0.87
0.38/0.52
V/ns
Output pin di/dt (max. drive)
tdit
25 pF
50 pF
7
7
43
46
112
118
mA/ns
Output pin di/dt (high drive)
tdit
25 pF
50 pF
11
12
31
33
81
85
mA/ns
Output pin di/dt (standard
drive)
tdit
25 pF
50 pF
9
10
27
28
71
74
mA/ns
Parameter
Duty cycle
Table 20. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode
[NVCC = 2.25 V–2.75 V]
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
—
60
%
Output pin slew rate (max. drive)
tps
25 pF
40 pF
50 pF
0.63/0.85
0.52/0.67
0.41/0.59
1.10/1.40
0.90/1.10
0.73/0.99
1.86/2.20
1.53/1.73
1.20/1.50
V/ns
Output pin slew rate (high drive)
tps
25 pF
40 pF
50 pF
0.40/0.58
0.33/0.43
0.25/0.37
0.71/0.98
0.56/0.70
0.43/0.60
1.16/1.40
0.93/1.07
0.68/0.90
V/ns
Output pin slew rate (standard drive)
tps
25 pF
40 pF
50 pF
0.24/0.36
0.19/0.25
0.13/0.21
0.41/0.59
0.32/0.35
0.23/0.33
0.66/0.87
0.51/0.59
0.36/0.48
V/ns
Output pin di/dt (max. drive)
tdit
25 pF
50 pF
22
23
62
65
148
151
mA/ns
Output pin di/dt (high drive)
tdit
25 pF
50 pF
15
16
42
44
102
107
mA/ns
Output pin di/dt (standard
drive)
tdit
25 pF
50 pF
7
8
21
22
52
54
mA/ns
Parameter
Duty cycle
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
26
Freescale Semiconductor
Table 21. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode
[NVCC = 2.25 V–2.75 V]
Parameter
Symbol
Duty cycle
Test
Min.
Condition Rise/Fall
Fduty
—
Output pin slew rate (max. drive)
tps
25 pF
40 pF
50 pF
Output pin slew rate (high drive)
tps
Output pin slew rate (standard drive)
Max.
Units Notes
Rise/Fall
Typ.
%
—
0.84/1.10 1.45/1.80 2.40/2.80
0.68/0.83 1.14/1.34 1.88/2.06
0.58/0.72 0.86/1.10 1.40/1.70
V/ns
2
25 pF
40 pF
50 pF
0.69/0.96 1.18/1.50 1.90/2.30
0.55/0.69 0.92/1.10 1.49/1.67
0.40/0.59 0.67/0.95 1.10/1.30
V/ns
tps
25 pF
40 pF
50 pF
0.24/0.36 0.80/1.00 1.30/1.60
0.37/0.47 0.62/0.76 1.00/1.14
0.13/0.21 0.45/0.65 0.70/0.95
V/ns
Output pin di/dt (max. drive)
tdit
25 pF
50 pF
46
49
124
131
310
324
mA/ns
Output pin di/dt (high drive)
tdit
25 pF
50 pF
33
35
89
94
290
304
mA/ns
Output pin di/dt (standard
drive)
tdit
25 pF
50 pF
28
29
75
79
188
198
mA/ns
4.8.2
40
—
60
3
AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and
SDRAM Modes)
Table 22. AC Electrical Characteristics of DDR Type IO Pins in DDR2 Mode
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
45
50
55
%
f
—
—
133
—
MHz
Output pin slew rate
tps
25 pF
50 pF
0.86/0.98
0.46/054
1.35/1.5
0.72/0.81
2.15/2.19
1.12/1.16
V/ns
Output pin di/dt
tdit
25 pF
50 pF
65
70
157
167
373
396
mA/ns
Parameter
Duty cycle
Clock frequency
Table 23. AC Requirements of DDR2 Pins
Parameter1
Symbol
Min.
Max.
AC input logic high
VIH(ac)
NVCC ÷ 2 + 0.25
NVCC + 0.3
V
AC input logic low
VIL(ac)
–0.3
NVCC ÷ 2 – 0.25
V
AC differential cross point voltage for output2
Vox(ac)
NVCC ÷ 2 – 0.125
NVCC ÷ 2 + 0.125
V
1
Units
The Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any specification in this
document.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
27
2
The typical value of Vox(ac) is expected to be about 0.5 × NVCC and Vox(ac) is expected to track variation in NVCC. Vox(ac)
indicates the voltage at which the differential output signal must cross. Cload = 25 pF.
Table 24. AC Electrical Characteristics of DDR Type IO Pins in mDDR Mode
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
45
50
55
%
f
—
—
133
—
MHz
Output pin slew rate (max. drive)
tps
25 pF
50 pF
0.80/0.92
0.43/0.50
1.35/1.50
0.72/0.81
2.23/2.27
1.66/1.68
V/ns
Output pin slew rate (high drive)
tps
25 pF
50 pF
0.37/0.43
0.19/0.23
0.62/0.70
0.33/0.37
1.03/1.05
0.75/0.77
V/ns
Output pin slew rate (standard drive)
tps
25 pF
50 pF
0.18/0.22
0.10/0.12
0.31/0.35
0.16/0.18
0.51/0.53
0.38/0.39
V/ns
Output pin di/dt (max. drive)
tdit
25 pF
50 pF
64
69
171
183
407
432
mA/ns
Output pin di/dt (high drive)
tdit
25 pF
50 pF
37
39
100
106
232
246
mA/ns
Output pin di/dt (standard drive)
tdit
25 pF
50 pF
18
20
50
52
116
123
mA/ns
Parameter
Duty cycle
Clock frequency
Table 25. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode
Symbol
Test Condition
Min.
Rise/Fall
Min. Clock
Frequency
Max.
Rise/Fall
Units
f
—
—
125
—
MHz
Output pin slew rate (max. drive)
tps
25 pF
50 pF
1.11/1.20
0.97/0.65
1.74/1.75
0.92/0.94
2.42/2.46
1.39/1.30
V/ns
Output pin slew rate (high drive)
tps
25 pF
50 pF
0.76/0.80
0.40/0.43
1.16/1.19
0.61/0.63
1.76/1.66
0.93/0.87
V/ns
Output pin slew rate (standard drive)
tps
25 pF
50 pF
0.38/0.41
0.20/0.22
0.59/0.60
0.31/0.32
0.89/0.82
0.47/0.43
V/ns
Output pin di/dt (max. drive)
tdit
25 pF
50 pF
89
94
198
209
398
421
mA/ns
Output pin di/dt (high drive)
tdit
25 pF
50 pF
59
62
132
139
265
279
mA/ns
Output pin di/dt (standard drive)
tdit
25 pF
50 pF
29
31
65
69
132
139
mA/ns
Parameter
Clock frequency
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
28
Freescale Semiconductor
Table 26. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V)
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
f
—
125
—
—
MHz
Output pin slew rate (max. drive)
tps
25 pF
50 pF
2.83/2.68
1.59/1.49
1.84/1.85
1.03/1.05
1.21/1.40
0.70/0.75
V/ns
Output pin di/dt (max. drive)2
didt
25 pF
50 pF
89
95
202
213
435
456
mA/ns
Input pin transition times3
trfi
1.0 pF
0.07/0.08
0.11/0.12
0.16/0.20
ns
Input pin propagation delay, 50%–50%
tpi
1.0 pF
0.35/1.17
0.63/1.53
1.16/2.04
ns
Input pin propagation delay, 40%–60%
tpi
1.0 pF
1.18/1.99
1.45/2.35
1.97/2.85
ns
Parameter
Clock frequency
1
1
Min. condition for tps: wcs model, 1.1 V, IO 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and between
VIH to VIL for falling edge.
2 Max. condition for tdit: bcs model, 1.3 V, IO 1.95 V, and –40 °C.
3 Max. condition for tpi and trfi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Min. condition for tpi and trfi: bcs model, 1.3 V, IO 1.95 V
and –40 °C. Input transition time from pad is 5 ns (20%–80%).
4.9
Module-Level AC Electrical Specifications
This section contains the AC electrical information (including timing specifications) for the modules of
the i.MX35. The modules are listed in alphabetical order.
4.9.1
AUDMUX Electrical Specifications
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is hence governed by the SSI module. See the electrical specification for SSI.
4.9.2
CSPI AC Electrical Specifications
The i.MX35 provides two CSPI modules. CSPI ports are multiplexed in the i.MX35 with other pins. See
the “External Signals and Multiplexing” chapter of the reference manual for more details.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
29
Figure 7 and Figure 8 depict the master mode and slave mode timings of the CSPI, and Table 27 lists the
timing parameters.
SPI_RDY
CS11
SSn[3:0]
CS1
CS3
CS2
CS6
CS3
CS5
CS4
SCLK
CS2
CS7 CS8
MOSI
CS9
CS10
MISO
Figure 7. CSPI Master Mode Timing Diagram
SSn[3:0]
CS1
CS3
CS2
CS5
CS6
CS4
SCLK
CS9
CS3
CS10
CS2
MISO
CS8
CS7
MOSI
Figure 8. CSPI Slave Mode Timing Diagram
Table 27. CSPI Interface Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
CS1
SCLK cycle time
tclk
60
—
ns
CS2
SCLK high or low time
tSW
30
—
ns
CS3
SCLK rise or fall
tRISE/FALL
—
7.6
ns
CS4
SSn[3:0] pulse width
tCSLH
30
—
ns
CS5
SSn[3:0] lead time (CS setup time)
tSCS
30
—
ns
CS6
SSn[3:0] lag time (CS hold time)
tHCS
30
—
ns
CS7
MOSI setup time
tSmosi
5
—
ns
CS8
MOSI hold time
tHmosi
5
—
ns
CS9
MISO setup time
tSmiso
5
—
ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
30
Freescale Semiconductor
Table 27. CSPI Interface Timing Parameters (continued)
ID
Parameter
Symbol
Min.
Max.
Units
CS10
MISO hold time
tHmiso
5
—
ns
CS11
SPI_RDY setup time
tSDRY
5
—
ns
4.9.3
DPLL Electrical Specifications
There are three PLLs inside the i.MX35, all based on the same PLL design. The reference clock for these
PLLs is normally generated from an external 24-MHz crystal connected to an internal oscillator via
EXTAL24M and XTAL24 pins. It is also possible to connect an external 24-MHz clock directly to
EXTAL24M, bypassing the internal oscillator.
DPLL specifications are listed in Table 28.
Table 28. DPLL Specifications
Parameter
Min. Typ. Max.
Unit
Comments
Reference clock frequency
10
24
100
Max. allowed reference clock phase noise
—
—
0.03 2 Tdck1 Fmodulation < 50 kHz
0.01
50 kHz < Fmodulation 300 Hz
0.15
Fmodulation > 300 KHz
Frequency lock time (FOL mode or non-integer MF)
—
—
80
μs
—
Phase lock time
—
—
100
μs
—
Max. allowed PL voltage ripple
—
—
150
100
150
mV
1
MHz
Fmodulation < 50 kHz
50 kHz < Fmodulation 300 Hz
Fmodulation > 300 KHz
There are two PLL are used in the i.MX35, MPLL and PPLL. Both are based on same DPLL design.
If crystals are used instead of external oscillators, they should meed the following specifications:
Table 29. Clock Input Tolerance
Parameters
OSC24M
OSC_AUDIO
Normal Frequency
24 MHz
25.576 MHz
Frequency Tolerance
30 ppm
20 ppm (high quality)
ESR
<80 Ω
<80 Ω
Load Capacitance
8 pF-12 pF
8 pF-12 pF
Shunt capacitance
<7 pF
<7 pF
Level of drive
>150 μW
>150 μW
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
31
4.9.4
Embedded Trace Macrocell (ETM) Electrical Specifications
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point
access (TPA) that supports TRACECLK frequencies up to 133 MHz.
Figure 9 depicts the TRACECLK timings of ETM, and Table 30 lists the timing parameters.
Figure 9. ETM TRACECLK Timing Diagram
Table 30. ETM TRACECLK Timing Parameters
ID
Parameter
Min.
Max.
Unit
Frequency dependent
—
ns
Tcyc
Clock period
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Figure 10 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and
Table 31 lists the timing parameters.
Figure 10. Trace Data Timing Diagram
Table 31. ETM Trace Data Timing Parameters
ID
Parameter
Min.
Max.
Unit
Ts
Data setup
2
—
ns
Th
Data hold
1
—
ns
4.9.4.1
Half-Rate Clocking Mode
When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling
edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 10. The same
Ts and Th parameters from Table 31 still apply with respect to the falling edge of the TRACECLK signal.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
32
Freescale Semiconductor
4.9.5
EMI Electrical Specifications
This section provides electrical parametrics and timing for the EMI module.
4.9.5.1
NAND Flash Controller Interface (NFC)
The i.MX35 NFC supports normal timing mode, using two flash clock cycles for one access of RE and
WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 11, Figure 12,
Figure 13, and Figure 14 depict the relative timing requirements among different signals of the NFC at
module level for normal mode. Table 32 lists the timing parameters.
NFCLE
NF2
NF1
NF3
NF4
NFCE
NF5
NFWE
NF6
NF7
NFALE
NF8
NF9
Command
NFIO[7:0]
Figure 11. Command Latch Cycle Timing DIagram
NFCLE
NF1
NF4
NF3
NFCE
NF10
NF11
NF5
NFWE
NF7
NF6
NFALE
NF8
NF9
NFIO[7:0]
Address
Figure 12. Address Latch Cycle Timing DIagram
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
33
NFCLE
NF1
NF3
NFCE
NF10
NF11
NF5
NFWE
NF7
NF6
NFALE
NF8
NF9
NFIO[15:0]
Data to NF
Figure 13. Write Data Latch Cycle Timing DIagram
NFCLE
NFCE
NF14
NF15
NF13
NFRE
NF16
NF17
NFRB
NF12
NFIO[15:0]
Data from NF
Figure 14. Read Data Latch Cycle Timing DIagram
Table 32. NFC Timing Parameters1
ID
Parameter
Symbol
Timing
T = NFC Clock Cycle2
Example Timing for
NFC Clock ≈ 33 MHz
T = 30 ns
Min.
Max.
Min.
Max.
Unit
NF1
NFCLE setup time
tCLS
T – 4.0 ns
—
26
—
ns
NF2
NFCLE hold time
tCLH
T – 5.0 ns
—
25
—
ns
NF3
NFCE setup time
tCS
T – 2.0 ns
—
28
—
ns
NF4
NFCE hold time
tCH
T – 1.0 ns
—
29
—
ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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Freescale Semiconductor
Table 32. NFC Timing Parameters1 (continued)
ID
Parameter
Symbol
Timing
T = NFC Clock Cycle2
Min.
1
2
Max.
Example Timing for
NFC Clock ≈ 33 MHz
T = 30 ns
Min.
T – 1.0 ns
Unit
Max.
NF5
NF_WP pulse width
tWP
29
ns
NF6
NFALE setup time
tALS
T – 4.0 ns
—
26
—
ns
NF7
NFALE hold time
tALH
T – 4.5 ns
—
25.5
—
ns
NF8
Data setup time
tDS
T – 2.0 ns
—
28
—
ns
NF9
Data hold time
tDH
T – 5.0 ns
—
25
—
ns
NF10
Write cycle time
tWC
2T – 3.0 ns
57
ns
NF11
NFWE hold time
tWH
T – 5.0 ns
25
ns
NF12
Ready to NFRE low
tRR
6T
—
180
—
ns
NF13
NFRE pulse width
tRP
1.5T – 1.0 ns
—
44
—
ns
NF14
READ cycle time
tRC
2T – 5.5 ns
—
54.5
—
ns
NF15
NFRE high hold time
tREH
0.5T – 4.0 ns
11
—
ns
NF16
Data setup on READ
tDSR
N/A
9
—
ns
NF17
Data hold on READ
tDHR
N/A
0
—
ns
The flash clock maximum frequency is 50 MHz.
Subject to DPLL jitter specification listed in Table 28, "DPLL Specifications," on page 31.
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not NFC clock related.
4.9.5.2
Wireless External Interface Module (WEIM)
All WEIM output control signals may be asserted and deasserted by internal clocks related to the BCLK
rising edge or falling edge according to the corresponding assertion or negation control fields. The address
always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed
mode according to control register configuration. Output data begins related to BCLK rising edge except
in muxed mode where both rising and falling edge may be used according to control register configuration.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
35
Input data, ECB and DTACK all captured according to BCLK rising edge time. Figure 15 depicts the
timing of the WEIM module, and Table 33 lists the timing parameters.
WEIM Output Timing
WE2
WE3
WE1
BCLK
...
WE4
WE5
WE6
WE7
WE8
WE9
WE10
WE11
WE12
WE13
WE14
WE15
WE16
WE17
Address
CSx_B
RW_B
OE_B
EBy_B
LBA_B
Output Data
WEIM Input Timing
BCLK
WE18
Input Data
WE20
WE22
ECB_B
WE24
WE26
DTACK_B
WE27
Figure 15. WEIM Bus Timing Diagram
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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Freescale Semiconductor
Table 33. WEIM Bus Timing Parameters1
ID
Parameter
Min.
Max.
Unit
14.5
—
ns
WE1
BCLK cycle time2
WE2
BCLK low-level width2
7
—
ns
WE3
BCLK high-level width2
7
—
ns
WE4
Address valid to Clock rise/fall
15
21
ns
WE5
Clock rise/fall to address invalid
22
25
ns
WE6
Clock rise/fall to CSx_B valid
15
19
ns
WE7
Clock rise/fall to CSx_B invalid
3.6
5
ns
WE8
Clock rise/fall to RW_B valid
8
12
ns
WE9
Clock rise/fall to RW_B invalid
3
8
ns
WE10
Clock rise/fall to OE_B valid
7
12
ns
WE11
Clock rise/fall to OE_B invalid
3.8
5.5
ns
WE12
Clock rise/fall to EBy_B valid
6
11.5
ns
WE13
Clock rise/fall to EBy_B invalid
6
10
ns
WE14
Clock rise/fall to LBA_B valid
17.5
20
ns
WE15
Clock rise/fall to LBA_B invalid
0
1
ns
WE16
Clock rise/fall to Output Data valid
5
10
ns
WE17
Clock rise to Output Data invalid
0
2.5
ns
WE18
Input Data Valid to Clock rise3
1
—
ns
WE19
Input Data Valid to Clock rise, FCE=0 (in the case there is ECB_B asserted
during access)
(BCLK/2)
+ 3.01
—
ns
WE19
Input Data Valid to Clock rise, FCE=0 (in the case there is NO ECB_B
asserted during access)
6.9
—
ns
WE20
Clock rise to Input Data invalid3
1
—
ns
WE22
ECB_B setup time3
5
—
ns
WE24
ECB_B hold time3
0
—
ns
WE26
DTACK_B setup time
5.4
—
ns
WE27
DTACK_B hold time
–3.2
—
ns
1
“High” is defined as 80% of signal value, and “low” is defined as 20% of signal value.
BCLK parameters are measured from the 50% point. For example, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value.
3 Parameters W18, W20, W22, and W24 are tested when FCE=1. i.MX35 does not support FCE=0.
2
NOTE
Test conditions: load capacitance, 25 pF. Recommended drive strength for
all controls, address, and BCLK is set to maximum drive.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
37
Recommended drive strength for all controls, address and BCLK is set to
maximum drive.
Figure 16 through Figure 21 depict some examples of basic WEIM accesses to external memory devices
with the timing parameters mentioned in Table 33 for specific control parameter settings.
BCLK
WE5
WE4
ADDR
V1
Last Valid Address
Next Address
WE6
WE7
WE14
WE15
WE10
WE11
WE12
WE13
CS[x]
RW
LBA
OE
EB[y]
WE20, WE21
V1
DATA
WE18, WE 19
Figure 16. Synchronous Memory Timing Diagram for Read Access—WSC = 1
BCLK
WE5
WE4
ADDR
CS[x]
RW
LBA
Last Valid Address
Next Address
V1
WE6
WE7
WE8
WE9
WE14
WE15
OE
EB[y]
WE12
WE13
WE17
DATA
V1
WE16
Figure 17. Synchronous Memory Timing Diagram for Write Access—
WSC = 1, EBWA = 1, EBWN = 1, LBN = 1
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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Freescale Semiconductor
BCLK
WE4
WE5
ADDR Last Valid Addr
Address V1
Address V2
WE7
WE6
CS[x]
RW
WE14
LBA
WE15
WE11
WE10
OE
WE13
WE12
EB[y]
WE24, WE25
WE24, WE25
ECB
WE22, WE23
WE20, WE21
WE22, WE23
WE20, WE21
V1
V1+2
Halfword Halfword
DATA
WE18, WE19
V2
Halfword
V2+2
Halfword
WE18, WE19
Figure 18. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses—
WSC = 2, SYNC = 1, DOL = 0
BCLK
WE5
WE4
ADDR Last Valid Addr
CS[x]
RW
LBA
Address V1
WE6
WE7
WE8
WE9
WE14
WE15
OE
EB[y]
WE13
WE12
WE24, WE25
ECB
WE22, WE23
WE17
V1+4 V1+8 V1+12
V1
DATA
WE16
WE17
WE16
Figure 19. Synchronous Memory TIming Diagram for Burst Write Access—
BCS = 1, WSC = 4, SYNC = 1, DOL = 0, PSR = 1
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
39
BCLK
WE4
ADDR/
Last
Valid
Addr
M_DATA
CS[x]
RW
WE17
WE5
Write Data
Address V1
WE16
WE6
WE7
WE8
WE9
Write
WE14
WE15
LBA
OE
EB[y]
WE12
WE13
Figure 20. Muxed A/D Mode Timing Diagram for Synchronous Write Access—
WSC = 7, LBA = 1, LBN = 1, LAH = 1
BCLK
WE4
ADDR/
Last
Valid
Addr
M_DATA
WE6
CS[x]
WE5
WE20, WE21
Address V1
Read Data
WE18, WE19
WE7
RW
WE14
WE15
LBA
WE10
OE
EB[y]
WE12
WE11
WE13
Figure 21. Muxed A/D Mode Timing Diagram for Synchronous Read Access—
WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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Freescale Semiconductor
Figure 22 through Figure 26, and Table 34 help to determine timing parameters relative chip select (CS)
state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing
parameters mentioned above.
CS [x]
WE31
ADDR
Last Valid Address
WE32
Next Address
Address V1
RW
WE39
WE40
WE35
WE36
WE37
WE38
LBA
OE
EB[y]
WE44
DATA
V1
WE43
Figure 22. Asynchronous Memory Read Access
CS[x]
MAXDI
WE31
D(V1)
Addr. V1
ADDR/
M_DATA
WE32A
WE
WE44
WE40
WE39
LBA
WE35A
WE36
OE
WE37
WE38
BE[y]
MAXCO
Figure 23. Asynchronous A/D muxed Read Access (RWSC = 5)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
41
CS[x]
WE31
ADDR
Last Valid Address
WE33
WE32
Next Address
Address V1
WE34
RW
WE39
WE40
WE45
WE46
LBA
OE
BE[y]
WE42
DATA
D(V1)
WE41
Figure 24. Asynchronous Memory Write Access
CS[x]
WE41
WE31
ADDR/
Addr. V1
M_DATA
WE32A
WE33
D(V1)
WE34
WE42
RW
WE40A
LBA
WE39
OE
WE45
WE46
BE[y]
WE42
Figure 25. Asynchronous A/D Mux Write Access
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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Freescale Semiconductor
CS [x]
WE31
ADDR
WE32
Last Valid Address
Next Address
Address V1
RW
WE39
WE40
WE35
WE36
WE37
WE38
LBA
OE
EB[y]
WE44
DATA
V1
WE43
WE48
DATA
WE47
Figure 26. DTACK Read Access
Table 34. WEIM Asynchronous Timing Parameters Relative Chip Select Table
Ref No.
Parameter
Determination By
Synchronous Measured
Parameters1
Min
Max
(If 133 MHz is
supported by SoC)
Unit
WE31
CS[x] valid to Address valid
WE4 – WE6 – CSA2
—
3 – CSA
ns
WE32
Address invalid to CS[x] invalid
WE7 – WE5 – CSN3
—
3 – CSN
ns
WE32A(
muxed
A/D
CS[x] valid to address invalid
—
ns
WE33
CS[x] valid to WE valid
WE8 – WE6 + (WEA – CSA)
—
3 + (WEA – CSA)
ns
WE34
WE invalid to CS[x] invalid
WE7 – WE9 + (WEN – CSN)
—
3 – (WEN_CSN)
ns
WE35
CS[x] valid to OE valid
WE10 – WE6 + (OEA – CSA)
—
3 + (OEA – CSA)
ns
WE35A
(muxed
A/D)
CS[x] valid to OE valid
WE10 – WE6 + (OEA + RLBN
+ RLBA + ADH + 1 – CSA)
–3 + (OEA +
RLBN + RLBA +
ADH + 1 – CSA)
3 + (OEA + RLBN +
RLBA + ADH + 1 –
CSA)
ns
WE36
OE invalid to CS[x] invalid
WE7 – WE11 + (OEN – CSN)
—
3 – (OEN – CSN)
ns
CS[x] valid to BE[y] valid (read WE12 – WE6 + (RBEA – CSA)
access)
—
3 + (RBEA4 – CSA)
ns
WE37
WE4 – WE7 + (LBN + LBA + 1 –3 + (LBN + LBA +
– CSA2)
1 – CSA)
WE38
BE[y] invalid to CS[x] invalid
(read access)
WE7 – WE13 + (RBEN – CSN)
—
3 – (RBEN5 – CSN)
ns
WE39
CS[x] valid to LBA valid
WE14 – WE6 + (LBA – CSA)
—
3 + (LBA – CSA)
ns
WE40
LBA invalid to CS[x] invalid
WE7 – WE15 – CSN
—
3 – CSN
ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
43
Table 34. WEIM Asynchronous Timing Parameters Relative Chip Select Table (continued)
Ref No.
Parameter
WE40A
(muxed
A/D)
CS[x] valid to LBA invalid
WE41
CS[x] valid to Output Data valid
WE41A CS[x] valid to Output Data valid
(muxed
A/D)
WE42
WE43
WE44
WE45
Output Data invalid to CS[x]
Invalid
Determination By
Synchronous Measured
Parameters1
Max
(If 133 MHz is
supported by SoC)
WE14 – WE6 + (LBN + LBA + 1 –3 + (LBN + LBA + 3 + (LBN + LBA + 1 –
– CSA)
1 – CSA)
CSA)
Unit
ns
WE16 – WE6 – WCSA
—
3 – WCSA
ns
WE16 – WE6 + (WLBN +
WLBA + ADH + 1 – WCSA)
—
3 + (WLBN + WLBA +
ADH + 1 – WCSA)
ns
WE17 – WE7 – CSN
—
3 – CSN
ns
MAXCO6 –
MAXCSO7 +
MAXDI8
—
ns
0
—
ns
—
3 + (WBEA – CSA)
ns
Input Data valid to CS[x] invalid MAXCO – MAXCSO + MAXDI
CS[x] invalid to Input Data
invalid
Min
0
CS[x] valid to BE[y] valid (write WE12 – WE6 + (WBEA – CSA)
access)
WE46
BE[y] invalid to CS[x] invalid
(write access)
WE7 – WE13 + (WBEN – CSN)
—
–3 + (WBEN – CSN)
ns
WE47
DTACK valid to CS[x] invalid
MAXCO – MAXCSO + MAXDTI
MAXCO6 –
MAXCSO7 +
MAXDTI9
—
ns
WE48
CS[x] Invalid to DTACK invalid
0
0
—
ns
1
For the value of parameters WE4–WE21, see column BCD = 0 in Table 33.
CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles.
3 CS Negation. This bit field determines when the CS signal is negated during read/write cycles.
4 BE Assertion. This bit field determines when the BE signal is asserted during read cycles.
5 BE Negation. This bit field determines when the BE signal is negated during read cycles.
6
Output maximum delay from internal driving ADDR/control FFs to chip outputs.
7 Output maximum delay from CS[x] internal driving FFs to CS[x] out.
8 DATA maximum delay from chip input data to its internal FF.
9 DTACK maximum delay from chip dtack input to its internal FF.
Note: All configuration parameters (CSA, CSN, WBEA, WBEN, LBA, LBN, OEN, OEA, RBEA, and RBEN) are in cycle units.
2
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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4.9.5.3
ESDCTL Electrical Specifications
Figure 27 through Figure 35 depict the timings pertaining to the ESDCTL module, which interfaces with
mobile DDR or SDR SDRAM. Table 35 through Table 45 list the timing parameters.
SD1
SDCLK
SDCLK
SD2
SD3
SD4
CS
SD5
RAS
SD4
SD5
SD4
CAS
SD4
SD5
SD5
WE
SD6
SD7
ADDR
ROW/BA
COL/BA
SD8
SD10
SD9
DQ
Data
SD4
DQM
Note: CKE is high during the read/write cycle.
SD5
Figure 27. SDRAM Read Cycle Timing Diagram
Table 35. DDR/SDR SDRAM Read Cycle Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Unit
SD1
SDRAM clock high-level width
tCH
3.4
4.1
ns
SD2
SDRAM clock low-level width
tCL
3.4
4.1
ns
SD3
SDRAM clock cycle time
tCK
7.0
—
ns
SD4
CS, RAS, CAS, WE, DQM, CKE setup time
tCMS
2.0
—
ns
SD5
CS, RAS, CAS, WE, DQM, CKE hold time
tCMH
1.8
—
ns
SD6
Address setup time
tAS
2.0
—
ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
45
Table 35. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
ID
1
Parameter
SD7
Address hold time
SD8
SDRAM access time
Symbol
Min.
Max.
Unit
tAH
1.8
—
ns
tAC
—
6.47
ns
SD9
1
Data out hold time
tOH
1.2
—
ns
SD10
Active to read/write command period
tRC
10
—
clock
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Table 44 and Table 45.
NOTE
SDR SDRAM CLK parameters are measured from the 50% point—that is,
high is defined as 50% of signal value and low is defined as 50% of signal
value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 35 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
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Freescale Semiconductor
SD1
SDCLK
SDCLK
SD2
SD3
SD4
CS
SD5
RAS
SD4
CAS
SD5
SD4
SD4
WE
SD5
SD5
SD7
SD6
ADDR
BA
COL/BA
ROW / BA
SD13
DQ
SD14
DATA
DQM
Figure 28. SDR SDRAM Write Cycle Timing Diagram
Table 36. SDR SDRAM Write Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Unit
SD1
SDRAM clock high-level width
tCH
0.45
0.55
ns
SD2
SDRAM clock low-level width
tCL
0.45
0.55
ns
SD3
SDRAM clock cycle time
tCK
7.0
—
ns
SD4
CS, RAS, CAS, WE, DQM, CKE setup time
tCMS
2.4
—
ns
SD5
CS, RAS, CAS, WE, DQM, CKE hold time
tCMH
1.4
—
ns
SD6
Address setup time
tAS
2.4
—
ns
SD7
Address hold time
tAH
1.4
—
ns
SD13
Data setup time
tDS
2.4
—
ns
SD14
Data hold time
tDH
1.4
—
ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
47
NOTE
Test conditions are: pin voltage 1.7 V–1.95 V, capacitance 15 pF for all pins
(both DDR and non-DDR pins), drive strength is high (7.2 mA). “High” is
defined as 80% of signal value and “low” is defined as 20% of signal value.
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value, and “low” is defined as 50% of
signal value. tCH + tCL will not exceed 7.5 ns for 133 MHz. DDR SDRAM
CLK parameters are measured at the crossing point of SDCLK and SDCLK
(inverted clock).
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 36 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
SD1
SDCLK
SDCLK
SD2
SD3
CS
RAS
SD11
CAS
SD10
SD10
WE
SD7
SD6
ADDR
BA
ROW/BA
Figure 29. SDRAM Refresh Timing Diagram
Table 37. SDRAM Refresh Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Unit
SD1
SDRAM clock high-level width
tCH
3.4
4.1
ns
SD2
SDRAM clock low-level width
tCL
3.4
4.1
ns
SD3
SDRAM clock cycle time
tCK
7.5
—
ns
SD6
Address setup time
tAS
1.8
—
ns
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Freescale Semiconductor
Table 37. SDRAM Refresh Timing Parameters (continued)
ID
Parameter
SD7
Address hold time
SD10
Precharge cycle period1
SD11
1
Auto precharge command period
1
Symbol
Min.
Max.
Unit
tAH
1.8
—
ns
tRP
1
4
clock
tRC
2
20
clock
SD10 and SD11 are determined by SDRAM controller register settings.
NOTE
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value and “low” is defined as 50% of
signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 37 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
SDCLK
CS
RAS
CAS
WE
ADDR
BA
SD16
CKE
SD16
Don’t care
Figure 30. SDRAM Self-Refresh Cycle Timing Diagram
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
49
NOTE
The clock will continue to run unless both CKEs are low. Then the clock will
be stopped in low state.
Table 38. SDRAM Self-Refresh Cycle Timing Parameters
ID
Parameter
SD16
CKE output delay time
Symbol
Min.
Max.
Unit
tCKS
1.8
—
ns
DDR1
SDCLK
SDCLK
DDR2
DDR4
DDR3
CS
DDR5
DDR4
RAS
DDR5
DDR4
CAS
DDR4
DDR5
DDR5
WE
CKE
DDR4
DDR6
ADDR
DDR7
ROW/BA
COL/BA
Figure 31. DDR2 SDRAM Basic Timing Parameters
Table 39. DDR2 SDRAM Timing Parameter Table
DDR2-400
ID
PARAMETER
Symbol
Unit
Min
Max
DDR1
SDRAM clock high-level width
tCH
0.45
0.55
tCK
DDR2
SDRAM clock low-level width
tCL
0.45
0.55
tCK
DDR3
SDRAM clock cycle time
tCK
7.0
8.0
ns
DDR4
CS, RAS, CAS, CKE, WE setup time
tIS1
1.5
—
ns
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Table 39. DDR2 SDRAM Timing Parameter Table
DDR2-400
ID
DDR5
PARAMETER
CS, RAS, CAS, CKE, WE hold time
Symbol
tIH1
Unit
Min
Max
1.25
—
ns
1
1.5
—
ns
1.5
—
ns
DDR6
Address output setup time
tIS
DDR7
Address output hold time
tIH1
NOTE
These values are for command/address slew rate of 1 V/ns and SDCLK,
SDCLK_B differential slew rate of 2 V/ns. For different values, use the
derating table.
Table 40. Derating Values for DDR2–400, DDR2–533
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
51
SDCLK
SDCLK_B
DDR21
DDR22
DQS (output)
DDR18
DDR17
DQ (output)
DDR20
DDR23
DDR17
DDR19
DDR18
Data
Data
Data
Data
Data
Data
Data
Data
DM
DM
DM
DM
DM
DM
DM
DM
DQM (output)
DDR17
DDR18
DDR17
DDR18
Figure 32. DDR2 SDRAM Write Cycle Timing Diagram
Table 41. DDR2 SDRAM Write Cycle Parameters
DDR2-400
ID
PARAMETER
Symbol
Unit
Min
Max
DDR17 DQ and DQM setup time to DQS (single-ended strobe)
tDS1(base)
0.5
—
ns
DDR18 DQ and DQM hold time to DQS (single-ended strobe)
tDH1(base)
0.5
—
ns
DDR19 Write cycle DQS falling edge to SDCLK output setup time.
tDSS
0.2
—
tCK
DDR20 Write cycle DQS falling edge to SDCLK output hold time.
tDSH
0.2
—
tCK
DDR21 DQS latching rising transitions to associated clock edges
tDQSS
–0.25
0.25
tCK
DDR22 DQS high level width
tDQSH
0.35
—
tCK
DDR23 DQS low level width
tDQSL
0.35
—
tCK
NOTE
These values are for DQ/DM slew rate of 1 V/ns and DQS slew rate of
1 V/ns. For different values use the derating table.
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Table 42. DDR Single-ended Slew Rate
NOTE
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value and “low” is defined as 50% of
signal value. DDR SDRAM CLK parameters are measured at the crossing
point of SDCLK and SDCLK (inverted clock).
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended
drive strength is Medium for SDCLK and High for Address and controls.
SDCLK
SDCLK_B
DDR26
DQS (input)
DDR25
DDR24
DQ (input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Figure 33. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram
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53
Table 43. DDR2 SDRAM Read Cycle Parameter Table
DDR2-400
ID
PARAMETER
Symbol
DDR24
DQS – DQ Skew (defines the Data valid window in
read cycles related to DQS).
DDR25
DQS DQ in HOLD time from DQS1
DDR26
DQS output access time from SDCLK posedge
Unit
Min
Max
tDQSQ
—
0.35
ns
tQH
2.925
—
ns
tDQSCK
–0.5
0.5
ns
1
The value was calculated for an SDCLK frequency of 133 MHz by the formula tQH = tHP – tQHS = min (tCL,tCH) – tQHS =
0.45 × tCK – tQHS = 0.45 × 7.5 – 0.45 = 2.925 ns.
NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value. DDR SDRAM CLK parameters are measured at the
crossing point of SDCLK and SDCLK (inverted clock).
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended
drive strength is Medium for SDCLK and High for Address and controls.
SDCLK
SDCLK
SD19
DQS (output)
SD18
SD17
DQ (output)
DQM (output)
SD17
SD20
SD18
Data
Data
Data
Data
Data
Data
Data
Data
DM
DM
DM
DM
DM
DM
DM
DM
SD17
SD17
SD18
SD18
Figure 34. Mobile DDR SDRAM Write Cycle Timing Diagram
Table 44. Mobile DDR SDRAM Write Cycle Timing Parameters1
ID
Parameter
Symbol
Min.
Max.
Unit
SD17
DQ and DQM setup time to DQS
tDS
0.95
—
ns
SD18
DQ and DQM hold time to DQS
tDH
0.95
—
ns
SD19
Write cycle DQS falling edge to SDCLK output delay time.
tDSS
1.8
—
ns
SD20
Write cycle DQS falling edge to SDCLK output hold time.
tDSH
1.8
—
ns
1
Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
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NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 44 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
SDCLK
SDCLK
SD23
DQS (input)
SD22
SD21
DQ (input)
Data
Data
Data
Data
Data
Data
Data
Data
Figure 35. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
Table 45. Mobile DDR SDRAM Read Cycle Timing Parameters
ID
Parameter
SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS).
SD22 DQS DQ HOLD time from DQS
SD23 DQS output access time from SDCLK posedge
Symbol
Min. Max. Unit
tDQSQ
—
0.85
ns
tQH
2.3
—
ns
tDQSCK
—
6.7
ns
NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value, and “low” is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 45 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
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4.9.6
Enhanced Serial Audio Interface (ESAI) Timing Specifications
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 46 shows the interface timing values. The number field in the table refers to timing signals
found in Figure 36 and Figure 37.
Table 46. Enhanced Serial Audio Interface Timing
Characteristics1,2
No.
Symbol
Expression2
Min.
Max.
Condition3 Unit
tSSICC
4 × Tc
4 × Tc
30.0
30.0
—
—
i ck
i ck
62
Clock cycle4
63
Clock high period
• For internal clock
—
2 × Tc − 9.0
6
—
—
• For external clock
—
2 × Tc
15
—
—
Clock low period
• For internal clock
—
2 × Tc − 9.0
6
—
—
• For external clock
—
2 × Tc
15
—
—
65
SCKR rising edge to FSR out (bl) high
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
66
SCKR rising edge to FSR out (bl) low
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
67
SCKR rising edge to FSR out (wr) high5
—
—
—
—
—
—
19.0
9.0
x ck
i ck a
ns
68
SCKR rising edge to FSR out (wr) low5
—
—
—
—
—
—
19.0
9.0
x ck
i ck a
ns
69
SCKR rising edge to FSR out (wl) high
—
—
—
—
—
—
16.0
6.0
x ck
i ck a
ns
70
SCKR rising edge to FSR out (wl) low
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
71
Data in setup time before SCKR (SCK in synchronous
mode) falling edge
—
—
—
—
12.0
19.0
—
—
x ck
i ck
ns
72
Data in hold time after SCKR falling edge
—
—
—
—
3.5
9.0
—
—
x ck
i ck
ns
73
FSR input (bl, wr) high before SCKR falling edge5
—
—
—
—
2.0
12.0
—
—
x ck
i ck a
ns
74
FSR input (wl) high before SCKR falling edge
—
—
—
—
2.0
12.0
—
—
x ck
i ck a
ns
75
FSR input hold time after SCKR falling edge
—
—
—
—
2.5
8.5
—
—
x ck
i ck a
ns
78
SCKT rising edge to FST out (bl) high
—
—
—
—
—
—
18.0
8.0
x ck
i ck
ns
79
SCKT rising edge to FST out (bl) low
—
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
64
ns
ns
ns
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Table 46. Enhanced Serial Audio Interface Timing (continued)
Characteristics1,2
No.
1
2
3
4
5
6
Symbol
Expression2
Min.
Max.
Condition3 Unit
80
SCKT rising edge to FST out (wr) high5
—
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
81
SCKT rising edge to FST out (wr) low5
—
—
—
—
—
—
22.0
12.0
x ck
i ck
ns
82
SCKT rising edge to FST out (wl) high
—
—
—
—
—
—
19.0
9.0
x ck
i ck
ns
83
SCKT rising edge to FST out (wl) low
—
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
84
SCKT rising edge to data out enable from high
impedance
—
—
—
—
—
—
22.0
17.0
x ck
i ck
ns
86
SCKT rising edge to data out valid
—
—
—
—
—
—
18.0
13.0
x ck
i ck
ns
87
SCKT rising edge to data out high impedance 67
—
—
—
—
—
—
21.0
16.0
x ck
i ck
ns
89
FST input (bl, wr) setup time before SCKT falling edge5
—
—
—
—
2.0
18.0
—
—
x ck
i ck
ns
90
FST input (wl) setup time before SCKT falling edge
—
—
—
—
2.0
18.0
—
—
x ck
i ck
ns
91
FST input hold time after SCKT falling edge
—
—
—
—
4.0
5.0
—
—
x ck
i ck
ns
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
Periodically sampled and not 100% tested.
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62
63
64
SCKT
(Input/Output)
78
79
FST (Bit)
Out
82
FST (Word)
Out
83
86
86
84
87
First Bit
Data Out
Last Bit
89
91
FST (Bit) In
90
91
FST (Word) In
Figure 36. ESAI Transmitter Timing
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62
63
64
SCKR
(Input/Output)
65
66
FSR (Bit)
Out
69
70
FSR (Word)
Out
72
71
Data In
First Bit
Last Bit
75
73
FSR (Bit)
In
74
75
FSR (Word)
In
Figure 37. ESAI Receiver Timing
4.9.7
eSDHCv2 AC Electrical Specifications
Figure 38 depicts the timing of eSDHCv2, and Table 47 lists the eSDHCv2 timing characteristics. The
following definitions apply to values and signals described in Table 47:
• LS: low-speed mode. Low-speed card can tolerate a clock up to 400 kHz.
• FS: full-speed mode. For a full-speed MMC card, the card clock can reach 20 MHz; a full-speed
SD/SDIO card can reach 25 MHz.
• HS: high-speed mode. For a high-speed MMC card, the card clock can reach 52 MHz; SD/SDIO
can reach 50 MHz.
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SD4
SD2
SD1
SD5
SDHCx_CLK
SD3
output from eSDHCv2 to card
SDHCx_CMD
SDHCx_DAT_0
SDHCx_DAT_1
SD6
SDHCx_DAT_7
SD7
output from card to eSDHCv2
SD8
SDHCx_CMD
SDHCx_DAT_0
SDHCx_DAT_1
SDHCx_DAT_7
Figure 38. eSDHCv2 Timing
Table 47. eSDHCv2 Interface Timing Specification
ID
Parameter
Symbols Min. Max. Unit
Card Input Clock
fPP1
0
Clock frequency (SD/SDIO Full Speed/High Speed)
fPP2
0
25/50 MHz
Clock frequency (MMC Full Speed/High Speed)
fPP3
0
20/52 MHz
Clock frequency (Identification Mode)
fOD
100
400
kHz
SD2 Clock Low time
tWL
7
—
ns
SD3 Clock high time
tWH
7
—
ns
SD4 Clock rise time
tTLH
—
3
ns
SD5 Clock fall time
tTHL
—
3
ns
tOD
–3
3
ns
SD7 eSDHC input setup time
tISU
5
—
ns
SD8 eSDHC input hold time
tIH4
2.5
—
ns
SD1 Clock frequency (Low Speed)
400
kHz
eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)
SD6 eSDHC output delay
eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)
1
2
3
4
In low-speed mode, the card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal-speed mode for the SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
In normal-speed mode for MMC card, clock frequency can be any value between 0 and 20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
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4.9.8
Fast Ethernet Controller (FEC) AC Electrical Specifications
This section describes the electrical information of the FEC module. The FEC is designed to support both
10- and 100-Mbps Ethernet networks. An external transceiver interface and transceiver function are
required to complete the interface to the media. The FEC supports the 10/100 Mbps Media Independent
Interface (MII) using a total of 18 pins. The 10-Mbps 7-wire interface that is restricted to a 10-Mbps data
rate uses seven of the MII pins for connection to an external Ethernet transceiver.
4.9.8.1
FEC AC Timing
This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.
4.9.8.2
MII Receive Signal Timing
The MII receive timing signals consist of FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_RX_CLK frequency. Table 48 lists MII receive channel timings.
Table 48. MII Receive Signal Timing
Characteristic1
Num.
Min.
Max.
Unit
M1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
—
ns
M2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
—
ns
M3
FEC_RX_CLK pulse width high
35%
65%
FEC_RX_CLK period
M4
FEC_RX_CLK pulse width low
35%
65%
FEC_RX_CLK period
1 FEC_RX_DV,
FEC_RX_CLK, and FEC_RXD0 have the same timing when in 10 Mbps 7-wire interface mode.
Figure 39 shows the MII receive signal timings listed in Table 48.
M3
FEC_RX_CLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M1
M2
Figure 39. MII Receive Signal Timing Diagram
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4.9.8.3
MII Transmit Signal Timing
The transmitter timing signals consist of FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency. Table 49 lists MII transmit channel timings.
Table 49. MII Transmit Signal Timing
Characteristic1
Num
Min.
Max.
Unit
M5
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
invalid
5
—
ns
M6
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
valid
—
20
ns
M7
FEC_TX_CLK pulse width high
35%
65%
FEC_TX_CLK period
M8
FEC_TX_CLK pulse width low
35%
65%
FEC_TX_CLK period
1 FEC_TX_EN,
FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode.
Figure 40 shows the MII transmit signal timings listed in Table 49.
M7
FEC_TX_CLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M6
Figure 40. MII Transmit Signal Timing Diagram
4.9.8.4
MII Asynchronous Inputs Signal Timing
The MII asynchronous timing signals are FEC_CRS and FEC_COL. Table 50 lists MII asynchronous
inputs signal timing.
Table 50. MII Asynch Inputs Signal Timing
1
Num
Characteristic
Min.
Max.
Unit
M91
FEC_CRS to FEC_COL minimum pulse width
1.5
—
FEC_TX_CLK period
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
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Figure 41 shows MII asynchronous input timings listed in Table 50.
FEC_CRS, FEC_COL
M9
Figure 41. MII Asynch Inputs Timing Diagram
4.9.8.5
MII Serial Management Channel Timing
Serial management channel timing is accomplished using FEC_MDIO and FEC_MDC. The FEC
functions correctly with a maximum MDC frequency of 2.5 MHz. Table 51 lists MII serial management
channel timings.
The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII
specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz.
Table 51. MII Transmit Signal Timing
Num
Characteristic
Min.
Max.
Units
M10
FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11
FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
—
5
ns
M12
FEC_MDIO (input) to FEC_MDC rising edge setup
18
—
ns
M13
FEC_MDIO (input) to FEC_MDC rising edge hold
0
—
ns
M14
FEC_MDC pulse width high
40%
60%
FEC_MDC period
M15
FEC_MDC pulse width low
40%
60%
FEC_MDC period
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Figure 42 shows MII serial management channel timings listed in Table 51.
M14
M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 42. MII Serial Management Channel Timing Diagram
4.9.9
FIR Electrical Specifications
FIR implements asynchronous infrared protocols (FIR, MIR) defined by IrDA® (Infrared Data
Association). Refer to the IrDA® website for details on FIR and MIR protocols.
4.9.10
FlexCAN Module AC Electrical Specifications
The electrical characteristics are related to the CAN transceiver outside the chip. The i.MX35 has two
CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other
I/O pins. Refer to the IOMUX chapter of the MCIMX35 Multimedia Applications Processor Reference
Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN,
respectively.
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4.9.11
I2C AC Electrical Specifications
This section describes the electrical characteristics of the I2C module.
4.9.11.1
I2C Module Timing
Figure 43 depicts the timing of the I2C module. Table 52 lists the I2C module timing parameters.
I2CLK
IC11
IC10
I2DAT
IC2
START
IC7
IC4
IC8
IC10
IC11
IC6
IC9
IC3
STOP
START
START
IC5
IC1
Figure 43. I2C Bus Timing Diagram
Table 52. I2C Module Timing Parameters
ID
1
2
3
Standard Mode
Fast Mode
Min.
Max.
Min.
Max.
Parameter
Unit
IC1
I2CLK cycle time
10
—
2.5
—
μs
IC2
Hold time (repeated) START condition
4.0
—
0.6
—
μs
IC3
Set-up time for STOP condition
4.0
—
0.6
—
μs
IC4
Data hold time
01
3.452
01
0.92
μs
IC5
HIGH Period of I2CLK Clock
4.0
—
0.6
—
μs
IC6
LOW Period of the I2CLK Clock
4.7
—
1.3
—
μs
IC7
Set-up time for a repeated START condition
4.7
—
0.6
—
μs
IC8
Data set-up time
250
—
1003
—
ns
IC9
Bus free time between a STOP and START condition
4.7
—
1.3
—
μs
IC10 Rise time of both I2DAT and I2CLK signals
—
1000
—
300
ns
IC11 Fall time of both I2DAT and I2CLK signals
—
300
—
300
ns
IC12 Capacitive load for each bus line (Cb)
—
400
—
400
pF
A device must internally provide a hold time of at least 300 ns for the I2DAT signal in order to bridge the undefined region of
the falling edge of I2CLK.
The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the I2CLK line is released.
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4.9.12
IPU—Sensor Interfaces
This section contains a list of supported camera sensors, a functional description, and the electrical
characteristics.
4.9.12.1
Supported Camera Sensors
Table 53 lists the known supported camera sensors at the time of publication.
Table 53. Supported Camera Sensors1
Vendor
Model
Conexant
CX11646, CX204902, CX204502
Agilant
HDCP–2010, ADCS–10212, ADCS–10212
Toshiba
TC90A70
ICMedia
ICM202A, ICM1022
iMagic
IM8801
Transchip
TC5600, TC5600J, TC5640, TC5700, TC6000
Fujitsu
MB86S02A
Micron
MI-SOC–0133
Matsushita
MN39980
STMicro
W6411, W6500, W65012, W66002, W65522, STV09742
OmniVision
OV7620, OV6630, OV2640
Sharp
LZ0P3714 (CCD)
Motorola
MC30300 (Python)2, SCM200142, SCM201142, SCM221142, SCM200272
National Semiconductor
LM96182
1
2
Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only
camera suppliers.
These sensors have not been validated at the time of publication.
4.9.12.2
Functional Description
There are three timing modes supported by the IPU.
4.9.12.2.1
Pseudo BT.656 Video Mode
Smart camera sensors, which typically include image processing capability, support video mode transfer
operations. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC
signals. The timing syntax is defined by the BT.656 standard.
This operation mode follows the recommendations of the ITU BT.656 specifications. The only control
signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream.
An active line starts with a SAV code and ends with an EAV code. In some cases, digital blanking is
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inserted in between EAV and SAV code. The CSI decodes and filters out the timing coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.
4.9.12.2.2
Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure 44.
Active Line
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_HSYNC
SENSB_PIX_CLK
SENSB_DATA[9:0]
invalid
invalid
1st byte
1st byte
Figure 44. Gated Clock Mode Timing Diagram
A frame starts with a rising edge on SENSB_VSYNC (all the timing corresponds to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. The pixel clock
is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of the line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For the next line, the SENSB_HSYNC timing repeats. For the next frame,
the SENSB_VSYNC timing repeats.
4.9.12.2.3
Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.9.12.2.2, “Gated Clock Mode”),
except for the SENSB_HSYNC signal, which is not used. See Figure 45. All incoming pixel clocks are
valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_DATA[7:0]
invalid
invalid
1st byte
1st byte
Figure 45. Non-Gated Clock Mode Timing Diagram
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The timing described in Figure 45 is that of a Motorola sensor. Some other sensors may have slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.9.12.3
Electrical Characteristics
Figure 46 depicts the sensor interface timing, and Table 54 lists the timing parameters.
1/IP1
SENSB_MCLK
(Sensor Input)
SENSB_PIX_CLK
(Sensor Output)
IP3
IP2
1/IP4
SENSB_DATA,
SENSB_VSYNC,
SENSB_HSYNC
Figure 46. Sensor Interface Timing Diagram
Table 54. Sensor Interface Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
IP1
Sensor input clock frequency
Fmck
0.01
133
MHz
IP2
Data and control setup time
Tsu
5
—
ns
IP3
Data and control holdup time
Thd
3
—
ns
IP4
Sensor output (pixel) clock frequency
Fpck
0.01
133
MHz
4.9.13
IPU—Display Interfaces
This section describes the following types of display interfaces:
• Section 4.9.13.1, “Synchronous Interfaces”
• Section 4.9.13.2, “Interface to Sharp HR-TFT Panels”
• Section 4.9.13.3, “Synchronous Interface to Dual-Port Smart Displays”
• Section 4.9.13.4, “Asynchronous Interfaces”
• Section 4.9.13.5, “Serial Interfaces, Functional Description”
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4.9.13.1
Synchronous Interfaces
This section discusses the interfaces to active matrix TFT LCD panels, Sharp HR-TFT, and dual-port smart
displays.
4.9.13.1.4
Interface to Active Matrix TFT LCD Panels, Functional Description
Figure 47 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
signals are shown with negative polarity. The sequence of events for active matrix interface timing is as
follows:
• DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, DISPB_D3_CLK runs continuously.
• DISPB_D3_HSYNC causes the panel to start a new line.
• DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted to the display. When disabled, the data is invalid and the trace is off.
DISPB_D3_VSYNC
DISPB_D3_HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n – 1
LINE n
DISPB_D3_HSYNC
DISPB_D3_DRDY
1
2
3
m–1
m
DISPB_D3_CLK
DISPB_D3_DATA
Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels
4.9.13.1.5
Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 48 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
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of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC
and DISPB_D3_DRDY signals.
IP7
IP6
IP9
IP10
IP8
Start of line
IP5
DISPB_D3_CLK
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_DATA
Figure 48. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 49 depicts the vertical timing (timing of one frame). All figure parameters shown are
programmable.
End of frame
Start of frame
IP13
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
IP11
IP15
IP14
IP12
Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse
Table 55 shows timing parameters of signals presented in Figure 48 and Figure 49.
Table 55. Synchronous Display Interface Timing Parameters—Pixel Level
ID
Parameter
Symbol
Value
Units
IP5
Display interface clock period
Tdicp
Tdicp1
ns
IP6
Display pixel clock period
Tdpcp
(DISP3_IF_CLK_CNT_D + 1) × Tdicp
ns
IP7
Screen width
Tsw
(SCREEN_WIDTH + 1) × Tdpcp
ns
IP8
HSYNC width
Thsw
(H_SYNC_WIDTH + 1) × Tdpcp
ns
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Table 55. Synchronous Display Interface Timing Parameters—Pixel Level (continued)
ID
1
Parameter
Symbol
Value
Units
IP9
Horizontal blank interval 1
Thbi1
BGXP × Tdpcp
ns
IP10
Horizontal blank interval 2
Thbi2
(SCREEN_WIDTH – BGXP – FW) × Tdpcp
ns
IP11
HSYNC delay
Thsd
H_SYNC_DELAY × Tdpcp
ns
IP12
Screen height
Tsh
(SCREEN_HEIGHT + 1) × Tsw
ns
IP13
VSYNC width
Tvsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH + 1) × Tdpcp
else
(V_SYNC_WIDTH + 1) × Tsw
ns
IP14
Vertical blank interval 1
Tvbi1
BGYP × Tsw
ns
IP15
Vertical blank interval 2
Tvbi2
(SCREEN_HEIGHT – BGYP – FH) × Tsw
ns
Display interface clock period immediate value
Display interface clock period average value.
DISP3_IF_CLK_PER_WR
Tdicp = T HSP_CLK ⋅ -----------------------------------------------------------------HSP_CLK_PERIOD
Figure 50 depicts the synchronous display interface timing for access level, and Table 56 lists the timing
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
IP20
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
other controls
DISPB_D3_CLK
IP16
IP17
IP19
IP18
DISPB_DATA
Figure 50. Synchronous Display Interface Timing Diagram—Access Level
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Table 56. Synchronous Display Interface Timing Parameters—Access Level
ID
Parameter
Symbol
Typ.1
Min.
Max.
Units
IP16 Display interface clock low time
Tckl
Tdicd – Tdicu – 1.5
Tdicd2 – Tdicu3
Tdicd – Tdicu + 1.5
ns
IP17 Display interface clock high time
Tckh
Tdicp – Tdicd +
Tdicu – 1.5
Tdicp – Tdicd +
Tdicu
Tdicp – Tdicd +
Tdicu + 1.5
ns
IP18 Data setup time
Tdsu
Tdicd – 3.5
Tdicu
—
ns
IP19 Data holdup time
Tdhd
Tdicp – Tdicd – 3.5
Tdicp – Tdicu
—
ns
IP20 Control signals setup time to
display interface clock
Tcsu
Tdicd – 3.5
Tdicu
—
ns
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
Display interface clock down time
2
1
2 ⋅ DISP3_IF_CLK_DOWN_WR
Tdicd = --- T HSP_CLK ⋅ ceil --------------------------------------------------------------------------------2
HSP_CLK_PERIOD
3
Display interface clock up time
1
2 ⋅ DISP3_IF_CLK_UP_WR
Tdicu = --- T HSP_CLK ⋅ ceil ---------------------------------------------------------------------2
HSP_CLK_PERIOD
where CEIL(X) rounds the elements of X to the nearest integers toward infinity.
4.9.13.2
Interface to Sharp HR-TFT Panels
Figure 51 depicts the Sharp HR-TFT panel interface timing, and Table 57 lists the timing parameters. The
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
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Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” The timing
images correspond to straight polarity of the Sharp signals.
Horizontal timing
DISPB_D3_CLK
D1 D2
DISPB_D3_DATA
DISPB_D3_SPL
IP21
D320
1 DISPB_D3_CLK period
DISPB_D3_HSYNC
IP23
IP22
DISPB_D3_CLS
IP24
DISPB_D3_PS
IP25
IP26
DISPB_D3_REV
Example is drawn with FW + 1 = 320 pixel/line, FH + 1 = 240 lines.
SPL pulse width is fixed and aligned to the first data of the line.
REV toggles every HSYNC period.
Figure 51. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
Table 57. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
ID
Parameter
Symbol
Value
Units
IP21
SPL rise time
Tsplr
(BGXP – 1) × Tdpcp
ns
IP22
CLS rise time
Tclsr
CLS_RISE_DELAY × Tdpcp
ns
IP23
CLS fall time
Tclsf
CLS_FALL_DELAY × Tdpcp
ns
IP24
CLS rise and PS fall time
Tpsf
PS_FALL_DELAY × Tdpcp
ns
IP25
PS rise time
Tpsr
PS_RISE_DELAY × Tdpcp
ns
IP26
REV toggle time
Trev
REV_TOGGLE_DELAY × Tdpcp
ns
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4.9.13.3
Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are
identical to parameters of the synchronous interface. See Section 4.9.13.1.5, “Interface to Active Matrix
TFT LCD Panels, Electrical Characteristics.”
4.9.13.3.6
Interface to a TV Encoder—Functional Description
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits
D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 52 depicts the
interface timing.
• The frequency of the clock DISPB_D3_CLK is 27 MHz.
• The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.
• The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It
remains low for a single clock cycle.
• The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC
signal. It remains low for at least one clock cycle.
— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC
and DISPB_D3_HSYNC coincide.
— At a transition to an even field (of the same frame), they do not coincide.
• The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC
signal being high.
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DISPB_D3_CLK
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_DRDY
DISPB_DATA
Cb
Y
Cr
Y
Cb
Y
Cr
Pixel Data Timing
DISPB_D3_HSYNC
523
524
525
1
2
3
5
4
6
10
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
261
262
Odd Field
263
264
265
266
267
268
269
273
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
Odd Field
Line and Field Timing - NTSC
621
DISPB_D3_HSYNC
622
623
624
625
1
3
2
4
23
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
308
309
Odd Field
310
311
312
313
314
315
316
336
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
Odd Field
Line and Field Timing - PAL
Figure 52. TV Encoder Interface Timing Diagram
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4.9.13.3.7
Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display
characteristics. See Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical
Characteristics.”
4.9.13.4
Asynchronous Interfaces
This section discusses the asynchronous parallel and serial interfaces.
4.9.13.4.8
Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces:
• System 80 interface
— Type 1 (sampling with the chip select signal) with and without byte enable signals.
— Type 2 (sampling with the read and write signals) with and without byte enable signals.
• System 68k interface
— Type 1 (sampling with the chip select signal) with or without byte enable signals.
— Type 2 (sampling with the read and write signals) with or without byte enable signals.
For each of four system interfaces, there are three burst modes:
1. Burst mode without a separate clock—The burst length is defined by the corresponding parameters
of the IDMAC (when data is transferred from the system memory) or by the HBURST signal (when
the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type
1 interfaces, data is sampled by the CS signal and other control signals change only when transfer
direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals
(system 80) or by the ENABLE signal (system 68k), and the CS signal stays active during the
whole burst.
2. Burst mode with the separate clock DISPB_BCLK—In this mode, data is sampled with the
DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are
changed simultaneously with data when the bus state (read, write or wait) is altered. The CS
signals and other controls move to non-active state after burst has been completed.
3. Single access mode—In this mode, slave AHB and DMA burst are broken to single accesses. The
data is sampled with CS or other controls according to the interface type as described above. All
controls (including CS) become non-active for one display interface clock after each access. This
mode corresponds to the ATI single access mode.
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 53,
Figure 54, Figure 55, and Figure 56. These timing images correspond to active-low DISPB_Dn_CS,
DISPB_Dn_WR and DISPB_Dn_RD signals.
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Additionally, the IPU allows a programmable pause between two bursts. The pause is defined in the
HSP_CLK cycles. It allows the prevention of timing violation between two sequential bursts or two
accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by CS signal
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 53. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram
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DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by WR/RD signals
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 54. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram
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DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by CS signal
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 55. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram
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DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by ENABLE signal
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 56. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram
Display read operation can be performed with wait states when each read access takes up to 4 display
interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the
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DI_DISPn_TIME_CONF_3 registers (n = 0,1,2). Figure 57 shows the timing of the parallel interface with
read wait states.
WRITE OPERATION
READ OPERATION
DISP0_RD_WAIT_ST=00
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISP0_RD_WAIT_ST=01
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISP0_RD_WAIT_ST=10
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
Figure 57. Parallel Interface Timing Diagram—Read Wait States
4.9.13.4.9
Parallel Interfaces, Electrical Characteristics
Figure 58, Figure 60, Figure 59, and Figure 61 depict timing of asynchronous parallel interfaces based on
the system 80 and system 68k interfaces. Table 58 lists the timing parameters at display access level. All
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timing images are based on active low control signals (signal polarity is controlled via the
DI_DISP_SIG_POL register).
IP28, IP27
DISPB_PAR_RS
DISPB_RD (READ_L)
DISPB_DATA[17]
(READ_H)
IP35, IP33
IP36, IP34
DISPB_D#_CS
DISPB_WR (WRITE_L)
DISPB_DATA[16]
(WRITE_H)
IP31, IP29
IP32, IP30
read point
IP38
IP37
DISPB_DATA
(Input)
Read Data
IP40
IP39
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 58. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
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IP28, IP27
DISPB_PAR_RS
DISPB_D#_CS
IP35, IP33
IP36, IP34
DISPB_RD (READ_L)
DISPB_DATA[17]
(READ_H)
DISPB_WR (WRITE_L)
DISPB_DATA[16]
(WRITE_H)
IP31, IP29
IP32, IP30
read point
IP37
DISPB_DATA
(Input)
IP38
Read Data
IP39
IP40
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 59. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
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IP28, IP27
DISPB_PAR_RS
DISPB_RD (ENABLE_L)
DISPB_DATA[17]
(ENABLE_H)
IP35,IP33
IP36, IP34
DISPB_D#_CS
DISPB_WR
(READ/WRITE)
IP31, IP29
IP32, IP30
read point
IP37
DISPB_DATA
(Input)
IP38
Read Data
IP39
IP40
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 60. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
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IP28, IP27
DISPB_PAR_RS
DISPB_D#_CS
IP35,IP33
IP36, IP34
DISPB_RD (ENABLE_L)
DISPB_DATA[17]
(ENABLE_H)
DISPB_WR
(READ/WRITE)
IP32, IP30
IP31, IP29
read point
IP38
IP37
DISPB_DATA
(Input)
Read Data
IP39
IP40
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 61. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram
Table 58. Asynchronous Parallel Interface Timing Parameters—Access Level
ID
Parameter
IP27 Read system cycle time
IP28 Write system cycle time
Symbol
Tcycr
Tcycw
Min.
Typ.1
Tdicpr – 1.5
Tdicpr2
Tdicpw – 1.5
Tdicpw3
Max.
5
Units
Tdicpr + 1.5
ns
Tdicpw + 1.5
ns
Tdicdr – Tdicur + 1.5
ns
IP29 Read low pulse width
Trl
Tdicdr – Tdicur – 1.5
Tdicdr4
IP30 Read high pulse width
Trh
Tdicpr – Tdicdr +
Tdicur – 1.5
Tdicpr – Tdicdr + Tdicpr – Tdicdr + Tdicur
Tdicur
+ 1.5
ns
IP31 Write low pulse width
Twl
Tdicdw – Tdicuw
– 1.5
Tdicdw6 –
Tdicuw7
ns
IP32 Write high pulse width
Twh
Tdicpw – Tdicdw +
Tdicuw – 1.5
Tdicpw – Tdicdw Tdicpw – Tdicdw +
+ Tdicuw
Tdicuw + 1.5
ns
– Tdicur
Tdicdw – Tdicuw + 1.5
IP33 Controls setup time for read
Tdcsr
Tdicur – 1.5
Tdicur
—
ns
IP34 Controls hold time for read
Tdchr
Tdicpr – Tdicdr – 1.5
Tdicpr – Tdicdr
—
ns
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Table 58. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)
ID
Parameter
Symbol
Typ.1
Min.
Max.
Units
IP35 Controls setup time for write
Tdcsw
Tdicuw – 1.5
Tdicuw
—
ns
IP36 Controls hold time for write
Tdchw
Tdicpw – Tdicdw – 1.5
Tdicpw – Tdicdw
—
ns
IP37 Slave device data delay8
Tracc
0
—
Tdrp9 – Tlbd10 – Tdicur –
1.5
ns
IP38 Slave device data hold time8
Troh
Tdrp – Tlbd – Tdicdr
+ 1.5
—
Tdicpr – Tdicdr – 1.5
ns
IP39 Write data setup time
Tds
Tdicdw – 1.5
Tdicdw
—
ns
IP40 Write data hold time
Tdh
Tdicpw – Tdicdw – 1.5
Tdicpw – Tdicdw
—
ns
Tdicpr – 1.5
Tdicpr
Tdicpr + 1.5
ns
Tdicpw Tdicpw – 1.5
Tdicpw
Tdicpw + 1.5
ns
Tdicdr
Tdicdr – 1.5
Tdicdr
Tdicdr + 1.5
ns
Tdicur
Tdicur – 1.5
Tdicur
Tdicur + 1.5
ns
Tdicdw Tdicdw – 1.5
Tdicdw
Tdicdw + 1.5
ns
Tdicuw Tdicuw – 1.5
Tdicuw
Tdicuw + 1.5
ns
Tdrp
Tdrp + 1.5
ns
IP41 Read
period2
Tdicpr
IP42 Write period3
IP43 Read down time4
5
IP44 Read up time
IP45 Write down
IP46 Write up
time6
time7
IP47 Read time point9
Tdrp
Tdrp – 1.5
1The
exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device-specific.
2 Display interface clock period value for read:
DISP#_IF_CLK_PER_RD
Tdicpr = T HSP_CLK ⋅ ceil ---------------------------------------------------------------HSP_CLK_PERIOD
3
Display interface clock period value for write:
DISP#_IF_CLK_PER_WR
Tdicpw = T HSP_CLK ⋅ ceil -----------------------------------------------------------------HSP_CLK_PERIOD
4
Display interface clock down time for read:
1
2 ⋅ DISP#_IF_CLK_DOWN_RD
Tdicdr = --- T HSP_CLK ⋅ ceil ------------------------------------------------------------------------------2
HSP_CLK_PERIOD
5
Display interface clock up time for read:
1
2 ⋅ DISP#_IF_CLK_UP_RD
Tdicur = --- T HSP_CLK ⋅ ceil -------------------------------------------------------------------2
HSP_CLK_PERIOD
6
Display interface clock down time for write:
1
2 ⋅ DISP#_IF_CLK_DOWN_WR
Tdicdw = --- T
⋅ ceil --------------------------------------------------------------------------------2 HSP_CLK
HSP_CLK_PERIOD
7
Display interface clock up time for write:
1
2 ⋅ DISP#_IF_CLK_UP_WR
Tdicuw = --- T HSP_CLK ⋅ ceil ---------------------------------------------------------------------2
HSP_CLK_PERIOD
8
This parameter is a requirement to the display connected to the IPU
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9
Data read point
Tdrp = T
10
HSP_CLK
DISP#_READ_EN
⋅ ceil -------------------------------------------------HSP_CLK_PERIOD
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device – level output delay, board delays, a device – level input delay, an IPU input delay. This value is device specific.
The following parameters are programmed via the DI_DISP#_TIME_CONF_1,
DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers:
• DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD
• HSP_CLK_PERIOD
• DISP#_IF_CLK_DOWN_WR
• DISP#_IF_CLK_UP_WR
• DISP#_IF_CLK_DOWN_RD
• DISP#_IF_CLK_UP_RD
• DISP#_READ_EN
4.9.13.5
Serial Interfaces, Functional Description
The IPU supports the following types of asynchronous serial interfaces:
• 3-wire (with bidirectional data line)
• 4-wire (with separate data input and output lines)
• 5-wire type 1 (with sampling RS by the serial clock)
• 5-wire type 2 (with sampling RS by the chip select signal)
Figure 62 depicts timing of the 3-wire serial interface. The timing images correspond to active-low
DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal.
For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and
output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux connects the
internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal
provided by the IPU.
Each data transfer can be preceded by an optional preamble with programmable length and contents. The
preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is
programmable. The RW bit can be disabled. The following data can consist of one word or of a whole
burst. The interface parameters are controlled by the DI_SER_DISPn_CONF registers (n = 1, 2).
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DISPB_D#_CS
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
RW
RS
D7
D6
D5
D4
D3
D2
D1
D0
Input or output data
Preamble
Figure 62. 3-Wire Serial Interface Timing Diagram
Figure 63 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output
data lines both inside and outside the device.
Write
DISPB_D#_CS
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
RS
D7
D6
D5
Preamble
D4
D3
D2
D1
D0
Output data
DISPB_SD_D
(Input)
Read
DISPB_D#_CS
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
RS
Preamble
DISPB_SD_D
(Input)
D7
D6
D5
D4
D3
D2
D1
D0
Input data
Figure 63. 4-Wire Serial Interface Timing Diagram
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Freescale Semiconductor
Figure 64 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is
added. When a burst is transmitted within a single active chip select interval, the RS can be changed at
boundaries of words.
Write
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
D7
D6
D5
Preamble
D4
D3
D2
D1
D0
Output data
DISPB_SD_D
(Input)
DISPB_SER_RS
Read
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
Preamble
DISPB_SD_D
(Input)
D7
D6
D5
D4
D3
D2
D1
D0
Input data
DISPB_SER_RS
Figure 64. 5-Wire Serial Interface (Type 1) Timing Diagram
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Figure 65 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is
added. When a burst is transmitted within a single active chip select interval, the RS can be changed at
boundaries of words.
Write
DISPB_D#_CS
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
D7
D6
D5
D4
D3
D2
D1
D0
Output data
Preamble
DISPB_SD_D
(Input)
DISPB_SER_RS
1 display IF
clock cycle
Read
DISPB_D#_CS
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
Preamble
DISPB_SD_D
(Input)
DISPB_SER_RS
D7
1 display IF
clock cycle
D6
D5
D4
D3
D2
D1
D0
Input data
Figure 65. 5-Wire Serial Interface (Type 2) Timing Diagram
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4.9.13.5.10 Serial Interfaces, Electrical Characteristics
Figure 66 depicts timing of the serial interface. Table 59 lists the timing parameters at display access level.
IP49, IP48
DISPB_SER_RS
IP56,IP54
IP57, IP55
DISPB_SD_D_CLK
IP51, IP53
IP50, IP52
read point
IP59
IP58
DISPB_DATA
(Input)
Read Data
IP60
IP61
DISPB_DATA
(Output)
IP67,IP65
IP47
IP64, IP66
IP62, IP63
Figure 66. Asynchronous Serial Interface Timing Diagram
Table 59. Asynchronous Serial Interface Timing Parameters—Access Level
ID
Parameter
IP48 Read system cycle time
IP49 Write system cycle time
Symbol
Tcycr
Tcycw
Min.
Typ.1
Max.
Units
Tdicpr – 1.5
Tdicpr2
Tdicpr + 1.5
ns
Tdicpw – 1.5
Tdicpw3
Tdicpw + 1.5
ns
IP50 Read clock low pulse width
Trl
Tdicdr – Tdicur – 1.5
Tdicdr4 – Tdicur5 Tdicdr – Tdicur + 1.5
ns
IP51 Read clock high pulse width
Trh
Tdicpr – Tdicdr + Tdicur
– 1.5
Tdicpr – Tdicdr + Tdicpr – Tdicdr + Tdicur
Tdicur
+ 1.5
ns
IP52 Write clock low pulse width
Twl
Tdicdw – Tdicuw – 1.5
Tdicdw6 –
Tdicuw7
ns
IP53 Write clock high pulse width
Twh
Tdicpw – Tdicdw +
Tdicuw – 1.5
Tdicpw – Tdicdw Tdicpw – Tdicdw +
+ Tdicuw
Tdicuw + 1.5
ns
IP54 Controls setup time for read
Tdcsr
Tdicur – 1.5
Tdicur
ns
Tdicdw – Tdicuw + 1.5
—
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Table 59. Asynchronous Serial Interface Timing Parameters—Access Level (continued)
ID
Parameter
Symbol
Typ.1
Min.
Max.
Units
IP55 Controls hold time for read
Tdchr
Tdicpr – Tdicdr – 1.5
Tdicpr – Tdicdr
—
ns
IP56 Controls setup time for write
Tdcsw
Tdicuw – 1.5
Tdicuw
—
ns
IP57 Controls hold time for write
Tdchw
Tdicpw – Tdicdw – 1.5
Tdicpw – Tdicdw
—
ns
IP58 Slave device data
delay8
9
10
Tracc
0
—
Tdrp – Tlbd
– 1.5
IP59 Slave device data hold time8
Troh
Tdrp – Tlbd – Tdicdr
+ 1.5
—
Tdicpr – Tdicdr – 1.5
IP60 Write data setup time
Tds
Tdicdw – 1.5
Tdicdw
—
ns
IP61 Write data hold time
Tdh
Tdicpw – Tdicdw – 1.5
Tdicpw – Tdicdw
—
ns
Tdicpr – 1.5
Tdicpr
Tdicpr + 1.5
ns
Tdicpw Tdicpw – 1.5
Tdicpw
Tdicpw + 1.5
ns
Tdicdr
Tdicdr – 1.5
Tdicdr
Tdicdr + 1.5
ns
Tdicur
Tdicur – 1.5
Tdicur
Tdicur + 1.5
ns
Tdicdw Tdicdw – 1.5
Tdicdw
Tdicdw + 1.5
ns
Tdicuw Tdicuw – 1.5
Tdicuw
Tdicuw + 1.5
ns
Tdrp
Tdrp + 1.5
ns
IP62 Read period2
Tdicpr
IP63 Write period3
IP64 Read down time
IP65 Read up
4
time5
IP66 Write down
time6
IP67 Write up time7
IP68 Read time
1
2
Tdrp – 1.5
ns
HSP_CLK
DISP#_IF_CLK_PER_RD
⋅ ceil ---------------------------------------------------------------HSP_CLK_PERIOD
Display interface clock period value for write:
Tdicpw = T
4
Tdrp
ns
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
Display interface clock period value for read:
Tdicpr = T
3
point9
– Tdicur
HSP_CLK
DISP#_IF_CLK_PER_WR
⋅ ceil -----------------------------------------------------------------HSP_CLK_PERIOD
Display interface clock down time for read:
1
2 ⋅ DISP#_IF_CLK_DOWN_RD
Tdicdr = --- T HSP_CLK ⋅ ceil ------------------------------------------------------------------------------2
HSP_CLK_PERIOD
5
Display interface clock up time for read:
1
2 ⋅ DISP#_IF_CLK_UP_RD
Tdicur = --- T
⋅ ceil -------------------------------------------------------------------2 HSP_CLK
HSP_CLK_PERIOD
6
Display interface clock down time for write:
1
2 ⋅ DISP#_IF_CLK_DOWN_WR
Tdicdw = --- T HSP_CLK ⋅ ceil --------------------------------------------------------------------------------2
HSP_CLK_PERIOD
7
Display interface clock up time for write:
1
2 ⋅ DISP#_IF_CLK_UP_WR
Tdicuw = --- T
⋅ ceil ---------------------------------------------------------------------2 HSP_CLK
HSP_CLK_PERIOD
8
This parameter is a requirement to the display connected to the IPU.
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9
Data read point:
Tdrp = T
10
HSP_CLK
DISP#_READ_EN
⋅ ceil -------------------------------------------------HSP_CLK_PERIOD
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, and an IPU input delay. This value is device specific.
The following parameters are programmed via the DI_DISP#_TIME_CONF_1,
DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers:
• DISP#_IF_CLK_PER_WR
• DISP#_IF_CLK_PER_RD
• HSP_CLK_PERIOD
• DISP#_IF_CLK_DOWN_WR
• DISP#_IF_CLK_UP_WR
• DISP#_IF_CLK_DOWN_RD
• DISP#_IF_CLK_UP_RD
• DISP#_READ_EN
4.9.14
Memory Stick Host Controller (MSHC)
Figure 67, Figure 68, and Figure 69 depict the MSHC timings, and Table 60 and Table 61 list the timing
parameters.
tSCLKc
tSCLKwh
tSCLKwl
MSHC_SCLK
tSCLKr
tSCLKf
Figure 67. MSHC_CLK Timing Diagram
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tSCLKc
MSHC_SCLK
tBSsu
tBSh
MSHC_BS
tDsu
tDh
MSHC_DATA
(Output)
tDd
MSHC_DATA
(Intput)
Figure 68. Transfer Operation Timing Diagram (Serial)
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Freescale Semiconductor
tSCLKc
MSHC_SCLK
tBSsu
tBSh
MSHC_BS
tDsu
tDh
MSHC_DATA
(Output)
tDd
MSHC_DATA
(Input)
Figure 69. Transfer Operation Timing Diagram (Parallel)
NOTE
The memory stick host controller is designed to meet the timing
requirements per Sony's Memory Stick Pro Format Specifications. Tables in
this section detail the specifications’ requirements for parallel and serial
modes, and not the i.MX35 timing.
Table 60. Serial Interface Timing Parameters1
Standards
Signal
Parameter
MSHC_SCLK
MSHC_BS
Symbol
Unit
Min.
Max.
Cycle
tSCLKc
50
—
ns
H pulse length
tSCLKwh
15
—
ns
L pulse length
tSCLKwl
15
—
ns
Rise time
tSCLKr
—
10
ns
Fall time
tSCLKf
—
10
ns
Setup time
tBSsu
5
—
ns
Hold time
tBSh
5
—
ns
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Table 60. Serial Interface Timing Parameters1 (continued)
Standards
Signal
Parameter
MSHC_DATA
1
Symbol
Unit
Min.
Max.
Setup time
tDsu
5
—
ns
Hold time
tDh
5
—
ns
Output delay time
tDd
—
15
ns
Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC
restrictions described in Table 61.
Table 61. Parallel Interface Timing Parameters1
Standards
Signal
Parameter
MSHC_SCLK
Unit
Min.
Max.
Cycle
tSCLKc
25
—
ns
H pulse length
tSCLKwh
5
—
ns
L pulse length
tSCLKwl
5
—
ns
Rise time
tSCLKr
—
10
ns
Fall time
tSCLKf
—
10
ns
Setup time
tBSsu
8
—
ns
Hold time
tBSh
1
—
ns
Setup time
tDsu
8
—
ns
Hold time
tDh
1
—
ns
Output delay time
tDd
—
15
ns
MSHC_BS
MSHC_DATA
1
Symbol
Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See the NVCC
restrictions described in Table 8.
4.9.15
MediaLB Controller Electrical Specifications
This section describes the electrical information of the MediaLB Controller module.
Table 62. MLB 256/512 Fs Timing Parameters
Parameter
Symbol
Min
MLBCLK operating frequency1
fmck
11.264
Typ
Max
Units
Comment
MHz
Min: 256 × Fs at 44.0 kHz
Typ: 256 × Fs at 48.0 kHz
Typ: 512 × Fs at 48.0 kHz
Max: 512 × Fs at 48.1 kHz
Max: 512 × Fs PLL unlocked
ns
VIL TO VIH
12.288
24.576
24.6272
25.600
MLBCLK rise time
tmckr
—
—
3
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Table 62. MLB 256/512 Fs Timing Parameters (continued)
Parameter
Symbol
Min
Typ
Max
Units
Comment
MLB fall time
tmckf
—
—
3
ns
VIH TO VIL
MLBCLK cycle time
tmckc
—
—
81
40
—
—
ns
256 × Fs
512 × Fs
MLBCLK low time
tmckl
31.5
30
37
35.5
—
—
ns
256 × Fs
256 × Fs PLL unlocked
14.5
14
17
16.5
—
—
ns
512 × Fs
512 × Fs PLL unlocked
31.5
30
38
36.5
—
—
ns
256 × Fs
256 × Fs PLL unlocked
14.5
14
17
16.5
—
—
ns
512 × Fs
512 × Fs PLL unlocked
MLBCLK high time
tmckh
MLBCLK pulse width variation
tmpwv
—
—
2
ns pp
Note2
MLBSIG/MLBDAT input valid to
MLBCLK falling
tdsmcf
1
—
—
ns
—
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf
0
—
—
ns
—
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0
—
tmckl
ns
—
Bus Hold Time
tmdzh
4
—
—
ns
Note3
1
2
3
The MLB controller can shut off MLBCLK to place MediaLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp)
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters
specified from the valid voltage threshold as listed below unless otherwise noted.
Table 63. MLB Device 1024Fs Timing Parameters
Parameter
Symbol
Min
MLBCLK Operating
Frequency1
fmck
45.056
Typ
Max
Units
Comment
MHz
Min: 1024 × Fs at 44.0 kHz
Typ: 1024 × Fs at 48.0 kHz
Max: 1024 × Fs at 48.1 kHz
Max: 1024 × Fs PLL unlocked
49.152
49.2544
51.200
MLBCLK rise time
tmckr
—
—
1
ns
VIL TO VIH
MLB fall time
tmckf
—
—
1
ns
VIH TO VIL
MLBCLK cycle time
tmckc
—
20.3
—
ns
—
MLBCLK low time
tmckl
6.5
6.1
7.7
7.3
—
ns
PLL unlocked
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Table 63. MLB Device 1024Fs Timing Parameters (continued)
Parameter
Symbol
Min
Typ
Max
Units
Comment
MLBCLK high time
tmckh
9.7
9.3
10.6
10.2
—
—
ns
PLL unlocked
MLBCLK pulse width variation
tmpwv
—
—
0.7
ns pp
Note2
MLBSIG/MLBDAT input valid
to MLBCLK falling
tdsmcf
1
—
—
ns
—
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf
0
—
—
ns
—
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0
—
tmckl
ns
—
Bus Hold Time
tmdzh
2
—
—
ns
Note3
1
2
3
The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge,
measured in ns peak-to-peak (pp)
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
4.9.16
1-Wire Timing Specifications
Figure 70 depicts the RPP timing, and Table 64 lists the RPP timing parameters.
1-WIRE Tx
“Reset Pulse”
DS2502 Tx
“Presence Pulse”
OW2
1-Wire bus
(BATT_LINE)
OW3
OW1
OW4
Figure 70. Reset and Presence Pulses (RPP) Timing Diagram
Table 64. RPP Sequence Delay Comparisons Timing Parameters
ID
Parameters
Symbol
Min.
Typ.
Max.
Units
OW1
Reset time low
tRSTL
480
511
—
µs
OW2
Presence detect high
tPDH
15
—
60
µs
OW3
Presence detect low
tPDL
60
—
240
µs
OW4
Reset time high
tRSTH
480
512
—
µs
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Figure 71 depicts write 0 sequence timing, and Table 65 lists the timing parameters.
OW6
1-Wire bus
(BATT_LINE)
OW5
Figure 71. Write 0 Sequence Timing Diagram
Table 65. WR0 Sequence Timing Parameters
ID
Parameter
OW5
Write 0 low time
OW6
Transmission time slot
Symbol
Min.
Typ.
Max.
Units
tWR0_low
60
100
120
µs
tSLOT
OW5
117
120
µs
Figure 72 shows write 1 sequence timing, and Figure 73 depicts the read sequence timing. Table 66 lists
the timing parameters.
OW8
1-Wire bus
(BATT_LINE)
OW7
Figure 72. Write 1 Sequence Timing Diagram
OW8
1-Wire bus
(BATT_LINE)
OW7
OW9
Figure 73. Read Sequence Timing Diagram
Table 66. WR1/RD Timing Parameters
ID
Parameter
Symbol
Min.
Typ.
Max.
Units
OW7
Write 1/read low time
tLOW1
1
5
15
µs
OW8
Transmission time slot
tSLOT
60
117
120
µs
OW9
Release time
tRELEASE
15
—
45
µs
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4.9.17
Parallel ATA Module AC Electrical Specifications
The parallel ATA module can work on PIO/multiword DMA/ultra-DMA transfer modes (not available for
the MCIMX351). Each transfer mode has a different data transfer rate, Ultra DMA mode 4 data transfer
rate is up to 100 MBps.
The parallel ATA module interface consists of a total of 29 pins. Some pins have different functions in
different transfer modes. There are various requirements for timing relationships among the function pins,
in compliance with the ATA/ATAPI-6 specification, and these requirements are configurable by the ATA
module registers.
4.9.17.1
General Timing Requirements
Table 67 and Figure 74 define the AC characteristics of the interface signals on all data transfer modes.
Table 67. AC Characteristics of All Interface Signals
ID
1
Parameter
Symbol
Min.
Max.
Unit
SI1
Rising edge slew rate for any signal on the ATA interface1
Srise1
—
1.25
V/ns
SI2
Falling edge slew rate for any signal on the ATA interface1
Sfall1
—
1.25
V/ns
SI3
Host interface signal capacitance at the host connector
Chost
—
20
pF
SRISE and SFALL meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with
all capacitive loads from 15 pF through 40 pF, where all signals have the same capacitive load value.
ATA Interface Signals
SI2
SI1
Figure 74. ATA Interface Signals Timing Diagram
4.9.17.2
ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses ATA parameters. For a detailed description, refer to the ATA-6 specification.
Level shifters are required for 3.3-V or 5.0-V compatibility on the ATA interface.
The use of bus buffers introduces delays on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. Use of bus
buffers is not recommended if fast UDMA mode is required.
The ATA specification imposes a slew rate limit on the ATA bus. According to this limit, any signal driven
on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Few vendors of bus buffers
specify the slew rate of the outgoing signals.
When bus buffers are used the ata_data bus buffer is bidirectional, and uses the direction control signal
ata_buffer_en. When ata_buffer_en is asserted, the bus should drive from host to device. When
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ata_buffer_en is negated, the bus drives from device to host. Steering of the signal is such that contention
on the host and device tri-state buses is always avoided.
4.9.17.3
Timing Parameters
Table 68 shows the parameters used in the timing equations. These parameters depend on the
implementation of the ATA interface on silicon, the bus buffer used, the cable delay, and the cable skew.
Table 68. ATA Timing Parameters
Name
T
ti_ds
ti_dh
Value/
Contributing Factor1
Description
Bus clock period (ipg_clk_ata)
Peripheral clock
frequency
Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2, UDMA3
UDMA4
UDMA5
15 ns
10 ns
7 ns
5 ns
4 ns
Hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA5
5.0 ns
4.6 ns
tco
Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
12.0 ns
tsu
Set-up time ata_data to bus clock L-to-H
8.5 ns
tsui
Set-up time ata_iordy to bus clock H-to-L
8.5 ns
thi
Hold time ata_iordy to bus clock H to L
2.5 ns
tskew1 Maximum difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
7 ns
tskew2 Maximum difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
Transceiver
tskew3 Maximum difference in buffer propagation delay for any of following signals ata_iordy,
ata_data (read)
Transceiver
tbuf
Maximum buffer propagation delay
Transceiver
tcable1 Cable propagation delay for ata_data
Cable
tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
Cable
tskew4 Maximum difference in cable propagation delay between ata_iordy and ata_data (read)
Cable
tskew5 Maximum difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack)
and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
Cable
tskew6 Maximum difference in cable propagation delay without accounting for ground bounce
Cable
1
Values provided where applicable.
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4.9.17.4
PIO Mode Timing
Figure 75 shows timing for PIO read, and Table 69 lists the timing parameters for PIO read.
Figure 75. PIO Read Timing Diagram
Table 69. PIO Read Timing Parameters
ATA
Parameter from
Parameter
Figure 75
Controlling
Variable
Value
t1
t1
t1 (min.) = time_1 × T – (tskew1 + tskew2 + tskew5)
time_1
t2
t2r
t2 min.) = time_2r × T – (tskew1 + tskew2 + tskew5)
time_2r
t9
t9
t9 (min.) = time_9 × T – (tskew1 + tskew2 + tskew6)
time_3
t5
t5
t5 (min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
If not met, increase
time_2
t6
t6
0
tA
tA
tA (min.) = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2 × tbuf)
trd
trd1
t0
—
—
time_ax
trd1 (max.) = (–trd) + (tskew3 + tskew4)
trd1 (min.) = (time_pio_rdx – 0.5) × T – (tsu + thi)
(time_pio_rdx – 0.5) × T > tsu + thi + tskew3 + tskew4
t0 (min.) = (time_1 + time_2 + time_9) × T
time_pio_rdx
time_1, time_2r, time_9
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Figure 76 shows timing for PIO write, and Table 70 lists the timing parameters for PIO write.
Figure 76. PIO Write Timing Diagram
Table 70. PIO Write Timing Parameters
ATA
Parameter
Parameter
from
Figure 76
t1
t1
t2
t2w
t9
t9
t9 (min.) = time_9 × T – (tskew1 + tskew2 + tskew6)
t3
—
t3 (min.) = (time_2w – time_on) × T – (tskew1 + tskew2 +tskew5)
t4
t4
t4 (min.) = time_4 × T – tskew1
time_4
tA
tA
tA = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2*tbuf)
time_ax
t0
—
t0(min.) = (time_1 + time_2 + time_9) × T
—
—
Avoid bus contention when switching buffer on by making ton long enough.
—
—
—
Avoid bus contention when switching buffer off by making toff long enough.
—
Value
t1 (min.) = time_1 × T – (tskew1 + tskew2 + tskew5)
t2 (min.) = time_2w × T – (tskew1 + tskew2 + tskew5)
Controlling
Variable
time_1
time_2w
time_9
If not met, increase
time_2w
time_1, time_2r,
time_9
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Figure 77 shows timing for MDMA read, and Figure 78 shows timing for MDMA write. Table 71 lists the
timing parameters for MDMA read and write.
Figure 77. MDMA Read Timing Diagram
Figure 78. MDMA Write Timing Diagram
Table 71. MDMA Read and Write Timing Parameters
ATA
Parameter
Parameter
from
Figure 77,
Figure 78
tm, ti
tm
tm (min.) = ti (min.) = time_m × T – (tskew1 + tskew2 + tskew5)
time_m
td
td, td1
td1.(min.) = td (min.) = time_d × T – (tskew1 + tskew2 + tskew6)
time_d
tk
tk
tk.(min.) = time_k × T – (tskew1 + tskew2 + tskew6)
time_k
t0
—
t0 (min.) = (time_d + time_k) × T
tg(read)
tgr
tgr (min. – read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr.(min. – drive) = td – te(drive)
tf(read)
tfr
tfr (min. – drive) = 0
tg(write)
—
tg (min. – write) = time_d × T – (tskew1 + tskew2 + tskew5)
time_d
tf(write)
—
tf (min. – write) = time_k × T – (tskew1 + tskew2 + tskew6)
time_k
tL
—
tL (max.) = (time_d + time_k–2) × T – (tsu + tco + 2 × tbuf + 2 × tcable2)
Controlling
Variable
Value
time_d, time_k
time_d
—
time_d, time_k
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Table 71. MDMA Read and Write Timing Parameters (continued)
ATA
Parameter
Parameter
from
Figure 77,
Figure 78
tn, tj
tkjn
tn = tj = tkjn = (max.(time_k,. time_jn) × T – (tskew1 + tskew2 + tskew6)
—
ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
4.9.17.5
Value
Controlling
Variable
time_jn
—
UDMA-In Timing
Figure 79 shows timing when the UDMA-in transfer starts, Figure 80 shows timing when the UDMA-in
host terminates transfer, Figure 81 shows timing when the UDMA-in device terminates transfer, and
Table 72 lists the timing parameters for the UDMA-in burst.
Figure 79. UDMA-In Transfer Starts Timing Diagram
Figure 80. UDMA-In Host Terminates Transfer Timing Diagram
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Figure 81. UDMA-In Device Terminates Transfer Timing Diagram
Table 72. UDMA-In Burst Timing Parameters
ATA
Parameter
Parameters
from
Figure 79,
Figure 80,
Figure 81
tack
tack
tack (min.) = (time_ack × T) – (tskew1 + tskew2)
time_ack
tenv
tenv
tenv (min.) = (time_env × T) – (tskew1 + tskew2)
tenv (max.) = (time_env × T) + (tskew1 + tskew2)
time_env
tds
tds1
tds – (tskew3) – ti_ds > 0
tdh
tdh1
tdh – (tskew3) – ti_dh > 0
tcyc
tc1
(tcyc – tskew > T
trp
trp
trp (min.) = time_rp × T – (tskew1 + tskew2 + tskew6)
time_rp
time_rp
Description
Controlling Variable
tskew3, ti_ds, ti_dh
should be low enough
T big enough
—
tx1
(time_rp × T) – (tco + tsu + 3T + 2 × tbuf + 2 × tcable2) > trfs (drive)
tmli
tmli1
tmli1 (min.) = (time_mlix + 0.4) × T
time_mlix
tzah
tzah
tzah (min.) = (time_zah + 0.4) × T
time_zah
tdzfs
tdzfs
tdzfs = (time_dzfs × T) – (tskew1 + tskew2)
time_dzfs
tcvh
tcvh
tcvh = (time_cvh × T) – (tskew1 + tskew2)
time_cvh
—
ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
1
—
1
There is a special timing requirement in the ATA host that requires the internal DIOW to go high three clocks after the last active
edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2. Make ton and toff large enough to avoid bus contention.
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4.9.17.6
UDMA-Out Timing
Figure 82 shows timing when the UDMA-out transfer starts, Figure 83 shows timing when the UDMA-out
host terminates transfer, Figure 84 shows timing when the UDMA-out device terminates transfer, and
Table 73 lists the timing parameters for the UDMA-out burst.
Figure 82. UDMA-Out Transfer Starts Timing Diagram
Figure 83. UDMA-Out Host Terminates Transfer Timing Diagram
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Figure 84. UDMA-Out Device Terminates Transfer Timing Diagram
Table 73. UDMA-Out Burst Timing Parameters
ATA
Parameter
Parameter
from
Figure 82,
Figure 83,
Figure 84
tack
tack
tack (min.) = (time_ack × T) – (tskew1 + tskew2)
time_ack
tenv
tenv
tenv (min.) = (time_env × T) – (tskew1 + tskew2)
tenv (max.) = (time_env × T) + (tskew1 + tskew2)
time_env
tdvs
tdvs
tdvs = (time_dvs ×T) – (tskew1 + tskew2)
time_dvs
tdvh
tdvh
tdvs = (time_dvh × T) – (tskew1 + tskew2)
time_dvh
tcyc
tcyc
tcyc = time_cyc × T – (tskew1 + tskew2)
time_cyc
t2cyc
—
t2cyc = time_cyc × 2 × T
time_cyc
trfs1
trfs
trfs = 1.6 × T + tsui + tco + tbuf + tbuf
—
tdzfs
tss
tss
tmli
tdzfs_mli
tli
Controlling
Variable
Value
—
tdzfs = time_dzfs × T – (tskew1)
time_dzfs
tss = time_ss × T – (tskew1 + tskew2)
time_ss
tdzfs_mli = max. (time_dzfs, time_mli) × T – (tskew1 + tskew2)
—
tli1
tli1 > 0
—
tli
tli2
tli2 > 0
—
tli
tli3
tli3 > 0
—
tcvh
tcvh
tcvh = (time_cvh × T) – (tskew1 + tskew2)
—
ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
time_cvh
—
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4.9.18
Parallel Interface (ULPI) Timing
Electrical and timing specifications of the parallel interface are presented in the subsequent sections.
Table 74. Signal Definitions—Parallel Interface
Name
Direction
Signal Description
USB_Clk
In
Interface clock. All interface signals are synchronous to the clock.
USB_Data[7:0]
I/O
Bidirectional data bus, driven low by the link during idle. Bus ownership is determined by Dir.
USB_Dir
In
Direction. Control the direction of the data bus.
USB_Stp
Out
USB_Nxt
In
Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus.
Next. The PHY asserts this signal to throttle the data.
USB_Clk
US15
US16
USB_Stp
US15
US16
USB_Data
US17
US17
USB_Dir/Nxt
Figure 85. USB Transmit/Receive Waveform in Parallel Mode
Table 75. USB Timing Specification in VP_VM Unidirectional Mode
ID
Parameter
Min.
Max.
Unit
Conditions /
Reference Signal
US15
USB_TXOE_B
—
6.0
ns
10 pF
US16
USB_DAT_VP
—
0.0
ns
10 pF
US17
USB_SE0_VM
—
9.0
ns
10 pF
4.9.19
PWM Electrical Specifications
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
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109
pin. The modulated signal of the module is observed at this pin. It can be viewed as a clock signal whose
period and duty cycle can be varied with different settings of the PWM. The smallest period is two ipg_clk
periods with duty cycle of 50 percent.
4.9.20
SJC Electrical Specifications
This section details the electrical characteristics for the SJC module. Figure 86 depicts the SJC test clock
input timing. Figure 87 depicts the SJC boundary scan timing, Figure 88 depicts the SJC test access port,
Figure 89 depicts the SJC TRST timing, and Table 76 lists the SJC timing parameters.
SJ1
SJ2
TCK
(Input)
SJ2
VM
VIH
VM
VIL
SJ3
SJ3
Figure 86. Test Clock Input Timing Diagram
TCK
(Input)
VIH
VIL
SJ4
Data
Inputs
SJ5
Input Data Valid
SJ6
Data
Outputs
Output Data Valid
SJ7
Data
Outputs
SJ6
Data
Outputs
Output Data Valid
Figure 87. Boundary Scan (JTAG) Timing Diagram
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TCK
(Input)
VIH
VIL
SJ8
TDI
TMS
(Input)
SJ9
Input Data Valid
SJ10
TDO
(Output)
Output Data Valid
SJ11
TDO
(Output)
SJ10
TDO
(Output)
Output Data Valid
Figure 88. Test Access Port Timing Diagram
TCK
(Input)
SJ13
TRST
(Input)
SJ12
Figure 89. TRST Timing Diagram
Table 76. SJC Timing Parameters
All Frequencies
ID
Parameter
Unit
Min.
Max.
1001
—
ns
SJ1
TCK cycle time
SJ2
TCK clock pulse width measured at VM2
40
—
ns
SJ3
TCK rise and fall times
—
3
ns
SJ4
Boundary scan input data set-up time
10
—
ns
SJ5
Boundary scan input data hold time
50
—
ns
SJ6
TCK low to output data valid
—
50
ns
SJ7
TCK low to output high impedance
—
50
ns
SJ8
TMS, TDI data set-up time
10
—
ns
SJ9
TMS, TDI data hold time
50
—
ns
SJ10
TCK low to TDO data valid
—
44
ns
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Table 76. SJC Timing Parameters (continued)
All Frequencies
ID
1
2
Parameter
Unit
Min.
Max.
—
44
ns
SJ11
TCK low to TDO high impedance
SJ12
TRST assert time
100
—
ns
SJ13
TRST set-up time to TCK low
40
—
ns
On cases where SDMA TAP is put in the chain, the max. TCK frequency is limited by max. ratio of 1:8 of SDMA core frequency
to TCK limitation. This implies max. frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
VM = mid point voltage
4.9.21
SPDIF Timing
SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by
a clock that is twice the bit rate of the data signal.
Figure 90 shows SPDIF timing parameters, including the timing of the modulating Rx clock (SRCK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK). for SPDIF in Tx mode.
Table 77. SPDIF Timing Parameters
Timing Parameter Range
Parameters
Symbol
Units
Min.
Max.
SPDIFIN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
SPDIFOUT output (Load = 50 pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
SPDIFOUT1 output (Load = 30 pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
13.6
18.0
ns
Modulating Rx clock (SRCK) period
srckp
40.0
—
ns
SRCK high period
srckph
16.0
—
ns
SRCK low period
srckpl
16.0
—
ns
Modulating Tx clock (STCLK) period
stclkp
40.0
—
ns
STCLK high period
stclkph
16.0
—
ns
STCLK low period
stclkpl
16.0
—
ns
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srckp
srckpl
srckph
VM
SRCK
(Output)
VM
Figure 90. SRCK Timing
stclkp
stclkpl
stclkph
VM
STCLK
(Input)
VM
Figure 91. STCLK Timing
4.9.22
SSI Electrical Specifications
This section describes electrical characteristics of the SSI.
•
•
•
•
NOTE
All of the timing for the SSI is given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timing is on AUDMUX signals when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the transmit and receive sections of the SSI,
respectively.
For internal frame sync operations using the external clock, the FS
timing will be the same as that of Tx Data (for example, during AC97
mode of operation).
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4.9.22.1
SSI Transmitter Timing with Internal Clock
Figure 92 depicts the SSI transmitter timing with internal clock, and Table 78 lists the timing parameters.
SS1
SS3
SS5
SS2
SS4
AD1_TXC
(Output)
SS8
SS6
AD1_TXFS (bl)
(Output)
SS10
SS12
AD1_TXFS (wl)
(Output)
SS14
SS15
SS16
SS18
SS17
AD1_TXD
(Output)
SS43
SS42
SS19
AD1_RXD
(Input)
Note: SRXD Input in Synchronous mode only
SS1
SS3
SS5
SS2
SS4
DAM1_T_CLK
(Output)
SS6
SS8
DAM1_T_FS (bl)
(Output)
SS10
DAM1_T_FS (wl)
(Output)
SS12
SS14
SS16
SS15
SS18
SS17
DAM1_TXD
(Output)
SS43
SS42
SS19
DAM1_RXD
(Input)
Note: SRXD Input in Synchronous mode only
Figure 92. SSI Transmitter with Internal Clock Timing Diagram
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Table 78. SSI Transmitter with Internal Clock Timing Parameters
ID
Parameter
Min.
Max.
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
—
ns
SS2
(Tx/Rx) CK clock high period
36.0
—
ns
SS3
(Tx/Rx) CK clock rise time
—
6
ns
SS4
(Tx/Rx) CK clock low period
36.0
—
ns
SS5
(Tx/Rx) CK clock fall time
—
6
ns
SS6
(Tx) CK high to FS (bl) high
—
15.0
ns
SS8
(Tx) CK high to FS (bl) low
—
15.0
ns
SS10
(Tx) CK high to FS (wl) high
—
15.0
ns
SS12
(Tx) CK high to FS (wl) low
—
15.0
ns
SS14
(Tx/Rx) Internal FS rise time
—
6
ns
SS15
(Tx/Rx) Internal FS fall time
—
6
ns
SS16
(Tx) CK high to STXD valid from high impedance
—
15.0
ns
SS17
(Tx) CK high to STXD high/low
—
15.0
ns
SS18
(Tx) CK high to STXD high impedance
—
15.0
ns
SS19
STXD rise/fall time
—
6
ns
10.0
—
ns
Synchronous Internal Clock Operation
SS42
SRXD setup before (Tx) CK falling
SS43
SRXD hold after (Tx) CK falling
0
—
ns
SS52
Loading
—
25
pF
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4.9.22.2
SSI Receiver Timing with Internal Clock
Figure 93 depicts the SSI receiver timing with internal clock. Table 79 lists the timing parameters shown
in Figure 93.
SS1
SS3
SS5
SS4
SS2
AD1_TXC
(Output)
SS9
SS7
AD1_TXFS (bl)
(Output)
SS11
SS13
AD1_TXFS (wl)
(Output)
SS20
SS21
AD1_RXD
(Input)
SS51
SS47
SS48
SS49
SS50
AD1_RXC
(Output)
SS1
SS3
SS5
SS2
SS4
DAM1_T_CLK
(Output)
SS7
DAM1_T_FS (bl)
(Output)
SS9
SS11
SS13
DAM1_T_FS (wl)
(Output)
SS20
SS21
DAM1_RXD
(Input)
SS47
SS48
SS51
SS50
SS49
DAM1_R_CLK
(Output)
Figure 93. SSI Receiver with Internal Clock Timing Diagram
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Table 79. SSI Receiver with Internal Clock Timing Parameters
ID
Parameter
Min.
Max.
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
—
ns
SS2
(Tx/Rx) CK clock high period
36.0
—
ns
SS3
(Tx/Rx) CK clock rise time
—
6
ns
SS4
(Tx/Rx) CK clock low period
36.0
—
ns
SS5
(Tx/Rx) CK clock fall time
—
6
ns
SS7
(Rx) CK high to FS (bl) high
—
15.0
ns
SS9
(Rx) CK high to FS (bl) low
—
15.0
ns
SS11
(Rx) CK high to FS (wl) high
—
15.0
ns
SS13
(Rx) CK high to FS (wl) low
—
15.0
ns
SS20
SRXD setup time before (Rx) CK low
10.0
—
ns
SS21
SRXD hold time after (Rx) CK low
0
—
ns
15.04
—
ns
Oversampling Clock Operation
SS47
Oversampling clock period
SS48
Oversampling clock high period
6
—
ns
SS49
Oversampling clock rise time
—
3
ns
SS50
Oversampling clock low period
6
—
ns
SS51
Oversampling clock fall time
—
3
ns
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4.9.22.3
SSI Transmitter Timing with External Clock
Figure 94 depicts the SSI transmitter timing with external clock, and Table 80 lists the timing parameters.
SS22
SS23
AD1_TXC
(Input)
SS25
SS26
SS27
SS24
SS29
AD1_TXFS (bl)
(Input)
SS33
SS31
AD1_TXFS (wl)
(Input)
SS39
SS37
SS38
AD1_TXD
(Output)
SS45
SS44
AD1_RXD
(Input)
SS46
Note: SRXD Input in Synchronous mode only
SS22
SS26
SS25
SS23
SS24
DAM1_T_CLK
(Input)
SS27
SS29
DAM1_T_FS (bl)
(Input)
SS33
SS31
DAM1_T_FS (wl)
(Input)
SS39
SS37
SS38
DAM1_TXD
(Output)
SS44
SS45
DAM1_RXD
(Input)
Note: SRXD Input in Synchronous mode only
SS46
Figure 94. SSI Transmitter with External Clock Timing Diagram
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Table 80. SSI Transmitter with External Clock Timing Parameters
ID
Parameter
Min.
Max.
Unit
External Clock Operation
SS22
(Tx/Rx) CK clock period
81.4
—
ns
SS23
(Tx/Rx) CK clock high period
36.0
—
ns
SS24
(Tx/Rx) CK clock rise time
—
6.0
ns
SS25
(Tx/Rx) CK clock low period
36.0
—
ns
SS26
(Tx/Rx) CK clock fall time
—
6.0
ns
SS27
(Tx) CK high to FS (bl) high
–10.0
15.0
ns
SS29
(Tx) CK high to FS (bl) low
10.0
—
ns
SS31
(Tx) CK high to FS (wl) high
–10.0
15.0
ns
SS33
(Tx) CK high to FS (wl) low
10.0
—
ns
SS37
(Tx) CK high to STXD valid from high impedance
—
15.0
ns
SS38
(Tx) CK high to STXD high/low
—
15.0
ns
SS39
(Tx) CK high to STXD high impedance
—
15.0
ns
Synchronous External Clock Operation
SS44
SRXD setup before (Tx) CK falling
10.0
—
ns
SS45
SRXD hold after (Tx) CK falling
2.0
—
ns
SS46
SRXD rise/fall time
—
6.0
ns
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4.9.22.4
SSI Receiver Timing with External Clock
Figure 95 depicts the SSI receiver timing with external clock, and Table 81 lists the timing parameters.
SS22
SS26
SS24
SS25
SS23
AD1_TXC
(Input)
SS30
SS28
AD1_TXFS (bl)
(Input)
SS32
AD1_TXFS (wl)
(Input)
SS34
SS35
SS41
SS40
SS36
AD1_RXD
(Input)
SS22
SS24
SS26
SS23
SS25
DAM1_T_CLK
(Input)
SS30
SS28
DAM1_T_FS (bl)
(Input)
DAM1_T_FS (wl)
(Input)
SS32
SS34
SS35
SS41
SS36
SS40
DAM1_RXD
(Input)
Figure 95. SSI Receiver with External Clock Timing Diagram
Table 81. SSI Receiver with External Clock Timing Parameters
ID
Parameter
Min.
Max.
Unit
External Clock Operation
SS22
(Tx/Rx) CK clock period
81.4
—
ns
SS23
(Tx/Rx) CK clock high period
36.0
—
ns
SS24
(Tx/Rx) CK clock rise time
—
6.0
ns
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Table 81. SSI Receiver with External Clock Timing Parameters (continued)
ID
Parameter
Min.
Max.
Unit
36.0
—
ns
—
6.0
ns
SS25
(Tx/Rx) CK clock low period
SS26
(Tx/Rx) CK clock fall time
SS28
(Rx) CK high to FS (bl) high
–10.0
15.0
ns
SS30
(Rx) CK high to FS (bl) low
10.0
—
ns
SS32
(Rx) CK high to FS (wl) high
–10.0
15.0
ns
SS34
(Rx) CK high to FS (wl) low
10.0
—
ns
SS35
(Tx/Rx) External FS rise time
—
6.0
ns
SS36
(Tx/Rx) External FS fall time
—
6.0
ns
SS40
SRXD setup time before (Rx) CK low
10.0
—
ns
SS41
SRXD hold time after (Rx) CK low
2.0
—
ns
4.9.23
UART Electrical
This section describes the electrical information of the UART module.
4.9.23.1
UART RS-232 Serial Mode Timing
The following subsections give the UART transmit and receive timings in RS-232 serial mode.
4.9.23.1.11 UART Transmitter
Figure 96 depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format.
Table 82 lists the UART RS-232 serial mode transmit timing characteristics.
UA1
TXD
(output)
Start
Bit
Possible
Parity
Bit
UA1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
UA1
Next
Start
Bit
UA1
Figure 96. UART RS-232 Serial Mode Transmit Timing Diagram
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Table 82. RS-232 Serial Mode Transmit Timing Parameters
ID
UA1
1
2
Parameter
Symbol
Min.
Max.
Units
tTbit
1/Fbaud_rate1 –
Tref_clk2
1/Fbaud_rate +
Tref_clk
—
Transmit Bit Time
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
4.9.23.1.12 UART Receiver
Figure 97 depicts the RS-232 serial mode receive timing, with 8 data bit/1 stop bit format. Table 83 lists
serial mode receive timing characteristics.
UA2
RXD
(input)
Start
Bit
Possible
Parity
Bit
UA2
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
Next
Start
Bit
UA2
UA2
Figure 97. UART RS-232 Serial Mode Receive Timing Diagram
Table 83. RS-232 Serial Mode Receive Timing Parameters
1
2
ID
Parameter
Symbol
Min.
Max.
Units
UA2
Receive Bit Time1
tRbit
1/Fbaud_rate2 –
1/(16 × Fbaud_rate)
1/Fbaud_rate +
1/(16 × Fbaud_rate)
—
The UART receiver can tolerate 1/(16 × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 × Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷ 16.
4.9.23.2
UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
4.9.23.2.13 UART IrDA Mode Transmitter
Figure 98 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 84 lists
the transmit timing characteristics.
UA3
UA4
UA3
UA3
UA3
TXD
(output)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Possible
Parity
Bit
STOP
BIT
Figure 98. UART IrDA Mode Transmit Timing Diagram
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Table 84. IrDA Mode Transmit Timing Parameters
1
2
ID
Parameter
Symbol
Min.
Max.
Units
UA3
Transmit bit time in IrDA mode
tTIRbit
1/Fbaud_rate1 –
Tref_clk2
1/Fbaud_rate + Tref_clk
—
UA4
Transmit IR pulse duration
tTIRpulse
(3/16) × (1/Fbaud_rate) (3/16) × (1/Fbaud_rate)
– Tref_clk
+ Tref_clk
—
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
4.9.23.2.14 UART IrDA Mode Receiver
Figure 99 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 85 lists the
receive timing characteristics.
UA5
UA6
UA5
UA5
UA5
RXD
(input)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Possible
Parity
Bit
Bit 7
STOP
BIT
Figure 99. UART IrDA Mode Receive Timing Diagram
Table 85. IrDA Mode Receive Timing Parameters
ID
1
2
Parameter
UA5
Receive bit time1 in IrDA mode
UA6
Receive IR pulse duration
Symbol
Min.
Max.
Units
tRIRbit
1/Fbaud_rate2 –
1/(16 × Fbaud_rate)
1/Fbaud_rate +
1/(16 × Fbaud_rate )
—
tRIRpulse
1.41 us
(5/16) × (1/Fbaud_rate)
—
The UART receiver can tolerate 1/(16 × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 × Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷ 16.
4.9.24
USB Electrical Specifications
In order to support four different serial interfaces, the USB serial transceiver can be configured to operate
in one of four modes:
• DAT_SE0 bidirectional, 3-wire mode
• DAT_SE0 unidirectional, 6-wire mode
• VP_VM bidirectional, 4-wire mode
• VP_VM unidirectional, 6-wire mode
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4.9.24.1
DAT_SE0 Bidirectional Mode
Table 86 defines the signals for DAT_SE0 bidirectional mode. Figure 100 and Figure 101 show the
transmit and receive waveforms respectively.
Table 86. Signal Definitions—DAT_SE0 Bidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
In
Tx data when USB_TXOE_B is low
Differential Rx data when USB_TXOE_B is high
USB_SE0_VM
Out
In
SE0 drive when USB_TXOE_B is low
SE0 Rx indicator when USB_TXOE_B is high
Transmit
US3
USB_TXOE_B
USB_DAT_VP
US1
USB_SE0_VM
US2
US4
Figure 100. USB Transmit Waveform in DAT_SE0 Bidirectional Mode
Receive
USB_TXOE_B
USB_DAT_VP
US7
US8
USB_SE0_VM
Figure 101. USB Receive Waveform in DAT_SE0 Bidirectional Mode
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Table 87 describes the port timing specification in DAT_SE0 bidirectional mode.
Table 87. Port Timing Specification in DAT_SE0 Bidirectional Mode
No.
Parameter
Signal Name
Direction
Min.
Max.
Unit
Conditions/Reference Signal
US1
Tx rise/fall time
USB_DAT_VP
Out
—
5.0
ns
50 pF
US2
Tx rise/fall time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US3
Tx rise/fall time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US4
Tx duty cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US7
Rx rise/fall time
USB_DAT_VP
In
—
3.0
ns
35 pF
US8
Rx rise/fall time
USB_SE0_VM
In
—
3.0
ns
35 pF
4.9.24.2
DAT_SE0 Unidirectional Mode
Table 88 defines the signals for DAT_SE0 unidirectional mode. Figure 102 and Figure 103 show the
transmit and receive waveforms respectively.
Table 88. Signal Definitions—DAT_SE0 Unidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
Tx data when USB_TXOE_B is low
USB_SE0_VM
Out
SE0 drive when USB_TXOE_B is low
USB_VP1
In
Buffered data on DP when USB_TXOE_B is high
USB_VM1
In
Buffered data on DM when USB_TXOE_B is high
USB_RCV
In
Differential Rx data when USB_TXOE_B is high
Transmit
US11
USB_TXOE_B
USB_DAT_VP
US9
USB_SE0_VM
US12
US10
Figure 102. USB Transmit Waveform in DAT_SE0 Unidirectional Mode
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Receive
USB_TXOE_B
USB_VP1
USB_RCV
US15/US17
US16
USB_VM1
Figure 103. USB Receive Waveform in DAT_SE0 Unidirectional Mode
Table 89 describes the port timing specification in DAT_SE0 unidirectional mode.
Table 89. USB Port Timing Specification in DAT_SE0 Unidirectional Mode
Signal
Source
Min.
Max.
Unit
Condition/
Reference Signal
USB_DAT_VP
Out
—
5.0
ns
50 pF
Tx rise/fall time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US11
Tx rise/fall time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US12
Tx duty cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US15
Rx rise/fall time
USB_VP1
In
—
3.0
ns
35 pF
US16
Rx rise/fall time
USB_VM1
In
—
3.0
ns
35 pF
US17
Rx rise/fall time
USB_RCV
In
—
3.0
ns
35 pF
No.
Parameter
US9
Tx rise/fall time
US10
4.9.24.3
Signal Name
VP_VM Bidirectional Mode
Table 90 defines the signals for VP_VM bidirectional mode. Figure 104 and Figure 105 show the transmit
and receive waveforms respectively.
Table 90. Signal Definitions—VP_VM Bidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
USB_DAT_VP
Out (Tx)
In (Rx)
Tx VP data when USB_TXOE_B is low
Rx VP data when USB_TXOE_B is high
USB_SE0_VM
Out (Tx)
In (Rx)
Tx VM data when USB_TXOE_B low
Rx VM data when USB_TXOE_B high
USB_RCV
In
Transmit enable, active low
Differential Rx data
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Transmit
US20
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US18
US21
US19
US22
US22
Figure 104. USB Transmit Waveform in VP_VM Bidirectional Mode
Receive
US26
USB_DAT_VP
USB_SE0_VM
US27
US28
USB_RCV
US29
Figure 105. USB Receive Waveform in VP_VM Bidirectional Mode
Table 91 describes the port timing specification in VP_VM bidirectional mode.
Table 91. USB Port Timing Specification in VP_VM Bidirectional Mode
No.
Parameter
Signal Name
Direction
Min.
Max.
Unit
Condition/
Reference Signal
US18
Tx rise/fall time
USB_DAT_VP
Out
—
5.0
ns
50 pF
US19
Tx rise/fall time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US20
Tx rise/fall time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US21
Tx duty cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US22
Tx overlap
USB_SE0_VM
Out
–3.0
+3.0
ns
USB_DAT_VP
US26
Rx rise/fall time
USB_DAT_VP
In
—
3.0
ns
35 pF
US27
Rx rise/fall time
USB_SE0_VM
In
—
3.0
ns
35 pF
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Table 91. USB Port Timing Specification in VP_VM Bidirectional Mode (continued)
No.
Parameter
Signal Name
Direction
Min.
Max.
Unit
Condition/
Reference Signal
US28
Rx skew
USB_DAT_VP
In
–4.0
+4.0
ns
USB_SE0_VM
US29
Rx skew
USB_RCV
In
–6.0
+2.0
ns
USB_DAT_VP
4.9.24.4
VP_VM Unidirectional Mode
Table 92 defines the signals for VP_VM unidirectional mode. Figure 106 and Figure 107 show the
transmit and receive waveforms respectively.
Table 92. Signal Definitions—VP_VM Unidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
Tx VP data when USB_TXOE_B is low
USB_SE0_VM
Out
Tx VM data when USB_TXOE_B is low
USB_VP1
In
Rx VP data when USB_TXOE_B is high
USB_VM1
In
Rx VM data when USB_TXOE_B is high
USB_RCV
In
Differential Rx data
Transmit
US32
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US30
US33
US31
US34
US34
Figure 106. USB Transmit Waveform in VP_VM Unidirectional Mode
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Receive
USB_TXOE_B
USB_VP1
US38
USB_VM1
US40
US39
USB_RCV
US41
Figure 107. USB Receive Waveform in VP_VM Unidirectional Mode
Table 93 describes the port timing specification in VP_VM unidirectional mode.
Table 93. USB Timing Specification in VP_VM Unidirectional Mode
No.
Parameter
Signal
Direction
Min.
Max.
Unit
Conditions/Reference Signal
US30
Tx rise/fall time
USB_DAT_VP
Out
—
5.0
ns
50 pF
US31
Tx rise/fall time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US32
Tx rise/fall time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US33
Tx duty cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US34
Tx overlap
USB_SE0_VM
Out
–3.0
+3.0
ns
USB_DAT_VP
US38
Rx rise/fall time
USB_VP1
In
—
3.0
ns
35 pF
US39
Rx rise/fall time
USB_VM1
In
—
3.0
ns
35 pF
US40
Rx skew
USB_VP1
In
–4.0
+4.0
ns
USB_VM1
US41
Rx skew
USB_RCV
In
–6.0
+2.0
ns
USB_VP1
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5
Package Information and Pinout
This section includes the following:
• Mechanical package drawing
• Pin/contact assignment information
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5.1
MAPBGA Production Package 1568-01, 17 × 17 mm, 0.8 Pitch
See Figure 108 for the package drawing and dimensions of the production package.
Figure 108. Production Package: Mechanical Drawing
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5.2
MAPBGA Signal Assignments
Table 94 and Table 95 list MAPBGA signals, alphabetized by signal name, for silicon revisions 2.0 and
2.1, respectively. Table 96 and Table 97 show the signal assignment on the i.MX35 ball map for silicon
revisions 2.0 and 2.1, respectively. The ball map for silicon revision 2.1 is different than the ballmap for
silicon revision 2.0. The layout for each revision is not compatible, so it is important that the correct
ballmap be used to implement the layout.
Table 94. Silicon Revision 2.0 Signal Ball Map Locations
Signal ID
A0
A1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A2
A20
A21
A22
A23
A24
A25
A3
A4
A5
A6
A7
A8
A9
ATA_BUFF_EN1
ATA_CS01
ATA_CS11
ATA_DA01
ATA_DA11
ATA_DA21
ATA_DATA01
ATA_DATA11
ATA_DATA101
ATA_DATA111
ATA_DATA121
Ball Location
A5
D7
F15
D5
F6
B3
D14
D15
D13
D12
E11
D11
E7
D10
E10
D9
E9
D8
E8
C6
D6
B5
C5
A4
B4
A3
T5
V7
T7
R4
V1
R5
Y5
W5
V3
Y2
U3
Signal ID
Ball Location
1
ATA_DATA7
ATA_DATA81
ATA_DATA91
ATA_DIOR1
ATA_DIOW1
ATA_DMACK1
ATA_DMARQ1
ATA_INTRQ1
ATA_IORDY1
ATA_RESET_B1
BCLK
BOOT_MODE0
BOOT_MODE1
CAPTURE
CAS
CLK_MODE0
CLK_MODE1
CLKO
COMPARE
CONTRAST1
CS0
CS1
CS2
CS3
CS4
CS5
CSI_D101
CSI_D111
CSI_D121
CSI_D131
CSI_D141
CSI_D151
CSI_D81
CSI_D91
CSI_HSYNC1
CSI_MCLK1
CSI_PIXCLK1
Y3
U4
W3
Y6
W6
V6
T3
V2
U6
T6
E14
W10
U9
V12
E16
Y10
T10
V10
T12
L16
F17
E19
B20
C19
E18
F19
V16
T15
W16
V15
U14
Y16
U15
W17
V14
W15
Y15
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Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)
Signal ID
ATA_DATA131
ATA_DATA141
ATA_DATA151
ATA_DATA21
ATA_DATA3
ATA_DATA4
ATA_DATA5
ATA_DATA6
CTS2
D0
D1
D10
D11
D12
D13
D14
D15
D2
D3
D3_CLS1
D3_DRDY1
D3_FPSHIFT1
D3_HSYNC1
D3_REV1
D3_SPL1
D3_VSYNC1
D4
D5
D6
D7
D8
D9
DE_B
DQM0
DQM1
DQM2
DQM3
EB0
EB1
ECB
EXT_ARMCLK
EXTAL_AUDIO
EXTAL24M
FEC_COL
FEC_CRS
FEC_MDC
Ball Location
W2
W1
T4
V5
U5
Y4
W4
V4
G5
A2
D4
D2
E6
E3
F5
D1
E2
B2
E5
L17
L20
L15
L18
M17
M18
M19
C3
B1
D3
C2
C1
E4
W19
B19
D17
D16
C18
F18
F16
D19
V8
W20
T20
P3
N5
R1
Signal ID
Ball Location
1
CSI_VSYNC
CSPI1_MISO
CSPI1_MOSI
CSPI1_SCLK
CSPI1_SPI_RDY
CSPI1_SS0
CSPI1_SS1
CTS1
FEC_TDATA0
FEC_TDATA1
FEC_TDATA2
FEC_TDATA3
FEC_TX_CLK
FEC_TX_EN
FEC_TX_ERR
FSR
FST
FUSE_VDD
FUSE_VSS
GPIO1_0
GPIO1_1
GPIO2_0
GPIO3_0
HCKR
HCKT
I2C1_CLK
I2C1_DAT
I2C2_CLK
I2C2_DAT
LBA
LD01
LD11
LD101
LD111
LD121
LD131
LD141
LD151
LD161
LD171
LD181
LD191
LD21
LD201
LD211
LD221
T14
V9
W9
W8
T8
Y8
U8
R3
P5
M4
M5
L6
P4
T1
N4
K5
J1
P13
M11
T11
Y11
U11
V11
K2
J5
M20
N17
L3
M1
D20
F20
G18
H20
J18
J16
J19
J17
J20
K14
K19
K18
K20
G17
K16
K17
K15
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
133
Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)
Signal ID
FEC_MDIO
FEC_RDATA0
FEC_RDATA1
FEC_RDATA2
FEC_RDATA3
FEC_RX_CLK
FEC_RX_DV
FEC_RX_ERR
MA10
MGND
MLB_CLK
MLB_DAT
MLB_SIG
MVDD
NF_CE0
NFALE
NFCLE
NFRB
NFRE_B
NFWE_B
NFWP_B
NGND_ATA
NGND_ATA
NGND_ATA
NGND_CRM
NGND_CSI
NGND_EMI1
NGND_EMI1
NGND_EMI1
NGND_EMI2
NGND_EMI3
NGND_EMI3
NGND_JTAG
NGND_LCDC
NGND_LCDC
NGND_MISC
NGND_MISC
NGND_MLB
NGND_NFC
NGND_SDIO
NVCC_ATA
NVCC_ATA
NVCC_ATA
NVCC_ATA
NVCC_CRM
NVCC_CSI
Ball Location
Signal ID
Ball Location
P1
P2
N2
M3
N1
R2
T2
N3
C4
N11
W13
Y13
W12
P11
G3
F2
E1
F3
F1
G2
F4
M9
P9
L10
L11
N10
H8
H10
J10
J11
J12
K12
M13
K11
L12
M7
K8
M10
K9
N12
N6
P6
P7
P8
R9
R11
LD231
L19
G16
G19
H16
H18
G20
H17
H19
G12
F13
F14
G14
P16
H14
J14
L14
M14
K6
K7
L8
R10
G6
H6
H7
P14
E20
V20
U19
T19
T18
M12
M15
N20
N16
P20
R13
P12
W11
Y9
N13
E15
U10
U18
U1
G1
C20
LD31
LD41
LD51
LD61
LD71
LD81
LD91
NVCC_EMI2
NVCC_EMI2
NVCC_EMI2
NVCC_EMI3
NVCC_JTAG
NVCC_LCDC
NVCC_LCDC
NVCC_LCDC
NVCC_LCDC
NVCC_MISC
NVCC_MISC
NVCC_MISC
NVCC_MLB
NVCC_NFC
NVCC_NFC
NVCC_NFC
NVCC_SDIO
OE
OSC_AUDIO_VDD
OSC_AUDIO_VSS
OSC24M_VDD
OSC24M_VSS
PGND
PHY1_VDDA
PHY1_VDDA
PHY1_VSSA
PHY1_VSSA
PHY2_VDD
PHY2_VSS
POR_B
POWER_FAIL
PVDD
RAS
RESET_IN_B
RTCK
RTS1
RTS2
RW
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
134
Freescale Semiconductor
Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)
Signal ID
Ball Location
Signal ID
Ball Location
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
SD1_CLK
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD10
SD11
SD12
SD13
SD14
SD15
SD16
SD17
SD18
SD19
SD2
SD2_CLK
SD2_CMD
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
SD20
SD21
SD22
SD23
SD24
SD25
SD26
SD27
SD28
SD29
SD3
SD30
SD31
SD4
SD5
G7
G8
G9
H9
F10
G10
F11
G11
V18
Y19
R14
U16
W18
V17
A15
B15
C13
B14
A14
B13
C12
C11
A12
B12
B18
W14
U13
V13
T13
Y14
U12
B11
A11
C10
B10
A9
C9
B9
A8
B8
C8
C16
A7
B7
A18
C15
RXD1
RXD2
SCK4
SCK5
SCKR
SCKT
SD0
SD1
SDCLK
SDCLK_B
SDQS0
SDQS1
SDQS2
SDQS3
SDWE
SJC_MOD
SRXD4
SRXD5
STXD4
STXD5
STXFS4
STXFS5
TCK
TDI
TDO
TEST_MODE
TMS
TRSTB
TTM_PIN
TX0
TX1
TX2_RX3
TX3_RX2
TX4_RX1
TX5_RX0
TXD1
TXD2
USBOTG_OC
USBOTG_PWR
USBPHY1_DM
USBPHY1_DP
USBPHY1_RREF
USBPHY1_UID
USBPHY1_UPLLGND
USBPHY1_UPLLVDD
USBPHY1_UPLLVDD
U2
H3
L4
L5
K3
J4
C17
A19
E12
E13
B17
A13
A10
C7
G15
U17
L1
K4
M2
K1
L2
J6
R17
P15
R15
Y7
R16
T16
M16
G4
H1
H5
J2
H4
J3
R6
H2
U7
W7
N19
P19
R19
N18
N14
N15
P17
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
135
Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)
1
Signal ID
Ball Location
Signal ID
Ball Location
SD6
SD7
SD8
SD9
SDBA0
SDBA1
SDCKE0
SDCKE1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
A17
B16
C14
A16
A6
B6
D18
E17
L7
N7
R7
F8
R8
F9
F12
R12
G13
H15
J15
A1
Y1
J8
M8
N8
J9
USBPHY1_VBUS
USBPHY1_VDDA_BIAS
USBPHY1_VSSA_BIAS
USBPHY2_DM
USBPHY2_DP
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSTBY
WDOG_RST
XTAL_AUDIO
XTAL24M
P18
R20
R18
Y17
Y18
M6
F7
J7
L9
N9
K10
P10
H11
H12
H13
J13
K13
L13
T17
A20
Y20
T9
Y12
V19
U20
Not available for the MCIMX351.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
136
Freescale Semiconductor
Table 95. Silicon Revision 2.1 Signal Ball Map Locations
Signal ID
Ball Location
Signal ID
Ball Location
A0
A1
A10
A11
A12
A13
A14
A15
A16
A18
SDQS1
A19
A2
A21
SDQS2
A22
SDQS3
A24
A25
A3
A4
A5
A6
A7
A8
A9
ATA_BUFF_EN1
ATA_CS0
ATA_CS1
ATA_DA0
ATA_DA1
ATA_DA2
ATA_DATA0
ATA_DATA1
ATA_DATA10
ATA_DATA11
ATA_DATA12
ATA_DATA13
ATA_DATA14
ATA_DATA15
ATA_DATA2
ATA_DATA3
ATA_DATA4
ATA_DATA5
ATA_DATA6
A5
D7
F15
D5
F6
B3
D14
D15
D13
D12
E11
D11
E7
D10
E10
D9
E9
D8
E8
C6
D6
B5
C5
A4
B4
A3
T5
V7
T7
R4
V1
R5
Y5
W5
V3
Y2
U3
W2
W1
T4
V5
U5
Y4
W4
V4
ATA_DATA7
ATA_DATA8
ATA_DATA9
ATA_DIOR
ATA_DIOW
ATA_DMACK
ATA_DMARQ
ATA_INTRQ
ATA_IORDY
ATA_RESET_B
SDQS0
BOOT_MODE0
BOOT_MODE1
CAPTURE
RAS
CLK_MODE0
CLK_MODE1
CLKO
COMPARE
CONTRAST
CS0
CS1
CS2
CS3
CS4
CS5
CSI_D10
CSI_D11
CSI_D12
CSI_D13
CSI_D14
CSI_D15
CSI_D8
CSI_D9
CSI_HSYNC
CSI_MCLK
CSI_PIXCLK
CSI_VSYNC
CSPI1_MISO
CSPI1_MOSI
CSPI1_SCLK
CSPI1_SPI_RDY
CSPI1_SS0
CSPI1_SS1
CTS1
Y3
U4
W3
Y6
W6
V6
T3
V2
U6
T6
E14
W10
U9
V12
E16
Y10
T10
V10
T12
L16
F17
E19
B20
C19
E18
F19
V16
T15
W16
V15
U14
Y16
U15
W17
V14
W15
Y15
T14
V9
W9
W8
T8
Y8
U8
R3
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
137
Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)
Signal ID
Ball Location
Signal ID
Ball Location
CTS2
D0
D1
D10
D11
D12
D13
D14
D15
D2
D3
D3_CLS
D3_DRDY
D3_FPSHIFT
D3_HSYNC
D3_REV
D3_SPL
D3_VSYNC
D4
D5
D6
D7
D8
D9
DE_B
DQM0
SDCKE1
DQM2
DQM3
EB0
EB1
ECB
EXT_ARMCLK
EXTAL_AUDIO
EXTAL24M
FEC_COL
FEC_CRS
FEC_MDC
FEC_MDIO
FEC_RDATA0
FEC_RDATA1
FEC_RDATA2
FEC_RDATA3
FEC_RX_CLK
FEC_RX_DV
FEC_RX_ERR
G5
A2
D4
D2
E6
E3
F5
D1
E2
B2
E5
L17
L20
L15
L18
M17
M18
M19
C3
B1
D3
C2
C1
E4
W19
B19
D17
D16
C18
F18
F16
D19
V8
W20
T20
P3
N5
R1
P1
P2
N2
M3
N1
R2
T2
N3
FEC_TDATA0
FEC_TDATA1
FEC_TDATA2
FEC_TDATA3
FEC_TX_CLK
FEC_TX_EN
FEC_TX_ERR
FSR
FST
FUSE_VDD
FUSE_VSS
GPIO1_0
GPIO1_1
GPIO2_0
GPIO3_0
HCKR
HCKT
I2C1_CLK
I2C1_DAT
I2C2_CLK
I2C2_DAT
LBA
LD0
LD1
LD10
LD11
LD12
LD13
LD14
LD15
LD16
LD17
LD18
LD19
LD2
LD20
LD21
LD22
LD23
LD3
LD4
LD5
LD6
LD7
LD8
LD9
P5
M4
M5
L6
P4
T1
N4
K5
J1
P13
M11
T11
Y11
U11
V11
K2
J5
M20
N17
L3
M1
D20
F20
G18
H20
J18
J16
J19
J17
J20
K14
K19
K18
K20
G17
K16
K17
K15
L19
G16
G19
H16
H18
G20
H17
H19
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
138
Freescale Semiconductor
Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)
Signal ID
Ball Location
Signal ID
Ball Location
MA10
MGND
MLB_CLK
MLB_DAT
MLB_SIG
MVDD
NF_CE0
NFALE
NFCLE
NFRB
NFRE_B
NFWE_B
NFWP_B
NGND_ATA
NGND_ATA
NGND_ATA
NGND_CRM
NGND_CSI
NGND_EMI1
NVCC_EMI1
NGND_EMI1
NGND_EMI2
NGND_EMI3
NGND_EMI3
NGND_JTAG
NGND_LCDC
NGND_LCDC
NGND_MISC
NGND_MISC
NGND_MLB
NGND_NFC
NGND_SDIO
NVCC_ATA
NVCC_ATA
NVCC_ATA
NVCC_ATA
NVCC_CRM
NVCC_CSI
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
NGND_EMI1
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
C4
N11
W13
Y13
W12
P11
G3
F2
E1
F3
F1
G2
F4
M9
P9
L10
L11
N10
H8
H10
J10
J11
J12
K12
M13
K11
L12
M7
K8
M10
K9
N12
N6
P6
P7
P8
R9
R11
G7
G8
G9
H9
F10
G10
F11
G11
NVCC_EMI2
NVCC_EMI2
VSS
NVCC_EMI3
NVCC_JTAG
NVCC_LCDC
NVCC_LCDC
NVCC_LCDC
NVCC_LCDC
NVCC_MISC
NVCC_MISC
NVCC_MISC
NVCC_MLB
NVCC_NFC
NVCC_NFC
NVCC_NFC
NVCC_SDIO
OE
OSC_AUDIO_VDD
OSC_AUDIO_VSS
OSC24M_VDD
OSC24M_VSS
PGND
PHY1_VDDA
PHY1_VDDA
PHY1_VSSA
PHY1_VSSA
PHY2_VDD
PHY2_VSS
POR_B
POWER_FAIL
PVDD
BCLK
RESET_IN_B
RTCK
RTS1
RTS2
RW
RXD1
RXD2
SCK4
SCK5
SCKR
SCKT
DQM1
SD1
G12
F13
F14
G14
P16
H14
J14
L14
M14
K6
K7
L8
R10
G6
H6
H7
P14
E20
V20
U19
T19
T18
M12
M15
N20
N16
P20
R13
P12
W11
Y9
N13
E15
U10
U18
U1
G1
C20
U2
H3
L4
L5
K3
J4
C17
A19
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
139
Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)
Signal ID
Ball Location
Signal ID
Ball Location
SD1_CLK
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD10
SD11
A17
SD13
SD14
SD12
SD16
SD17
SD18
SD19
SD2
SD2_CLK
SD2_CMD
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
SD20
SD21
A20
SD22
SD24
SD25
SD26
SD27
SD28
SD29
SD3
SD30
SD31
SD4
SD5
SD6
SD7
SD8
SD9
SDBA0
SDBA1
SDCKE0
CAS
V18
Y19
R14
U16
W18
V17
A15
B15
C13
B14
A14
B13
C12
C11
A12
B12
B18
W14
U13
V13
T13
Y14
U12
B11
A11
C10
B10
A9
C9
B9
A8
B8
C8
C16
A7
B7
A18
C15
A17
B16
C14
A16
A6
B6
D18
E17
SDCLK
SDCLK_B
SD0
SD15
SD23
A23
SDWE
SJC_MOD
SRXD4
SRXD5
STXD4
STXD5
STXFS4
STXFS5
TCK
TDI
TDO
TEST_MODE
TMS
TRSTB
TTM_PIN
TX0
TX1
TX2_RX3
TX3_RX2
TX4_RX1
TX5_RX0
TXD1
TXD2
USBOTG_OC
USBOTG_PWR
USBPHY1_DM
USBPHY1_DP
USBPHY1_RREF
USBPHY1_UID
USBPHY1_UPLLGND
USBPHY1_UPLLVDD
USBPHY1_UPLLVDD
USBPHY1_VBUS
USBPHY1_VDDA_BIAS
USBPHY1_VSSA_BIAS
USBPHY2_DM
USBPHY2_DP
VDD
VDD
VDD
E12
E13
B17
A13
A10
C7
G15
U17
L1
K4
M2
K1
L2
J6
R17
P15
R15
Y7
R16
T16
M16
G4
H1
H5
J2
H4
J3
R6
H2
U7
W7
N19
P19
R19
N18
N14
N15
P17
P18
R20
R18
Y17
Y18
M6
F7
J7
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
140
Freescale Semiconductor
Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)
1
Signal ID
Ball Location
Signal ID
Ball Location
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
L7
N7
R7
F8
R8
F9
F12
R12
G13
H15
J15
A1
Y1
J8
M8
N8
J9
VSS
VSS
VSS
VSS
VSS
VSS
NVCC_EMI2
VSS
VSS
VSS
VSS
VSS
VSS
VSTBY
WDOG_RST
XTAL_AUDIO
XTAL24M
L9
N9
K10
P10
H11
H12
H13
J13
K13
L13
T17
A20
Y20
T9
Y12
V19
U20
Not available for the MCIMX351.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
141
Table 96. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
VSS
D0
A9
A7
A0
SDB
A0
SD3
0
SD2
7
SD2
4
SDQ
S2
SD2
1
SD1
8
SDQ
S1
SD1
4
SD1
0
SD9
SD6
SD4
SD1
VSS
A
B
D5
D2
A13
A8
A5
SDB
A1
SD3
1
SD2
8
SD2
6
SD2
3
SD2
0
SD1
9
SD1
5
SD1
3
SD1
1
SD7
SDQ
S0
SD2
DQM
0
CS2
B
C
D8
D7
D4
MA1
0
A6
A3
SDQ
S3
SD2
9
SD2
5
SD2
2
SD1
7
SD1
6
SD1
2
SD8
SD5
SD3
SD0
DQM
3
CS3
RW
C
D
D14
D10
D6
D1
A11
A4
A1
A24
A22
A20
A19
A17
A16
A14
A15
DQM DQM
2
1
SDC
KE0
ECB
LBA
D
E
NFC
LE
D15
D12
D9
D3
D11
A2
A25
A23
A21
A18
SDC
LK
SDC
LK_
B
BCL
K
RAS
CAS
SDC
KE1
CS4
CS1
OE
E
F
NFR
E_B
NFA
LE
NFR
B
NFW
P_B
D13
A12
VDD
VDD
VDD
NVC
C_E
MI1
NVC
C_E
MI1
VDD
NVC
C_E
MI2
NVC
C_E
MI2
A10
EB1
CS0
EB0
CS5
LD0
F
G
RTS
2
NFW
E_B
NF_
CE0
TX0
CTS
2
NVC
C_N
FC
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI2
VDD
NVC
C_E
MI3
SDW
E
LD3
LD2
LD1
LD4
LD7
G
H
TX1
TXD
2
RXD
2
TX4_ TX2_
RX1 RX3
NVC
C_N
FC
NVC
C_N
FC
NGN
D_E
MI1
NVC
C_E
MI1
NGN
D_E
MI1
VSS
VSS
VSS
NVC
C_L
CDC
VDD
LD5
LD8
LD6
LD9
LD10
H
J
FST
TX3_ TX5_
RX2 RX0
SCK
T
HCK
T
STX
FS5
VDD
VSS
VSS
NGN
D_E
MI1
NGN
D_E
MI2
NGN
D_E
MI3
VSS
NVC
C_L
CDC
VDD
LD12 LD14 LD11 LD13 LD15
J
K
STX
D5
HCK
R
SCK
R
SRX
D5
FSR
NVC NVC NGN NGN
C_MI C_MI D_MI D_N
SC
SC
FC
SC
VSS
NGN
D_L
CDC
NGN
D_E
MI3
VSS
LD16 LD22 LD20 LD21 LD18 LD17 LD19
K
L
SRX
D4
STX
FS4
I2C2
_CL
K
SCK
4
SCK
5
FEC
_TD
ATA3
VDD
NVC
C_MI
SC
VSS
NGN
D_A
TA
NGN
D_C
RM
NGN
D_L
CDC
VSS
NVC
C_L
CDC
D3_
FPS
HIFT
CON
TRA
ST
D3_
CLS
D3_
HSY
NC
LD23
D3_
DRD
Y
L
M
I2C2
_DAT
STX
D4
FEC
_RD
ATA2
FEC
_TD
ATA1
FEC
_TD
ATA2
VDD
NGN
D_MI
SC
VSS
NGN
D_A
TA
NGN
D_M
LB
FUS
E_V
SS
PGN NGN
D
D_JT
AG
NVC
C_L
CDC
PHY
1_V
DDA
TTM
_PIN
D3_
REV
D3_
SPL
D3_
VSY
NC
I2C1
_CL
K
M
N
FEC
_RD
ATA3
FEC
_RD
ATA1
FEC
_RX
_ER
R
FEC
_TX_
ERR
FEC
_CR
S
NVC
C_A
TA
VDD
VSS
VSS
NGN
D_C
SI
MGN
D
NGN
D_S
DIO
PVD
D
USB
PHY
1_U
PLL
GND
USB
PHY
1_U
PLLV
DD
PHY
1_V
SSA
I2C1
_DAT
USB
PHY
1_UI
D
USB
PHY
1_D
M
PHY
1_V
DDA
N
P
FEC FEC
_MDI _RD
O
ATA0
FEC
_CO
L
FEC FEC
_TX_ _TD
CLK ATA0
NVC
C_A
TA
NVC
C_A
TA
NVC
C_A
TA
NGN
D_A
TA
VSS
MVD
D
PHY
2_V
SS
FUS
E_V
DD
NVC
C_S
DIO
TDI
NVC
C_JT
AG
USB
PHY
1_U
PLLV
DD
USB
PHY
1_V
BUS
USB
PHY
1_D
P
PHY
1_V
SSA
P
R
FEC
_MD
C
FEC
_RX
_CL
K
CTS
1
ATA_
DA0
ATA_
DA2
TXD
1
VDD
VDD
NVC
C_C
RM
NVC
C_M
LB
NVC
C_C
SI
VDD
PHY
2_V
DD
SD1
_DAT
A0
TDO
TMS
TCK
USB
PHY
1_V
SSA
_BIA
S
USB
PHY
1_R
REF
USB
PHY
1_V
DDA
_BIA
S
R
T
FEC
_TX_
EN
FEC
_RX
_DV
ATA_ ATA_ ATA_
DMA DATA BUF
RQ
15
F_E
N
ATA_
RES
ET_
B
ATA_ CSPI
CS1 1_S
PI_R
DY
VST
BY
CLK
_MO
DE1
GPI
O1_
0
COM SD2 CSI_
PAR _DAT VSY
E
A1
NC
CSI_
D11
TRS
TB
VSS
OSC
24M
_VS
S
OSC
24M
_VD
D
EXT
AL24
M
T
U
RTS
1
RXD
1
ATA_ ATA_ ATA_ ATA_
DATA DATA DATA IOR
12
8
3
DY
USB
OTG
_OC
BOO
T_M
ODE
1
RES
ET_I
N_B
GPI
O2_
0
SD2
_DAT
A3
CSI_ SD1
D8 _DAT
A1
SJC
_MO
D
RTC
K
OSC XTAL
_AU 24M
DIO_
VSS
U
CSPI
1_S
S1
SD2
_CM
D
CSI_
D14
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
142
Freescale Semiconductor
Table 96. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch1 (continued)
7
8
9
10
11
12
ATA_ ATA_ ATA_ ATA_ ATA_ ATA_
DA1 INTR DATA DATA DATA DMA
Q
10
6
2
CK
1
ATA_
CS0
EXT
_AR
MCL
K
CSPI
1_MI
SO
CLK
O
GPI
O3_
0
CAP
TUR
E
SD2 CSI_
_DAT HSY
A0
NC
CSI_
D13
CSI_ SD1
D10 _DAT
A3
W ATA_ ATA_ ATA_ ATA_ ATA_ ATA_
DATA DATA DATA DATA DATA DIO
14
13
9
5
1
W
USB
OTG
_PW
R
CSPI CSPI
1_S 1_M
CLK OSI
BOO
T_M
ODE
0
POR
_B
MLB
_SIG
MLB
_CL
K
CSI_
MCL
K
CSI_
D12
CSI_ SD1
D9 _DAT
A2
DE_
B
EXT W
AL_
AUDI
O
Y
TES
T_M
ODE
CSPI POW
1_S ER_
S0
FAIL
CLK
_MO
DE0
GPI
O1_
1
WD
OG_
RST
MLB SD2 CSI_
_DAT _DAT PIXC
A2
LK
CSI_
D15
USB
PHY
2_D
M
SD1
_CM
D
VSS
V
1
VSS
2
3
4
5
6
ATA_ ATA_ ATA_ ATA_ ATA_
DATA DATA DATA DATA DIO
11
7
4
0
R
13
14
SD2
_CL
K
15
16
17
18
SD1
_CL
K
USB
PHY
2_D
P
19
20
XTAL OSC
_AU _AU
DIO DIO_
VDD
V
Y
See Table 95 for pins unavailable in the MCIMX351 SoC.
Table 97. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch
1
2
3
4
5
6
7
8
9
16
17
18
19
20
A
GND
D0
A9
A7
A0
SDB
A0
SD30 SD27 SD24 SD23 SD21 SD18 SD15 SD14 SD10
SD9
SD6
SD4
SD1
GND
A
B
D5
D2
A13
A8
A5
SDB
A1
SD31 SD28 SD26 SD22 SD20 SD19 SD12 SD13 SD11
SD7
SD0
SD2
DQM
0
CS2
B
C
D8
D7
D4
MA1
0
A6
A3
A23
D
D14
D10
D6
D1
A11
A4
A1
A24
A22
A21
A19
E
NFC
LE
D15
D12
D9
D3
D11
A2
A25
SDQ
S3
SDQ
S2
F
NFR
E_B
NFAL
E
NFR
B
NFW
P_B
D13
A12
VDD
7
VDD
7
VDD
7
G
RTS
2
NFW
E_B
NF_
CE0
TX0
CTS
2
NVC
C_N
FC
NVC
C_E
MI1
NVC
C_E
MI1
H
TX1
TXD
2
RXD
2
TX4_ TX2_
RX1 RX3
NVC
C_N
FC
NVC
C_N
FC
J
FST
TX3_ TX5_
RX2 RX0
SCK
T
HCK
T
STX
FS5
K
STX
D5
HCK
R
SCK
R
SRX
D5
L
SRX
D4
STX
FS4
I2C2
_CLK
SCK
4
M
I2C2
_DAT
N
FEC
_RD
ATA3
A20
11
12
SD17 SD16
13
14
15
A17
SD8
SD5
SD3
DQM
1
DQM
3
CS3
RW
C
A18
A16
A14
A15
DQM
2
SDC
KE1
SDC
KE0
ECB
LBA
D
SDQ
S1
SDC
LK
SDC
LK_B
SDQ
S0
BCL
K
RAS
CAS
CS4
CS1
OE
E
GND
NVC
C_E
MI1
VDD
7
NVC
C_E
MI2
GND
A10
EB1
CS0
EB0
CS5
LD0
F
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI2
VDD
6
NVC
C_E
MI3
SDW
E
LD3
LD2
LD1
LD4
LD7
G
GND
NVC
C_E
MI1
NVC
C_E
MI1
GND
GND
NVC
C_E
MI2
NVC
C_L
CDC
VDD
5
LD5
LD8
LD6
LD9
LD10
H
VDD
1
GND
GND
GND
GND
GND
GND
NVC
C_L
CDC
VDD
5
LD12 LD14 LD11 LD13 LD15
J
FSR
NVC NVC
C_MI C_MI
SC
SC
GND
GND
GND
GND
GND
GND
LD16 LD22 LD20 LD21 LD18 LD17 LD19
K
SCK
5
FEC
_TDA
TA3
VDD
2
NVC
C_MI
SC
GND
GND
GND
GND
GND
NVC
C_L
CDC
D3_F
PSHI
FT
CON
TRA
ST
D3_
CLS
D3_
HSY
NC
D3_
DRD
Y
L
STX
D4
FEC FEC FEC
_RD _TDA _TDA
ATA2 TA1
TA2
VDD
2
GND
GND
GND
GND
FUS
E_V
SS
PGN
D
GND
NVC
C_L
CDC
PHY TTM
1_VD _PAD
DA
D3_
REV
D3_S D3_V I2C1
PL
SYN _CLK
C
M
FEC
_RD
ATA1
FEC FEC
_RX_ _TX_
ERR ERR
NVC
C_AT
A
VDD
3
GND
GND
GND
MGN
D
GND
PVD
D
USB USB PHY I2C1
PHY PHY 1_VS _DAT
1_UP 1_UP SA
LLG LLVD
ND
D
USB
PHY
1_UI
D
N
FEC
_CR
S
SD29 SD25
10
LD23
USB
PHY
1_D
M
PHY
1_VD
DA
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
143
Table 97. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch (continued)
1
2
3
P
FEC
_MDI
O
FEC
_RD
ATA0
FEC
_CO
L
R
FEC
_MD
C
FEC
_RX_
CLK
T
9
10
11
12
13
14
15
FEC FEC NVC NVC NVC
_TX_ _TDA C_AT C_AT C_AT
CLK
TA0
A
A
A
GND
GND
MVD
D
PHY
2_VS
S
FUS
E_V
DD
NVC
C_S
DIO
TDI
NVC USB USB USB PHY
C_JT PHY PHY PHY 1_VS
AG 1_UP 1_VB 1_DP SA
LLVD
US
D
P
CTS
1
ATA_
DA0
ATA_
DA2
TXD
1
VDD
3
VDD
3
NVC
C_C
RM
NVC
C_M
LB
NVC
C_C
SI
VDD
4
PHY SD1_
2_VD DATA
D
0
TDO
TMS
TCK
USB
PHY
1_VS
SA_
BIAS
USB
PHY
1_VD
DA_
BIAS
R
FEC FEC
_TX_ _RX_
EN
DV
ATA_
DMA
RQ
ATA_
DATA
15
ATA_
BUF
F_E
N
ATA_
RES
ET_B
ATA_
CS1
CSPI
1_SP
I_RD
Y
VST
BY
CLK_ GPIO COM SD2_
MOD 1_0
PAR DATA
E1
E
1
CSI_
VSY
NC
CSI_
D11
TRS
TB
GND
OSC OSC EXTA
24M_ 24M_ L24M
VSS VDD
T
U
RTS
1
RXD
1
ATA_
DATA
12
ATA_ ATA_ ATA_
DATA DATA IORD
8
3
Y
USB
OTG
_OC
CSPI
1_SS
1
BOO
T_M
ODE
1
RES
ET_I
N_B
GPIO SD2_ SD2_
2_0 DATA CMD
3
CSI_
D14
CSI_
D8
SD1_ SJC_
DATA MOD
1
OSC
_AU
DIO_
VSS
XTAL
24M
U
V
ATA_
DA1
ATA_
INTR
Q
ATA_
DATA
10
ATA_ ATA_
DATA DATA
6
2
ATA_
DMA
CK
ATA_
CS0
EXT_ CSPI
ARM 1_MI
CLK
SO
CLK
O
GPIO
3_0
CAP
TUR
E
CSI_
HSY
NC
CSI_
D13
CSI_
D10
SD1_ SD1_ XTAL
DATA CLK _AU
3
DIO
OSC
_AU
DIO_
VDD
V
W
ATA_ ATA_ ATA_
DATA DATA DATA
14
13
9
ATA_ ATA_
DATA DATA
5
1
ATA_
DIO
W
USB
OTG
_PW
R
CSPI CSPI
1_SC 1_M
LK
OSI
BOO
T_M
ODE
0
POR
_B
MLB MLB SD2_
_SIG _CLK CLK
CSI_
MCL
K
CSI_
D12
CSI_
D9
SD1_
DATA
2
DE_
B
EXTA
L_AU
DIO
W
Y
GND
ATA_ ATA_ ATA_
DATA DATA DIOR
4
0
TES
T_M
ODE
CSPI POW CLK_ GPIO WDO MLB SD2_ CSI_
1_SS ER_ MOD 1_1
G_R _DAT DATA PIXC
0
FAIL
E0
ST
2
LK
CSI_
D15
USB
PHY
2_D
M
USB SD1_
PHY CMD
2_DP
GND
Y
16
17
1
6
ATA_ ATA_
DATA DATA
11
7
2
3
4
4
5
5
6
6
7
7
8
8
9
10
11
12
SD2_
DATA
0
13
14
15
16
17
18
RTC
K
18
19
USB
PHY
1_R
REF
19
20
20
Product Documentation
All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
144
Freescale Semiconductor
7
Revision History
Table 98 shows the revision history of this document. Note: There were no revisions of this document
between revision 1 and revision 4 or between revision 6 and revision 7.
Table 98. i.MX35 Data Sheet Revision History
Revision
Number
Date
10
06/2012
• In Table 2, "Functional Differences in the i.MX35 Parts," on page 3, added two columns for part
numbers MCIMX353 and MCIMX357.
• Added Table 29, "Clock Input Tolerance," on page 31 in Section 4.9.3, “DPLL Electrical
Specifications.”
• Updated Table 39, "DDR2 SDRAM Timing Parameter Table," on page 50 for DDR2-400 values.
• Updated Table 41, "DDR2 SDRAM Write Cycle Parameters," on page 52 for DDR2-400 values.
• Added Table 15, "AC Requirements of I/O Pins," on page 24.
• Updated WE4 parameter in Table 33, "WEIM Bus Timing Parameters," on page 37.
9
08/2010
• Updated Table 32, “NFC Timing Parameters.”
• Updated Table 33, “WEIM Bus Timing Parameters.”
8
04/2010
• Updated Table 14, “I/O Pin DC Electrical Characteristics.”
Substantive Change(s)
7
12/18/2009 • Updated Table 1, “Ordering Information.”
6
10/21/2009 •
•
•
•
Added information for silicon rev. 2.1
Updated Table 1, “Ordering Information.”
Added Table 95, “Silicon Revision 2.1 Signal Ball Map Locations.”
Added Table 97, “Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch.”
5
08/06/2009 •
•
•
•
Added a line for TA = –40 to 85 oC in Table 14, “I/O Pin DC Electrical Characteristics”
Filled in TBDs in Table 14.
Revised Figure 15 and Table 33 by removing FCE = 0 and FCE = 1. Added footnote 3 to the table.
Added Table 26, “AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive
(1.8 V).”
4
04/30/2009 Note: There were no revisions of this document between revision 1 and revision 4.
• In Section 4.3.1, “Powering Up,” reverse positions of steps 5 and 6.
• Updated values in Table 10, “i.MX35 Power Modes.”
• Added Section 4.4, “Reset Timing.”
• In Section 4.8.2, “AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and SDRAM
Modes),” removed Slow Slew rate tables, relabeled Table 24, “AC Electrical Characteristics of DDR
Type IO Pins in mDDR Mode,” and Table 25, “AC Electrical Characteristics of DDR Type IO Pins in
SDRAM Mode,” to exclude mention of slew rate.
• In Section 4.9.5.2, “Wireless External Interface Module (WEIM),” modified Figure 16, “Synchronous
Memory Timing Diagram for Read Access—WSC = 1,” through Figure 21, “Muxed A/D Mode Timing
Diagram for Synchronous Read Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7.”
• In Section 4.9.6, “Enhanced Serial Audio Interface (ESAI) Timing Specifications,” modified
Figure 36, “ESAI Transmitter Timing,” and Figure 37, “ESAI Receiver Timing,” to remove extraneous
signals. Removed a note from Figure 36, “ESAI Transmitter Timing.”
3
03/2009
• In Section 4.3.1, “Powering Up,” reverse positions of steps 5 and 6.
2
02/2009
• Added the following parts to Table 1, “Ordering Information”: PCIMX357CVM5B,
MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Throughout
consumer data sheet: Removed or updated information related to Media Local Bus
interface.Updated Section 4.3.1, “Powering Up.”
• Updated values in Table 10, “i.MX35 Power Modes.”
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
145
Table 98. i.MX35 Data Sheet Revision History (continued)
Revision
Number
Date
1
12/2008
• Updated Section 4.3.1, “Powering Up.”
• Section 4.7, “Module-Level AC Electrical Specifications”: Updated NFC, SDRAM and mDDR
SDRAM timing. Inserted DDR2 SDRAM timing.
0
10/2008
Initial public release
Substantive Change(s)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
146
Freescale Semiconductor
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Rev. 10
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