Data Sheet

NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5777M
Rev. 6, 06/2016
MPC5777M
MPC5777M Microcontroller
Data Sheet
• Three main CPUs, single issue, 32-bit CPU core complexes
(e200z7), one of which is a dedicated lockstep core.
– Power Architecture® embedded specification
compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 16 KB I-Cache and 4 KB D-Cache
• I/O Processor, dual issue, 32-bit CPU core complex
(e200z4), with
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– Lightweight Signal Processing Auxiliary Processing
Unit (LSP APU) instruction support for digital signal
processing (DSP)
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 8 KB I-Cache
• 8640 KB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 404 KB on-chip general-purpose SRAM including 64 KB
standby RAM (+ 192 KB data RAM included in the
CPUs). Of this 404 KB, 64 KB can be powered by a
separate supply so the contents of this portion can be
preserved when the main MCU is powered down.
• Multichannel direct memory access controllers (eDMA): 2
x 64 channels per eDMA (128 channels total)
• Triple Interrupt controller (INTC)
•
•
•
•
•
•
•
•
•
•
•
416 TEPBGA
512 TEPBGA
27mm x 27 mm
25 mm x 25 mm
– Dual phase-locked loops with stable clock domain for
peripherals and FM modulation domain for
computational shell
Dual crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters with
end-to-end ECC
Hardware Security Module (HSM) to provide robust
integrity checking of flash memory
System Integration Unit Lite (SIUL)
Boot Assist Module (BAM) supports factory programming
using serial bootload through ‘UART Serial Boot Mode
Protocol’. Physical interface (PHY) can be:
– UART/LIN
– CAN
GTM104 — generic timer module
Enhanced analog-to-digital converter system with
– Twelve separate 12-bit SAR analog converters
– Ten separate 16-bit Sigma-Delta analog converters
Eight deserial serial peripheral interface (DSPI) modules
Two Peripheral Sensor Interface (PSI5) controllers
Three LIN and three UART communication interface
(LINFlexD) modules (6 total)
– LINFlexD_0 is a Master/Slave
– LINFlexD_1, LINFlexD_2, LINFlexD_14,
LINFlexD_15, and LINFlexD_16 are Masters
Four modular controller area network (MCAN) modules
and one time-triggered controller area network
(M-TTCAN)
External Bus Interface (EBI)
– Dual routing of accesses to EBI
– Access path determined by access address
– Access path downstream of PFLASH controller
– Allows EBI accesses to share buffer and prefetch
capabilities of internal flash
– Allows internal flash accesses to be remapped to
memories connected to EBI
NXP reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
Table of Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Device feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Package pinouts and signal descriptions . . . . . . . . . . . . . . . .10
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Pin/ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2.1 Power supply and reference voltage pins/balls .15
2.2.2 System pins/balls. . . . . . . . . . . . . . . . . . . . . . . .16
2.2.3 LVDS pins/balls . . . . . . . . . . . . . . . . . . . . . . . . .17
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21
3.3 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . .23
3.4 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.5 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . .27
3.6 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.6.1 I/O input DC characteristics . . . . . . . . . . . . . . . .31
3.6.2 I/O output DC characteristics. . . . . . . . . . . . . . .35
3.7 I/O pad current specification . . . . . . . . . . . . . . . . . . . . .42
3.8 Reset pad (PORST, ESR0) electrical characteristics . .45
3.9 Oscillator and FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.10 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.10.1 ADC input description . . . . . . . . . . . . . . . . . . . .53
3.10.2 SAR ADC electrical specification. . . . . . . . . . . .54
3.10.3 S/D ADC electrical specification . . . . . . . . . . . .58
3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.12 LVDS Fast Asynchronous Serial Transmission
(LFAST) pad electrical characteristics . . . . . . . . . . . . .67
3.12.1 LFAST interface timing diagrams . . . . . . . . . . .68
3.12.2 LFAST and MSC/DSPI LVDS interface
electrical characteristics . . . . . . . . . . . . . . . . . .69
3.12.3 LFAST PLL electrical characteristics . . . . . . . . .72
3.13 Aurora LVDS electrical characteristics . . . . . . . . . . . . .73
3.14 Power management: PMC, POR/LVD, sequencing . . .75
3.14.1 Power management electrical characteristics . .75
4
5
3.14.2 Power management integration . . . . . . . . . . . . 75
3.14.3 3.3 V flash supply . . . . . . . . . . . . . . . . . . . . . . . 76
3.14.4 Device voltage monitoring . . . . . . . . . . . . . . . . 77
3.14.5 Power up/down sequencing . . . . . . . . . . . . . . . 79
3.15 Flash memory electrical characteristics. . . . . . . . . . . . 80
3.15.1 Flash memory program and erase
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.15.2 Flash memory FERS program and
erase specifications . . . . . . . . . . . . . . . . . . . . . 82
3.15.3 Flash memory Array Integrity and Margin
Read specifications . . . . . . . . . . . . . . . . . . . . . 83
3.15.4 Flash memory module life specifications . . . . . 84
3.15.5 Data retention vs program/erase cycles. . . . . . 84
3.15.6 Flash memory AC timing specifications . . . . . . 85
3.15.7 Flash read wait state and address pipeline
control settings . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.16.1 Debug and calibration interface timing . . . . . . . 86
3.16.2 DSPI timing with CMOS and LVDS pads . . . . . 94
3.16.3 FEC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.16.4 FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . 115
3.16.5 PSI5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.16.6 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.16.7 External Bus Interface (EBI) Timing . . . . . . . . 119
3.16.8 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.16.9 GPIO delay timing . . . . . . . . . . . . . . . . . . . . . 124
3.16.10Package characteristics. . . . . . . . . . . . . . . . . 124
3.17 416 TEPBGA (production) case drawing . . . . . . . . . 125
3.18 416 TEPBGA (emulation) case drawing. . . . . . . . . . 127
3.19 512 TEPBGA case drawing . . . . . . . . . . . . . . . . . . . 130
3.20 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . 132
3.20.1 General notes for specifications at
maximum junction temperature . . . . . . . . . . . 132
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MPC5777M Microcontroller Data Sheet, Rev. 6
2
NXP Semiconductors
•
•
•
•
— Access path via dedicated AXBS slave port
– Avoids contention with other memory accesses
Two Dual-channel FlexRay controllers
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard
Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)
Self-test capability
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
3
Introduction
1
Introduction
1.1
Document overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5777M series of
microcontroller units (MCUs). For functional characteristics, see the MPC5777M Microcontroller Reference Manual.
1.2
Description
This family of MCUs is targeted at automotive powertrain controller and chassis control applications from single cylinder
motorcycles at the very bottom end; through 4 to 8 cylinder gasoline and diesel engines; transmission control; steering and
breaking applications; to high end hybrid and advanced combustion systems at the top end.
Many of the applications are considered to be functionally safe and the family is designed to achieve ISO26262 ASIL-D
compliance.
1.3
Device feature
Table 1. MPC5777M feature
Feature
MPC5777M
Process
Main processor
55 nm
Core
e200z7
Number of main cores
2
Number of checker cores
1
Local RAM (per main core)
Single precision floating point
Yes
LSP
No
VLE
Yes
Cache
I/O processor
16 KB Instruction
64 KB Data
16 KB Instruction
4 KB Data
Core
e200z4
Local RAM
16 KB instruction
64 KB Data
Single precision floating point
Yes
LSP
Yes
VLE
Yes
Cache
8 KB instruction
Main processor frequency
300 MHz1
I/O processor frequency
200 MHz
MMU entries
0
MPU
Yes
Semaphores
Yes
MPC5777M Microcontroller Data Sheet, Rev. 6
4
NXP Semiconductors
Introduction
Table 1. MPC5777M feature (continued)
Feature
MPC5777M
CRC channels
2
Software watchdog timer
(Task SWT/Safety SWT)
4 (3/1)
Core Nexus class
3+
Sequence processing unit (SPU)
Yes
Debug and calibration interface (DCI) / run control
module
Yes
System SRAM
404 KB
Flash memory
8640 KB
Flash memory fetch accelerator
4  256 bit
Data flash memory (EEPROM)
8  64 KB
+ 2  16 KB
Flash memory overlay RAM
16 KB
External bus
32 bit
Calibration interface
64-bit IPS Slave
2  64
DMA channels
DMA Nexus Class
3+
LINFlex (UART/MSC)
6 (3/3)
MCAN/TTCAN
4/1
DSPI
(SPI/MSC/sync SCI)
8 (4/3/1)
Microsecond bus downlink
Yes
SENT bus
15
I
2C
2
PSI5 bus
5
PSI5-S UART-to-PSI5 interface
Yes
FlexRay
2  dual channel
Ethernet
MII / RMII
(SIPI / LFAST2) Interprocessor Communication
Zipwire
Interface
System timers
High speed
8 PIT channels
3 AUTOSAR® (STM)
64-bit PIT
BOSCH GTM Timer3
Yes
GTM RAM
Interrupt controller
58 KB
727 sources
ADC (SAR)
12
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
5
Introduction
Table 1. MPC5777M feature (continued)
Feature
MPC5777M
ADC (SD)
10
Temperature sensor
Yes
Self test controller
Yes
PLL
Dual PLL with FM
Integrated linear voltage regulator
None
External power supplies
5V
3.3 V7
1.2 V
Low-power modes
Packages
1
2
3
4
5
Stop mode
Slow mode
• 416 TEPBGA4
• 512 TEPBGA5
Includes four user-programmable CPU cores and one safety core. The main computational shell consists of
dual e200z7 CPUs operating at 300 MHz with a third identical core running as a safety checker core in delayed
lockstep mode with one of the dual e200z7 cores. The I/O subsystem includes a CPU targeted at managing
the peripherals. This is an e200z4 CPU running at 200 MHz. The fifth CPU is an e200z0 running at 100 MHz
and is embedded in the Hardware Security Module. All CPUs are compatible with the Power Architecture.
LVDS Fast Asynchronous Serial Transmission
BOSCH® is a registered trademark of Robert Bosch GmbH.
416 TEPBGA package supports development and production applications with the same package footprint.
512 TEPBGA package supports development and production applications with the same package footprint.
MPC5777M Microcontroller Data Sheet, Rev. 6
6
NXP Semiconductors
Block diagram
7
1.4
Introduction
The figures below show the top-level block diagrams.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductor s
NXP Semiconductors
MPC5777M Microcontroller Data Sheet, Rev. 6
8
Introduction
Figure 1. Block diagram
Package pinouts and signal descriptions
EBI
TDM
PCM
LVIIO
2 x XBIC
LVIFLASH
2 x AXBS
LVI 1.2V
2 x SMPU
HVI 1.2V
PRAM
PMC
PFLASH
SEMA4
TSENS
INTC_0
4 x SWT
3 x STM
FLEXRAY_1
IIC_1
2 x DMA
9 x SAR ADC
12 x CMU
FEC
PSI5_1
PSI5_S_0
BAF
GTM
SENT_1
CRC_1
SSCM
3 x SAR ADC
3 x DSPI
FCCU
Peripheral Bus (AIPS_1)
PASS
CFLASH_0
PSI5_0
2 x LFAST
FLEXRAY_0
2 x LINFlexD
SENT_0
Peripheral
Cluster B
5 x SD ADC
IIC_0
2 x SIPI
SUIL2
5 x DSPI
ME
4 x LINFlexD
CMU_PLL
4 x MCAN
PLL
TTCAN_0
OSC_DIG
SRAM CAN
RCOSC_DIG_0
5 x SD ADC
CGM
HSM INTERFACE
RGM
DTS
PCU
Peripheral
Cluster A
JDC
WKPU
Peripheral Bus (AIPS_0)
STCU2
JTAGM
MEMU
IMA
CRC_0
10 x DMAMUX
ATX
2 x PIT_RTC
Figure 2. Periphery allocation
2
Package pinouts and signal descriptions
See the MPC5777M Microcontroller Reference Manual for signal information.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
9
NXP Semiconductors
2.1
Package pinouts
The BGA ballmap package pinouts for the 416 and 512 production and emulation devices are shown in the following figures.
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W>΀ϭϮ΁
W>΀ϭϰ΁
W:΀ϲ΁
E
W'΀ϳ΁
W<΀ϭϭ΁
W<΀ϭϬ΁
W΀ϭϰ΁
W΀ϯ΁
W΀ϭ΁
W>΀ϵ΁
W>΀ϭϭ΁
W>΀ϭϯ΁
W>΀ϭϱ΁
W:΀ϳ΁
W:΀ϱ΁
s^^ͺ,s
WZ΀ϭϯ΁
Wz΀ϯ΁
Wz΀Ϯ΁
sͺ,sͺ s^^ͺ,sͺ
Zͺ
Zͺ
WZ΀ϭϭ΁
WZ΀ϭϬ΁
W/΀Ϯ΁
W/΀ϯ΁
Wz΀ϭ΁
Wz΀Ϭ΁
W/΀ϰ΁
W/΀ϱ΁
WZ΀ϴ΁
WZ΀ϵ΁
W'΀ϱ΁
W'΀ϲ΁
W/΀ϲ΁
Wy΀ϭϱ΁
Wy΀ϭϰ΁
E
W΀ϳ΁
W΀ϲ΁
&
WZ΀ϲ΁
WZ΀ϳ΁
'
W/΀ϳ΁
W'΀ϴ΁
W'΀ϵ΁
W'΀ϭϭ΁
s^^ͺ,sͺ sͺ,sͺ sͺ,sͺ s^^ͺ,sͺ
s ^
s ^
Z ^
Z ^
sͺ>s
W΀ϵ΁
W΀ϴ΁
d^dDK
W&΀ϭϰ΁
Wt΀ϴ΁
Wt΀ϵ΁
E
s^^ͺ>s
s^^ͺ>s
W΀ϲ΁
W/΀ϭϱ΁
W΀ϳ΁
W΀ϭϰ΁
Wt΀ϲ΁
Wt΀ϳ΁
W
s^^ͺ>s
s^^ͺ>s
E
W΀ϳ΁
W/΀ϭϰ΁
W&΀ϭϯ΁
W΀ϲ΁
Wt΀ϰ΁
Wt΀ϱ΁
Z
s^^ͺ>s
s^^ͺ>s
E
W<΀ϭϯ΁
W<΀ϭϮ΁
W΀ϱ΁
s^^ͺ,sͺ
K^
Wt΀Ϯ΁
Wt΀ϯ΁
d
s^^ͺ>s
s^^ͺ>s
W:΀ϭϱ΁
W:΀ϭϰ΁
yd>
yd>
Wt΀Ϭ΁
Wt΀ϭ΁
h
sͺ>s
W:΀ϭϯ΁
W:΀ϭϮ΁
E
sͺ,sͺ
/Kͺ:d'
s^^ͺ,s
sͺ,sͺ
/Kͺ/
s
W:΀ϭϬ΁
W:΀ϭϭ΁
W&΀ϭϬ΁
W&΀ϵ΁
Ws΀ϲ΁
E
t
W:΀ϴ΁
W:΀ϵ΁
W&΀ϭϮ΁
W&΀ϭϭ΁
Ws΀ϭϰ΁
Ws΀ϭϱ΁
z
s^^ͺ,s
W,΀ϲ΁
W:΀ϰ΁
W,΀ϱ΁
Ws΀ϭϮ΁
Ws΀ϭϯ΁
W&΀ϴ΁
W:΀ϯ΁
Ws΀ϭϬ΁
Ws΀ϭϭ΁
sͺ,sͺ/
KͺD/E
W:΀Ϯ΁
Ws΀ϴ΁
Ws΀ϵ΁
W΀ϭϱ΁
W΀Ϯ΁
W/΀ϭϯ΁
W/΀ϭϭ΁
W&΀ϭ΁
W΀ϵ΁
W΀ϭϭ΁
W΀ϵ΁
W΀ϯ΁
W&΀ϳ΁
W΀ϭϱ΁
s^^ͺ,s
sͺ,sͺ
/KͺD/E
Ws΀ϳ΁
Ws΀ϱ΁
W'΀ϭϮ΁
W΀ϭϯ΁
W/΀ϭϮ΁
W/΀ϭϬ΁
W&΀Ϭ΁
W΀ϭϬ΁
W΀ϭϬ΁
W΀ϴ΁
W΀ϴ΁
W&΀ϲ΁
W:΀Ϭ΁
W:΀ϭ΁
s^^ͺ,s
Ws΀ϰ΁
Ws΀ϯ΁
Ws΀Ϯ΁
Ws΀ϭ΁
&
Wz΀ϰ΁
Ws΀Ϭ΁
'
sͺ,sͺ s^^ͺ,sͺ
Z Ϯ Z Ϯ
,
E
E
:
E
E
E
WZ΀ϰ΁
WZ΀Ϯ΁
Wy΀ϭϮ΁
WZ΀ϭ΁
E
E
WZ΀ϱ΁
WZ΀ϯ΁
Wy΀ϭϯ΁
WZ΀Ϭ΁
Ϯ
ϯ
ϰ
ϱ
ϲ
ϳ
<
ϭ
s^^ͺ,sͺ sͺ,sͺ
sͺ,sͺ
s^^ͺ,s
sͺ^
sͺ^
/Kͺ&>y
s^^ͺ,sͺ sͺ,sͺ
sͺ,sͺ
s^^ͺ,s
sͺ
sͺ
/Kͺ&>y
ϴ
ϵ
ϭϬ
ϭϭ
:
<
W'΀ϭϯ΁
WE΀ϵ΁
WE΀ϭϬ΁
WZ΀ϭϮ΁
Wt΀ϭϱ΁
^ZϬ
WE΀ϴ΁
WE΀ϭϭ΁
z
Wt΀ϭϰ΁
W΀ϰ΁
>
D
sͺ,sͺ sͺ,sͺ
/Kͺ/
/Kͺ/
W^΀Ϭ΁
W^΀Ϯ΁
W^΀ϰ΁
W^΀ϲ΁
W^΀ϴ΁
W^΀ϭϬ΁
W^΀ϭϮ΁
W^΀ϭϰ΁
E
Wd΀Ϭ΁
Wd΀Ϯ΁
Wd΀ϰ΁
Wd΀ϲ΁
Wd΀ϴ΁
Wd΀ϭϬ΁
Wd΀ϭϮ΁
Wd΀ϭϰ΁
W^΀ϭ΁
W^΀ϯ΁
W^΀ϱ΁
W^΀ϳ΁
W^΀ϵ΁
W^΀ϭϭ΁
W^΀ϭϯ΁
W^΀ϭϱ΁
sͺ,sͺ
/Kͺ&>y
Wd΀ϭ΁
Wd΀ϯ΁
Wd΀ϱ΁
Wd΀ϳ΁
Wd΀ϵ΁
Wd΀ϭϭ΁
Wd΀ϭϯ΁
Wd΀ϭϱ΁
ϭϮ
ϭϯ
ϭϰ
ϭϱ
ϭϲ
ϭϳ
ϭϴ
ϭϵ
ϮϬ
Ϯϭ
ϮϮ
Ϯϯ
Ϯϰ
Ϯϱ
Ϯϲ
Ϯϳ
Ϯϴ
Figure 5. 512-ball BGA production device pinout (top view)
sͺ,sͺ sͺ,sͺ
/KͺD/E /Kͺ/
sͺ,sͺ
s^^ͺ,s
/KͺD/E
sͺ,sͺ
/Kͺ&>y
Ϯϵ
ϯϬ
,
:
<
12
Package pinouts and signal descriptions
MPC5777M Microcontroller Data Sheet, Rev. 6
13
Ϯ
ϯ
ϰ
ϱ
ϲ
ϳ
ϴ
ϵ
ϭϬ
ϭϭ
ϭϮ
ϭϯ
ϭϰ
ϭϱ
ϭϲ
ϭϳ
ϭϴ
ϭϵ
ϮϬ
Ϯϭ
ϮϮ
Ϯϯ
Ϯϰ
Ϯϱ
Ϯϲ
Ϯϳ
Ϯϴ
Ϯϵ
sͺ,sͺ
/KͺD/E
E
E
Wy΀Ϭ΁
WD΀ϭϱ΁
WE΀Ϭ΁
E
E
E
Wy΀ϰ΁
Wy΀ϯ΁
Wy΀ϭ΁
WY΀ϭϯ΁
WY΀ϭϭ΁
WY΀ϵ΁
E
WY΀ϳ΁
WY΀ϱ΁
WY΀ϯ΁
E
Wy΀ϭϭ΁
Wy΀ϵ΁
Wy΀ϳ΁
E
E
E
E
sͺ,sͺ
/KͺD/E
sͺ,sͺ
/KͺD/E
E
WD΀ϭϰ΁
WD΀ϭϯ΁
WD΀ϭϮ΁
WD΀ϭϭ΁
E
E
Wy΀Ϯ΁
WY΀ϭϱ΁
WY΀ϭϰ΁
WY΀ϭϮ΁
WY΀ϭϬ΁
WY΀ϴ΁
E
WY΀ϲ΁
WY΀ϰ΁
E
E
Wy΀ϭϬ΁
Wy΀ϴ΁
Wy΀ϲ΁
Wy΀ϱ΁
E
E
sͺ,sͺ
s^^ͺ,s
/KͺD/E
ϯϬ
E
s^^ͺ,s
E
E
E
E
E
E
E
E
s^^ͺ,s
MPC5777M Microcontroller Data Sheet, Rev. 6
E
E
E
E
&
WE΀Ϯ΁
WE΀ϭ΁
s^^ͺ,s
sͺ,sͺ
/KͺD/E
W,΀ϭϯ΁
W&΀Ϯ΁
W&΀ϱ΁
WD΀ϭϬ΁
W,΀ϭϱ΁
W΀ϭϭ΁
W΀ϭϯ΁
W΀ϭϮ΁
W΀Ϭ΁
W΀Ϯ΁
W,΀ϵ΁
W,΀ϯ΁
W΀ϭϭ΁
WD΀ϵ΁
W΀Ϭ΁
W΀ϭ΁
sͺ,sͺ/
KͺD/E
s^^ͺ,s
E
E
&
'
WE΀ϰ΁
WE΀ϯ΁
W΀ϭϰ΁
s^^ͺ,s
sͺ,sͺ
/KͺD/E
W,΀ϭϮ΁
W&΀ϯ΁
W,΀ϭϰ΁
W&΀ϰ΁
W΀ϭϬ΁
W΀ϭϮ΁
W΀ϭϱ΁
W΀ϭ΁
W΀ϯ΁
W,΀ϰ΁
W΀ϭϬ΁
W΀ϭϭ΁
W΀ϭϬ΁
W΀ϭϯ΁
sͺ,sͺ
/KͺD/E
s^^ͺ,s
W΀Ϯ΁
E
E
'
,
E
E
W΀ϵ΁
W΀ϭϱ΁
W΀ϭϮ΁
W΀ϵ΁
s^^ͺ,s
s^^ͺ,s
,
:
E
WE΀ϱ΁
W΀ϳ΁
W΀ϴ΁
s^^ͺ,s
sͺ,sͺ
/Kͺ&>y
WD΀Ϯ΁
WD΀Ϭ΁
W<΀ϭϰ΁
W΀ϭϰ΁
WD΀ϲ΁
W,΀ϳ΁
W,΀ϴ΁
W,΀ϭϬ΁
W,΀ϭ΁
W,΀Ϭ΁
W΀ϱ΁
W΀ϴ΁
<
WE΀ϲ΁
WE΀ϳ΁
W΀ϱ΁
W΀ϲ΁
W>΀ϭ΁
s^^ͺ,s
WD΀ϯ΁
WD΀ϭ΁
W<΀ϭϱ΁
WD΀ϰ΁
WD΀ϱ΁
WD΀ϳ΁
WD΀ϴ΁
W,΀Ϯ΁
W'΀ϭϱ΁
W΀ϲ΁
W΀ϳ΁
W΀ϰ΁
Wt΀ϭϰ΁
^ZϬ
W'΀ϭϯ΁
W'΀ϭϰ΁
W΀ϱ΁
Wt΀ϭϮ΁
Wt΀ϭϯ΁
>
sͺ>sͺ
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
sͺ>s
W΀ϰ΁
WKZ^d
W,΀ϭϭ΁
W&΀ϭϱ΁
Wt΀ϭϬ΁
Wt΀ϭϭ΁
D
s^^ͺ>s
>
WE΀ϴ΁
WE΀ϵ΁
W΀ϯ΁
W΀ϰ΁
W>΀Ϯ΁
W>΀Ϭ΁
D
WE΀ϭϭ΁
WE΀ϭϬ΁
W΀Ϯ΁
W΀ϭ΁
W>΀ϯ΁
W>΀ϰ΁
E
WE΀ϭϯ΁
WE΀ϭϮ΁
W΀Ϭ΁
W΀Ϭ΁
W>΀ϲ΁
W>΀ϱ΁
sͺ>sͺ
W
WE΀ϭϱ΁
WE΀ϭϰ΁
W΀ϭ΁
W΀Ϯ΁
W΀ϭϮ΁
W>΀ϳ΁
s^^ͺ>s
s^^ͺ>s
Z
E
E
W΀ϭϯ΁
W΀ϰ΁
W΀ϯ΁
W'΀Ϭ΁
dyϯW
s^^ͺ>s
d
W>΀ϴ΁
WY΀ϭ΁
W/΀ϴ΁
W/΀ϵ΁
W<΀Ϭ΁
W<΀ϭ΁
dyϯE
s^^ͺ>s
h
WY΀Ϯ΁
WY΀Ϭ΁
W'΀Ϯ΁
W'΀ϭ΁
W<΀Ϯ΁
W<΀ϯ΁
s^^ͺ>s
s^^ͺ>s
sͺ>s
s
E
E
W'΀ϰ΁
W'΀ϯ΁
W΀ϭϮ΁
W΀ϭϰ΁
t
WZ΀ϭϰ΁
WZ΀ϭϱ΁
W΀ϭϱ΁
W΀ϭϯ΁
W/΀ϭ΁
W<΀ϱ΁
W/΀Ϭ΁
W΀ϱ΁
W<΀ϰ΁
W<΀ϲ΁
W<΀ϳ΁
W<΀ϴ΁
W<΀ϵ΁
E
W'΀ϳ΁
W<΀ϭϭ΁
z
WZ΀ϭϮ΁
WZ΀ϭϯ΁
Wz΀ϯ΁
Wz΀Ϯ΁
WZ΀ϭϭ΁
WZ΀ϭϬ΁
W/΀Ϯ΁
W/΀ϯ΁
Wz΀ϭ΁
Wz΀Ϭ΁
W/΀ϰ΁
W/΀ϱ΁
WZ΀ϴ΁
WZ΀ϵ΁
W'΀ϱ΁
W'΀ϲ΁
W/΀ϲ΁
Wy΀ϭϱ΁
Wy΀ϭϰ΁
E
W΀ϳ΁
W΀ϲ΁
&
WZ΀ϲ΁
WZ΀ϳ΁
'
,
:
sͺ,sͺ s^^ͺ,sͺ
Zͺ
Zͺ
W/΀ϳ΁
W'΀ϴ΁
W'΀ϵ΁
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
sͺ,sͺ
s^^ͺ,s
&>
sͺ,sͺ
s^^ͺ,s
&>
sͺ,sͺ sͺ,sͺ
/Kͺ/
/Kͺ/
sͺ>s
W΀ϵ΁
W΀ϴ΁
d^dDK
W&΀ϭϰ΁
Wt΀ϴ΁
Wt΀ϵ΁
E
s^^ͺ>s
W΀ϲ΁
W/΀ϭϱ΁
W΀ϳ΁
W΀ϭϰ΁
Wt΀ϲ΁
Wt΀ϳ΁
W
s^^ͺ>s
s^^ͺ>s
sͺ,sͺ
/Kͺ
W΀ϳ΁
W/΀ϭϰ΁
W&΀ϭϯ΁
W΀ϲ΁
Wt΀ϰ΁
Wt΀ϱ΁
Z
s^^ͺ>s
s^^ͺ>s
E
W<΀ϭϯ΁
W<΀ϭϮ΁
W΀ϱ΁
s^^ͺ,sͺ
K^
Wt΀Ϯ΁
Wt΀ϯ΁
d
s^^ͺ>s
s^^ͺ>s
W:΀ϭϱ΁
W:΀ϭϰ΁
yd>
yd>
Wt΀Ϭ΁
Wt΀ϭ΁
h
sͺ>s
W:΀ϭϯ΁
W:΀ϭϮ΁
E
sͺ,sͺ
/Kͺ:d'
s^^ͺ,s
sͺ,sͺ
/Kͺ/
s
W:΀ϭϬ΁
W:΀ϭϭ΁
W&΀ϭϬ΁
W&΀ϵ΁
Ws΀ϲ΁
E
t
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
s^^ͺ>s
sͺ>s
s^^ͺ>s
dyϮE
dyϮW
s^^ͺ>s
sͺ>s
W:΀ϴ΁
W:΀ϵ΁
W&΀ϭϮ΁
W&΀ϭϭ΁
Ws΀ϭϰ΁
Ws΀ϭϱ΁
z
W'΀ϭϬ΁
W΀ϰ΁
W΀ϭϭ΁
W΀Ϭ΁
s^dz
W>΀ϭϬ΁
W>΀ϭϮ΁
W>΀ϭϰ΁
W:΀ϲ΁
s^^ͺ,s
W,΀ϲ΁
W:΀ϰ΁
W,΀ϱ΁
Ws΀ϭϮ΁
Ws΀ϭϯ΁
W<΀ϭϬ΁
W΀ϭϰ΁
W΀ϯ΁
W΀ϭ΁
dyϭE
dyϭW
dyϬE
dyϬW
><E
><W
s^^ͺ,s
W'΀ϭϭ΁
s^^ͺ,sͺ sͺ,sͺ sͺ,sͺ s^^ͺ,sͺ
s ^
s ^
Z ^
Z ^
W&΀ϴ΁
W:΀ϯ΁
Ws΀ϭϬ΁
Ws΀ϭϭ΁
sͺ,sͺ/
KͺD/E
W:΀Ϯ΁
Ws΀ϴ΁
Ws΀ϵ΁
W΀ϭϱ΁
W΀Ϯ΁
W/΀ϭϯ΁
W/΀ϭϭ΁
W&΀ϭ΁
W΀ϵ΁
W΀ϭϭ΁
W΀ϵ΁
W΀ϯ΁
W&΀ϳ΁
W΀ϭϱ΁
s^^ͺ,s
sͺ,sͺ
/KͺD/E
Ws΀ϳ΁
Ws΀ϱ΁
W'΀ϭϮ΁
W΀ϭϯ΁
W/΀ϭϮ΁
W/΀ϭϬ΁
W&΀Ϭ΁
W΀ϭϬ΁
W΀ϭϬ΁
W΀ϴ΁
W΀ϴ΁
W&΀ϲ΁
W:΀Ϭ΁
W:΀ϭ΁
s^^ͺ,s
Ws΀ϰ΁
Ws΀ϯ΁
Ws΀Ϯ΁
Ws΀ϭ΁
&
Wz΀ϰ΁
Ws΀Ϭ΁
'
E
NXP Semiconductor s
<
ϭ
E
E
E
WZ΀ϰ΁
WZ΀Ϯ΁
Wy΀ϭϮ΁
WZ΀ϭ΁
E
E
WZ΀ϱ΁
WZ΀ϯ΁
Wy΀ϭϯ΁
WZ΀Ϭ΁
Ϯ
ϯ
ϰ
ϱ
ϲ
ϳ
s^^ͺ,sͺ sͺ,sͺ
sͺ,sͺ
s^^ͺ,s
sͺ^
sͺ^
/Kͺ&>y
s^^ͺ,sͺ sͺ,sͺ
sͺ,sͺ
s^^ͺ,s
sͺ
sͺ
/Kͺ&>y
ϴ
ϵ
ϭϬ
ϭϭ
:
<
s^^ͺ>s
sͺ,sͺ s^^ͺ,sͺ
Z Ϯ Z Ϯ
E
Wt΀ϭϱ΁
W^΀Ϭ΁
W^΀Ϯ΁
W^΀ϰ΁
W^΀ϲ΁
W^΀ϴ΁
W^΀ϭϬ΁
W^΀ϭϮ΁
W^΀ϭϰ΁
E
Wd΀Ϭ΁
Wd΀Ϯ΁
Wd΀ϰ΁
Wd΀ϲ΁
Wd΀ϴ΁
Wd΀ϭϬ΁
Wd΀ϭϮ΁
Wd΀ϭϰ΁
W^΀ϭ΁
W^΀ϯ΁
W^΀ϱ΁
W^΀ϳ΁
W^΀ϵ΁
W^΀ϭϭ΁
W^΀ϭϯ΁
W^΀ϭϱ΁
sͺ,sͺ
/Kͺ&>y
Wd΀ϭ΁
Wd΀ϯ΁
Wd΀ϱ΁
Wd΀ϳ΁
Wd΀ϵ΁
Wd΀ϭϭ΁
Wd΀ϭϯ΁
Wd΀ϭϱ΁
ϭϮ
ϭϯ
ϭϰ
ϭϱ
ϭϲ
ϭϳ
ϭϴ
ϭϵ
ϮϬ
Ϯϭ
ϮϮ
Ϯϯ
Ϯϰ
Ϯϱ
Ϯϲ
Ϯϳ
Ϯϴ
Figure 6. 512-ball BGA emulation device pinout (top view)
sͺ,sͺ sͺ,sͺ
/KͺD/E /Kͺ/
sͺ,sͺ
s^^ͺ,s
/KͺD/E
sͺ,sͺ
/Kͺ&>y
Ϯϵ
ϯϬ
,
:
<
Package pinouts and signal descriptions
ϭ
Package pinouts and signal descriptions
2.2
Pin/ball descriptions
The following sections provide signal descriptions and related information about device functionality and configuration.
2.2.1
Power supply and reference voltage pins/balls
Table 2 contains information on power supply and reference pin functions for the devices.
NOTE
All ground supplies must be tied to ground. They can NOT float.
Table 2. Power supply and reference pins
Supply
Symbol
Type
BGA ball
Description
416PD
416ED
512PD
512ED
VSS_HV
Ground
High voltage ground
A26, B25, C24, D23, B2, B29, B30, F6,
D15, D8, J4, L23, F25, G7, G24, H29,
R23, T4, W23, AC23, H30, J9, J22, K10,
AC19
K21,V29, AA21,
AB22, AD24, AE25,
AJ10, AJ29, AK10
VSS_LV
Ground
Low voltage ground
K10, K11, K12, K13,
K14, K15, K16, K17,
L10, L11, L12, L13,
L14, L15, L16, L17,
M10, M11, M12,
M13, M14, M15,
M16, M17, N10, N11,
N12, N13, N14,
N15,N 16, N17, P11,
P12, P13, P14, P15,
P16, R 11, R12, R13,
R14, R15, R16, T10,
T11, T12, T13, T14,
T15, T16, T17
VDD_LV
Power
Low voltage power supply for
B26, C25, D9, D24,
production device
E23, H4, P23, V23,
(PLL is also powered by this pin.)
AB23, AC20
VDD_LV_BD
Power
Low voltage power supply for
buddy die
VDD_HV_PMC
Power
High voltage power supply for
internal power management unit
VDD_HV_IO_MAIN
Power
High voltage power supply for I/O A25, B24, C23, D22, A2, A29, B3, B28,
K4, AC16, AD16,
F7, F24, G8, G23,
AE16, AF16
AC24, AD25, AH29,
AJ30
VDD_HV_IO_BD
Power
High voltage power supply for
buddy die I/O
VSS_HV_OSC
Ground
Oscillator ground supply
F25
T25
VDD_HV_JTAG
Power
JTAG/Oscillator power supply
E26
V25
—
R1, R4
M14, M15, M16,
M17, N14, N15,
N16, N17, P12, P13,
P15, P16, P18, P19,
R13, R14, R15,
R16, R17, R18,
T13,T14, T15, T16,
T17, T18, U12, U13,
U 15, U16, U18,
U19, V14, V15 V16,
V17, W14, W17
M18, N19, V12,
V19, W13, W18
—
D14
—
M13,
N12
—
P17
—
R19
MPC5777M Microcontroller Data Sheet, Rev. 6
14
NXP Semiconductors
Package pinouts and signal descriptions
Table 2. Power supply and reference pins (continued)
Supply
Symbol
Type
BGA ball
Description
416PD
416ED
512PD
512ED
VDD_HV_IO_FLEX
Power
FlexRay/Ethernet 3.3 V I/O
supply
D7
J10
VDD_HV_IO_FLEXE
Power
FLexRay/Ethernet/EBI I/O
Segment Voltage Supply
AC18, AC22
AJ11, AK11, AK20,
AK29
VDD_HV_IO_EBI
Power
EBI Address/Control I/O Segment
Voltage Supply
M23,T23,Y23
J29, J30, V30, AH30
VDD_HV_FLA
Power
Decoupling supply pin for flash
A18, B18
J21, K20
VSS_HV_ADV_S
Ground
Ground supply for ADC SAR
AF9
AE9, AJ8
VDD_HV_ADV_S
Power
Voltage supply for ADC SAR
AE9
AE10, AJ9
VSS_HV_ADV_D
Ground
Ground supply for ADC SD
AF5
AK8
VDD_HV_ADV_D
Power
Voltage supply for ADC SD
AE5
AK9
VSS_HV_ADR_S
Reference
Ground reference for ADC SAR
AE8
AE12
VDD_HV_ADR_S
Reference
Voltage reference for ADC SAR
AF8
AE11
VSS_HV_ADR_D
Reference
Ground reference for ADC SD
Y4, AC6
AA7
VDD_HV_ADR_D
Reference
Voltage reference for ADC SD
W4, AD6
AA6
VDDSTBY
Power
Standby RAM supply
AD9
AA16
2.2.2
System pins/balls
Table 3 contains information on system pin functions for the devices.
Table 3. System pins
BGA ball
Symbol
Description
Direction
416PD
416ED
512PD
512ED
PORST
Power on reset with Schmitt trigger
characteristics and noise filter. PORST is
active low
Bidirectional
B22
M22
ESR0
External functional reset with Schmitt
trigger characteristics and noise filter.
ESR0 is active low
Bidirectional
A23
L21
TESTMODE
Pin for testing purpose only. TESTMODE
pull-down is implemented to prevent the
device from entering TESTMODE. It is
recommended to connect the
TESTMODE pin to VSS_HV_IO on the
board. The value of the TESTMODE pin
is latched at the negation of reset and has
no affect afterward.
Note: The device will not exit reset with
the TESTMODE pin asserted
during power-up.
Input only
B23
N24
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
15
Package pinouts and signal descriptions
Table 3. System pins (continued)
BGA ball
Symbol
Description
Direction
416PD
2.2.3
416ED
512PD
512ED
XTAL
Analog output of the oscillator amplifier
circuit
needs to be grounded if oscillator is used
in bypass mode.
Output
G25
U24
EXTAL
Analog input of the oscillator amplifier
circuit when oscillator is not in bypass
mode
Analog input for the clock generator when
oscillator is in bypass mode
Input
G26
U25
LVDS pins/balls
The following table contains information on LVDS pin functions for the devices.
Functional block
SIPI / LFAST1
High-Speed
Debug (HSD) /
LFAST1,2
Direction
Table 4. LVDS pin descriptions
BGA ball
(416 PD,
416 ED)
BGA ball
(512 PD,
512 ED)
O
C26
P25
Interprocessor Bus LFAST,
LVDS Transmit Negative
Terminal
O
D26
R25
SIPI_RXP
Interprocessor Bus LFAST,
LVDS Receive Positive
Terminal
I
G23
P24
PF[13]
SIPI_RXN
Interprocessor Bus LFAST,
LVDS Receive Negative
Terminal
I
H23
R24
PA[7]
DEBUG_TXP
Debug LFAST, LVDS
Transmit Positive Terminal
O
F24
R21
PA[8]
DEBUG_TXN
Debug LFAST, LVDS
Transmit Negative Terminal
O
E25
N22
PA[9]
DEBUG_RXP
Debug LFAST, LVDS Receive
Positive Terminal
I
D25
N21
PA[5]
DEBUG_RXN
Debug LFAST, LVDS Receive
Negative Terminal
I
F23
T24
Port pin
Signal
Signal description
PA[14]
SIPI_TXP
Interprocessor Bus LFAST,
LVDS Transmit Positive
Terminal
PD[6]
SIPI_TXN
PD[7]
MPC5777M Microcontroller Data Sheet, Rev. 6
16
NXP Semiconductors
Package pinouts and signal descriptions
Direction
Table 4. LVDS pin descriptions (continued)
BGA ball
(416 PD,
416 ED)
BGA ball
(512 PD,
512 ED)
O
C18
F17
DSPI 4 Microsecond Bus
Serial Clock, LVDS Negative
Terminal
O
C17
G17
SOUT_P
DSPI 4 Microsecond Bus
Serial Data, LVDS Positive
Terminal
O
C16
F16
PD[1]
SOUT_N
DSPI 4 Microsecond Bus
Serial Data, LVDS Negative
Terminal
O
D17
G16
PF[10]
SCK_P
DSPI 5 Microsecond Bus
Serial Clock, LVDS Positive
Terminal
O
J24
W24
PF[9]
SCK_N
DSPI 5 Microsecond Bus
Serial Clock, LVDS Negative
Terminal
O
K23
W25
PF[12]
SOUT_P
DSPI 5 Microsecond Bus
Serial Data, LVDS Positive
Terminal
O
J26
Y24
PF[11]
SOUT_N
DSPI 5 Microsecond Bus
Serial Data, LVDS Negative
Terminal
O
J25
Y25
PQ[9]
SCK_P
DSPI 6Microsecond Bus
Serial Clock, LVDS Positive
Terminal
O
A17
A16
PQ[8]
SCK_N
DSPI 6 Microsecond Bus
Serial Clock, LVDS Negative
Terminal
O
B17
B16
PQ[11]
SOUT_P
DSPI 6 Microsecond Bus
Serial Data, LVDS Positive
Terminal
O
B16
A15
PQ[10]
SOUT_N
DSPI 6 Microsecond Bus
Serial Data, LVDS Negative
Terminal
O
A16
B15
Functional block
Port pin
Signal
DSPI 4
Microsecond Bus
PD[2]
SCK_P
DSPI 4 Microsecond Bus
Serial Clock, LVDS Positive
Terminal
PD[3]
SCK_N
PD[0]
DSPI 5
Microsecond Bus
DSPI 6
Microsecond Bus
Signal description
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
17
Package pinouts and signal descriptions
Functional block
Differential DSPI
2
Differential DSPI
5
Direction
Table 4. LVDS pin descriptions (continued)
BGA ball
(416 PD,
416 ED)
BGA ball
(512 PD,
512 ED)
O
C18
F17
Differential DSPI 2 Clock,
LVDS Negative Terminal
O
C17
G17
SOUT_P
Differential DSPI 2 Serial
Output, LVDS Positive
Terminal
O
C16
F16
PD[1]
SOUT_N
Differential DSPI 2 Serial
Output, LVDS Negative
Terminal
O
D17
G16
PD[7]
SIN_P
Differential DSPI 2 Serial
Input, LVDS Positive Terminal
I
G23
P24
PF[13]
SIN_N
Differential DSPI 2 Serial
Input, LVDS Negative
Terminal
I
H23
R24
PF[10]
SCK_P
Differential DSPI 5 Clock,
LVDS Positive Terminal
O
J24
W24
PF[9]
SCK_N
Differential DSPI 5 Clock,
LVDS Negative Terminal
O
K23
W25
PF[12]
SOUT_P
Differential DSPI 5 Serial
Output, LVDS Positive
Terminal
O
J26
Y24
PF[11]
SOUT_N
Differential DSPI 5 Serial
Output, LVDS Negative
Terminal
O
J25
Y25
PD[7]
SIN_P
Differential DSPI 5 Serial
Input, LVDS Positive Terminal
I
G23
P24
PF[13]
SIN_N
Differential DSPI 5 Serial
Input, LVDS Negative
Terminal
I
H23
R24
PI[15]
SIN_P
Differential DSPI 5 Serial
Input, LVDS Positive Terminal
I
G24
P22
PI[14]
SIN_N
Differential DSPI 5 Serial
Input, LVDS Negative
Terminal
I
J23
R22
Port pin
Signal
Signal description
PD[2]
SCK_P
Differential DSPI 2 Clock,
LVDS Positive Terminal
PD[3]
SCK_N
PD[0]
1
DRCLK and TCK/DRCLK usage for SIPI LFAST and Debug LFAST are described in the MPC5777M
Microcontroller Reference Manual SIPI LFAST and Debug LFAST chapters.
2 Pads use special enable signal form DCI block: DCI driven enable for Debug LFAST pads is transparent to user.
MPC5777M Microcontroller Data Sheet, Rev. 6
18
NXP Semiconductors
Package pinouts and signal descriptions
Functional
Block
Nexus Aurora
High Speed
Trace
PAD
Signal
Signal Description
Direction
Table 5. Aurora pin descriptions
BGA
416PD
416ED
512PD
512ED
—
TX0P
Nexus Aurora High Speed
Trace Lane 0, LVDS Positive
Terminal
O
—
U15
—
AB19
—
TX0N
Nexus Aurora High Speed
Trace Lane 0, LVDS Negative
Terminal
O
—
U14
—
AB18
—
TX1P
Nexus Aurora High Speed
Trace Lane 1, LVDS Positive
Terminal
O
—
U13
—
AB17
—
TX1N
Nexus Aurora High Speed
Trace Lane 1, LVDS Negative
Terminal
O
—
U12
—
AB16
—
TX2P
Nexus Aurora High Speed
Trace Lane 2, LVDS Positive
Terminal
O
—
U11
—
W16
—
TX2N
Nexus Aurora High Speed
Trace Lane 2, LVDS Negative
Terminal
O
—
U10
—
W15
—
TX3P
Nexus Aurora High Speed
Trace Lane 3, LVDS Positive
Terminal
O
—
P10
—
R12
—
TX3N
Nexus Aurora High Speed
Trace Lane 3, LVDS Negative
Terminal
O
—
R10
—
T12
—
CLKP Nexus Aurora High Speed
(BD-AGB Trace Clock, LVDS Positive
TCLKP) Terminal
I
—
U17
—
AB21
—
CLKN Nexus Aurora High Speed
(BD-AGB Trace Clock, LVDS Negative
TCLKN) Terminal
I
—
U16
—
AB20
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
19
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” (Controller
Characteristics) is included in the “Symbol” column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” (System Requirement) is included in the “Symbol” column.
NOTE
Within this document, VDD_HV_IO refers to supply pins VDD_HV_IO_MAIN,
VDD_HV_IO_JTAG, VDD_HV_IO_FLEX, VDD_HV_IO_FLEXE, VDD_HV_IO_EBI, and
VDD_HV_FLA. VDD_HV_ADV refers to ADC supply pins VDD_HV_ADV_S and
VDD_HV_ADV_D. VDD_HV_ADR refers to ADC reference pins VDD_HV_ADR_S and
VDD_HV_ADR_D. VSS_HV_ADV refers to ADC ground pins VSS_HV_ADV_S and
VSS_HV_ADV_D. VSS_HV_ADR refers to ADC reference pins VSS_HV_ADR_S and
VSS_HV_ADR_D.
3.2
Absolute maximum ratings
Table 6 describes the maximum ratings of the device.
Table 6. Absolute maximum ratings1
Value
Symbol
Cycle
Parameter
SR Lifetime power cycles
VDD_LV
VDD_LV_BD
Unit
Min
Max
—
—
1000 k
—
SR 1.2 V core supply
voltage2,3,4
—
–0.3
1.5
V
SR Emulation module
voltage2,3,4
—
–0.3
1.5
V
—
–0.3
6.0
V
SR I/O supply
VDD_HV_IO
Conditions
voltage5,6
VDD_HV_PMC
SR Power Management Controller
supply voltage5
—
–0.3
6.0
V
VDD_HV_FLA
SR Flash core voltage7
—
–0.3
4.5
V
—
–0.3
6.0
V
SR SAR and S/D ADC ground voltage Reference to VSS_HV
–0.3
0.3
V
SR SAR and S/D ADC supply voltage
Reference to corresponding
VSS_HV_ADV
–0.3
6.0
V
VSS_HV_ADR10
SR SAR and S/D ADC low reference
Reference to VSS_HV
–0.3
0.3
V
VDD_HV_ADR11
SR SAR and S/D ADC high reference
Reference to corresponding
VSS_HV_ADR
–0.3
6.0
V
–0.3
6.0
V
SR RAM standby supply
VDDSTBY
VSS_HV_ADV8
VDD_HV_ADV
9
VDD_HV_IO_JTAG
voltage5
SR Crystal oscillator, FEC MDIO/MDC, Reference to VSS_HV
LFAST, JTAG5
MPC5777M Microcontroller Data Sheet, Rev. 6
20
NXP Semiconductors
Electrical characteristics
Table 6. Absolute maximum ratings1 (continued)
Value
Symbol
VDD_HV_IO_EBI
Parameter
Conditions
Max
—
–0.3
6.0
V
—
–0.3
1.5
V
—
–0.3
6.0
V
Relative to VSS_HV_IO13,14
–0.3
—
Relative to VDD_HV_IO13,14
—
0.3
SR External Bus Interface supply
voltage
VDD_LV_BD – VDD_LV SR Emulation module supply
differential to 1.2 V core supply
VIN
SR Maximum DC injection current for
digital pad
Per pin, applies to all digital
pins
–5
5
mA
IINJA
SR Maximum DC injection current for
analog pad
Per pin, applies to all analog
pins
–5
5
mA
IMAXD
SR Maximum output DC current when
driven
Medium
7
8
mA
Strong
–10
10
Very strong
–11
11
SR Maximum current per power
segment15
—
–90
90
mA
SR Storage temperature range and
non-operating times
—
–55
175
°C
SR Maximum storage time, assembled No supply; storage
part programmed in ECU
temperature in range –40 °C
to 60 °C
—
20
years
TSDR
SR Maximum solder temperature16
Pb-free package
—
—
260
°C
MSL
SR Moisture sensitivity level17
—
—
3
—
tXRAY
SR X-ray screen time18
—
3
min
TSTG
STORAGE
2
3
4
5
6
7
8
SR I/O input voltage range12
IINJD
IMAXSEG
1
Unit
Min
At 160 KeV at max 5 mm
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum TJ = 150 °C, remaining time as defined in note 3
and note 4
Allowed 1.38– 1.45 V– for 10 hours cumulative time at maximum TJ = 150 °C, remaining time as defined in note 4
1.32 – 1.38 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.326 V at
maximum TJ = 150 °C.
Allowed 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset,
TJ = 150 °C, remaining time at or below 5.5 V.
VDD_HV_IO applies to VDD_HV_IO_MAIN, VDD_HV_IO_FLEX, VDD_HV_IO_FLEXE, VDD_HV_IO_JTAG, and VDD_HV_IO_EBI I/O
power supplies.
Allowed 3.6–4.5 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset,
TJ = 150 °C, remaining time at or below 3.6 V.
Includes ADC grounds VSS_HV_ADV_S and VSS_HV_ADV_D.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
21
Electrical characteristics
9
Includes ADC supplies VDD_HV_ADV_S and VDD_HV_ADV_D. VDD_HV_ADV_S is also the supply for the device
temperature sensor, RCOSC, and bandgap reference.
10
Includes ADC low references VSS_HV_ADR_S and VSS_HV_ADR_D.
11
Includes ADC high references VDD_HV_ADR_S and VDD_HV_ADR_D.
12
The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
condition on a pin, the voltage equals the supply plus the voltage drop across the internal ESD diode from I/O pin to
supply. The diode voltage varies significantly across process and temperature, but a value of 0.3V can be used for
nominal calculations.
13
VDD_HV_IO/VSS_HV_IO refers to supply pins and corresponding grounds: VDD_HV_IO_MAIN, VDD_HV_IO_FLEX,
VDD_HV_IO_JTAG, VDD_HV_OSC, VDD_HV_FLA.
14 Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameters I
INJD
and IINJA).
15
Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDD_HV_IO power segment
is defined as one or more GPIO pins located between two VDD_HV_IO supply pins.
16
Solder profile per IPC/JEDEC J-STD-020D
17
Moisture sensitivity per JEDEC test method A112
18 Three Screen done, 1 minute each. No change in device parameters during characterization of at least 10 devices at
30 minutes exposure of 150 KeV at maximum 5 mm.
3.3
Electrostatic discharge (ESD)
The following table describes the ESD ratings of the device.
Table 7. ESD ratings1,2
Parameter
Conditions
Value
Unit
ESD for Human Body Model (HBM)3
All pins
2000
V
ESD for field induced Charged Device Model (CDM)4
All pins
500
V
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot
temperature. Maximum DC parametrics variation within 10% of maximum specification”
3 This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing
4 This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level
3.4
Operating conditions
The following table describes the operating conditions for the device for which all specifications in the data sheet are valid,
except where explicitly noted.
The device operating conditions must not be exceeded or the functionality of the device is not guaranteed.
Table 8. Device operating conditions1
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
—
—
300
Frequency
fSYS
SR Device operating
frequency2
TJ  40 °C to 150 °C
MHz
MPC5777M Microcontroller Data Sheet, Rev. 6
22
NXP Semiconductors
Electrical characteristics
Table 8. Device operating conditions1 (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Temperature
TJ
TA (TL to TH)
SR Operating temperature
range - junction
—
–40.0
—
150.0
°C
SR Ambient operating
temperature range
—
–40.0
—
125.0
°C
1.24
—
1.385
V
5
Voltage
VDD_LV
SR External core supply
voltage3,4
LVD/HVD
disabled6,7,8,9
1.19
—
1.38
LVD400/HVD600
enabled18
4.5
—
5.512
LVD400/HVD600
disabled 6,13,14,15,18
4.2
—
5.5
LVD360/HVD600
disabled 6,13,14,16,17,18
3.0
—
5.5
SR JTAG I/O supply
voltage6,19
5 V range
4.5
—
5.5
3.3 V range
3.0
—
3.6
SR FlexRay I/O supply
voltage
5 V range
4.5
—
5.5
3.3 V range
3.0
—
3.6
SR FlexRay/EBI I/O supply 5 V range
voltage
3.3 V range
4.5
—
5.5
3.0
—
3.6
VDD_HV_IO_MAIN10,11 SR I/O supply voltage
VDD_HV_IO_JTAG
VDD_HV_IO_FLEX
VDD_HV_IO_FLEXE
VDD_HV_IO_EBI
VDD_HV_OSC
VDD_HV_PMC21
LVD/HVD enabled
V
V
V
V
SR External Bus Interface
supply voltage
5 V range
4.5
—
5.5
3.3 V range
3.0
—
3.6
SR Oscillator supply
voltage6,20
5 V range
4.5
—
5.5
3.3 V range
3.0
—
3.6
SR Power Management
Controller (PMC)
supply voltage
Full functionality22,23
3.524,25
—
5.5
Reduced internal
regulator output
capability26
3.15
—
3.5
Supply monitoring
activity only (LVD/HVD)
3.0
—
3.15
—
1.1
—
5.5
V
LVD400 enabled
4.5
—
5.5
V
LVD400
disabled30,31,34
4.0
—
5.532
LVD300
disabled6,30,31,33,34
3.7
—
5.532
VDDSTBY
SR RAM standby supply
voltage27,28,29
VDD_HV_ADV
SR SARADC, SDADC,
Temperature Sensor,
and Bandgap
Reference supply
voltage
V
V
V
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
23
Electrical characteristics
Table 8. Device operating conditions1 (continued)
Value
Symbol
VDD_HV_ADR_D
Parameter
SR SD ADC supply
reference voltage
Conditions
Reduced SNR
Full SNR
Unit
Min
Typ
Max
3.0
VDD_HV_ADV_D
4.5
4.5
—
5.5
—
V
32
VDD_HV_ADR_D –
VDD_HV_ADV_D
SR SD ADC reference
differential voltage
—
25
VSS_HV_ADR_D
SR SD ADC ground
reference voltage
—
VSS_HV_ADR_D –
VSS_HV_ADV_D
SR VSS_HV_ADR_D
differential voltage
—
–25
—
25
mV
VDD_HV_ADR_S35
SR SARADC reference
—
2.0
VDD_HV_ADV_S
4.0
V
VSS_HV_ADV_D
4.0
VSS_HV_ADR_S
mV
V
5.5
32
SR SAR ADC ground
reference voltage
—
VDD_HV_ADR_S –
VDD_HV_ADV_S
SR SARADC reference
differential voltage
—
—
—
25
mV
VSS_HV_ADR_S –
VSS_HV_ADV_S
SR VSS_HV_ADR_S
differential voltage
—
–25
—
25
mV
SR VSS_HV_ADV differential
voltage
—
–25
—
25
mV
VRAMP_LV
SR Slew rate on core
power supply pins
—
—
—
100
V/ms
VRAMP_HV
SR Slew rate on HV power
supply pins
—
—
—
100
V/ms
Vpor_rel
CC POR release trip point
-40 °C < Tj < 150 °C
3.10
—
4.26
V
Vpor_hys
CC POR hysteresis
-40 °C < Tj < 150 °C
150
—
300
mV
—
0
—
5.5
V
Digital pins and analog
pins
–3.0
—
3.0
mA
—
–80
—
80
mA
VSS_HV_ADV – VSS
VIN
SR I/O input voltage range
VSS_HV_ADV_S
V
Injection current
IIC
IMAXSEG
SR DC injection current
(per pin)36,37,38
SR Maximum current per
power segment39
1
The ranges in this table are design targets and actual data may vary in the given range.
Maximum operating frequency is applicable to the computational cores and platform for the device. See the Clocking chapter
in the MPC5777M Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks
on the device.
3 Core voltage as measured on device pin to guarantee published silicon performance.
4
During power ramp, voltage measured on silicon might be lower. maximum performance is not guaranteed, but correct
silicon operation is guaranteed. Refer to the Power Management and Reset Generation Module chapters in the MPC5777M
Microcontroller Reference Manual for further information.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
24
NXP Semiconductors
Electrical characteristics
5
Although the maximum VDD_LV operating voltage is 1.38 V, reset is not entered at that voltage. An external voltage monitor
is needed or the HVD140_C can be monitored (via an interrupt or by polling the HVD140_C flag bit). Performance above
1.38 V is not guaranteed, and allowed operation above 1.38 V is defined in Absolute maximum ratings.
6
In the LVD/HVD disabled case, it is necessary for the system to be within a higher voltage range during destructive reset
events.
7
Maximum core voltage is not permitted for entire product life. See Absolute maximum rating.
8
When internal LVD/HVDs are disabled, external monitoring is required to guarantee correct device operation.
9
Vdd_lv should be above 1.24 V during destructive resets or POR events.
10
VDD_HV_IO_MAIN range limited to 4.75–5.25 V when FERS = 1 to enable the fast erase time of the flash memory.
11
During power up operation, the minimum required voltage to come out of reset state is determined by the VPORUP_HV
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the VPORUP_HV monitor is connected
to the VDD_HV_IO_MAIN0 physical I/O segment.
12
When the LVD/HVDs are enabled, the VDD_HV_IO_MAIN must be less than 5.412 V to exit from a destructive reset.
13
Maximum voltage is not permitted for entire product life. See Absolute maximum rating.
14
When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor
externally supply voltage may result in erroneous operation of the device.
15 When these LVD/HVDs are disabled, the V
DD_HV_IO_MAIN supply must be between 3.182 V and 5.412 V.
16 Reduced output capabilities below 4.2 V. See performance derating values in I/O pad electrical characteristics.
17 When the LVD/HVDs are disabled, the VDD_HV_IO_MAIN must be between 3.024 V and 5.412 V.
18 The PMC supply voltage (V
DD_HV_PMC) must be within the correct range (see the VDD_HV_PMC specification).
19 When the LVD/HVDs are disabled, the HV I/O JTAG supply (V
DD_HV_IO_JTAG) must be above 3.024 V.
20 When the LVD/HVDs are disabled, the HV OSC supply (V
DD_HV_OSC) must be above 3.024 V.
21 Flash read operation is supported for a minimum V
DD_HV_PMC value of 3.15 V. Flash read, program, and erase operations
are supported for a minimum VDD_HV_PMC value of 3.5 V.
22 When the LVD/HVDs are disabled, the V
DD_HV_PMC must be below 5.412 V during destructive reset events.
23 A minimum of 4.5 V is required to guarantee correct user logic BIST operation.
24 During power up operation, the minimum required voltage to come out of reset state is determined by the V
PORUP_HV
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the VPORUP_HV monitor is connected
to the VDD_HV_IO_MAIN0 physical I/O segment.
25 Above Ta = 25°C, the minimum V
DD_HV_PMC voltage is 3.6 V.
26 With the reduced internal regulator output capability, erases and writes to the device flash cannot be guaranteed for a single
event and multiple erases and writes may be necessary. User logic BIST is not supported with reduced capability.
27 RAM data retention is guaranteed at a voltage that is always below the maximum brownout flag trip point voltage (see the
DC Electrical Specification table). The minimum VDDSTBY voltage at the pin is larger in order to account for on-chip IR drop
and noise. There is no effect on RAM operation when VDDSTBY is below 1.1 V, and VDD_LV is above the minimum operating
value.
28 Non-regulated supplies can be used on the VDDSTBY pin if the absolute maximum and operating condition voltage limits
are met. There is no static clamp to a supply rail for the VDDSTBY pin, only dynamic protection for ESD events.
29 The VDDSTBY pin should be connected to ground in the application when the standby RAM feature is not used.
30 V
DD_HV_ADV_S is required to be between 4.5 V and 5.5 V to read the internal Temperature Sensor and Bandgap Reference.
31 SAR ADC only. SDADC minimum is 4.5 V.
32 The ADC is functional up to 5.9V with no reliability issues, but performance is not guaranteed.
33
When the LVD/HVDs are disabled, the HV ADC supply (VDD_HV_ADV) must be above 3.182 V.
34 For supply voltages between 3.0 V and 4.0 V there is no guaranteed precision of ADC (accuracy/linearity). ADCs recover to
a fully functional state when the voltage rises above 4.0 V.
35 V
DD_HV_ADR_S must be between 4.5 V and 5.5 V for accurate reading of the device Temperature Sensor.
36 Full device lifetime without performance degradation
37
I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the
Absolute maximum ratings table for maximum input current for reliability requirements.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
25
Electrical characteristics
38
The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is above
the supply rail, current is injected through the clamp diode to the supply rail. For external RC network calculation, assume
typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
39
Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDD_HV_IO power segment is defined
as one or more GPIO pins located between two VDD_HV_IO supply pins.
Table 9. Emulation (buddy) device operating conditions1
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Frequency
—
SR Standard JTAG 1149.1/1149.7 frequency
—
—
—
50
MHz
—
SR High-speed debug frequency
—
—
—
320
MHz
—
SR Data trace frequency
—
—
—
1250
MHz
Temperature
TJ_BD
SR Device junction operating temperature
range
—
–40.0
—
150.0
°C
TA _BD
SR Ambient operating temperature range
—
–40.0
—
125.0
°C
—
1.2
—
1.365
V
VDD_HV_IO_BD SR Buddy I/O supply voltage
—
3.0
—
5.5
V
VRAMP_LV_BD SR Buddy slew rate on core power supply pins
—
—
—
100
V/ms
VRAMP_HV_BD SR Buddy slew rate on HV power supply pins
—
—
—
100
V/ms
Voltage
VDD_LV_BD
1
3.5
SR Buddy core supply voltage
The ranges in this table are design targets and actual data may vary in the given range.
DC electrical specifications
The following table describes the DC electrical specifications.
Table 10. DC electrical specifications1
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
IDD_LV
CC
Maximum operating
current on the VDD_LV
supply2
TJ = 150 oC
VDD_LV = 1.325 V
fMAX
—
—
1140
mA
IDDAPP_LV
CC
Application use case
operating current on the
VDD_LV supply3
TJ = 150 °C
VDD_LV = 1.325 V
fMAX
—
—
950
mA
IDD_LV_PE
CC
Operating current on
the VDD_LV supply for
flash program/erase
TJ = 150 oC
—
—
40
mA
MPC5777M Microcontroller Data Sheet, Rev. 6
26
NXP Semiconductors
Electrical characteristics
Table 10. DC electrical specifications1 (continued)
Value
Symbol
IDD_HV_PMC
Parameter
CC
Operating current on
the VDD_HV_PMC
supply4,5
Conditions
Unit
Min
Typ
Max
Flash read
—
—
10
Flash P/E
—
—
40
PMC only
—
—
256
mA
IDD_MAIN_CORE_AC7
CC
Main Core 0/1 dynamic 300 MHz
operating current
—
—
115
mA
IDD_CHKR_CORE_AC
CC
Checker Core 0
dynamic operating
current
300 MHz
—
—
80
mA
IDD_HSM_AC
CC
HSM platform dynamic 100 MHz
operating current
—
—
20
mA
IDDSTBY_RAM
CC
64 KB RAM Standby
Leakage Current
(RAM not
operational)8,9,10,11
VDDSTBY @1.1 V
to 5.5 V, TJ =
150 °C
—
—
350
µA
VDDSTBY @1.1 V
to 5.5 V, TA =
40 °C
—
—
60
VDDSTBY @1.1 V
to 5.5 V, TA =
85 °C
—
—
100
CC
CC
IDDSTBY_REG
CC
64 KB RAM Standby
Leakage Current12
VDDSTBY @1.3 V
to 5.5 V, TA =
125 °C
—
—
50
µA
IDD_LV_BD
CC
BD Debug/Emulation
low voltage supply
operating current13
TJ = 150 °C
VDD_LV_BD =
1.32 V
—
—
290
mA
IDD_HV_IO_BD
CC
Debug/Emulation high
voltage supply
operating current
(Aurora +
JTAGM/LFAST)
TJ = 150 °C
—
—
130
mA
IDD_BD_STBY
CC
BD Debug/Emulation
low voltage supply
standby current14,15
VDD_LV_BD =
1.32 V,
TJ = 150 °C
—
—
230
mA
VDD_LV_BD =
1.32 V,
TJ = 55 °C
—
—
5
CC
ISPIKE
CC
Maximum short term
current spike16
< 20 µs
observation
window
—
—
90
mA
dI
CC
Current difference ratio 20 µs
to average current
observation
(dI/avg(I))17
window
—
—
20
%
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
27
Electrical characteristics
Table 10. DC electrical specifications1 (continued)
Value
Symbol
1
2
3
4
5
6
7
8
Parameter
Conditions
Unit
Min
Typ
Max
ISR18
CC
Current variation during See footnote19
power up/down
—
—
90
mA
IBG
CC
Bandgap reference
current consumption
—
—
600
µA
IDDOFF
CC
Power-off current on
high voltage supply
rails20
100
—
—
µA
VSTBY_BO
CC
Standby RAM brownout
flag trip point voltage
—
—
—
0.921
V
VDD_LV_STBY_SW
CC
Standby RAM switch
VDD_LV voltage
threshold
—
0.93
—
—
V
VREF_BG_T
CC
Bandgap trimmed
reference voltage
TJ = 40 °C to
150 °C
VDD_HV_ADV =
5 V ± 10%
1.200
—
1.237
V
VREF_BG_TC
CC
Bandgap temperature
coefficient22
TJ = 40 °C to
150 °C
VDD_HV_ADV =
5V
—
—
50
ppm/°
C
VREF_BG_LR
CC
Bandgap line
regulation22
TJ = 40 °C
VDD_HV_ADV =
5 V ± 10%
—
—
8000
ppm/V
TJ = 150 °C
VDD_HV_ADV =
5 V ± 10%
—
—
4000
VDD_HV = 2.5 V
All parameters in this data sheet are valid for operation within an operating range of -40° C  TJ 150 °C except where
otherwise noted
fMAX as specified per IP. Excludes flash P/E and HSM dynamic current. Measured on an application specific pattern.
Calculation of total current for the device, all rails, is done by adding the applicable dynamic currents to the IDD_LV value
for the core supply, and summing the currents based on use case for the 5 V blocks, for which current consumption values
are defined in later sections of the DC electrical specification.
fMAX as specified per IP. Excludes flash P/E and HSM dynamic current. Measured on an application specific pattern.
VDD_HV_PMC only available in the 416 BGA package. PMC supply is shorted to VDD_HV_IO_MAIN in the 512 BGA, with an
external bypass capacitor connected to the VDD_HV_PMC_BYP ball. The flash read and P/E current, and PMC current apply
to VDD_HV_IO_MAIN for the 512 BGA.
The flash read and flash P/E currents are mutually exclusive, and are not cumulative.
This includes PMC consumption, LFAST PLL regulator current, and Nwell bias regulator current. If the VDD_LV auxiliary
regulator is enabled, the PMC supply may see short term (10 µs) spikes of up to 150 mA depending on transient current
conditions from use case of the device. The auxiliary regulator can be disabled at power-up in the user DCF clients in the
flash memory.
There is an additional 25 mA when FERS = 1 to enable the fast erase time of the flash memory.
Data is retained for full TJ range of -40 °C to 150 °C. RAM supply switch to the standby regulator occurs when the VDD_LV
supply falls below 0.95V.
MPC5777M Microcontroller Data Sheet, Rev. 6
28
NXP Semiconductors
Electrical characteristics
9
VDDSTBY may be supplied with a non-regulated power supply, but the absolute maximum voltage on VDDSTBY given in
the absolute maximum ratings table must be observed.
10
Standby current is reduced by a factor of two from TJ=150 °C, for approximately every ~20 °C drop in operating
temperature.
11
The maximum value for IDDSTBY_ON is also valid when switching from the core supply to the standby supply, and when
powering up the device and switching the RAM supply back to VDD_LV.
12
The standby RAM regulator current is present on the VDDSTBY pin whenever a voltage is applied to the pin. This also
applies to normal operation where the RAM is powered by the VDD_LV supply. Connecting the VDDSTBY pin to ground
when not using the standby RAM feature will remove the leakage current on the VDDSTBY pin.
13
If Aurora and JTAGM/LFAST not used, VDD_LV_BD current is reduced by ~20mA.
14
Applies to 2MB calibration RAM in the BD.
15
Buddy device leakage dependency on temperature can be estimated by dividing the 150 °C leakage by two for each
temperature drop of ~20 °C.
16
Current spike may occur during normal operation that are above average current, valid for IDDAPP and its conditions given
in Table 10 (DC electrical specifications). Internal schemes must be used (eg frequency ramping, feature enable) to
ensure that incremental demands are made on the external power supply. An internal fast regulator providing ~40mA peak
current within 1us to filter any core power supply droops is available on the device. Assumption is minimum 13.3 µF (20 µF
typical) capacitance on the core supply.]
17 Moving window, valid for I
DDAPP and its conditions given in Table 10 (DC electrical specifications), with a maximum of
90 mA for the worst case application
18 This specification is the maximum value and is a boundary for the dl specification.
19 Condition1: For power on period from 0 V up to normal operation with reset asserted. Condition 2: From reset asserted
until PLL running free. Condition 3: Increasing PLL from free frequency to full frequency. Condition 4: reverse order for
power down to 0 V.
20 I
DDOFF is the minimum guaranteed consumption of the device during power-up. It can be used to correctly size power-off
ballast in case of current injection during power-off state.Power up/down current transients can be limited by controlling
the clock ramp rates with the Progressive Clock Frequency Switching block on the device.
21 V
STBY_BO is the maximum voltage that sets the standby RAM brown-out flag in the device logic. The minimum voltage for
RAM data retention is guaranteed to always be less than the VSTBY_BO maximum value.
22 The temperature coefficient and line regulation specifications are used to calculate the reference voltage drift at an
operating point within the specified voltage and temperature operating conditions.
3.6
I/O pad specification
The following table describes the different pad type configurations.
Table 11. I/O pad specification descriptions
Pad type
Description
Weak configuration
Provides a good compromise between transition time and low electromagnetic emission.
Pad impedance is centered around 800 
Medium configuration
Provides transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
Pad impedance is centered around 200 
Strong configuration
Provides fast transition speed; used for fast interface.
Pad impedance is centered around 50 
Very strong configuration Provides maximum speed and controlled symmetric behavior for rise and fall transition.
Used for fast interface including Ethernet, FlexRay, and the EBI data bus interfaces
requiring fine control of rising/falling edge jitter.
Pad impedance is centered around 40 
EBI configuration
Provides necessary speed for fast external memory interfaces on the EBI address and
control signals. Drive strength is matched to four selectable loads.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
29
Electrical characteristics
Table 11. I/O pad specification descriptions (continued)
Pad type
Description
Differential configuration
A few pads provide differential capability providing very fast interface together with good
EMC performances.
Input only pads
These low input leakage pads are associated with the ADC channels.
NOTE
Each I/O pin on the device supports specific drive configurations. See the signal description
table in the device reference manual for the available drive configurations for each I/O pin.
The device supports both 3.3 V and 5 V nominal I/O voltages. In order to use 3.3 V on the
VDD_HV_IO_MAIN0 physical I/O segment, the HV supply low voltage monitor (VLVD400)
must be disabled by DCF client. All other physical I/O segments are unaffected by the
LVD400.
3.6.1
I/O input DC characteristics
Table 12 provides input DC electrical characteristics as described in Figure 7.
VIN
VDD
VIH
VHYS
VIL
VINTERNAL
(SIUL register)
Figure 7. I/O input DC electrical characteristics definition
Table 12. I/O input DC electrical characteristics
Symbol
Parameter
Value
Conditions1
Unit
Min
Typ
Max
TTL
VIHTTL
SR Input high level TTL
4.5 V < VDD_HV_IO < 5.5 V6
2
—
VDD_HV_IO
+ 0.3
VILTTL
SR Input low level TTL
4.5 V < VDD_HV_IO < 5.5 V6
–0.3
—
0.8
0.275
—
—
VHYSTTL
— Input hysteresis TTL
6
4.5 V < VDD_HV_IO < 5.5 V
V
MPC5777M Microcontroller Data Sheet, Rev. 6
30
NXP Semiconductors
Electrical characteristics
Table 12. I/O input DC electrical characteristics (continued)
Symbol
VDRFTTTL
Parameter
— Input VIL/VIH temperature
drift TTL
Value
Conditions1
Unit
Min
Typ
Max
—
—
—
100
mV
AUTOMOTIVE
VIHAUT2
SR Input high level
AUTOMOTIVE
4.5 V < VDD_HV_IO < 5.5 V
3.8
—
VDD_HV_IO
+ 0.3
V
VILAUT3
SR Input low level
AUTOMOTIVE
4.5 V < VDD_HV_IO < 5.5 V
–0.3
—
2.2
V
VHYSAUT4
— Input hysteresis
AUTOMOTIVE
4.5 V < VDD_HV_IO < 5.5 V
0.4
—
—
V
VDRFTAUT
— Input VIL/VIH temperature
drift
4.5 V < VDD_HV_IO < 5.5 V
—
—
1005
mV
3.0 V < VDD_HV_IO < 3.6 V
0.70 *
VDD_HV_IO
—
VDD_HV_IO
+ 0.3
V
0.6 *
VDD_HV_IO
—
VDD_HV_IO
+ 0.3
V
–0.3
—
0.35 *
VDD_HV_IO
V
–0.3
—
0.4 *
VDD_HV_IO
V
0.1 *
VDD_HV_IO
—
—
V
—
—
1005
mV
CMOS/EBI
VIHCMOS_H SR Input high level CMOS
6
(with hysteresis)
VIHCMOS6
SR Input high level CMOS
(without hysteresis)
VILCMOS_H6 SR Input low level CMOS
(with hysteresis)
VILCMOS
6
SR Input low level CMOS
(without hysteresis)
VHYSCMOS — Input hysteresis CMOS
4.5 V < VDD_HV_IO < 5.5 V
3.0 V < VDD_HV_IO < 3.6 V
4.5 V < VDD_HV_IO < 5.5 V
3.0 V < VDD_HV_IO < 3.6 V
4.5 V < VDD_HV_IO < 5.5 V
3.0 V < VDD_HV_IO < 3.6 V
4.5 V < VDD_HV_IO < 5.5 V
3.0 V < VDD_HV_IO < 3.6 V
4.5 V < VDD_HV_IO < 5.5
VDRFTCMOS — Input VIL/VIH temperature
drift CMOS
V7
3.0 V < VDD_HV_IO < 3.6 V
4.5 V < VDD_HV_IO < 5.5 V
INPUT CHARACTERISTICS8
ILKG
1
CC Digital input leakage
4.5 V < VDD_HV < 5.5 V
VSS_HV < VIN < VDD_HV
TJ = 150 °C
—
—
750
nA
ILKG_EBI
CC Digital input leakage for
EBI pad
4.5 V < VDD_HV < 5.5 V
VSS_HV < VIN < VDD_HV
TJ = 150 °
—
—
750
nA
CIN
CC Digital input capacitance
GPIO input pins
—
—
7
pF
EBI input pins
—
—
7
During power up operation, the minimum required voltage to come out of reset state is determined by the VPORUP_HV
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the VPORUP_HV monitor is
connected to the VDD_HV_IO_MAIN0 physical I/O segment.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
31
Electrical characteristics
2
3
4
5
6
7
8
A good approximation for the variation of the minimum value with supply is given by formula
VIHAUT = 0.69 × VDD_HV_IO.
A good approximation for the variation of the maximum value with supply is given by formula
VILAUT = 0.49 × VDD_HV_IO.
A good approximation of the variation of the minimum value with supply is given by formula
VHYSAUT = 0.11 × VDD_HV_IO.
In a 1 ms period, assuming stable voltage and a temperature variation of ±30 °C, VIL/VIH shift is within ±50 mV. For
SENT requirement refer to NOTE on page 41.
Only for VDD_HV_IO_JTAG and VDD_HV_IO_FLEX power segment. The TTL threshold are controlled by the VSIO bit.
VSIO[VSIO_xx] = 0 in the range 3.0 V < VDD_HV_IO < 4.0 V, VSIO[VSIO_xx] = 1 in the range
4.5 V < VDD_HV_IO < 5.5 V.
Only for VDD_HV_IO_JTAG and VDD_HV_IO_FLEX power segment.
For LFAST, microsecond bus and LVDS input characteristics, refer to dedicated communication module chapters.
Table 13 provides weak pull figures. Both pull-up and pull-down current specifications are provided.
Table 13. I/O pull-up/pull-down DC electrical characteristics
Symbol
Parameter
Value
Conditions1
Unit
Min
IWPU
RWPU
CC Weak pull-up current VIN = 0 V
10.6 * VDD_HV – 10.6
absolute value2
VDD_POR3 < VDD_HV_IO < 3.0 V4,5
CC Weak pull-up
resistance
Typ
Max
—
—
VIN > VIL = 1.1 V (TTL)
4.5 V < VDD< 5.5 V
—
—
130
VIN = 0.75*VDD_HV_IO (AUTO)
3.0 V < VDD_HV_IO < 3.6 V
10
—
—
VIN = 0.35* VDD_HV_IO (AUTO)
3.0 V < VDD_HV_IO < 3.6 V
—
—
70
VIN = 0.35* VDD_HV_IO (CMOS)
3.0 V < VDD_HV_IO < 3.6 V
25
—
80
VIN = 0.69* VDD_HV_IO (AUTO)
4.5 V < VDD_HV_IO < 5.5 V
23
—
—
VIN = 0.49* VDD_HV_IO (AUTO)
4.5 V < VDD_HV_IO < 5.5 V
—
—
82
VIN = 0.35* VDD_HV_IO (CMOS)
4.5 V < VDD_HV_IO < 5.5 V
40
—
120
34
—
62
—
µA
k
MPC5777M Microcontroller Data Sheet, Rev. 6
32
NXP Semiconductors
Electrical characteristics
Table 13. I/O pull-up/pull-down DC electrical characteristics (continued)
Symbol
IWPD
RWPD
1
2
3
4
5
Parameter
Unit
Min
Typ
Max
16
—
—
VIN = 0.75* VDD_HV_IO (AUTO)
3.0 V < VDD_HV_IO < 3.6 V
—
—
92
VIN = 0.35* VDD_HV_IO (AUTO)
3.0 V < VDD_HV_IO < 3.6 V
19
—
—
VIN = 0.65* VDD_HV_IO (CMOS)
3.0 V < VDD_HV_IO < 3.6 V
25
—
80
VIN = 0.69* VDD_HV_IO (AUTO)
4.5 V < VDD_HV_IO < 5.5 V
—
—
130
VIN = 0.49* VDD_HV_IO (AUTO)
4.5 V < VDD_HV_IO < 5.5 V
40
—
—
VIN = 0.65* VDD_HV_IO (CMOS)
4.5 V < VDD_HV_IO < 5.5 V
40
—
120
30
—
55
CC Weak pull-down
VIN < VIL = 0.9 V (TTL)
current absolute value 4.5 V < VDD < 5.5 V
CC Weak pull-down
resistance
Value
Conditions1
—
µA
k
During power up operation, the minimum required voltage to come out of reset state is determined by the
VPORUP_HV monitor, which is defined in the voltage monitor electrical characteristics table. Note that the VPORUP_HV
monitor is connected to the VDD_HV_IO_MAIN0 physical I/O segment.
Weak pull-up/down is enabled within tWK_PU = 1 µs after internal/external reset has been asserted. Output voltage
will depend on the amount of capacitance connected to the pin.
VDD_POR is the minimum VDD_HV_IO supply voltage for the activation of the device pull-up/down, and is given in the
Reset electrical characteristics table of Section Reset pad (PORST, ESR0) electrical characteristics in this Data
Sheet.
VDD_POR is defined in the Reset electrical characteristics table of Section Reset pad (PORST, ESR0) electrical
characteristics in this Data Sheet.
Weak pull-up behavior during power-up. Operational with VDD_HV_IO > VDD_POR.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
33
Electrical characteristics
tWK_PU
tWK_PU
VDD_HV_IO
VDD_POR
RESET(INTERNAL)
pull-up
enabled
YES
NO
(1)
PAD
(1)
(1)
POWER-UP
Application defined
RESET
Application defined
POWER-DOWN
1. Actual PAD slopes will depend on external capacitances and VDD_HV_IO supply.
Figure 8. Weak pull-up electrical characteristics definition
3.6.2
I/O output DC characteristics
The figure below provides description of output DC electrical characteristics.
MPC5777M Microcontroller Data Sheet, Rev. 6
34
NXP Semiconductors
Electrical characteristics
VINTERNAL
(SIUL register)
VHYS
tPD50-50
tPD50-50
tSKEW20-80
Vout
90%
80%
50%
20%
10%
tR20-80
tF20-80
tR10-90
tF10-90
tTR(max) = MAX(tR10-90;tF10-90)
tTR20-80(max) = MAX(tR20-80;tF20-80)
tTR(min) = MIN(tR10-90;tF10-90)
tTR20-80(min) = MIN(tR20-80;tF20-80)
tSKEW20-80
= tR20-80-tF20-80
Figure 9. I/O output DC electrical characteristics definition
The following tables provide DC characteristics for bidirectional pads:
•
•
•
•
•
Table 14 provides output driver characteristics for I/O pads when in WEAK configuration.
Table 15 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 16 provides output driver characteristics for I/O pads when in STRONG configuration.
Table 17 provides output driver characteristics for I/O pads when in VERY STRONG configuration.
Table 18 provides output driver characteristics for the EBI pads.
NOTE
Driver configuration is controlled by SIUL2_MSCRn registers. It is available within two
PBRIDGEA_CLK clock cycles after the associated SIUL2_MSCRn bits have been written.
Table 14 shows the WEAK configuration output buffer electrical characteristics.
Table 14. WEAK configuration output buffer electrical characteristics
Symbol
Parameter
Value
Conditions1,2
Unit
Min
Typ
Max
ROH_W
CC PMOS output impedance
weak configuration
4.5 V < VDD_HV_IO < 5.5 V
Push pull, IOH < 0.5 mA
520
800
1052

ROL_W
CC NMOS output impedance
weak configuration
4.5 V < VDD_HV_IO < 5.5 V
Push pull, IOL < 0.5 mA
520
800
1052

MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
35
Electrical characteristics
Table 14. WEAK configuration output buffer electrical characteristics (continued)
Symbol
fMAX_W
tTR_W
Parameter
CC Output frequency
weak configuration
CC Transition time output pin
weak configuration4
Value
Conditions1,2
Unit
Min
Typ
Max
CL = 25 pF3
—
—
2
3
—
—
1
CL = 200 pF3
—
—
0.25
CL = 25 pF,
4.5 V < VDD_HV_IO < 5.5 V
40
—
120
CL = 50 pF,
4.5 V < VDD_HV_IO < 5.5 V
80
—
240
CL = 200 pF,
4.5 V < VDD_HV_IO < 5.5 V
320
—
820
CL = 25 pF,
3.0 V < VDD_HV_IO < 3.6 V5
50
—
150
CL = 50 pF,
3.0 V < VDD_HV_IO < 3.6 V5
100
—
300
CL = 200 pF,
3.0 V < VDD_HV_IO < 3.6 V5
350
—
1050
CL = 50 pF
MHz
ns
tSKEW_W CC Difference between rise and
fall time
—
—
—
25
%
IDCMAX_W CC Maximum DC current
—
—
—
4
mA
1
2
3
4
5
All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V
are valid for VSIO[VSIO_xx] = 0
During power up operation, the minimum required voltage to come out of reset state is determined by the
VPORUP_HV monitor, which is defined in the voltage monitor electrical characteristics table. Note that the
VPORUP_HV monitor is connected to the VDD_HV_IO_MAIN0 physical I/O segment.
CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be added
to calculate total signal capacitance (CTOT = CL + CIN).
Transition time maximum value is approximated by the following formula:
tTR_W(ns) = 22 ns + CL(pF)  4.4 ns/pF
0 pF < CL < 50 pF
50 pF < CL < 200 pF tTR_W(ns) = 50 ns + CL(pF)  3.85 ns/pF
Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_FLEX segment when VSIO[VSIO_IF] = 0.
Table 15 shows the MEDIUM configuration output buffer electrical characteristics.
Table 15. MEDIUM configuration output buffer electrical characteristics
Symbol
Parameter
Value
Conditions1,2
Unit
Min
Typ
Max
ROH_M
CC PMOS output impedance
MEDIUM configuration
4.5 V < VDD_HV_IO < 5.5 V
Push pull, IOH < 2 mA
135
200
260

ROL_M
CC NMOS output impedance
MEDIUM configuration
4.5 V < VDD_HV_IO < 5.5 V
Push pull, IOL < 2 mA
135
200
260

MPC5777M Microcontroller Data Sheet, Rev. 6
36
NXP Semiconductors
Electrical characteristics
Table 15. MEDIUM configuration output buffer electrical characteristics (continued)
Symbol
fMAX_M
tTPD50-50
tTR_M
1
2
3
4
5
6
Parameter
CC Output frequency
MEDIUM configuration
4
CC 50-50 % Output pad
propagation delay time
CC Transition time output pin
MEDIUM configuration5
Value
Conditions1,2
Unit
Min
Typ
Max
CL = 25 pF3
—
—
12
3
—
—
6
CL = 200 pF3
—
—
1.5
VDD_HV_IO = 5 V +/- 10 %, CL
= 25 pF
—
—
21/17
ns
VDD_HV_IO = 5.0 V +/- 10 %,
CL = 50 pF
—
—
35/27
ns
CL = 25 pF
4.5 V < VDD_HV_IO < 5.5 V
10
—
30
ns
CL = 50 pF
4.5 V < VDD_HV_IO < 5.5 V
20
—
60
CL = 200 pF
4.5 V < VDD_HV_IO < 5.5 V
60
—
200
CL = 25 pF,
3.0 V < VDD_HV_IO < 3.6 V6
12
—
42
CL = 50 pF,
3.0 V < VDD_HV_IO < 3.6 V6
24
—
86
CL = 200 pF,
3.0 V < VDD_HV_IO < 3.6 V6
70
—
300
CL = 50 pF
MHz
tSKEW_M CC Difference between rise and fall
time
—
—
—
25
%
IDCMAX_M CC Maximum DC current
—
—
—
4
mA
All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V
are valid for VSIO[VSIO_xx] = 0
During power up operation, the minimum required voltage to come out of reset state is determined by the
VPORUP_HV monitor, which is defined in the voltage monitor electrical characteristics table. Note that the
VPORUP_HV monitor is connected to the VDD_HV_IO_MAIN0 physical I/O segment.
CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be added
to calculate total signal capacitance (CTOT = CL + CIN).
If two values are given for propagation delay, the first value is for rising edge signals and the second for falling
edge signals.
Transition time maximum value is approximated by the following formula:
tTR_M(ns) = 5.6 ns + CL(pF)  1.11 ns/pF
0 pF < CL < 50 pF
50 pF < CL < 200 pF tTR_M(ns) = 13 ns + CL(pF)  0.96 ns/pF
Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_FLEX segment when VSIO[VSIO_IF] = 0
Table 16 shows the STRONG configuration output buffer electrical characteristics.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
37
Electrical characteristics
Table 16. STRONG configuration output buffer electrical characteristics
Symbol
Parameter
Value
Conditions1,2
Unit
Min
Typ
Max
ROH_S
CC PMOS output impedance
STRONG configuration
4.5 V < VDD_HV_IO < 5.5 V
Push pull, IOH < 8 mA
30
50
77

ROL_S
CC NMOS output impedance
STRONG configuration
4.5 V < VDD_HV_IO < 5.5 V
Push pull, IOL < 8 mA
30
50
77

fMAX_S
CC Output frequency
STRONG configuration
CL = 25 pF3
—
—
40
MHz
—
—
20
—
—
5
VDD_HV_IO = 5 V +/- 10 %, CL
= 25 pF
—
—
8/7
ns
VDD_HV_IO = 5.0 V +/- 10 %,
CL = 50 pF
—
—
11/9
ns
CL = 25 pF
4.5 V < VDD_HV_IO < 5.5 V
3
—
10
ns
CL = 50 pF
4.5 V < VDD_HV_IO < 5.5 V
5
—
16
CL = 200 pF
4.5 V < VDD_HV_IO < 5.5 V
17
—
50
CL = 25 pF,
3.0 V < VDD_HV_IO < 3.6 V6
4
—
15
CL = 50 pF,
3.0 V < VDD_HV_IO < 3.6 V6
6
—
27
CL = 200 pF,
3.0 V < VDD_HV_IO < 3.6 V6
20
—
83
3
CL = 50 pF
CL = 200 pF
tTPD50-504 CC 50-50 % Output pad
propagation delay time
tTR_S
CC Transition time output pin
STRONG configuration5
3
tSKEW_S CC Difference between rise and fall
time
—
—
—
25
%
IDCMAX_S CC Maximum DC current
—
—
—
10
mA
1
2
3
4
5
6
All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V
are valid for VSIO[VSIO_xx] = 0
During power up operation, the minimum required voltage to come out of reset state is determined by the
VPORUP_HV monitor, which is defined in the voltage monitor electrical characteristics table. Note that the
VPORUP_HV monitor is connected to the VDD_HV_IO_MAIN0 physical I/O segment.
CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be
added to calculate total signal capacitance (CTOT = CL + CIN).
If two values are given for propagation delay, the first value is for rising edge signals and the second for falling
edge signals.
Transition time maximum value is approximated by the following formula: tTR_S(ns) = 4.5 ns + CL(pF) x 0.23 ns/pF.
Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_FLEX segment when VSIO[VSIO_IF] = 0
Table 17 shows the VERY STRONG configuration output buffer electrical characteristics.
MPC5777M Microcontroller Data Sheet, Rev. 6
38
NXP Semiconductors
Electrical characteristics
Table 17. VERY STRONG configuration output buffer electrical characteristics1
Symbol
ROH_V
ROL_V
fMAX_V
Parameter
tTR20-80
tTRTTL
tTR20-80
tSKEW_V
Unit
Min
Typ
Max
CC PMOS output impedance
VDD_HV_IO = 5.0 V ± 10%,
VERY STRONG configuration VSIO[VSIO_xx] = 1
IOH = 8 mA
20
40
72
VDD_HV_IO = 3.3 V ± 10%,
VSIO[VSIO_xx] = 0,
IOH = 7 mA4
30
50
90
CC NMOS output impedance
VDD_HV_IO = 5.0 V ± 10%,
VERY STRONG configuration VSIO[VSIO_xx] = 1
IOL = 8 mA
20
40
72
VDD_HV_IO = 3.3 V ± 10%,
VSIO[VSIO_xx] = 0,
IOL = 7 mA4
30
50
90
CC Output frequency
VDD_HV_IO = 5.0 V ± 10%,
VERY STRONG configuration CL = 25 pF5
—
—
50
VSIO[VSIO_xx] = 1,
CL = 15 pF4,5
—
—
50
VDD_HV_IO = 5 V +/- 10 %, CL =
25 pF
—
—
5.5
ns
VDD_HV_IO = 5.0 V +/- 10 %, CL
= 50 pF
—
—
6.5
ns
VDD_HV_IO = 3.3 V +/- 10 %, CL
= 15 pF
—
—
7.3/7.6
ns
VDD_HV_IO = 5.0 V ± 10%,
CL = 25 pF5
1
—
5.3
ns
VDD_HV_IO = 5.0 V ± 10%,
CL = 50 pF5
3
—
12
VDD_HV_IO = 5.0 V ± 10%,
CL = 200 pF5
14
—
45
VDD_HV_IO = 5.0 V ± 10%,
CL = 25 pF5
0.8
—
4
VDD_HV_IO = 3.3 V ± 10%,
CL = 15 pF5
1
—
5
CC TTL threshold transition time8 VDD_HV_IO = 3.3 V ± 10%,
for output pin in VERY
CL = 25 pF5
STRONG configuration
1
—
5
ns
CC Sum of transition time
20–80% output pin VERY
STRONG configuration9
VDD_HV_IO = 5.0 V ± 10%,
CL = 25 pF
—
—
9
ns
VDD_HV_IO = 3.3 V ± 10%,
CL = 15 pF5
—
—
9
VDD_HV_IO = 5.0 V ± 10%,
CL = 25 pF5
0
—
1
tTPD50-506 CC 50-50 % Output pad
propagation delay time
tTR_V
Value
Conditions2,3
CC 10–90% threshold transition
time output pin VERY
STRONG configuration
CC 20–80% threshold transition
time7 output pin VERY
STRONG configuration
CC Difference between rise and
fall time at 20–80%


MHz
ns
ns
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
39
Electrical characteristics
Table 17. VERY STRONG configuration output buffer electrical characteristics1 (continued)
Symbol
Parameter
IDCMAX_VS CC Maximum DC current
1
2
3
4
5
6
7
8
9
Value
Conditions2,3
—
Unit
Min
Typ
Max
—
—
10
mA
Refer to FlexRay section for parameter dedicated to this interface.
All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V
are valid for VSIO[VSIO_xx] = 0.
During power up operation, the minimum required voltage to come out of reset state is determined by the
VPORUP_HV monitor, which is defined in the voltage monitor electrical characteristics table. Note that the
VPORUP_HV monitor is connected to the VDD_HV_IO_MAIN0 physical I/O segment.
Only available on the VDD_HV_IO_JTAG, VDD_HV_IO_FLEXE, and VDD_HV_IO_FLEX segments.
CL is the sum of external capacitance. Add device and package capacitances (CIN, defined in the I/O input DC
electrical characteristics table in this Data Sheet) to calculate total signal capacitance (CTOT = CL + CIN).
If two values are given for propagation delay, the first value is for rising edge signals and the second for falling
edge signals.
20–80% transition time as per FlexRay standard.
TTL transition time as for Ethernet standard.
For specification per Electrical Physical Layer Specification 3.0.1, see the dCCTxDRISE25+dCCTxDFALL25 (Sum of
Rise and Fall time of TxD signal at the output pin) specification in TxD output characteristics table in Section TxD
of this Data Sheet.
Table 18 shows the EBI pad electrical specification.
Table 18. EBI pad output electrical specification
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
CC External Bus Load Capacitance MSCR[OERC] = b101
—
—
10
MSCR[OERC] = b110
—
—
20
MSCR[OERC] = b111
—
—
30
—
—
66.7
MHz
EBI Mode Output Specifications1
CDRV
fMAX_EBI CC External Bus Maximum Operat- CDRV = 10/20/30 pF
ing Frequency
pF
tTR_EBI
CC 10%–90% threshold transition
time External Bus output pins
CDRV= 10/20/30 pF
0.9
—
3.0
ns
tPD_EBI
CC 50%–50% threshold propagation delay time External Bus
output pins
CDRV = 10/20/30 pF
1.9
—
4.0
ns
tSKEW_EB CC Difference between rise and fall
time
I
—
—
—
25
%
IDCMAX_E CC Maximum DC current
—
—
—
12
mA
BI
GPIO Mode Output Specifications - MSCR[OERC] = b100
MPC5777M Microcontroller Data Sheet, Rev. 6
40
NXP Semiconductors
Electrical characteristics
Table 18. EBI pad output electrical specification (continued)
Value
Symbol
Parameter
ROH_EBI_ CC PMOS output impedance
GPIO
ROL_EBI_ CC NMOS output impedance
GPIO
fMAX_EBI_ CC Output frequency
GPIO
Conditions
Unit
Min
Typ
Max
4.5 V < VDD_HV_IO_EBI < 5.5 V
Push pull, IOH < 2 mA
100
225
400

4.5 V < VDD_HV_IO_EBI < 5.5 V
Push pull, IOH < 2 mA
100
200
400

CL = 25 pF2
—
—
12
MHz
CL = 50 pF
—
—
6
CL = 200 pF
—
—
1.5
—
—
4
IDCMAX_E CC Maximum DC current
—
mA
BI_GPIO
1
2
3.7
All EBI mode specifications are valid for VDD_HV_IO_EBI = 3.3V +/- 10%.
CL is the sum of the capacitance loading external to the device.
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair.
Table 19 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment remain below the IMAXSEG value given
in the Table 6 (Absolute maximum ratings). Use the RMS current consumption values to calculate total segment current.
In order to ensure device functionality, the sum of the dynamic and static currents of the I/O on a single segment should remain
below the IMAXSEG value given in the Table 8 (Device operating conditions). Use the dynamic current consumption values to
calculate total segment current.
Pad mapping on each segment can be optimized using the pad usage information provided in the I/O Signal Description table.
The sum of all pad usage ratios within a segment should remain below 100%.
NOTE
In order to maintain the required input thresholds for the SENT interface, the sum of all I/O
pad output percent IR drop as defined in the I/O Signal Description table, must be below
50 %. See the I/O Signal Description attachment.
NOTE
The MPC5777M I/O Signal Description and Input Multiplexing Tables are contained in a
Microsoft Excel workbook file attached to this document. Locate the paperclip symbol on
the left side of the PDF window, and click it. Double-click on the Excel file to open it and
select the I/O Signal Description Table tab.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
41
Electrical characteristics
Table 19. I/O consumption1
Symbol
IRMS_W
IRMS_M
IRMS_S
IRMS_V
IRMS_EBI
Parameter
Value
Conditions2
Unit
Min
Typ
Max
CL = 25 pF, 2 MHz
VDD = 5.0 V ± 10%
—
—
1.1
CL = 50 pF, 1 MHz
VDD = 5.0 V ± 10%
—
—
1.1
CL = 25 pF, 2 MHz
VDD = 3.3 V ± 10%
—
—
0.6
CL = 50 pF, 1 MHz
VDD = 3.3 V ± 10%
—
—
0.6
CL = 25 pF, 12 MHz
VDD = 5.0 V ± 10%
—
—
4.7
CL = 50 pF, 6 MHz
VDD = 5.0 V ± 10%
—
—
4.8
CL = 25 pF, 12 MHz
VDD = 3.3 V ± 10%
—
—
2.6
CL = 50 pF, 6 MHz
VDD = 3.3 V ± 10%
—
—
2.7
CL = 25 pF, 50 MHz
VDD = 5.0 V ± 10%
—
—
19
CL = 50 pF, 25 MHz
VDD = 5.0 V ± 10%
—
—
19
CL = 25 pF, 50 MHz
VDD = 3.3 V ± 10%
—
—
10
CL = 50 pF, 25 MHz
VDD = 3.3 V ± 10%
—
—
10
CC RMS I/O current for VERY STRONG CL = 25 pF, 50 MHz,
configuration
VDD = 5.0V +/- 10%
—
—
22
CL = 50 pF, 25 MHz,
VDD = 5.0V ± 10%
—
—
22
CL = 25 pF, 50 MHz,
VDD = 3.3V ± 10%
—
—
11
CL = 25 pF, 25 MHz,
VDD = 3.3V ± 10%
—
—
11
CDRV = 6 pF, fEBI = 66.7 MHz,
VDD_HV_IO_EBI = 3.3 V ± 10%
—
—
9
CDRV = 12 pF, fEBI = 66.7 MHz,
VDD_HV_IO_EBI = 3.3 V ± 10%
—
—
15
CDRV = 18 pF, fEBI = 66.7 MHz,
VDD_HV_IO_EBI = 3.3 V ± 10%
—
—
27
CDRV = 30 pF, fEBI = 66.7 MHz,
VDD_HV_IO_EBI = 3.3 V ± 10%
—
—
42
CC RMS I/O current for WEAK
configuration
CC RMS I/O current for MEDIUM
configuration
CC RMS I/O current for STRONG
configuration
CC RMS I/O current for External Bus
output pins
mA
mA
mA
mA
mA
MPC5777M Microcontroller Data Sheet, Rev. 6
42
NXP Semiconductors
Electrical characteristics
Table 19. I/O consumption1
Symbol
IDYN_W3
IDYN_M
IDYN_S
IDYN_V
IDYN_EBI4
1
Parameter
Value
Conditions2
Unit
Min
Typ
Max
CL = 25 pF,
VDD = 5.0 V ± 10%
—
—
5.0
CL = 50 pF,
VDD = 5.0 V ± 10%
—
—
5.1
CL = 25 pF,
VDD = 3.3 V ± 10%
—
—
2.2
CL = 50 pF,
VDD = 3.3 V ± 10%
—
—
2.3
CL = 25 pF,
VDD = 5.0 V ± 10%
—
—
15
CL = 50 pF,
VDD = 5.0 V ± 10%
—
—
15.5
CL = 25 pF,
VDD = 3.3 V ± 10%
—
—
7.0
CL = 50 pF,
VDD = 3.3 V ± 10%
—
—
7.1
CL = 25 pF,
VDD = 5.0 V ± 10%
—
—
50
CL = 50 pF,
VDD = 5.0 V ± 10%
—
—
55
CL = 25 pF,
VDD = 3.3 V ± 10%
—
—
22
CL = 50 pF,
VDD = 3.3 V ± 10%
—
—
25
CL = 25 pF,
VDD = 5.0 V ± 10%
—
—
60
CL = 50 pF,
VDD = 5.0 V ± 10%
—
—
64
CL = 25 pF,
VDD = 3.3 V ± 10%
—
—
26
CL = 50 pF,
VDD = 3.3 V ± 10%
—
—
29
CC Dynamic I/O current for External Bus CDRV = 10 pF, fEBI = 66.7 MHz,
output pins
VDD_HV_IO_EBI = 3.3 V ± 10%
—
—
30
CDRV = 20 pF, fEBI = 66.7 MHz,
VDD_HV_IO_EBI = 3.3 V ± 10%
—
—
50
CDRV = 30 pF, fEBI = 66.7 MHz,
VDD_HV_IO_EBI = 3.3 V ± 10%
—
—
80
CC Dynamic I/O current for WEAK
configuration
CC Dynamic I/O current for MEDIUM
configuration
CC Dynamic I/O current for STRONG
configuration
CC Dynamic I/O current for VERY
STRONG configuration
mA
mA
mA
mA
mA
I/O current consumption specifications for the 4.5 V <= VDD_HV_IO <= 5.5 V range are valid for VSIO_[VSIO_xx] = 1,
and VSIO[VSIO_xx] = 0 for 3.0 V <= VDD_HV_IO <= 3.6 V.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
43
Electrical characteristics
2
During power up operation, the minimum required voltage to come out of reset state is determined by the VPORUP_HV
monitor, which is defined in the voltage monitor electrical characterstics table. Note that the VPORUP_HV monitor is
connected to the VDD_HV_IO_MAIN0 physical I/O segment.
3
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible
(timed output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.
4
For IDYN_EBI_GPIO dynamic current for EBI GPIO mode use the IDYN_M values.
3.8
Reset pad (PORST, ESR0) electrical characteristics
The device implements a dedicated bidirectional reset pin (PORST).
NOTE
PORST pin does not require active control. It is possible to implement an external pull-up
to ensure correct reset exit sequence. Recommended value is 4.7 k.
VDD
VDDMIN
VDD_POR
PORST
VIH
VIL
PORST undriven.
Device reset by
internal power-on
reset.
device start-up phase
PORST driven low by
internal power-on reset.
Device reset forced by
external circuitry.
Figure 10. Start-up reset requirements
Figure 11 describes device behavior depending on supply signal on PORST:
1.
2.
3.
PORST low pulse amplitude is too low—it is filtered by input buffer hysteresis. Device remains in current state.
PORST low pulse duration is too short—it is filtered by a low pass filter. Device remains in current state.
PORST low pulse generates a reset:
a) PORST low but initially filtered during at least WFRST. Device remains initially in current state.
b) PORST potentially filtered until WNFRST. Device state is unknown: it may either be reset or remains in current
state depending on other factors (temperature, voltage, device).
c) PORST asserted for longer than WNFRST. Device is under reset.
MPC5777M Microcontroller Data Sheet, Rev. 6
44
NXP Semiconductors
Electrical characteristics
VPORST, VESR0
VDD
VIH
VHYS
VIL
internal
reset
filtered by
hysteresis
filtered by
lowpass filter
WFRST
1
2
filtered by
lowpass filter
WFRST
unknown reset
state
device under hardware reset
WNFRST
3a
3b
3c
Figure 11. Noise filtering on reset signal
Table 20. Reset electrical characteristics
Value1
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
2.2
—
VDD_HV_IO
+0.4
V
VIH
SR Input high level TTL
(Schmitt trigger)
VIL
SR Input low level TTL
(Schmitt trigger)
—
–0.4
—
0.8
V
CC Input hysteresis TTL
(Schmitt trigger)
—
300
—
—
mV
CC Minimum supply for strong
pull-down activation
—
—
—
1.2
V
VHYS
VDD_POR
—
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
45
Electrical characteristics
Table 20. Reset electrical characteristics (continued)
Value1
Symbol
IOL_R
|IWPU|
|IWPD|
Parameter
Conditions
Unit
Min
Typ
Max
Device under power-on reset
VDD_HV_IO = VDD_POR,
VOL = 0.35 * VDD_HV_IO
0.2
—
—
mA
Device under power-on reset
3.0 V < VDD_HV_IO < 5.5 V,
VOL > 0.9 V
11
—
—
mA
CC Weak pull-up current absolute ESR0 pin
value
VIN = 0.69 * VDD_HV_IO
23
—
—
µA
ESR0 pin
VIN = 0.49 * VDD_HV_IO
—
—
82
PORST pin
VIN = 0.69 * VDD_HV_IO
—
—
130
PORST pin
VIN = 0.49 * VDD_HV_IO
40
—
—
CC Strong pull-down current2
CC Weak pull-down current
absolute value
µA
WFRST
SR PORST and ESR0 input
filtered pulse
—
—
—
500
ns
WNFRST
SR PORST and ESR0 input not
filtered pulse
—
2000
—
—
ns
WFNMI
SR ESR1 input filtered pulse
—
—
—
15
ns
WNFNMI
SR ESR1 input not filtered pulse
—
400
—
—
ns
1
An external 4.7 KOhm pull-up resistor is recommended to be used with the PORST and ESR0 pins for fast negation
of the signals.
2 I
OL_R applies to both PORST and ESR0: Strong pull-down is active on PHASE0 for PORST. Strong pull-down is active
on PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for ESR0.
NOTE
PORST can optionally be connected to an external power-on supply circuitry.
NOTE
No restrictions exist on reset signal slew rate apart from absolute maximum rating
compliance.
MPC5777M Microcontroller Data Sheet, Rev. 6
46
NXP Semiconductors
Electrical characteristics
3.9
Oscillator and FMPLL
The Reference PLL (PLL0) and the System PLL (PLL1) generate the system and auxiliary clocks from the main oscillator
driver.
PLL0_PHI
RCOSC
PLL0
PLL0_PHI1
XOSC
PLL1_PHI
PLL1
Figure 12. PLL integration
Table 21. PLL0 electrical characteristics
Value
Symbol
fPLL0IN
Parameter
SR
Conditions
PLL0 input clock1,2
Unit
Min
Typ
Max
—
8
—
44
MHz
—
40
—
60
%
PLL0IN
SR
PLL0 input clock duty
fPLL0VCO
CC
PLL0 VCO frequency
—
600
—
1250
MHz
fPLL0VCOFR
CC
PLL0 VCO free running
frequency
—
35
—
400
MHz
fPLL0PHI
CC
PLL0 output frequency
—
4.762
—
400
MHz
tPLL0LOCK
CC
PLL0 lock time
—
—
—
110
µs
fPLL0PHI = 400 MHz,
6-sigma
—
—
200
ps
PLL0_PHI1 single period jitter3 fPLL0PHI1 = 40 MHz,
6-sigma
fPLL0IN = 20 MHz (resonator)
—
—
3004
ps
PLL0PHISPJ|
CC
cycle2
PLL0_PHI single period
jitter3
fPLL0IN = 20 MHz (resonator)
PLL0PHI1SPJ|
CC
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
47
Electrical characteristics
Table 21. PLL0 electrical characteristics (continued)
Value
Symbol
PLL0LTJ
Parameter
CC
CC
IPLL0
Conditions
PLL0 output long term jitter3,4
fPLL0IN = 20 MHz (resonator),
VCO frequency = 800 MHz
PLL0 consumption
Unit
Min
Typ
Max
10 periods
accumulated jitter
(80 MHz equivalent
frequency), 6-sigma
pk-pk
—
—
±250
ps
16 periods
accumulated jitter
(50 MHz equivalent
frequency), 6-sigma
pk-pk
—
—
±300
ps
long term jitter
(< 1 MHz equivalent
frequency), 6-sigma
pk-pk)
—
—
±500
ps
FINE LOCK state
—
—
5
mA
1
fPLL0IN frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure PFD input signal is in the range 8
MHz–20 MHz.
2 PLL0IN clock retrieved directly from either internal RCOSC or external XOSC clock. Input characteristics are granted when
using internal RCOSC or external oscillator is used in functional mode.
3 PLL jitter is guaranteed when transient currents on the V
DDLV supply are within the ISPIKE parameter value in Table 10 (DC
electrical specifications).
4 Noise on the V
DD_LV supply with frequency content below 40 KHz and above 50 MHz is filtered by the PLL. Noise on the
VDD_LV supply with frequency content in the range of 40 KHz – 50 MHz must be filtered externally to the device.
Table 22. PLL1 electrical characteristics
Value
Symbol
fPLL1IN
SR
Conditions
PLL1 input clock1
Unit
Min
Typ
Max
—
38
—
78
MHz
—
35
—
65
%
PLL1IN
SR
PLL1 input clock duty
fPLL1VCO
CC
PLL1 VCO frequency
—
600
—
1250
MHz
fPLL1VCOFR
CC
PLL1 VCO free running
frequency
—
35
—
400
MHz
fPLL1PHI
CC
PLL1 output clock PHI
—
4.762
—
600
MHz
tPLL1LOCK
CC
PLL1 lock time
—
—
—
100
µs
fPLL1MOD
CC
PLL1 modulation frequency
—
—
—
250
kHz
PLL1MOD|
CC
PLL1 modulation depth (when
enabled)
Center spread
0.25
—
2
%
Down spread
0.5
—
4
%
PLL1 consumption
FINE LOCK state
—
—
6
mA
IPLL1
1
Parameter
CC
cycle1
PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when
using internal PLL0 or external oscillator is used in functional mode.
MPC5777M Microcontroller Data Sheet, Rev. 6
48
NXP Semiconductors
Electrical characteristics
Table 23. External Oscillator electrical specifications1
Value
Symbol
fXTAL
Parameter
CC
Crystal Frequency Range2
3,4
Conditions
Unit
Min
Max
—
4
8
—
>8
20
—
>20
40
TJ = 150 °C
—
5
ms
—
—
0.5
ms
MHz
tcst
CC
Crystal start-up time
trec
CC
Crystal recovery time5
VIHEXT
CC
EXTAL input high voltage6,7
(External Clock Input)
VREF = 0.28 * VDD_HV_IO_JTAG
VREF +
0.6
—
V
VILEXT
CC
EXTAL input low voltage6,7
(External Clock Input)
VREF = 0.28 * VDD_HV_IO_JTAG
—
VREF - 0.6
V
CS_xtal
CC
Total on-chip stray capacitance
on XTAL/EXTAL pins8
BGA416, BGA512
8
8.6
pF
VEXTAL
CC
Oscillation Amplitude on the
EXTAL pin after startup9
TJ = –40 °C to 150 °C
0.5
1.6
V
VHYS
CC
Comparator Hysteresis
TJ = –40 °C to 150 °C
0.1
1.0
V
CC
current13,10
TJ = –40 °C to 150 °C
—
14
mA
IXTAL
XTAL
1
All oscillator specifications are valid for VDD_HV_IO_JTAG = 3.0 V – 5.5 V.
The range is selectable by UTEST miscellaneous DCF clients XOSC_LF_EN and XOSC_EN_40MHZ.
3 This value is determined by the crystal manufacturer and board design.
4 Proper PC board layout procedures must be followed to achieve specifications.
5
Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load
capacitor value.
6 This parameter is guaranteed by design rather than 100% tested.
7 Applies to an external clock input and not to crystal mode.
8
See crystal manufacturer’s specification for recommended load capacitor (CL) values.The external oscillator requires
external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (CS_EXTAL/CS_XTAL)
and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load
capacitor value is selected via S/W to match the crystal manufacturer’s specification, while accounting for on-chip and PCB
capacitance.
9
Amplitude on the EXTAL pin after startup is determined by the ALC block, i.e., the Automatic Level Control Circuit. The
function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to
reduce power, distortion, and RFI, and to avoid over-driving the crystal. The operating point of the ALC is dependent on the
crystal value and loading conditions.
10
IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum
current during startup of the oscillator. The current after oscillation is typically in the 2–3 mA range and is dependent on the
load and series resistance of the crystal. Test circuit is shown in Figure 13.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
49
Electrical characteristics
Table 24. Selectable load capacitance
load_cap_sel[4:0] from DCF record
Load capacitance1,2 (pF)
00000
1.032
00001
1.976
00010
2.898
00011
3.823
00100
4.751
00101
5.679
00110
6.605
00111
7.536
01000
8.460
01001
9.390
01010
10.317
01011
11.245
01100
12.173
01101
13.101
01110
14.029
01111
14.957
1
Values are determined from simulation across process corners and voltage and temperature
variation. Capacitance values vary ±12% across process, 0.25% across voltage, and no variation
across temperature.
2 Values in this table do not include the die and package capacitances given by Cs_xtal/Cs_extal in
Table 23 (External Oscillator electrical specifications).
MPC5777M Microcontroller Data Sheet, Rev. 6
50
NXP Semiconductors
Electrical characteristics
VDDOSC
Bias
Current
ALC
IXTAL
XTAL
EXTAL
A
+
OFF
VSSOSC
Comparator
V
VSS
Conditions
Z = R + jL
Tester
VEXTAL=0 V
VXTAL=0 V
ALC INACTIVE
PCB
GND
Figure 13. Test circuit
Table 25. Internal RC Oscillator electrical specifications
Value
Symbol
Parameter
Unit
Min
Typ
Max
—
—
16
—
MHz
fTarget
CC
IRC target frequency
fvar_noT
CC
IRC frequency variation
without temperature
compensation
T < 150 oC
–8
—
8
%
fvar_T
CC
IRC frequency variation with
temperature compensation
T < 150 oC
–3
—
3
%
fvar_SW1
CC
IRC software trimming
accuracy
Trimming
temperature
–1
—
1
%
—
-48
—
+40
kHz
f
1
Conditions
IRC Software trimming step
Tstart_noT
CC
Startup time to reach within
fvar_noT
No trimming
—
—
5
µs
Tstart_T
CC
Startup time to reach within
fvar_T
Factory
trimming
already applied
—
—
120
µs
IAVDD5
CC
Current consumption on 5 V
power supply
After Tstart_T
—
—
400
µA
IDVDD12
CC
Current consumption on 1.2 V After Tstart_T
power supply
—
—
175
µA
IRC software trimmed accuracy is performed either with the CMU_0 clock monitor, using the XOSC as a reference or
through the CCCU (CAN clock control Unit), extracting reference clock from CAN master clock. Software trim must be
repeated as the device operating temperature varies in order to maintain the specified accuracy.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
51
Electrical characteristics
3.10
ADC specifications
3.10.1
ADC input description
Figure 14 shows the input equivalent circuit for fast SARn channels.
INTERNAL CIRCUIT SCHEME
VDD
Channel
Selection
Sampling
RSW1
RAD
CP1
CP2
CS
Common mode
switch
RSW1
RAD
CP
CS
RCMSW
RCML
Channel Selection Switch Impedance
Sampling Switch Impedance
Pin Capacitance (two contributions, CP1 and CP2)
Sampling Capacitance
Common mode switch
Common mode resistive ladder
Common mode
resistive ladder
This figure can be used as approximation circuitry for external filtering definition.
Figure 14. Input equivalent circuit (Fast SARn channels)
Figure 15 shows the input equivalent circuit for SARB channels.
INTERNAL CIRCUIT SCHEME
VDD
CP1
Channel
Selection
Extended
Switch
Sampling
RSW1
RSW2
RAD
CP3
CP2
CS
Common mode
switch
RSW: Channel Selection Switch Impedance (two contributions RSW1 and RSW2)
Sampling Switch Impedance
RAD:
Pin Capacitance (three contributions, CP1, CP2 and CP3)
CP:
Sampling Capacitance
CS:
RCMSW: Common mode switch
RCML: Common mode resistive ladder
Common mode
resistive ladder
The above figure can be used as approximation circuitry for external filtering definition.
Figure 15. Input equivalent circuit (SARB channels)
MPC5777M Microcontroller Data Sheet, Rev. 6
52
NXP Semiconductors
Electrical characteristics
Table 26. ADC pin specification1
Value
Symbol
ILK_INUD
ILK_INUSD
ILK_INREF
ILK_INOUT
Parameter
CHV_ADC
—
50
TJ < 150 °C
—
150
CC Input leakage current, two ADC
channels input with weak pull-up and
strong pull-down
TJ < 40 °C
—
80
TJ < 150 °C
—
250
CC Input leakage current, two ADC
TJ < 40 °C
channels input with weak pull-up and
T < 150 °C
weak pull-down and alternate reference J
—
160
—
400
—
140
—
380
–3
3
mA
1
2.2
µF
—
0
10
pF
SARn channels
0
0.5
pF
SARB channels
0
1
Only for SARB channels
0
1
pF
—
6
8.5
pF
SARn channels
0
1.1
k
SARB channels
0
1.7
CC ADC input analog switches resistance
—
0
0.6
k
CC Common mode switch resistance
—
0
2.6
k
CC Common mode resistive ladder
—
0
3.5
k
CC Discharge resistance for AN7/AN35
channels (strong pull-down for safety)
—
0
300

CC Input leakage current, two ADC
TJ < 40 °C
channels input, GPIO output buffer with
TJ < 150 °C
weak pull-up and weak pull-down
CP2
CC Internal routing capacitance
CP3
CC Internal routing capacitance
CS
CC SAR ADC sampling capacitance
CC Analog switches resistance
RCMSW
RCMRL
RSAFEPD
3
Applies to any analog pins
SR VDD_HV_ADV external capacitance2
CC Pad capacitance
RAD
Max
TJ < 40 °C
CP1
RSWn
Unit
Min
CC Input leakage current, two ADC
channels input with weak pull-up and
weak pull-down
CC Injection current on analog input
preserving functionality
IINJ
Conditions
nA
nA
nA
nA
1
All specifications in this table valid for the full input voltage range for the analog inputs.
For noise filtering, add a high frequency bypass capacitance of 0.1 µF between VDD_HV_ADV and VSS_HV_ADV.
3 Safety pull-down is available for port pin PB[5] and PE[14].
2
3.10.2
SAR ADC electrical specification
The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The
SARn architecture allows input channel multiplexing.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
53
Electrical characteristics
Table 27. SARn ADC electrical specification1
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VALTREF
SR ADC alternate
reference voltage
VALTREF < VDD_HV_IO_MAIN
2.0
VDD_HV_ADV_S
V
VIN
SR ADC input signal
0 < VIN < VDD_HV_IO_MAIN
VSS_HV_ADR_S
VDD_HV_ADR_S
V
fADCK
SR Clock frequency
TJ < 150 °C
7.5
14.6
MHz
SR ADC precharge time
Fast SAR—fast precharge
135
—
ns
Fast SAR—full precharge
270
—
Slow SAR (SARADC_B)—fast
precharge
270
—
Slow SAR (SARADC_B)—full
precharge
540
—
Full precharge
VPRECH = VDD_HV_ADR_S/2
TJ < 150 °C
–0.25
0.25
V
Fast precharge
VPRECH = VDD_HV_ADR_S/2
TJ < 150 °C
–0.5
0.5
V
tADCPRECH
VPRECH
SR Precharge voltage
precision
VINTREF
CC Internal reference
voltage precision
Applies to all internal reference
points (VSS_HV_ADR_S,
1/3 * VDD_HV_ADR_S,
2/3 * VDD_HV_ADR_S,
VDD_HV_ADR_S)
0.20
0.20
V
tADCSAMPLE
SR ADC sample time2
Fast SAR – 12-bit configuration
0.750
—
µs
Slow SAR (SARADC_B) – 12-bit
configuration
1.500
—
1.712
—
µs
µA
tADCEVAL
SR ADC evaluation time
12-bit configuration (25 clock
cycles)
IADCREFH3,4
CC ADC high reference
current
Run mode tconv  5 µs
(average across all codes)
—
7
Run mode tconv = 2.5 µs
(average across all codes)
—
7
Power Down mode
—
6
Current5
—
+2
Run mode tconv  5 µs
VDD_HV_ADR_S <= 5.5 V
—
15
Run mode tconv = 2.5 µs
VDD_HV_ADR_S <= 5.5 V
—
30
Power Down mode
VDD_HV_ADR_S <= 5.5 V
—
1
Bias
IADCREFL
4
CC ADC low reference
current
µA
MPC5777M Microcontroller Data Sheet, Rev. 6
54
NXP Semiconductors
Electrical characteristics
Table 27. SARn ADC electrical specification1 (continued)
Value
Symbol
IADV_S4
TUE12
Parameter
CC VDD_HV_ADV_S power
supply current (each
ADC)
Conditions
Unit
Min
Max
Run mode tconv  5 µs
—
4.0
Run mode tconv = 2.5 µs
—
4.0
Power Down mode
—
1.0
–4
4
CC Total unadjusted error TJ < 150 °C,
in 12-bit configuration6 VDD_HV_ADV_S > 4 V,
VDD_HV_ADR_S > 4 V
mA
LSB
(12b)
TJ < 150 °C,
VDD_HV_ADV_S > 4 V,
4 V > VDD_HV_ADR_S > 2 V
–6
6
TJ < 150 °C,
4 V > VDD_HV_ADV_S > 3.5 V
–12
12
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
55
Electrical characteristics
Table 27. SARn ADC electrical specification1 (continued)
Value
Symbol
TUE12
DNL
INL
1
2
3
4
5
Parameter
Conditions
CC TUE degradation due VIN < VDD_HV_ADV_S
to VDD_HV_ADR_S offset VDD_HV_ADR_S  VDD_HV_ADV_S
with respect to
[0:25 mV]
VDD_HV_ADV_S
VIN < VDD_HV_ADV_S
VDD_HV_ADR_S  VDD_HV_ADV_S
[25:50 mV]
Unit
Min
Max
0
0
LSB
(12b)
–2
2
VIN < VDD_HV_ADV_S
VDD_HV_ADR_S  VDD_HV_ADV_S
[50:75 mV]
–4
4
VIN < VDD_HV_ADV_S
VDD_HV_ADR_S  VDD_HV_ADV_S
[75:100 mV]
–6
6
VDD_HV_ADV_S < VIN <
VDD_HV_ADR_S
VDD_HV_ADR_S  VDD_HV_ADV_S
[0:25 mV]
–2.5
2.5
VDD_HV_ADV_S< VIN <
VDD_HV_ADR_S
VDD_HV_ADR_S  VDD_HV_ADV_S
[25:50 mV]
–4
4
VDD_HV_ADV_S < VIN <
VDD_HV_ADR_S
VDD_HV_ADR_S  VDD_HV_ADV_S
[50:75 mV]
–7
7
VDD_HV_ADV_S < VIN <
VDD_HV_ADR_S
VDD_HV_ADR_S  VDD_HV_ADV_S
[75:100 mV]
–12
12
CC Differential
non-linearity
VDD_HV_ADV_S > 4 V
VDD_HV_ADR_S > 4 V
–1
2
CC Integral non-linearity
4.0 V < VDD_HV_ADV_S < 5.5 V
4.0 V < VDD_HV_ADR_S < 5.5 V
–3
VDD_HV_ADV_S = 2V
VDD_HV_ADR_S = 2 V
–5
LSB
(12b)
3
LSB
(12b)
5
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal
sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB
within the sampling window. Please refer to Figure 14 and Figure 15 for models of the internal ADC circuit, and the
values to use in external RC sizing and calculating the sampling window duration.
IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is
driven by the transfer of charge between internal capacitances during the conversion.
Current parameter values are for a single ADC.
Extra bias current is present only when BIAS is selected.
MPC5777M Microcontroller Data Sheet, Rev. 6
56
NXP Semiconductors
Electrical characteristics
6
This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to
± 6 LSB.
3.10.3
S/D ADC electrical specification
The SDn ADCs are Sigma Delta 16-bit analog-to-digital converters with 333 Ksps maximum output rate.
Table 28. SDn ADC electrical specification1
Value
Symbol
VIN
VIN_PK2PK2
Parameter
Conditions
SR ADC input signal
SR Input range peak to
peak
VIN_PK2PK = VINP3 –
VINM4
—
Unit
Min
Typ
Max
0
—
VDD_HV_ADV_D
Single ended
VINM = VSS_HV_ADR_D
VDD_HV_ADR_D/GAIN
Single ended
VINM = 0.5*VDD_HV_ADR_D
GAIN = 1
±0.5*VDD_HV_ADR_D
Single ended
VINM = 0.5*VDD_HV_ADR_D
GAIN = 2,4,8,16
±VDD_HV_ADR_D/GAIN
Differential,
0 < VIN < VDD_HV_IO_MAIN
±VDD_HV_ADR_D/GAIN
V
V
fADCD_M
SR S/D modulator Input
Clock
—
4
14.4
16
MHz
fADCD_S
SR Output conversion
rate
—
—
—
333
ksps
—
CC Oversampling ratio
Internal modulator
24
—
256
—
External modulator
—
—
256
—
RESOLUTION CC S/D register
2’s complement notation
16
bit
resolution5
GAIN
SR ADC gain
Defined via ADC_SD[PGA]
register. Only integer powers of 2
are valid gain values.
1
—
16
—
GAIN
CC Absolute value of the Before calibration (applies to gain
ADC gain error6,7
setting = 1)
—
—
1.5
%
After calibration, VDD_HV_ADR_D 
5%
VDD_HV_ADV_D  10%
TJ  50 °C
—
—
5
mV
After calibration, VDD_HV_ADR_D 
5%
VDD_HV_ADV_D  10%
TJ  100 °C
—
—
7.5
After calibration, VDD_HV_ADR_D 
5%
VDD_HV_ADV_D  10%
TJ  150 °C
—
—
10
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
57
Electrical characteristics
Table 28. SDn ADC electrical specification1 (continued)
Value
Symbol
VOFFSET
Parameter
Conditions
CC Input Referred Offset Before calibration (applies to all
Error6,7,8
gain settings – 1, 2, 4, 8, 16)
After calibration,
VDD_HV_ADR_D  10%
TJ  50 °C
Unit
Min
Typ
Max
—
10*
(1+1/gain)
20
—
—
5
After calibration, VDD_HV_ADV_D 
10%
TJ  100 °C
After calibration, VDD_HV_ADV_D 
10%
TJ  150 °C
SNRDIFF150
mV
7.5
0.5
10
CC Signal to noise ratio in 4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
differential mode
150 ksps output rate GAIN = 1
80
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 2
TJ < 150 °C
77
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 4
TJ < 150 °C
74
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 8
TJ < 150 °C
71
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 16
TJ < 150 °C
68
—
—
dBFS
TJ < 150 °C
MPC5777M Microcontroller Data Sheet, Rev. 6
58
NXP Semiconductors
Electrical characteristics
Table 28. SDn ADC electrical specification1 (continued)
Value
Symbol
SNRDIFF333
Parameter
Conditions
Unit
Min
Typ
Max
CC Signal to noise ratio in 4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
differential mode
333 ksps output rate GAIN = 1
74
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 2
TJ < 150 °C
71
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 4
TJ < 150 °C
68
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 8
TJ < 150 °C
65
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 16
TJ < 150 °C
62
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 1
TJ < 150 °C
74
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 2
TJ < 150 °C
71
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 4
TJ < 150 °C
68
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
VDD_HV_ADR_D = VDD_HV_ADV_D
GAIN = 8
TJ < 150 °C
65
—
—
4.5 < VDD_HV_ADV_D < 5.59,10,17
62
—
—
GAIN = 1
60
—
—
GAIN = 2
60
—
—
GAIN = 4
60
—
—
GAIN = 8
60
—
—
GAIN = 16
60
—
—
dBFS
TJ < 150 °C
SNRSE150
CC Signal to noise ratio in
single ended mode
150 ksps output
rate11
dBFS
VDD_HV_ADR_D=VDD_HV_ADV_D
GAIN = 16
TJ < 150 °C
SFDR
CC Spurious free
dynamic range
dBc
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
59
Electrical characteristics
Table 28. SDn ADC electrical specification1 (continued)
Value
Symbol
ZDIFF
ZCM
Parameter
D Differential Input
impedance1213
D Common Mode Input
impedance14 15
Conditions
Unit
Min
Typ
Max
GAIN=1
1000
1250
1500
GAIN=2
600
800
1000
GAIN=4
300
400
500
GAIN=8
200
250
300
GAIN=16
200
250
300
GAIN=1
1400
1800
2200
GAIN=2
1000
1300
1600
GAIN=4
700
950
1150
GAIN=8
500
650
800
GAIN=16
500
650
800
k
k
RBIAS
D Bare Bias resistance
—
110
144
180
k
VINTCM
D common mode input
reference voltage16
—
-12
—
+12
%
VBIAS
CC Bias voltage
—
—
VDD_HV_
ADR_D/2
—
V
VBIAS
CC Bias voltage accuracy
—
–2.5
—
+2.5
%
Vcmrr
SR Common mode
rejection ratio
—
54
—
—
dB
RCaaf
SR Anti-aliasing filter
External series resistance
—
—
20
k
CC
Filter capacitances
180
—
—
pF
—
0.01
—
0.333 *
fADCD_S
kHz
–1
—
1
%
CC Stop band attenuation [0.5 * fADCD_S, 1.0 * fADCD_S]
40
—
—
dB
[1.0 * fADCD_S, 1.5 * fADCD_S]
45
—
—
[1.5 * fADCD_S, 2.0 * fADCD_S]
50
—
—
[2.0 * fADCD_S, 2.5 * fADCD_S]
55
—
—
[2.5 * fADCD_S, fADCD_M/2]
60
—
—
fPASSBAND
RIPPLE
Frolloff
CC Pass
band17
CC Pass band ripple18
0.333 * fADCD_S
MPC5777M Microcontroller Data Sheet, Rev. 6
60
NXP Semiconductors
Electrical characteristics
Table 28. SDn ADC electrical specification1 (continued)
Value
Symbol
GROUP
Parameter
CC Group delay
Conditions
Unit
Min
Typ
Max
Within pass band – Tclk is fADCD_M
/2
—
—
—
—
OSR = 24
—
—
238.5
Tclk
OSR = 28
—
—
278
OSR = 32
—
—
317.5
OSR = 36
—
—
357
OSR = 40
—
—
396.5
OSR = 44
—
—
436
OSR = 48
—
—
475.5
OSR = 56
—
—
554.5
OSR = 64
—
—
633.5
OSR = 72
—
—
712.5
OSR = 75
—
—
699
OSR = 80
—
—
791.5
OSR = 88
—
—
870.5
OSR = 96
—
—
949.5
OSR = 112
—
—
1107.5
OSR = 128
—
—
1265.5
OSR = 144
—
—
1423.5
OSR = 160
—
—
1581.5
OSR = 176
—
—
1739.5
OSR = 192
—
—
1897.5
OSR = 224
—
—
2213.5
OSR = 256
—
—
2529.5
–0.5/
fADCD
—
+0.5/
fADCD_S
—
—
10e-5*
fADCD_S
—
—
—
—
100
µs
—
—
GROUP +
fADCD_S
—
—
—
GROUP
—
Distortion within pass band
_S
fHIGH
CC High pass filter 3dB
frequency
Enabled
tSTARTUP
CC Start-up time from
power down state
tLATENCY
CC Latency between
HPF = ON
input data and
converted data when
HPF = OFF
input mux does not
19
change
—
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
61
Electrical characteristics
Table 28. SDn ADC electrical specification1 (continued)
Value
Symbol
tSETTLING
Parameter
IBIAS
IADV_D
IADR_D
Unit
Min
Typ
Max
Analog inputs are muxed
HPF = ON
—
—
2*GROUP +
3*fADCD_S
—
HPF = OFF
—
—
2*GROUP +
2*fADCD_S
—
After input comes within range
from saturation
HPF = ON
—
—
2*GROUP +
fADCD_S
—
HPF = OFF
—
—
2*GROUP
—
CC S/D ADC sampling
capacitance after
sampling switch20
GAIN = 1, 2, 4, 8
—
—
75*GAIN
fF
GAIN = 16
—
—
600
fF
CC Bias consumption
At least 1 ADCD enabled
3.5
mA
CC Settling time after
mux change
tODRECOVERY CC Overdrive recovery
time
CS_D
Conditions
CC VDD_HV_ADV_D power ADCD enabled
supply current (each
ADC)
—
—
3.5
mA
CC Sum of all ADC
reference
consumption
ADCD enabled, fADCD_M =
14.4 MHz
—
—
30
µA
Gain = 1
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
72
—
—
dBFS
Gain = 2
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
72
—
—
Gain = 4
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
69
—
—
Gain = 8
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
68.8
—
—
Gain = 16
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
64.8
—
—
SINADDIFF150 CC Signal to Noise and
Distortion Ratio,
Differential Mode,
150 Ksps output rate
MPC5777M Microcontroller Data Sheet, Rev. 6
62
NXP Semiconductors
Electrical characteristics
Table 28. SDn ADC electrical specification1 (continued)
Value
Symbol
Parameter
SINADDIFF333 CC Signal to Noise and
Distortion Ratio,
Single-ended Mode,
150Ksps output rate
SINADSE150 CC Signal to Noise and
Distortion Ratio,
Single-ended Mode,
150Ksps output rate
Conditions
Unit
Min
Typ
Max
Gain = 1
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
66
—
—
Gain = 2
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
66
—
—
Gain = 4
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
63
—
—
Gain = 8
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
62
—
—
Gain = 16
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
59
—
—
Gain = 1
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
66
—
—
Gain = 2
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
66
—
—
Gain = 4
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
63
—
—
Gain = 8
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
62
—
—
Gain = 16
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
59
—
—
dBFS
dBFS
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
63
Electrical characteristics
Table 28. SDn ADC electrical specification1 (continued)
Value
Symbol
THDDIFF150
THDDIFF333
Parameter
CC Total Harmonic
Distortion, Differential
Mode, 150Ksps
output rate
CC Total Harmonic
Distortion, Differential
Mode, 333Ksps
output rate
Conditions
Unit
Min
Typ
Max
Gain = 1
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
65
—
—
Gain = 2
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
68
—
—
Gain = 4
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
74
—
—
Gain = 8
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
80
—
—
Gain = 16
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
80
—
—
Gain = 1
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
65
—
—
Gain = 2
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
68
—
—
Gain = 4
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
74
—
—
Gain = 8
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
80
—
—
Gain = 16
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
80
—
—
dBFS
dBFS
MPC5777M Microcontroller Data Sheet, Rev. 6
64
NXP Semiconductors
Electrical characteristics
Table 28. SDn ADC electrical specification1 (continued)
Value
Symbol
THDSE150
Parameter
CC Total Harmonic
Distortion,
Single-ended Mode,
150Ksps output rate
Conditions
Unit
Min
Typ
Max
Gain = 1
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
68
—
—
Gain = 2
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
68
—
—
Gain = 4
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
68
—
—
Gain = 8
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
68
—
—
Gain = 16
4.5 V < VDD_HV_ADV_D < 5.5 V
VDD_HV_ADR_D = VDD_HV_ADV_D
Tj < 150 °C
68
—
—
dBFS
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
2 For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and
the signal will only be ‘clipped’.
3 V
INP is the input voltage applied to the positive terminal of the SDADC.
4 V
INM is the input voltage applied to the negative terminal of the SDADC.
5 When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. The
gives an effective resolution of 15 bits.
6 Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device.
7 Calibration of gain is possible when gain = 1.
Offset Calibration should be done with respect to 0.5*VDD_HV_ADR_D for differential mode and single ended mode with
negative input=0.5*VDD_HV_ADR_D.
Offset Calibration should be done with respect to 0 for "single ended mode with negative input=0".
Both offset and Gain Calibration is guaranteed for ±5% variation of VDD_HV_ADR_D, ±10% variation of VDD_HV_ADV_D,
and ± 50 °C temperature variation.
8 Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred
offset error.
9 S/D ADC is functional in the range 3.6 V – 4.5 V, SNR parameter degrades by 3 dB. Degraded SNR value based on
simulation.
10 S/D ADC is functional in the range 3.0 V –4.5 V, SNR parameter degrades by 9 dB. Degraded SNR value based on
simulation.
11 This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to
a value of 6 dB less.
12 Input impedance in differential mode Z (input impedance) = Z
IN
DIFF.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
65
Electrical characteristics
13
Impedance given at FADCD_M= 16 MHz. Impedance is inversely proportional to SDADC clock frequency.
ZDIFF(FADCD_M) = (16 MHz / FADCD_M) * ZDIFF, ZCM (FADCD_M) = (16MHz / FADCD_M) * ZCM.
14
Input impedance in single-ended mode ZIN = (2 * ZDIFF * ZCM) / (ZDIFF + ZCM).
15
Impedance given at FADCD_M= 16 MHz. Impedance is inversely proportional to SDADC clock frequency.
ZDIFF(FADCD_M) = (16 MHz / FADCD_M) * ZDIFF, ZCM (FADCD_M) = (16MHz / FADCD_M) * ZCM.
16 Vintcm is the common mode input reference voltage for the SDADC, and has a nominal value of (V
DD_HV_ADC VSS_HV_ADC) / 2.
17
SNR values guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the
frequency range of fADCD_M – fADCD_S to fADCD_M + fADCD_S, where fADCD_M is the input sampling frequency, and
fADCD_S is the output sample frequency. A proper external input filter should be used to remove any interfering signals
in this frequency range.
18
The ±1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.087 dB.
19
Propagation of the information from the pin to the register CDR[CDATA] and flags SFR[DFEF], SFR[DFFF] is given by
the different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain
synchronizers. The time elapsed between data availability at pin and internal S/D module registers is given by the
below formula:
REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)fPBRIDGEx_CLK
where fADCD_S is the frequency of the sampling clock, fADCD_M is the frequency of the modulator, and
fPBRIDGEx_CLK is the frequency of the peripheral bridge clock feeds to the ADC S/D module. The (~+1) symbol
refers to the number of clock cycles uncertainty (from 0 to 1 clock cycle) to be added due to resynchronization of the
signal during clock domain crossing.
Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received
from the ADC S/D module.
20 This capacitance does not include pin capacitance, that can be considered together with external capacitance, before
sampling switch.
3.11
Temperature sensor
The following table describes the temperature sensor electrical characteristics.
Table 29. Temperature sensor electrical characteristics
Value
Symbol
—
Conditions
Unit
Min
Typ
Max
CC Temperature monitoring range
—
–40
—
150
°C
TSENS
CC Sensitivity
—
—
5.18
—
mV/°C
TACC
CC Accuracy
TJ  150 °C
–3
—
3
°C
—
—
—
700
µA
ITEMP_SENS
3.12
Parameter
CC VDD_HV_ADV_S power supply
current
LVDS Fast Asynchronous Serial Transmission (LFAST) pad
electrical characteristics
The LFAST pad electrical characteristics apply to both the SIPI and high-speed debug serial interfaces on the device. The same
LVDS pad is used for the Microsecond Channel (MSC) and DSPI LVDS interfaces, with different characteristics given in the
following tables.
MPC5777M Microcontroller Data Sheet, Rev. 6
66
NXP Semiconductors
Electrical characteristics
3.12.1
LFAST interface timing diagrams
Signal excursions above this level NOT allowed
1743 mV
Max. common mode input at RX
1600 mV
VOD
Max Differential Voltage =
285 mV p-p (LFAST)
400 mV p-p (MSC/DSPI)
Minimum Data Bit Time
Opening =
0.55 * T (LFAST)
0.50 * T (MSC/DSPI)
“No-Go” Area
VOS = 1.2 V +/- 10%
TX common mode
VOD
Min Differential Voltage =
100 mV p-p (LFAST)
150 mV p-p (MSC/DSPI)
VICOM
PEREYE
PEREYE
Data Bit Period
T = 1 /FDATA
Min. common mode input at RX
150 mV
0V
Signal excursions below this level NOT allowed
Figure 16. LFAST and MSC/DSPI LVDS timing definition
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
67
Electrical characteristics
H
lfast_pwr_down
L
tPD2NM_TX
Differential
Data Lines
TX
pad_p/pad_n
Data Valid
Figure 17. Power-down exit time
VIH
Differential
Data Lines
TX
90%
10%
pad_p/pad_n
VIL
tTR
tTR
Figure 18. Rise/fall time
3.12.2
LFAST and MSC/DSPI LVDS interface electrical characteristics
The following table contains the electrical characteristics for the LFAST interface.
Table 30. LVDS pad startup and receiver electrical characteristics1,2
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
STARTUP3,4
tSTRT_BIAS CC Bias current reference startup time5
—
—
0.5
4
µs
tPD2NM_TX CC Transmitter startup time (power
down to normal mode)6
—
—
0.4
2.75
µs
MPC5777M Microcontroller Data Sheet, Rev. 6
68
NXP Semiconductors
Electrical characteristics
Table 30. LVDS pad startup and receiver electrical characteristics1,2 (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
tSM2NM_TX CC Transmitter startup time (sleep mode Not applicable to the
to normal mode)7
MSC/DSPI LVDS pad
—
0.2
0.5
µs
tPD2NM_RX CC Receiver startup time (power down
to normal mode)8
—
20
40
ns
—
tPD2SM_RX CC Receiver startup time (power down
to sleep mode)9
Not applicable to the
MSC/DSPI LVDS pad
—
20
50
ns
ILVDS_BIAS CC LVDS bias current consumption
Tx or Rx enabled
—
—
0.95
mA
TRANSMISSION LINE CHARACTERISTICS (PCB Track)
Z0
ZDIFF
SR Transmission line characteristic
impedance
—
47.5
50
52.5

SR Transmission line differential
impedance
—
95
100
105

—
0.1510
—
1.611
V
—
100
—
—
mV
—
25
—
—
mV
3.0 V–5.5 V
80
125
150

—
—
3.5
6.0
pF
—
—
0.5
mA
RECEIVER
VICOM
SR Common mode voltage
|VI|
SR Differential input
VHYS
CC Input hysteresis
RIN
CIN
ILVDS_RX
voltage12
CC Terminating resistance
CC Differential input
capacitance13
CC Receiver DC current consumption
Enabled
1
The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed Debug (HSD) LVDS pad, and the MSC/DSPI LVDS pad except where noted in the conditions.
2 All LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
3 All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in
the LVDS control registers (LCR) of the LFAST and High-Speed Debug modules. The value of the LCR bits for the
LFAST/HSD modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode.
Startup times for MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS
in the corresponding SIUL2 MSCR ODC field.
4 Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter electrical characteristic tables.
5 Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after
being enabled.
6 Total transmitter startup time from power down to normal mode is t
STRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock
periods.
7 Total transmitter startup time from sleep mode to normal mode is t
SM2NM_TX + 2 peripheral bridge clock periods. Bias
block remains enabled in sleep mode.
8 Total receiver startup time from power down to normal mode is t
STRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock
periods.
9 Total receiver startup time from power down to sleep mode is t
PD2SM_RX + 2 peripheral bridge clock periods. Bias
block remains enabled in sleep mode.
10 Absolute min = 0.15 V – (285 mV/2) = 0 V
11
Absolute max = 1.6 V + (285 mV/2) = 1.743 V
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
69
Electrical characteristics
12
The LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to ensure proper LFAST receive
timing.
13
Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.
Table 31. LFAST transmitter electrical characteristics1,2
Value
Symbol
2
3
4
5
Conditions
Unit
Min
Typ
Max
312/3203 Mbps
fDATA
SR Data rate
—
—
—
VOS
CC Common mode voltage
—
1.08
—
1.32
V
|VOD|
CC Differential output voltage swing
(terminated)4,5
—
110
171
285
mV
tTR
CC Rise/Fall time (absolute value of the
differential output voltage swing)4,5
—
0.26
—
1.5
ns
CL
SR External lumped differential load
capacitance3
VDD_HV_IO = 4.5 V
—
—
10.0
pF
VDD_HV_IO = 3.0 V
—
—
8.5
—
—
3.2
ILVDS_TX
1
Parameter
CC Transmitter DC current consumption
Enabled
mA
The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance
values shown in Figure 19.
All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
The 312 Mbps data rate is achieved with a 26 MHz reference clock, and 320 Mbps is achieved with a 10 or 20 MHz
reference clock.
Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in
Figure 19.
Valid for maximum external load CL.
Table 32. MSC/DSPI LVDS transmitter electrical characteristics 1,2
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Data Rate
fDATA
SR Data rate
—
—
—
80
Mbps
VOS
CC Common mode voltage
—
1.08
—
1.32
V
|VOD|
CC Differential output voltage swing
(terminated)3,4
—
150
214
400
mV
tTR
CC Rise/Fall time (absolute value of the
differential output voltage swing)3,4
—
0.8
—
4.0
ns
CL
SR External lumped differential load
capacitance3
VDD_HV_IO = 4.5 V
—
—
50
pF
VDD_HV_IO = 3.0 V
—
—
39
—
—
4.0
ILVDS_TX
CC Transmitter DC current consumption
Enabled
mA
1
The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst case
internal capacitance values given in Figure 19.
2 All MSC and DSPI LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
MPC5777M Microcontroller Data Sheet, Rev. 6
70
NXP Semiconductors
Electrical characteristics
3
Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown
in Figure 19.
4
Valid for maximum external load CL.
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Figure 19. LVDS pad external load diagram
3.12.3
LFAST PLL electrical characteristics
The following table contains the electrical characteristics for the LFAST PLL.
Table 33. LFAST PLL electrical characteristics1
Value
Symbol
Parameter
Conditions
Unit
Min
Nominal
Max
fRF_REF
SR PLL reference clock frequency
—
10
—
26
MHz
ERRREF
CC PLL input reference clock frequency error
—
–1
—
1
%
CC PLL input reference clock duty cycle
—
45
—
55
%
fRF_REF = 20 MHz
—
—
–58
dBc
fRF_REF = 10 MHz
—
—
–64
DCREF
PN
CC Integrated phase noise (single side band)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
71
Electrical characteristics
Table 33. LFAST PLL electrical characteristics1 (continued)
Value
Symbol
fVCO
tLOCK
PERREF
Parameter
Conditions
Nominal
Max
—
—
6402
—
MHz
—
—
—
40
µs
Single period,
fRF_REF = 10 MHz
—
—
300
ps
Long term,
fRF_REF = 10 MHz
–500
—
500
ps
—
—
—
400
ps
CC PLL VCO frequency
CC PLL phase lock
3
SR Input reference clock jitter (peak to peak)
Unit
Min
PEREYE CC Output Eye Jitter (peak to peak)4
1
The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.
The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO
frequency is 624 MHz.
3 The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral
bridge clock that is connected to the PLL on the device.
4 Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. See
Figure 19.
2
3.13
Aurora LVDS electrical characteristics
The following table describes the Aurora LVDS electrical characteristics.
NOTE
The Aurora interface is AC coupled, so there is no common-mode voltage specification.
Table 34. Aurora LVDS electrical characteristics1,2
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
—
—
Max
Transmitter
CC Transmit Data Rate
—
CC Differential output voltage swing
(terminated)3
—
tTR_LVDS
CC Rise/Fall time (10%–90% of swing)
—
60
—
—
ps
RV_L_Tx
SR Differential Terminating resistance
—
81
100
120

—
—
64
dB
FTX
VOD_LVDS
TLoss
CC Transmission Line Loss due to loading
effects
—
1.25 Gbps
±400 ±600 ±800
mV
Transmission line characteristics (PCB track)
LLINE
SR Transmission line length
—
—
—
20
cm
ZLINE
SR Transmission line characteristic impedance
—
45
50
55

Cac_clk
SR Clock Receive Pin External AC Coupling
Capacitance
100
—
270
pF
Values are nominal, valid
for +/– 50% tolerance
MPC5777M Microcontroller Data Sheet, Rev. 6
72
NXP Semiconductors
Electrical characteristics
Table 34. Aurora LVDS electrical characteristics1,2 (continued)
Value
Symbol
Cac_tx
Parameter
Conditions
SR Transmit Lane External AC Coupling
Capacitance
Values are nominal, valid
for +/– 50% tolerance
Unit
Min
Typ
Max
250
—
2000
—
—
1.25 Gbps
pF
Receiver
FRX
VI_L
RV_L_Rx
CC Receive Clock Rate
TJ = 150 °C
SR Differential input voltage (peak to peak)
—
200
—
1000
mV
CC Differential Terminating resistance
—
81
100
120

1
All Aurora electrical characteristics are valid from –40 °C to 150 °C, except where noted.
All specifications valid for maximum transmit data rate FTX.
3 The minimum value of 400 mV is only valid for differential terminating resistance (R
V_L) = 99 ohm to 101 ohm. The
differential output voltage swing tracks with the value of RV_L.
4 Transmission line loss maximum value is specified for the maximum drive level of the Aurora transmit pad.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
73
Electrical characteristics
3.14
3.14.1
Power management: PMC, POR/LVD, sequencing
Power management electrical characteristics
The power management module monitors the different power supplies. It also generates the internal supplies that are required
for correct device functionality. The power management is supplied by the VDD_HV_PMC supply (see Table 8).
3.14.2
Power management integration
In order to ensure correct functionality of the device, it is recommended to follow below integration scheme.
CHV_PMC
VDD_HV_PMC
VDD_HV_FLA
VSS
CHV_FLA
VDD_HV_IO
CHV_IO(2)
VDD_LV
MPC5777M
CLV(1)
VSS
CHV_ADC
(1) One capacitance near each VDD_LV pin
(2) One capacitance near each VDD_HV pin
VSS_HV_ADV
VDD_HV_ADV
VSS
Figure 20. Recommended supply pin circuits
MPC5777M Microcontroller Data Sheet, Rev. 6
74
NXP Semiconductors
Electrical characteristics
The following table describes the supply stability capacitances required on the device for proper operation.
Table 35. Device power supply integration
Value1
Symbol
SR
CLV
1
2
3
4
5
6
7
8
Parameter
Conditions
Minimum VDD_LV external Bulk capacitance
capacitance2
Total bypass
capacitance at
external pin3
CHV_IO
SR
Minimum VDD_HV_IO external capacitance
CHV_FLA
SR
Minimum VDD_HV_FLA external capacitance4,5
6,7
CHV_PMC
SR
Minimum VDD_HV_PMC External Capacitance
CHV_ADC
SR
Minimum VDD_HV_ADV external capacitance8
Unit
Min
Typ
Max
10
—
—
Note
3
—
—
—
4.7
—
—
µF
—
0.75
1.5
—
µF
512 BGA balls A29,
B28, F24, and G23
2.2
4.7
—
µF
1.5
3.3
—
µF
External regulator
bandwidth > 20 KHz
µF
See Figure 20 for capacitor integration.
Recommended X7R or X5R ceramic low ESR capacitors, ±15% variation over voltage, temperature, and aging.
Each VDD_LV pin requires both a 0.1µF and 0.01µF capacitor for high-frequency bypass and EMC requirements.
The recommended flash regulator composition capacitor is 1.5 µF typical X7R or X5R, with –50% and +35% as min and
max. This puts the min cap at 0.75 µF.
Start-up time of the internal flash regulator from release of the LVD360 is worst case 500 us. This is based on the typical
CHV_FLA bulk capacitance value.
For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between VDD_HV_PMC and
VSS_HV.
In the 512BGA package, VDD_HV_PMC is shorted to VDD_HV_IO_MAIN. Use a local 200 nF capacitor on 512BGA balls A29,
B28, F24, G3, in addition to the normal VDD_HV_IO_MAIN bulk and local external capacitance.
For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between VDD_HV_ADV and
VSS_HV_ADV.
3.14.3
3.3 V flash supply
Table 36. Flash power supply
Value
Symbol
VDD_HV_FLA1
1
2
Parameter
CC
Flash regulator DC output voltage
Conditions
Unit
Min
Typ
Max
Before trimming
3.12
3.3
3.5
After trimming
–40°C  TJ  25°C
3.15
3.3
3.4
After trimming
25°C  TJ 150°C
3.10
3.3
3.4
V
Min value accounts for all static and dynamic variations of the regulator (min cap as 0,75uF).
Min value of 3.1 V for VDD_HV_REG at 3.15V assumes that the auxiliary regulator on VDD_LV does not actively provide
any current to the chip. If the auxiliary regulator actively provides current, the min value may go lower than 3.1 V drop to
IR drop caused by auxiliary current demanding on VDD_HV_REG supply.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
75
Electrical characteristics
3.14.4
Device voltage monitoring
The LVD/HVDs and their associated levels for the device are given in the following table. The figure below illustrates the
workings of voltage monitoring threshold.
VDD_xxx
VHVD(rise)
VHVD(fall)
VLVD(rise)
VLVD(fall)
tVDASSERT
tVDRELEASE
HVD TRIGGER
(INTERNAL)
tVDRELEASE
tVDASSERT
LVD TRIGGER
(INTERNAL)
Figure 21. Voltage monitor threshold definition
Table 37. Voltage monitor electrical characteristics1
Value
Symbol
Parameter
VPORUP_LV2 CC LV supply power on reset threshold
Conditions
Unit
Rising voltage (power up)
Falling voltage (power down)
Hysteresis on power-up
3
Min
Typ
Max
1111
—
1235
1015
—
1125
50
—
—
mV
VLVD096
CC LV internal4 supply low voltage
monitoring
See note 5
1015
—
1145
mV
VLVD108
CC Core LV internal4 supply low voltage See note 6
monitoring
1150
—
1220
mV
VLVD112
CC LV external7 supply low voltage
monitoring
1175
—
1235
mV
See note 5
MPC5777M Microcontroller Data Sheet, Rev. 6
76
NXP Semiconductors
Electrical characteristics
Table 37. Voltage monitor electrical characteristics1 (continued)
Value
Symbol
—
1475
mV
VHVD145
CC LV externa10 supply high voltage
reset threshold
—
1430
—
1510
mV
VPORUP_HV2 CC HV supply power on reset threshold9 Rising voltage (power up) on
PMC/IO Main supply
4040
—
Rising voltage (power up) on
IO JTAG and Osc supply
2730
—
3030
Rising voltage (power up) on
ADC supply
2870
—
3182
Falling voltage (power down)11
2850
—
3162
Hysteresis on power up12
878
—
1630
CC HV supply power-on reset voltage
monitoring
Rising voltage
2420
—
2780
Falling voltage
2400
—
2760
CC HV supply low voltage monitoring
Rising voltage
2750
—
3000
Falling voltage
2700
—
2950
Rising voltage
—
—
3120
Falling voltage
2920
—
3100
CC Flash supply high voltage monitoring Rising voltage
3435
—
3650
Falling voltage
3415
—
—
Rising voltage
—
—
4000
Falling voltage
3600
—
3880
Rising voltage
4110
—
4410
Falling voltage
3970
—
4270
Rising voltage
5560
—
5960
Falling voltage
5500
—
5900
VLVD360
VLVD400
VHVD600
CC Flash supply low voltage
monitoring13
CC HV supply low voltage monitoring
CC HV supply low voltage monitoring
CC HV supply high voltage monitoring
448010 mV
mV
mV
mV
mV
mV
mV
mV
CC Voltage detector threshold crossing
assertion
—
0.1
—
2
µs
tVDRELEASE CC Voltage detector threshold crossing
de-assertion
—
5
—
20
µs
tVDASSERT
5
Max
1385
VHVD360
4
Typ
See note 8
VLVD295
3
Unit
Min
CC LV external10 supply high voltage
monitoring
VLVD270
2
Conditions
VHVD140
VPOR240
1
Parameter
For VDD_LV levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on the die. For other LVD, the IR
drop is estimated by multiplying the supply current by 0.5 .
VPORUP_LV and VPORUP_HV threshold are untrimmed values before completion of the power-up sequence. All other
LVD/HVD thresholds are provided after trimming.
Assume all of LVDs on LV supplies disabled.
LV internal supply levels are measured on device internal supply grid after internal voltage drop.
LVD is released after tVDRELEASE temporization when upper threshold is crossed, LVD is asserted tVDASSERT after
detection when lower threshold is crossed.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
77
Electrical characteristics
6
This specification is driven by LVD108_C. There are additional LVDs on PLL and Flash VDD_LV supply nets which will
assert at voltage below LVD108_C.
7
LV external supply levels are measured on the die side of the package bond wire after package voltage drop. This is
monitoring external regulator supply voltage and board voltage drop. This does not guarantee device is working down
to minimum threshold. For minimum supply, refer to operating condition table.
8
HVD is released after tVDRELEASE temporization when lower threshold is crossed, HVD is asserted tVDASSERT after
detection when upper threshold is crossed. HVD140 does not cause reset.
9
This supply also needs to be below 5472 mV (untrimmed HVD600 min)
10
The PMC supply also needs to be below 5472 mV (untrimmed HVD600 mV).
11
Untrimmed LVD300_A will be asserted first on power down.
12
Hysteresis is implemented only between the VDD_HV_IO_MAIN High voltage Supplies and the ADC high voltage
supply. When these two supplies are shorted together, the hysteresis is as is shown in Table 37. If the supplies are not
shorted (VDD_IO_MAIN and ADC high voltage supply), then there will be no hysteresis on the high voltage supplies.
13
VDD_HV_FLA supply range is guaranteed by internal regulator.
3.14.5
Power up/down sequencing
Table 38 shows the constraints and relationships for the different power supplies
Table 38. Device supply relation during power-up/power-down sequence
Supply 21
VDD_LV VDD_HV_PMC VDD_HV_IO VDD_HV_FLA VDD_HV_ADV VDD_HV_ADR ALTREFn2 VDDSTBY
VDD_LV
VDD_HV_PMU
Supply 11
VDD_HV_IO
VDD_HV_FLA
2 mA3
VDD_HV_ADV
VDD_HV_ADR
ALTREFn
5 mA
10 mA4
10 mA4
VDDSTBY
1
Red cells: supply1 (row) can exceed supply2 (column), granted that external circuitry ensure current flowing from supply1
is less than absolute maximum rating current value provided.
2 ALTREFn are the alternate references for the ADC that can be used in place of the default reference (V
DD_HV_ADR_*). They
are SARB.ALTREF and SAR2.ALTREF.
3 V
DD_HV_FLA is generated internally in normal mode. Above current constraints is guaranteed.
4 ADC performances is not guaranteed with ALTREFn above V
DD_HV_IO / VDD_HV_ADV
During power-up, all functional terminals are maintained into a known state as described within the following table.
MPC5777M Microcontroller Data Sheet, Rev. 6
78
NXP Semiconductors
Electrical characteristics
Table 39. Functional terminals state during power-up and reset
1
2
3
4
5
6
TERMINAL
TYPE1
POWERUP2
pad state
RESET
pad state
DEFAULT
pad state3
PORST
Strong
pull-down4
Weak pull-down
Weak pull-down
ESR05
Strong
pull-down
Strong pull-down
Weak pull-up
ESR1
High impedance
Weak pull-up
Weak pull-up
—
TESTMODE
Weak pull-down
Weak pull-down6
Weak pull-down6
—
GPIO
Weak pull-up4
Weak pull-up
Weak pull-up
—
ANALOG
High impedance
High impedance
High impedance
—
ERROR0
High impedance
High impedance
High impedance
During functional reset, pad state
can be overridden by FCCU
JCOMP
High impedance
Weak pull-down
Weak pull-down
—
TCK
High impedance
Weak pull-down
Weak pull-down
—
TMS
High impedance
Weak pull-up
Weak pull-up
—
TDI
High impedance
Weak pull-up
Weak pull-up
—
TDO
High impedance
Weak pull-up
High impedance
—
Comments
Power-on reset pad
Functional reset pad.
Refer to pinout information for terminal type
POWERUP state is guaranteed from VDD_HV_IO>1.1 V and maintained until supply cross the power-on reset
threshold: VPORUP_LV for LV supply, VPORUP_HV for high voltage supply.
Before software configuration
Pull-down and pull-up strength are provided as part of Table 13 in Section 3.6.1, I/O input DC characteristics.
Pull-up/Pull-down are activated within 2 µs after internal reset has been asserted. Actual pad transition will depend
on external capacitance.
Unlike ESR0, ESR1 is provided as normal GPIO and implements weak pull-up during power-up.
An internal pull-down is implemented on the TESTMODE pin to prevent the device from entering test mode if the
package TESTMODE pin is not connected. It is recommended to connect the TESTMODE pin to VSS_HV_IO on the
board for maximum robustness, but not required. The value of TESTMODE is latched at the negation of reset and
has no affect afterward. The device will not exit functional reset with the TESTMODE pin asserted during power-up.
The TESTMODE pin can be connected externally directly to ground without any other components.
3.15
Flash memory electrical characteristics
The following sections contain flash memory electrical specifications.
3.15.1
Flash memory program and erase specifications
NOTE
All timing, voltage, and current numbers specified in this section are defined for a single
embedded flash memory within an SoC, and represent average currents for given supplies
and operations.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
79
Electrical characteristics
Table 40 shows the estimated Program/Erase times.
Table 40. Flash memory program and erase specifications (pending characterization)
Factory
Programming3,4
Symbol
Characteristic1
Typ2 Initial Max
Initial Max
Full Temp
Field Update
Typical
End of
Life5
20°C Ta  -40°C TJ -40°C TJ 
30°C
 150°C
150 °C
tdwpgm Doubleword (64 bits) program time
43
100
150
Lifetime Max6
1,000
cycles
55
Units
250,000
cycles
500
µs
tppgm
Page (256 bits) program time
73
200
300
108
500
µs
tqppgn
Quad-page (1024 bits) program time
268
800
1,200
396
2,000
µs
t16kers
16 KB Block erase time
168
290
320
250
1,000
ms
34
45
50
40
1,000
ms
217
360
390
310
1,200
ms
69
100
110
90
1.200
ms
315
490
590
420
1,600
ms
138
180
210
170
1,600
ms
t256kers 256 KB Block erase time
884
1,520
2,030
1,080
4,000
—
ms
t256kpgm 256 KB Block program time
552
720
880
650
4,000
—
ms
t16kpgn 16 KB Block program time
t32kers
32 KB Block erase time
t32kpgm 32 KB Block program time
t64kers
64 KB Block erase time
t64kpgm 64 KB Block program time
1
2
3
4
5
6
Program times are actual hardware programming times and do not include software overhead. Block program times assume
quad-page programming.
Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
Conditions:  150 cycles, nominal voltage.
Plant Programming times provide guidance for timeout limits used in the factory.
Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical
End of Life program and erase values may be used for throughput calculations.
Conditions: -40°C TJ  150°C; full spec voltage.
MPC5777M Microcontroller Data Sheet, Rev. 6
80
NXP Semiconductors
Electrical characteristics
3.15.2
Flash memory FERS program and erase specifications
Table 41. Flash memory FERS program and erase specifications (pending characterization)
Factory Programming with FERS=1 and Vfers
pin is
5V ± 5%2
Characteristic1
Symbol
Typ3
Initial Max
Initial Max
Full Temp
Units
20°CTA30°C4 -40°CTJ150°C4
tdwpgm
Doubleword (64 bits) program time
30
90
135
µs
tppgm
Page (256 bits) program time
43
145
218
µs
tqppgn
Quad-page (1024 bits) program time
134
530
795
µs
t16kers
16 KB erase time
160
782
782
ms
t16kpgn
16 KB program time
18
24
35
ms
t32kers
32 KB erase time
190
782
782
ms
t32kpgm
32 KB program time
36
47
68
ms
t64kers
64 KB erase time
250
782
782
ms
t64kpgm
64 KB program time
72
94
135
ms
t256kers
256 KB erase time
600
1,380
2,070
ms
t256kpgm
256 KB program time
288
374
568
ms
1
Program times are actual hardware programming times and do not include software overhead. Block program times assume
quad-page programming.
2 Conditions: 150 cycles, nominal voltage.
3 Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
4 Plant Programming times provide guidance for timeout limits used in the factory.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
81
Electrical characteristics
3.15.3
Flash memory Array Integrity and Margin Read specifications
Table 42. Flash memory Array Integrity and Margin Read specifications (characterized but not tested)
Symbol
Characteristic
Min
Typical
Max1
Units2
tai16kseq
Array Integrity time for sequential sequence on 16KB block.
—
—
512 ×
Tperiod ×
Nread
—
tai32kseq
Array Integrity time for sequential sequence on 32KB block.
—
—
1024 ×
Tperiod ×
Nread
—
tai64kseq
Array Integrity time for sequential sequence on 64KB block.
—
—
2048 ×
Tperiod ×
Nread
—
tai256kseq Array Integrity time for sequential sequence on 256KB block.
—
—
8192 ×
Tperiod ×
Nread
—
taifullseq
Array Integrity time for sequential sequence full array.
—
—
3.77e5 ×
Tperiod ×
Nread
—
taifullprop
Array Integrity time for proprietary sequence (applies to full
array or single block).
—
—
9.96e6 ×
Tperiod ×
Nread
—
tmr16kseq Margin Read time for sequential sequence on 16KB block.
73.81
—
110.7
µs
tmr32kseq Margin Read time for sequential sequence on 32KB block.
128.43
—
192.6
µs
tmr64kseq Margin Read time for sequential sequence on 64KB block.
237.65
—
356.5
µs
tmr256kseq Margin Read time for sequential sequence on 256KB block.
893.01
—
1,339.5
µs
45.21
—
60.26
ms
tmrfull
Margin Read time for sequential sequence full array.
1
Array Integrity times need to be calculated and are dependent on system frequency and number of clocks per read.
The equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal
5e-9) and Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup
that requires 6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read,
and has the address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2
The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
MPC5777M Microcontroller Data Sheet, Rev. 6
82
NXP Semiconductors
Electrical characteristics
3.15.4
Flash memory module life specifications
Table 43. Flash memory module life spec (pending characterization)
Symbol
Array P/E
cycles
Data
retention
1
2
Characteristic
Conditions
Min
Typical
Units
Number of program/erase cycles per
block for 16 KB, 32 KB and 64 KB
blocks.1
—
250,000
—
P/E
cycles
Number of program/erase cycles per
block for 256 KB blocks.2
—
1,000
250,000
P/E
cycles
Blocks with 0 – 1,000 P/E
cycles.
50
—
Years
Blocks with 100,000 P/E
cycles.
20
—
Years
Blocks with 250,000 P/E
cycles.
10
—
Years
Minimum data retention.
Program and erase supported across standard temperature specs.
Program and erase supported across standard temperature specs.
3.15.5
Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window
represents qualified limits. The extrapolated dotted line demonstrates technology capability, however is beyond the
qualification limits.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
83
Electrical characteristics
3.15.6
Flash memory AC timing specifications
Table 44. Flash memory AC timing specifications (characterized but not tested)
Symbol
Characteristic
Min
Typical
Max
Units
tpsus
Time from setting the MCR-PSUS bit until MCR-DONE bit
is set to a 1.
—
7 plus four
system
clock
periods
9.1 plus
four
system
clock
periods
µs
tesus
Time from setting the MCR-ESUS bit until MCR-DONE bit
is set to a 1.
—
16 plus
four
system
clock
periods
20.8 plus
four
system
clock
periods
µs
tres
Time from clearing the MCR-ESUS or PSUS bit with
EHV = 1 until DONE goes low.
—
—
100
ns
tdone
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared.
—
—
5
ns
tdones
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1.
—
16 plus
four
system
clock
periods
20.8 plus
four
system
clock
periods
µs
16 plus
seven
system
clock
periods
—
45 plus
seven
system
clock
periods
µs
tdrcv
Time to recover once exiting low power mode.
taistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin
Read or Array Integrity until the UT0-AID bit is cleared.
This time also applies to the resuming from a suspend or
breakpoint by clearing AISUS or clearing NAIBP
—
—
5
ns
taistop
Time from 1 to 0 transition of UTO-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also
applies to the UT0-AISUS to UT0-AID setting in the event
of a Array Integrity suspend request.
—
—
80
plus fifteen
system
clock
periods
ns
tmrstop
Time from 1 to 0 transition of UTO-AIE initiating a Margin
10.36
Read abort until the UT0-AID bit is set. This time also
plus four
applies to the UT0-AISUS to UT0-AID setting in the event system
of a Margin Read suspend request.
clock
periods
—
20.42
plus four
system
clock
periods
µs
3.15.7
Flash read wait state and address pipeline control settings
Table 45 describes the recommended RWSC and APC settings at various operating frequencies based on specified intrinsic
flash access times of the C55FMC array at 150 °C.
MPC5777M Microcontroller Data Sheet, Rev. 6
84
NXP Semiconductors
Electrical characteristics
Table 45. Flash Read Wait State and Address Pipeline Control Combinations
3.16
Flash Frequency
RWSC setting
APC setting
0 MHz < fFLASH  33 MHz
0
0
33 MHz < fFLASH  100 MHz
2
1
100 MHz < fFLASH  133 MHz
3
1
133 MHz < fFLASH  167 MHz
4
1
167 MHz < fFLASH  200 MHz
5
2
AC specifications
All AC timing specifications are valid up to 150 °C, except where explicitly noted.
3.16.1
Debug and calibration interface timing
3.16.1.1
JTAG interface timing
Table 46. JTAG pin AC electrical characteristics1,2
Value
#
Symbol
Characteristic
Unit
Min
Max
1
tJCYC
CC TCK cycle time
100
—
ns
2
tJDC
CC TCK clock pulse width
40
60
%
3
tTCKRISE
CC TCK rise and fall times (40%–70%)
—
3
ns
4
tTMSS, tTDIS
CC TMS, TDI data setup time
5
—
ns
5
tTMSH, tTDIH
CC TMS, TDI data hold time
5
—
ns
ns
6
tTDOV
CC TCK low to TDO data valid
—
163
7
tTDOI
CC TCK low to TDO data invalid
0
—
ns
8
tTDOHZ
CC TCK low to TDO high impedance
—
15
ns
9
tJCMPPW
CC JCOMP assertion time
100
—
ns
10
tJCMPS
CC JCOMP setup time to TCK low
40
—
ns
ns
11
tBSDV
CC TCK falling edge to output valid
—
6004
12
tBSDVZ
CC TCK falling edge to output valid out of high impedance
—
600
ns
13
tBSDHZ
CC TCK falling edge to output high impedance
—
600
ns
14
tBSDST
CC Boundary scan input valid to TCK rising edge
15
—
ns
15
tBSDHT
CC TCK rising edge to boundary scan input invalid
15
—
ns
1
These specifications apply to JTAG boundary scan only. See Table 47 for functional specifications.
JTAG timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in the
I/O section of the data sheet.
3 Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
85
Electrical characteristics
4
Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG
delay.
TCK
2
3
2
1
3
Figure 22. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
7
8
TDO
Figure 23. JTAG test access port timing
MPC5777M Microcontroller Data Sheet, Rev. 6
86
NXP Semiconductors
Electrical characteristics
TCK
10
JCOMP
9
Figure 24. JTAG JCOMP timing
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
87
Electrical characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 25. JTAG boundary scan timing
3.16.1.2
Nexus interface timing
Table 47. Nexus debug port timing1
Value
#
Symbol
Characteristic
Unit
Min
Max
7
tEVTIPW CC EVTI pulse width
4
—
tCYC2
8
tEVTOPW CC EVTO pulse width
40
—
ns
9
tTCYC
CC TCK cycle time
23,4
—
tCYC2
9
tTCYC
CC Absolute minimum TCK cycle time5 (TDO/TDOC sampled on posedge of
TCK)
406
—
ns
Absolute minimum TCK cycle time7 (TDO/TDOC sampled on negedge of
TCK)
206
—
5
—
118
tNTDIS
CC TDI/TDIC data setup time
ns
MPC5777M Microcontroller Data Sheet, Rev. 6
88
NXP Semiconductors
Electrical characteristics
Table 47. Nexus debug port timing1 (continued)
Value
#
Symbol
12
9
tNTDIH
Characteristic
CC TDI/TDIC data hold time
13
tNTMSS CC TMS/TMSC data setup time
14
tNTMSH CC TMS/TMSC data hold time
15
10
16
Unit
11
—
CC TDO/TDOC propagation delay from falling edge of TCK
—
CC TDO/TDOC hold time with respect to TCK falling edge (minimum
TDO/TDOC propagation delay)
Min
Max
5
—
ns
5
—
ns
5
—
ns
—
16
ns
2.25
—
ns
1
Nexus timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in the
I/O section of the data sheet.
2
tCYC is system clock period.
3 Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is
less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral
frequency being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided
by a number greater than or equal to that specified here.
4 This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the
Absolute minimum TCK period specification.
5 This value is TDO/TDOC propagation time 36ns + 4 ns setup time to sampling edge.
6 This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability
of the design (system frequency / 4) depending on the actual system frequency being used.
7 This value is TDO/TDOC propagation time 16ns + 4 ns setup time to sampling edge.
8 TDIC represents the TDI bit frame of the scan packet in compact JTAG 2-wire mode.
9 TMSC represents the TMS bit frame of the scan packet in compact JTAG 2-wire mode.
10 TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode.
11 Timing includes TCK pad delay, clock tree delay, logic delay and TDO/TDOC output pad delay.
TCK
EVTI
EVTO
9
Figure 26. Nexus event trigger and test clock timings
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
89
Electrical characteristics
TCK
11
13
12
14
TMS/TMSC,
TDI/TDIC
15
16
TDO/TDOC
Figure 27. Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing
3.16.1.3
Aurora LVDS interface timing
Table 48. Aurora LVDS interface timing specifications
Value
Symbol
Parameter
Unit
Min
Typ
Max
—
—
1250
Mbps
—
—
5
µs
—
—
5
µs
—
—
4
µs
Data Rate
—
SR Data rate
STARTUP
tSTRT_BIAS
tSTRT_TX
tSTRT_RX
CC Bias startup time1
CC Transmitter startup time2
3
CC Receiver startup time
1
Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.
2
Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality
is guaranteed only after the startup time.
MPC5777M Microcontroller Data Sheet, Rev. 6
90
NXP Semiconductors
Electrical characteristics
3
Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality
is guaranteed only after the startup time.
3.16.1.4
Aurora debug port timing
Table 49. Aurora debug port timing
Value
#
Characteristic
Unit
Max
625
1250
MHz
tREFCLK
1a
tMCYC
CC Reference clock rise/fall time
—
400
ps
2
tRCDC
CC Reference clock duty cycle
45
55
%
3
JRC
CC Reference clock jitter
—
40
ps
4
tSTABILITY
CC Reference clock stability
50
—
PPM
5
BER
6
CC Reference clock frequency
Min
1
–12
—
CC Bit error rate
—
10
JD
SR Transmit lane deterministic jitter
—
0.17
OUI
7
JT
SR Transmit lane total jitter
—
0.35
OUI
8
SO
CC Differential output skew
—
20
ps
9
SMO
CC Lane to lane output skew
—
1000
ps
OUI
1
625 Mbps
1600
1600
ps
1.25 Gbps
800
800
10
1
Symbol
CC Aurora lane unit interval
± 100 PPM
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
91
Electrical characteristics
1
2
2
CLOCKREF Zero Crossover
CLOCKREF +
1a
1a
1a
8
8
1a
8
Tx Data Ideal Zero Crossover
Tx Data +
Tx Data [n]
Zero Crossover
Tx Data [n+1]
Zero Crossover
Tx Data [m]
Zero Crossover
9
9
Figure 28. Aurora timings
MPC5777M Microcontroller Data Sheet, Rev. 6
92
NXP Semiconductors
Electrical characteristics
DSPI timing with CMOS and LVDS1 pads
3.16.2
DSPI channel frequency support is shown in Table 50. Timing specifications are shown in Table 51, Table 52, Table 54,
Table 55 and Table 56.
Table 50. DSPI channel frequency support
Max usable
frequency (MHz)1,2
DSPI use mode
CMOS (Master mode)
LVDS (Master mode)3
Full duplex – Classic timing (Table 51)
17
Full duplex – Modified timing (Table 52)
30
Output only mode (SCK/SOUT/PCS) (Table 51 and Table 52)
30
Output only mode TSB mode (SCK/SOUT/PCS) (Table 56)
30
Full duplex – Modified timing (Table 54)
33
Output only mode TSB mode (SCK/SOUT/PCS) (Table 55)
40
1
Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.
Maximum usable frequency does not take into account external device propagation delay.
3 µS Channel and LVDS timing is not supported for DSPI12.
2
3.16.2.1
DSPI master mode full duplex timing with CMOS and LVDS pads
3.16.2.1.1
DSPI CMOS Master Mode – Classic Timing
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 11
Value2
Condition
#
1
2
Symbol
tSCK
tCSC
Characteristic
CC SCK cycle time
Unit
Pad drive3
Load (CL)
Min
Max
SCK drive strength
Very strong
25 pF
33.0
—
Strong
50 pF
80.0
—
Medium
50 pF
200.0
—
25 pF
(N4 × tSYS5) – 16
—
Strong
50 pF
(N4
tSYS5)
– 16
—
Medium
50 pF
(N4 × tSYS5) – 16
—
tSYS5)
—
ns
CC PCS to SCK delay SCK and PCS drive strength
Very strong
PCS medium
PCS = 50 pF
and SCK strong SCK = 50 pF
(N4
×
×
– 29
ns
1. DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel bus protocol.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
93
Electrical characteristics
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 11
Value2
Condition
#
3
4
Symbol
tASC
tSDC
Characteristic
CC After SCK delay
CC SCK duty cycle7
Unit
Pad drive3
Load (CL)
Min
Max
SCK and PCS drive strength
Very strong
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
Strong
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
Medium
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
PCS medium
PCS = 0 pF
and SCK strong SCK = 50 pF
(M6 × tSYS5) – 35
—
ns
SCK drive strength
Very strong
Strong
Medium
0 pF
1/
0 pF
1/
0 pF
1/
2tSCK
2tSCK
2tSCK
–2
1/
2tSCK
+2
–2
1/
2tSCK
+2
–5
1/
2tSCK
+5
ns
PCS strobe timing
5
6
tPCSC
tPASC
CC PCSx to PCSS
time8
PCS and PCSS drive strength
CC PCSS to PCSx
time8
PCS and PCSS drive strength
Strong
Strong
25 pF
25 pF
16.0
—
ns
16.0
—
ns
ns
SIN setup time
7
tSUI
CC SIN setup time to
SCK9
SCK drive strength
Very strong
25 pF
25.0
—
Strong
50 pF
32.75
—
Medium
50 pF
52.0
—
–1.0
—
SIN hold time
8
tHI
CC SIN hold time from SCK drive strength
SCK9
Very strong
0 pF
Strong
0 pF
–1.0
—
Medium
0 pF
–1.0
—
ns
SOUT data valid time (after SCK edge)
9
tSUO
CC SOUT data valid
time from SCK10
SOUT and SCK drive strength
Very strong
25 pF
—
7.0
Strong
50 pF
—
8.0
Medium
50 pF
—
16.0
ns
SOUT data hold time (after SCK edge)
MPC5777M Microcontroller Data Sheet, Rev. 6
94
NXP Semiconductors
Electrical characteristics
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 11
Value2
Condition
#
10
Symbol
tHO
Characteristic
CC SOUT data hold
time after SCK10
Pad drive3
Unit
Load (CL)
Min
Max
SOUT and SCK drive strength
Very strong
25 pF
–7.7
—
Strong
50 pF
–11.0
—
Medium
50 pF
–15.0
—
ns
1
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
All timing values for output signals in this table are measured to 50% of the output voltage.
3
Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds
and may cause incorrect operation.
4
N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software
programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless
TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS
and SCK are driven by the same edge of DSPI_CLKn).
5 t
SYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
6 M is the number of clock cycles added to time between SCK negation and PCS negation and is software
programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
7 t
SDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8 PCSx and PCSS using same pad configuration.
9 Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
10 SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
95
Electrical characteristics
tCSC
tASC
PCSx
tSCK
tSDC
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
SIN
tSDC
tSUI
tHI
First Data
Data
Last Data
tSUO
SOUT
tHO
Data
First Data
Last Data
Figure 29. DSPI CMOS master mode – classic timing, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUI
SIN
tHI
First Data
Data
tSUO
SOUT
First Data
Data
Last Data
tHO
Last Data
Figure 30. DSPI CMOS master mode – classic timing, CPHA = 1
MPC5777M Microcontroller Data Sheet, Rev. 6
96
NXP Semiconductors
Electrical characteristics
tPCSC
tPASC
PCSS
PCSx
Figure 31. DSPI PCS strobe (PCSS) timing (master mode)
3.16.2.1.2
DSPI CMOS Master Mode – Modified Timing
Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 11
Value2
Condition
#
1
2
Symbol
tSCK
tCSC
Characteristic
CC SCK cycle time
CC PCS to SCK delay
Pad drive3
4
tSDC
CC After SCK delay
CC SCK duty cycle7
Max
Very strong
25 pF
33.0
—
Strong
50 pF
80.0
—
Medium
50 pF
200.0
—
25 pF
(N4 × tSYS5) – 16
—
50 pF
(N4
×
tSYS5)
– 16
—
Medium
50 pF
(N4
×
tSYS5)
– 16
—
PCS medium
and SCK
strong
PCS = 50 pF
SCK = 50 pF
(N4 × tSYS5) – 29
—
ns
SCK and PCS drive strength
Strong
tASC
Min
SCK drive strength
Very strong
3
Unit
Load (CL)
ns
SCK and PCS drive strength
Very strong
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
Strong
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
Medium
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
PCS medium
and SCK
strong
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
ns
SCK drive strength
Very strong
0 pF
1
Strong
0 pF
1/
0 pF
1/
Medium
/2tSCK – 2
2tSCK
2tSCK
1
/2tSCK + 2
–2
1/
2tSCK
+2
–5
1/
2tSCK
+5
ns
PCS strobe timing
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
97
Electrical characteristics
Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 11
Value2
Condition
#
5
6
Symbol
tPCSC
tPASC
Characteristic
Pad drive3
Unit
Load (CL)
CC PCSx to PCSS
time8
PCS and PCSS drive strength
CC PCSS to PCSx
time8
PCS and PCSS drive strength
Strong
Min
Max
16.0
—
ns
16.0
—
ns
25 – (P10 × tSYS5)
—
ns
25 pF
Strong
25 pF
SIN setup time
7
tSUI
CC SIN setup time to
SCK
CPHA = 09
SIN setup time to
SCK
CPHA = 19
SCK drive strength
Very strong
25 pF
10
Strong
50 pF
32.75 – (P
5
S )
× tSY
—
Medium
50 pF
52 – (P10 × tSYS5)
—
SCK drive strength
Very strong
25 pF
25.0
—
Strong
50 pF
32.75
—
Medium
50 pF
52.0
—
ns
SIN hold time
8
tHI
CC SIN hold time from SCK drive strength
SCK
Very strong
0 pF
CPHA = 09
Strong
0 pF
Medium
0 pF
–1 + (P9 × tSYS4)
—
×
tSYS4)
—
×
tSYS4)
—
–1 +
(P9
–1 +
(P9
SIN hold time from SCK drive strength
SCK
Very strong
0 pF
CPHA = 19
Strong
0 pF
Medium
0 pF
–1.0
—
–1.0
—
–1.0
—
—
7.0 + tSYS5
tSYS5
ns
ns
SOUT data valid time (after SCK edge)
9
tSUO
CC SOUT data valid
time from SCK
CPHA = 010
SOUT data valid
time from SCK
CPHA = 110
SOUT and SCK drive strength
Very strong
25 pF
Strong
50 pF
—
8.0 +
Medium
50 pF
—
16.0 + tSYS5
ns
SOUT and SCK drive strength
Very strong
25 pF
—
7.0
Strong
50 pF
—
8.0
Medium
50 pF
—
16.0
ns
SOUT data hold time (after SCK edge)
MPC5777M Microcontroller Data Sheet, Rev. 6
98
NXP Semiconductors
Electrical characteristics
Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 11
Value2
Condition
#
10
Symbol
tHO
Characteristic
CC SOUT data hold
time after SCK
CPHA = 011
Pad drive3
Min
Max
SOUT and SCK drive strength
Very strong
25 pF
–7.7 + tSYS5
—
Strong
50 pF
–11.0 + tSYS5
—
50 pF
tSYS5
—
Medium
SOUT data hold
time after SCK
CPHA = 111
Unit
Load (CL)
–15.0 +
ns
SOUT and SCK drive strength
Very strong
25 pF
–7.7
—
Strong
50 pF
–11.0
—
Medium
50 pF
–15.0
—
ns
1
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
All timing values for output signals in this table are measured to 50% of the output voltage.
3 Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds
and may cause incorrect operation.
4 N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software
programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless
TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS
and SCK are driven by the same edge of DSPI_CLKn).
5 t
SYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
6 M is the number of clock cycles added to time between SCK negation and PCS negation and is software
programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
7 t
SDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8 PCSx and PCSS using same pad configuration.
9 Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
10 P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is
automatically set to 1.
11 SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
99
Electrical characteristics
tCSC
tASC
PCSx
tSCK
tSDC
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
SIN
tSDC
tSUI
tHI
First Data
Data
Last Data
tSUO
SOUT
tHO
Data
First Data
Last Data
Figure 32. DSPI CMOS master mode – modified timing, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUI
SIN
tHI
tHI
Data
First Data
tSUO
SOUT
First Data
Data
Last Data
tHO
Last Data
Figure 33. DSPI CMOS master mode – modified timing, CPHA = 1
MPC5777M Microcontroller Data Sheet, Rev. 6
100
NXP Semiconductors
Electrical characteristics
tPCSC
tPASC
PCSS
PCSx
Figure 34. DSPI PCS strobe (PCSS) timing (master mode)
3.16.2.1.3
DSPI LVDS Master Mode – Modified Timing
Table 53. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or 1
Value1
Condition
#
Symbol
Characteristic
Unit
Pad drive
Load
Min
Max
15 pF
to 25 pF
differential
30.0
—
ns
(N2 × tSYS3) – 10
—
ns
50 pF
(N2
Medium
50 pF
(N2
Very strong
1
tSCK
CC SCK cycle time
LVDS
2
tCSC
CC PCS to SCK delay PCS drive strength
(LVDS SCK)
Very strong
25 pF
×
tSYS3)
– 10
—
ns
×
tSYS3)
– 32
—
ns
PCS = 0 pF
SCK = 25 pF
(M4 × tSYS3) – 8
—
ns
Strong
PCS = 0 pF
SCK = 25 pF
(M4 × tSYS3) – 8
—
ns
Medium
PCS = 0 pF
SCK = 25 pF
(M4 × tSYS3) – 8
—
ns
LVDS
15 pF
to 25 pF
differential
Strong
3
tASC
CC After SCK delay
(LVDS SCK)
4
tSDC
CC SCK duty cycle5
7
tSUI
CC
1/
2tSCK
–2
1/
2tSCK
+2
ns
SIN setup time
SIN setup time to SCK drive strength
SCK
LVDS
15 pF
CPHA = 06
to 25 pF
differential
23 – (P7 × tSYS3)
—
ns
SIN setup time to SCK drive strength
SCK
LVDS
15 pF
CPHA = 16
to 25 pF
differential
23
—
ns
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
101
Electrical characteristics
Table 53. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or 1
Value1
Condition
#
Symbol
Characteristic
Unit
Pad drive
8
tHI
9
tSUO
10
1
2
3
4
5
6
7
tHO
Load
CC
Min
Max
–1 + (P7 × tSYS3)
—
ns
–1
—
ns
—
7.0 + tSYS3
ns
—
7.0
ns
–7.5 + tSYS3
—
ns
–7.5
—
ns
SIN Hold Time
SIN hold time
from SCK
CPHA = 06
SCK drive strength
SIN hold time
from SCK
CPHA = 16
SCK drive strength
LVDS
LVDS
CC
0 pF differential
0 pF differential
SOUT data valid time (after SCK edge)
SOUT data valid
time from SCK
CPHA = 08
SOUT and SCK drive strength
SOUT data valid
time from SCK
CPHA = 18
SOUT and SCK drive strength
LVDS
LVDS
CC
15 pF
to 25 pF
differential
15 pF
to 25 pF
differential
SOUT data hold time (after SCK edge)
SOUT data hold
time after SCK
CPHA = 08
SOUT and SCK drive strength
SOUT data hold
time after SCK
CPHA = 18
SOUT and SCK drive strength
LVDS
LVDS
15 pF
to 25 pF
differential
15 pF
to 25 pF
differential
All timing values for output signals in this table are measured to 50% of the output voltage.
N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software
programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
M is the number of clock cycles added to time between SCK negation and PCS negation and is software
programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
Input timing assumes an input slew rate of 1 ns (10% – 90%) and LVDS differential voltage = ±100 mV.
P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically
set to 1.
MPC5777M Microcontroller Data Sheet, Rev. 6
102
NXP Semiconductors
Electrical characteristics
8
SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
Table 54. DSPI LVDS slave timing – full duplex – modified transfer format (MTFE = 0/1)1
Condition
#
Symbol
Unit
Pad drive
1
2
tSCK
tCSC
Value
Characteristic
CC SCK cycle time2
Load
Min
Max
—
—
—
62
2
—
—
16
—
ns
2
SR SS to SCK delay
ns
3
tASC
SR SCK to SS delay
—
—
16
—
ns
4
tSDC
CC SCK duty cycle2
—
—
30
—
ns
5
tA
CC Slave Access
Time2, 3, 4 (SS
active to SOUT
driven)
Very strong
25 pF
—
50
ns
Strong
50 pF
—
50
ns
Medium
50 pF
—
60
ns
CC Slave SOUT
Very strong
Disable Time 2, 3,
Strong
4(SS inactive to
SOUT High-Z or Medium
invalid)
25 pF
—
5
ns
50 pF
—
5
ns
50 pF
—
10
ns
6
tDIS
7
tSUI
CC Data setup time —
for inputs2
—
10
—
ns
8
tHI
CC Data hold time for —
inputs2
—
10
—
ns
9
tSUO
CC
SOUT Valid
Very strong
Time2, 3, 4 (after
Strong
SCK edge)
Medium
25 pF
—
30
ns
50 pF
—
30
ns
50 pF
—
50
ns
SOUT Hold
Very strong
Time2, 3, 4 (after
Strong
SCK edge)
Medium
25 pF
2.5
—
ns
50 pF
2.5
—
ns
50 pF
2.5
—
ns
10
tHO
CC
1
DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for that
case only.
2 Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.
3 All timing values for output signals in this table, are measured to 50% of the output voltage.
4 All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
103
Electrical characteristics
tCSC
tASC
PCSx
tSCK
tSDC
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
SIN
tSDC
tSUI
tHI
First Data
Data
Last Data
tSUO
SOUT
tHO
Data
First Data
Last Data
Figure 35. DSPI LVDS master mode – modified timing, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUI
SIN
tHI
tHI
Data
First Data
tSUO
SOUT
First Data
Data
Last Data
tHO
Last Data
Figure 36. DSPI LVDS master mode – modified timing, CPHA = 1
MPC5777M Microcontroller Data Sheet, Rev. 6
104
NXP Semiconductors
Electrical characteristics
3.16.2.1.4
DSPI Master Mode – Output Only
Table 55. DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or
1, continuous SCK clock1,2
Condition
#
Symbol
Value
Characteristic
Unit
Pad drive
Load
Min
Max
25.0
—
ns
1
tSCK
CC SCK cycle time
2
tCSV
CC PCS valid after SCK3 Very strong
(SCK with 50 pF
Strong
differential load cap.)
25 pF
—
6.0
ns
50 pF
—
10.5
ns
CC PCS hold after SCK3 Very strong
(SCK with 50 pF
Strong
differential load cap.)
0 pF
–4.0
—
ns
0 pF
–4.0
—
ns
CC SCK duty cycle
LVDS
(SCK with 50 pF
differential load cap.)
15 pF
to 50 pF
differential
3
4
tCSH
tSDC
LVDS
15 pF
to 50 pF
differential
1/
2tSCK
–2
1/ t
2 SCK
+2
ns
SOUT data valid time (after SCK edge)
5
tSUO
CC SOUT data valid time SOUT and SCK drive strength
from SCK4
LVDS
15 pF
to 50 pF
differential
—
3.5
ns
–3.5
—
ns
SOUT data hold time (after SCK edge)
6
tHO
CC SOUT data hold time SOUT and SCK drive strength
after SCK4
LVDS
15 pF
to 50 pF
differential
1
All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS
with pad driver strength as defined. Timing may degrade for weaker output drivers.
2 TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
3
With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of
DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.
4 SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
Table 56. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or
1, continuous SCK clock1,2
Value3
Condition
#
1
Symbol
tSCK
Characteristic
CC SCK cycle time
Unit
Pad drive4
Load (CL)
Min
Max
SCK drive strength
Very strong
25 pF
33.0
—
ns
Strong
50 pF
80.0
—
ns
Medium
50 pF
200.0
—
ns
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
105
Electrical characteristics
Table 56. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or
1, continuous SCK clock1,2 (continued)
Value3
Condition
#
2
Symbol
tCSV
Characteristic
CC PCS valid after SCK5
Unit
Pad drive4
Load (CL)
4
tCSH
tSDC
CC PCS hold after SCK5
CC SCK duty cycle6
Max
SCK and PCS drive strength
Very strong
25 pF
7
—
ns
Strong
50 pF
8
—
ns
Medium
50 pF
16
—
ns
29
—
ns
PCS medium
PCS = 50 pF
and SCK strong SCK = 50 pF
3
Min
SCK and PCS drive strength
Very strong
PCS = 0 pF
SCK = 50 pF
–14
—
ns
Strong
PCS = 0 pF
SCK = 50 pF
–14
—
ns
Medium
PCS = 0 pF
SCK = 50 pF
–33
—
ns
PCS medium
PCS = 0 pF
and SCK strong SCK = 50 pF
–35
—
ns
SCK drive strength
Very strong
Strong
Medium
0 pF
1/ t
2 SCK
0 pF
1/ t
2 SCK
0 pF
1/ t
2 SCK
–2
1/
2tSCK
+2
ns
–2
1/
2tSCK
+2
ns
–5
1/
2tSCK
+5
ns
SOUT data valid time (after SCK edge)
9
tSUO
CC SOUT data valid time from
SCK
CPHA = 17
SOUT and SCK drive strength
Very strong
25 pF
—
7.0
ns
Strong
50 pF
—
8.0
ns
Medium
50 pF
—
16.0
ns
SOUT data hold time (after SCK edge)
10
tHO
CC SOUT data hold time after
SCK
CPHA = 17
SOUT and SCK drive strength
Very strong
25 pF
–7.7
—
ns
Strong
50 pF
–11.0
—
ns
Medium
50 pF
–15.0
—
ns
1
TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
3 All timing values for output signals in this table are measured to 50% of the output voltage.
4
Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds
and may cause incorrect operation.
5
With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of
DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
106
NXP Semiconductors
Electrical characteristics
6
tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
7
SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
PCSx
tCSV
tSCK
tSDC
tCSH
SCK Output
(CPOL = 0)
tSUO
First Data
SOUT
tHO
Last Data
Data
Figure 37. DSPI LVDS and CMOS master timing – output only – modified transfer format MTFE = 1, CHPA = 1
3.16.2.2
Slave Mode timing
Table 57. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)1
Condition
#
Symbol
Characteristic
Pad Drive
Load
Min
Max
Unit
1
tSCK
CC
SCK Cycle Time2
-
-
62
—
ns
2
tCSC
SR
SS to SCK Delay2
-
-
16
—
ns
SR
SCK to SS
Delay2
-
-
16
—
ns
SCK Duty
Cycle2
-
-
30
—
ns
Very
Strong
25 pF
—
50
ns
Strong
50 pF
—
50
ns
Medium
50 pF
—
60
ns
Very
Strong
25 pF
—
5
ns
Strong
50 pF
—
5
ns
3
4
5
6
tASC
tSDC
tA
tDIS
CC
CC
CC
Time2,3,4
Slave Access
(SS active to SOUT driven)
Slave SOUT Disable
Time2,3,4
(SS inactive to SOUT High-Z
or invalid)
Medium
50 pF
—
10
ns
Inputs2
—
—
10
—
ns
—
—
10
—
ns
9
tSUI
CC Data Setup Time for
10
tHI
CC Data Hold Time for Inputs2
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
107
Electrical characteristics
Table 57. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)1
Condition
#
11
12
Symbol
tSUO
tHO
Characteristic
CC
CC
Min
Max
Unit
25 pF
—
30
ns
Strong
50 pF
—
30
ns
Medium
50 pF
—
50
ns
Very
Strong
25 pF
2.5
—
ns
Strong
50 pF
2.5
—
ns
Medium
50 pF
2.5
—
ns
Pad Drive
Load
Very
Strong
SOUT Valid Time2,3,4
(after SCK edge)
SOUT Hold Time2,3,4
(after SCK edge)
1
DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for
that case only.
2 Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.
3 All timing values for output signals in this table, are measured to 50% of the output voltage.
4 All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
tASC
tCSC
SS
tSCK
SCK Input
(CPOL=0)
tSDC
tSDC
SCK Input
(CPOL=1)
tSUO
tA
SOUT
First Data
Data
tSUI
SIN
First Data
tHO
tDIS
Last Data
tHI
Data
Last Data
Figure 38. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 0
MPC5777M Microcontroller Data Sheet, Rev. 6
108
NXP Semiconductors
Electrical characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
tSUO
tA
SOUT
First Data
tSUI
SIN
tDIS
tHO
Data
Last Data
Data
Last Data
tHI
First Data
Figure 39. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 1
3.16.3
FEC timing
The FEC provides both MII and RMII interfaces in the 416 TEPBGA and 512 TEPBGA packages, and the MII and RMII
signals can be configured for either CMOS or TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
3.16.3.1
MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency.
Table 58. MII receive signal timing1
Value
Symbol
1
Characteristic
Unit
Min
Max
M1
CC RXD[3:0], RX_DV, RX_ER to RX_CLK setup
5
—
ns
M2
CC RX_CLK to RXD[3:0], RX_DV, RX_ER hold
5
—
ns
M3
CC RX_CLK pulse width high
35%
65%
RX_CLK period
M4
CC RX_CLK pulse width low
35%
65%
RX_CLK period
All timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
109
Electrical characteristics
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
M2
Figure 40. MII receive signal timing diagram
3.16.3.2
MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the MPC5777M Microcontroller Reference Manual’s Fast Ethernet Controller (FEC) chapter for details of this option
and how to enable it.
Table 59. MII transmit signal timing1
Value2
Symbol
1
2
Characteristic
Unit
Min
Max
M5
CC TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
5
—
ns
M6
CC TX_CLK to TXD[3:0], TX_EN, TX_ER valid
—
25
ns
M7
CC TX_CLK pulse width high
35%
65%
TX_CLK period
M8
CC TX_CLK pulse width low
35%
65%
TX_CLK period
All timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.
Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
MPC5777M Microcontroller Data Sheet, Rev. 6
110
NXP Semiconductors
Electrical characteristics
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
Figure 41. MII transmit signal timing diagram
3.16.3.3
MII async inputs signal timing (CRS and COL)
Table 60. MII async inputs signal timing
Value
Symbol
Characteristic
M9
Unit
CC CRS, COL minimum pulse width
Min
Max
1.5
—
TX_CLK period
CRS, COL
M9
Figure 42. MII async inputs timing diagram
3.16.3.4
MII and RMII serial management channel timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 61. MII serial management channel timing1
Value2
Symbol
1
Unit
Characteristic
Min
Max
M10
CC MDC falling edge to MDIO output invalid (minimum
propagation delay)
0
—
ns
M11
CC MDC falling edge to MDIO output valid (max prop
delay)
—
25
ns
M12
CC MDIO (input) to MDC rising edge setup
10
—
ns
M13
CC MDIO (input) to MDC rising edge hold
0
—
ns
M14
CC MDC pulse width high
40%
60%
MDC period
M15
CC MDC pulse width low
40%
60%
MDC period
All timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and
2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
111
Electrical characteristics
2
Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
M14
M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
Figure 43. MII serial management channel timing diagram
3.16.3.5
RMII receive signal timing (RXD[1:0], CRS_DV)
The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of
the REF_CLK frequency.
Table 62. RMII receive signal timing1
Value
Symbol
1
Characteristic
Unit
Min
Max
R1
CC RXD[1:0], CRS_DV to REF_CLK setup
4
—
ns
R2
CC REF_CLK to RXD[1:0], CRS_DV hold
2
—
ns
R3
CC REF_CLK pulse width high
35%
65%
REF_CLK period
R4
CC REF_CLK pulse width low
35%
65%
REF_CLK period
All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.
MPC5777M Microcontroller Data Sheet, Rev. 6
112
NXP Semiconductors
Electrical characteristics
R3
REF_CLK (input)
R4
RXD[1:0] (inputs)
CRS_DV
R2
R1
Figure 44. RMII receive signal timing diagram
3.16.3.6
RMII transmit signal timing (TXD[1:0], TX_EN)
The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of
the REF_CLK frequency.
The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK,
and the timing is the same in either case. These options allows the use of non-compliant RMII PHYs.
Table 63. RMII transmit signal timing1, 2
Value3
Symbol
Unit
Characteristic
Min
Max
R5
CC REF_CLK to TXD[1:0], TX_EN invalid
2
—
ns
R6
CC REF_CLK to TXD[1:0], TX_EN valid
—
16
ns
R7
CC REF_CLK pulse width high
35%
65%
REF_CLK period
R8
CC REF_CLK pulse width low
35%
65%
REF_CLK period
1
RMII timing is valid only up to a maximum of 150 oC junction temperature.
All timing specifications are referenced for TTL or CMOS input levels for REF_CLK to the valid output levels, 0.8 V
and 2.0 V.
3
Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
2
R7
REF_CLK (input)
R5
R8
TXD[1:0] (outputs)
TX_EN
R6
Figure 45. RMII transmit signal timing diagram
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
113
Electrical characteristics
3.16.4
FlexRay timing
This section provides the FlexRay Interface timing characteristics for the input and output signals.
These are recommended numbers as per the FlexRay EPL v3.0 specification.
3.16.4.1
TxEN
TxEN
80 %
20 %
dCCTxENFALL
dCCTxENRISE
Figure 46. TxEN signal
Table 64. TxEN output characteristics1
Value
Symbol
Characteristic
Unit
Min
Max
dCCTxENRISE25 CC Rise time of TxEN signal at CC
—
9
ns
dCCTxENFALL25 CC Fall time of TxEN signal at CC
—
9
ns
1
dCCTxEN01
CC Sum of delay between Clk to Q of the last FF and the final output buffer,
rising edge
—
25
ns
dCCTxEN10
CC Sum of delay between Clk to Q of the last FF and the final output buffer,
falling edge
—
25
ns
TxEN pin load maximum 25 pF
MPC5777M Microcontroller Data Sheet, Rev. 6
114
NXP Semiconductors
Electrical characteristics
PE_Clk
TxEN
dCCTxEN10
dCCTxEN01
Figure 47. TxEN signal propagation delays
3.16.4.2
TxD
TxD
dCCTxD50%
80 %
50 %
20 %
dCCTxDRISE
dCCTxDFALL
Figure 48. TxD signal
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
115
Electrical characteristics
Table 65. TxD output characteristics1,2
Value
Symbol
dCCTxAsym
Characteristic
Unit
CC Asymmetry of sending CC at 25 pF load
(= dCCTxD50%  100 ns)
dCCTxDRISE25+dCCTxDFALL25 CC Sum of Rise and Fall time of TxD signal at the output
pin3,4
1
2
3
4
5
6
Min
Max
–2.45
2.45
ns
—
95
ns
—
96
dCCTxD01
CC Sum of delay between Clk to Q of the last FF and the
final output buffer, rising edge
—
25
ns
dCCTxD10
CC Sum of delay between Clk to Q of the last FF and the
final output buffer, falling edge
—
25
ns
TxD pin load maximum 25 pF
Specifications valid according to FlexRay EPL 3.0.1 standard with 20%–80% levels and a 10pF load at the end of a
50 Ohm, 1 ns stripline. Please refer to the Very Strong I/O pad specifications.
Pad configured as VERY STRONG
Sum of transition time simulation is performed according to Electrical Physical Layer Specification 3.0.1 and the entire
temperature range of the device has been taken into account.
VDD_HV_IO = 5.0 V ± 10%, Transmission line Z = 50 ohms, tdelay = 1 ns, CL = 10 pF
VDD_HV_IO = 3.3 V ± 10%, Transmission line Z = 50 ohms, tdelay = 0.6 ns, CL = 10 pF
PE_Clk*
TxD
dCCTxD10
dCCTxD01
* FlexRay Protocol Engine Clock
Figure 49. TxD Signal propagation delays
MPC5777M Microcontroller Data Sheet, Rev. 6
116
NXP Semiconductors
Electrical characteristics
3.16.4.3
RxD
Table 66. RxD input characteristics1
Value
Symbol
Unit
Min
Max
CC Input capacitance on RxD pin
—
7
pF
uCCLogic_1
CC Threshold for detecting logic high
35
70
%
uCCLogic_0
CC Threshold for detecting logic low
30
65
%
dCCRxD01
CC Sum of delay from actual input to the D input of the first
FF, rising edge
—
10
ns
dCCRxD10
CC Sum of delay from actual input to the D input of the first
FF, falling edge
—
10
ns
dCCRxAsymAccept15
CC Acceptance of asymmetry at receiving CC with 15 pF
load
–31.5
44
ns
dCCRxAsymAccept25
CC Acceptance of asymmetry at receiving CC with 25 pF
load
–30.5
43
ns
C_CCRxD
1
Characteristic
FlexRay RxD timing is valid for Automotive input levels with hysteresis enabled (hysteresis permanently enabled in
Automotive input levels) and CMOS input levels with hysteresis disabled, 4.5 V  VDD_HV_IO  5.5 V for both cases.
3.16.5
PSI5 timing
The following table describes the PSI5 timing.
Table 67. PSI5 timing
Value
Symbol
1
Parameter
Unit
Min
Max
tMSG_DLY
CC Delay from last bit of frame (CRC0) to assertion
of new message received interrupt
—
3
µs
tSYNC_DLY
CC Delay from internal sync pulse to sync pulse
trigger at the SDOUT_PSI5_n pin
—
2
µs
tMSG_JIT
CC Delay jitter from last bit of frame (CRC0) to
assertion of new message received interrupt
—
1
cycles1
tSYNC_JIT
CC Delay jitter from internal sync pulse to sync pulse
trigger at the SDOUT_PSI5_n pin
—
±(1 PSI5_1µs_CLK +
1 PBRIDGEn_CLK)
cycles
Measured in PSI5 clock cycles (PBRIDGEn_CLK on the device). Minimum PSI5 clock period is 20 ns.
3.16.6
UART timing
UART channel frequency support is shown in the following table.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
117
Electrical characteristics
Table 68. UART frequency support
LINFlexD clock frequency
LIN_CLK (MHz)
Oversampling rate
80
16
Max usable frequency
(Mbaud)
Voting scheme
3:1 majority voting
5
8
6
5
10
Limited voting on one
sample with configurable
sampling point
4
100
16
5
3:1 majority voting
6.25
12.5
Limited voting on one
sample with configurable
sampling point
4
3.16.7
16
20
8
6
13.33
16.67
20
25
External Bus Interface (EBI) Timing
Table 69. Bus Operation Timing1
66.7 MHz (Ext. Bus Freq)2 3
Spec
Characteristic
Symbol
Unit
Min
1
CLKOUT Period4
2
CLKOUT Duty Cycle
Max
tC
15.15
—
ns
tCDC
45%
55%
tC
ns
3
CLKOUT Rise Time
tCRT
—
—5
4
CLKOUT Fall Time
tCFT
—
—5
ns
5
CLKOUT Posedge to Output Signal Invalid or High Z
(Hold Time)6
tCOH
1.0
—
ns
tCOV
—
8.0
ns
ADDR[12:31]
ADDR[8:11]/WE[0:3]/BE[0:3]
BDIP
CS[0:3]
DATA[0:31]
OE
RD_WR
TS
6
CLKOUT Posedge to Output Signal Valid (Output
Delay)7,8
ADDR[12:31]
ADDR[8:11]/WE[0:3]/BE[0:3]
BDIP
CS[0:3]
DATA[0:31]
OE
RD_WR
TS
MPC5777M Microcontroller Data Sheet, Rev. 6
118
NXP Semiconductors
Electrical characteristics
Table 69. Bus Operation Timing1 (continued)
66.7 MHz (Ext. Bus Freq)2 3
Spec
7
Characteristic
Input Signal Valid to CLKOUT Posedge (Setup Time)
Symbol
Unit
Min
Max
tCIS
7.0
—
ns
tCIH
1.0
—
ns
DATA[0:31]
8
CLKOUT Posedge to Input Signal Invalid (Hold Time)
DATA[0:31]
1
2
3
4
5
6
7
8
EBI timing specified at VDD_HV_IO_EBI and VDD_HV_IO_FLEXE = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with
DSC = 0b10 for ADDR/CTRL and DSC = 0b11 for CLKOUT/DATA.
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including PLL jitter.
Depending on the internal bus speed, set the CGM_SC_DC4 register bits correctly not to exceed maximum
external bus frequency. The maximum external bus frequency is 66.7 MHz.
Signals are measured at 50% VDD_HV_IO_EBI or VDD_HV_IO_FLEXE.
Refer to Fast pad timing in Table 18.
CLKOUT may be required at the highest drive strength in order to meet the hold time specification.
One wait state must be added for all write accesses to external memories at the maximum external bus frequency.
One wait state must be added to the outut signal valid delay for external writes.
VOH_F
VDD_HV_IO_EBI / 2
D_CLKOUT
VOL_F
3
2
2
4
1
Figure 50. D_CLKOUT Timing
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
119
Electrical characteristics
D_CLKOUT
VDD_HV_IO_EBI / 2
6
5
5
Output
Bus
VDD_HV_IO_EBI / 2
6
5
5
Output
Signal
VDD_HV_IO_EBI / 2
6
Output
Signal
VDD_HV_IO_EBI / 2
Figure 51. Synchronous Output Timing
MPC5777M Microcontroller Data Sheet, Rev. 6
120
NXP Semiconductors
Electrical characteristics
D_CLKOUT
VDD_HV_IO_EBI / 2
7
8
VDD_HV_IO_EBI / 2
Input
Bus
7
8
Input
Signal
VDD_HV_IO_EBI / 2
Figure 52. Synchronous Input Timing
3.16.8
I2C timing
The I2C AC timing specifications are provided in the following tables.
Table 70. I2C input timing specifications — SCL and SDA1
Value
No.
Symbol
Parameter
Unit
Min
Max
1
—
CC Start condition hold time
2
—
PER_CLK Cycle2
2
—
CC Clock low time
8
—
PER_CLK Cycle
3
—
CC Bus free time between Start and Stop condition
4.7
—
µs
4
—
CC Data hold time
0.0
—
ns
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
121
Electrical characteristics
Table 70. I2C input timing specifications — SCL and SDA1 (continued)
Value
No.
1
Symbol
Parameter
Unit
Min
Max
5
—
CC Clock high time
4
—
PER_CLK Cycle
6
—
CC Data setup time
0.0
—
ns
7
—
CC Start condition setup time (for repeated start condition only)
2
—
PER_CLK Cycle
8
—
CC Stop condition setup time
2
—
PER_CLK Cycle
2
I C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower
than 1 ns (10% – 90%).
2
PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in
the device reference manual for more detail.
Table 71. I2C output timing specifications — SCL and SDA1,2 ,3,4
Value
No.
Symbol
Parameter
Unit
Min
Max
1
—
CC Start condition hold time
6
—
PER_CLK Cycle5
2
—
CC Clock low time
10
—
PER_CLK Cycle
3
—
CC Bus free time between Start and Stop condition
4.7
—
µs
4
—
CC Data hold time
7
—
PER_CLK Cycle
5
—
CC Clock high time
10
—
PER_CLK Cycle
6
—
CC Data setup time
2
—
PER_CLK Cycle
7
—
CC Start condition setup time (for repeated start condition only)
20
—
PER_CLK Cycle
8
—
CC Stop condition setup time
10
—
PER_CLK Cycle
1
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
3 Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and
may cause incorrect operation.
4 Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum
output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL
low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD
register.
5 PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter
in the device reference manual for more detail.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
122
NXP Semiconductors
Electrical characteristics
2
5
SCL
4
1
8
6
3
7
SDA
Figure 53. I2C input/output timing
3.16.9
GPIO delay timing
The GPIO delay timing specification is provided in the following table.
Table 72. GPIO delay timing
Value
Symbol
IO_delay
Parameter
CC
Unit
Delay from SIUL2 MSCR register bit update to pad function
enable at the input of the I/O pad
Min
Max
5
25
ns
3.16.10 Package characteristics
The following table lists the case numbers for each available package for the device.
Table 73. Package case numbers
Package Type
Device Type
Case Outline Number
416TEPBGA
Production
98ARE10523D
416TEPBGA
Emulation
98ASA00493D
512TEPBGA
Production or Emulation
98ASA00262D
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
123
Electrical characteristics
3.17
416 TEPBGA (production) case drawing
Figure 54. 416 TEPBGA (production) package mechanical drawing (Sheet 1 of 2)
MPC5777M Microcontroller Data Sheet, Rev. 6
124
NXP Semiconductors
Electrical characteristics
Figure 55. 416 TEPBGA (production) package mechanical drawing (Sheet 2 of 2)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
125
Electrical characteristics
3.18
416 TEPBGA (emulation) case drawing
Figure 56. 416 TEPBGA (emulation) package mechanical drawing (Sheet 1 of 3)
MPC5777M Microcontroller Data Sheet, Rev. 6
126
NXP Semiconductors
Electrical characteristics
Figure 57. 416 TEPBGA (emulation) package mechanical drawing (Sheet 2 of 3)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
127
Electrical characteristics
Figure 58. 416 TEPBGA (emulation) package mechanical drawing (Sheet 3 of 3)
MPC5777M Microcontroller Data Sheet, Rev. 6
128
NXP Semiconductors
Electrical characteristics
3.19
512 TEPBGA case drawing
2
Figure 59. 512 TEPBGA package mechanical drawing (Sheet 1 of 2)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
129
Electrical characteristics
Figure 60. 512 TEPBGA package mechanical drawing (Sheet 2 of 2)
MPC5777M Microcontroller Data Sheet, Rev. 6
130
NXP Semiconductors
Electrical characteristics
3.20
Thermal characteristics
The following tables describe the thermal characteristics of the device.
.
Table 74. Thermal characteristics
Symbol
RJA
RJMA
1
Parameter
Conditions
416
512
Value Value
Junction-to-Ambient, Natural
Convection
Single Layer board (1s)
25
24.1
Four layer board (2s2p)
17.2
16.8
Junction-to-Moving-Air, Ambient
@200 ft/min., single layer
board (1s)
18.1
16.6
@200 ft/min., four layer board
(2s2p)
13.4
12.4
Unit
Notes
°C/W
1,2
1,2,3
°C/W
1,3
1,3
RJB
Junction-to-board
—
8.6
8.8
°C/W
4
RJC
Junction-to-case
—
5.0
5.0
°C/W
5
JT
Junction-to-package top
Natural convection
0.2
0.2
°C/W
6
JB
Junction-to-package bottom/solder
balls
Natural convection
3.5
3.0
°C/W
7
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance,
mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on
the board, and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
Thermal characterization parameter indicating the temperature difference between package bottom center and
the junction temperature per JEDEC JESD51-12.
2
3
4
5
6
7
3.20.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RJA * PD)
Eqn. 1
where:
TA = ambient temperature for the package (oC)
RJA = junction-to-ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a
four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance
is not a constant. The thermal resistance depends on the:
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
131
Electrical characteristics
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit
board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components are well separated
Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the
ambient temperature varies widely within the application. For many natural convection and especially closed box applications,
the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the
device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RJB * PD)
Eqn. 2
where:
TB = board temperature for the package perimeter (oC)
RJB = junction-to-board thermal resistance (oC/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable
if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal
resistance:
RJA = RJC + RCA
Eqn. 3
where:
RJA = junction-to-ambient thermal resistance (oC/W)
RJC = junction-to-case thermal resistance (oC/W)
RCA = case to ambient thermal resistance (oC/W)
RJC is device related and is not affected by other factors. The thermal environment can be controlled to change the
case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the
mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding
the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat
sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the
junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the
thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple
estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be
generated upon request.
MPC5777M Microcontroller Data Sheet, Rev. 6
132
NXP Semiconductors
Ordering information
To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization
parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using
the following equation:
TJ = TT + (JT x PD)
Eqn. 4
where:
TT = thermocouple temperature on top of the package (oC)
JT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests
on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from
the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling
effects of the thermocouple wire.
When board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter
(JPB) to determine the junction temperature by measuring the temperature at the bottom center of the package case (exposed
pad) using the following equation:
TJ = TB + (JPB x PD)
Eqn. 5
where:
TT = thermocouple temperature on bottom of the package (oC)
JT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
4
Ordering information
Table 75 shows the orderable part numbers for the MPC5777M series.
Table 75. Orderable part number summary
Part Number
Device Type1,2
Package
PPC5777MK0MVU8B
Sample
416 TEPBGA
PPC5777MK0MVA8B
Sample
512 TEPBGA
PPC5777M2K0MVU8B
Sample ED
416 TEPBGA
PPC5777M2K0MVA8B
Sample ED
512 TEPBGA
SPC5777MK0MVU8
Production PD
416 TEPBGA
SPC5777MK0MVU8R
Production PD
416 TEPBGA
w/Tape and Reel
SPC5777MK0MVA8
Production PD
512 TEPBGA
SPC5777MK0MVA8R
Production PD
512 TEPBGA
w/Tape and Reel
1
“PD” refers to a production device, orderable in quantity
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
133
Ordering information
2
“ED" refers to an emulation device, orderable in limited quantities. An emulation
device (ED) is for use during system development only and is not to be used in
production. An ED is a Production PD chip combined with a companion chip to form
an Emulation and Debug Device (ED) and includes additional RAM memory and
debug features. EDs are provided “as is" without warranty of any kind. In the event
of a suspected ED failure, NXP agrees to exchange the suspected failing ED from
the customer at no additional charge; however, NXP will not analyze ED returns.
MPC5777M Microcontroller Data Sheet, Rev. 6
134
NXP Semiconductors
Ordering information
Example code:
PC
M
4
57
6
M
Q
F0
M
xx
5
R
MC Qualification Status
Power Architecture Core
Automotive Platform
Processor Core
Flash Memory Size
Product/Family Name
Miscellaneous (Optional)
Fab and Mask Revision
Temperature
Package Code
Maximum Frequency
Tape or Reel
Qualification Status
MPC = Full specification qualified
SPC = Mask specification qualified
PPC = Engineering samples
Automotive Platform
55 = PPC in 130 nm
56 = PPC in 90 nm
57 = PPC in 55 nm
Processor Core
0 = e200z0
1 = e200z1
2 = e200z2
3 = e200z3
4 = e200z4
5 = e200z6 without VLE
6 = e200z6
7 = e200z7
Miscellaneous
D = Dual Core
T = Triple Core
Q = Quad Core
S = Single Core
2 = Emulation Device
Flash Memory Size
z0, z2
z4
z7
1
256 KB
1 MB
1 MB
2
384 KB
1.5 MB
1.5 MB
3
512 KB
2 MB
2 MB
4
768 KB
2.5 MB
3 MB
5
1 MB
3 MB
4 MB
6
1.5 MB
4 MB
6 MB
7
2 MB
5 MB
8 MB
8
2.5 MB
6 MB
12 MB
9
3 MB
8 MB
16 MB
Temperature Specification
C = –40 °C to 85 °C
V = –40 °C to 105 °C
M = –40 °C to 125 °C
K = –40 °C to 135 °C
Fab and Mask Revision
F = ATMC
K = TSMC
0 = Revision
Package Code
ZP = 416 PBGA SnPb
VA = 416 PBGA Pb-free
VA = 512 TEPBGA Pb-free
VU = 416 TEPBGA Pb-free
VF = 208 MAPBGA SnPb
VM = 208 MAPBGA Pb-free
ZQ = 324 PBGA SnPb
VZ = 324 PBGA Pb-free
LQ = 144 LQFP Pb-free
LU = 176 LQFP Pb-free
KU = 176 LQFP ep Pb-free
MP = 292 MAPBGA Pb-free
OU = 216 FQ (176 leads)
Maximum Frequency
0 = 64 MHz
1 = 80 MHz
2 = 120 MHz
3 = 150 MHz
4 = 160 MHz
5 = 200 MHz
8 = 300 MHz
Suffix
A = cut2.0 revision
T = Tape
R = Reel
Figure 61. Product code structure
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
135
Document revision history
5
Document revision history
Table 76 summarizes revisions to this document.
Table 76. Revision history
Revision
Date
1
12/2011
2
4/2013
Description of changes
Initial release
Throughout
• Data sheet now includes both KGD (TJ165 °C) and non-KGD (TJ150 °C)
specifications
• The interfaces and components formerly including the name “DigRF” have been
renamed to “LFAST.”
Introduction
• Changed on-chip general-purpose SRAM to 404 KB (was 384 KB)
• Changed item describing Boot Assist Flash support to “Boot Assist Module (BAM)
supports factory programming using serial bootload through ’UART Serial Boot Mode
Protocol’. Physical interface (PHY) can be: UART/LIN, CAN, FlexRay”
Table 1 (Family comparison):
• Changed feature from “Zipwire/LFAST7 bus” to “Zipwire (SIPI / LFAST7) Interprocessor
Communication Interface”
Figure 1 (Block diagram):
• Changed SRAM from 320 to 340 KB
• Changed figure to include “Triple INTC”
• Added “LFAST Switch” block to Computational Shell
• Added “Debug SIPI” block to the Peripheral Domain 50 MHz Concentrator
Figure 2 (Periphery allocation):
• Added PSI5_S_0 module
• Changed “Peripheral Cluster A” to “Peripheral Cluster B” and “Peripheral Cluster B” to
“Peripheral Cluster A”
• Added PSI5_S_0 module
Package pinouts and signal descriptions
Figure 3 (292-ball BGA production device pinout (top view))
Figure 4 (292-ball BGA emulation device pinout (top view))
Figure 5 (512-ball BGA production device pinout (top view))
Figure 8 (512-ball BGA emulation device pinout (top view)):
• Changed “VDD_HV_PMC_BYP” to “VDD_HV_IO_MAIN”
Table 2 (Power supply and reference pins):
• Removed VDD_HV_PMC_BYP (PMC Voltage Supply Bypass Capacitor) row.
Table 3 (System pins):
• Clarification of TESTMODE pin definition: “TESTMODE pull-down is implemented to
prevent the device from entering TESTMODE. It is recommended to connect the
TESTMODE pin to VSS_HV_IO on the board. The value of the TESTMODE pin is
latched at the negation of reset and has no affect afterward. The device will not exit
reset with the TESTMODE pin asserted during power-up.” (Added detail regarding
when TESTMODE pin value is latched and that device will not exit reset when pin is
asserted during power-up)
MPC5777M Microcontroller Data Sheet, Rev. 6
136
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Package pinouts and signal descriptions (con’t)
Table 4 (LVDS pin descriptions):
• In SIPI/LFAST, Differential DSPI2, and Differential DSPI 5 groups, changed port pin
“PF[7]” to “PD[7]”
• Changed the polarity of the signal assigned to several port pins. For example, the
signal for port pin PD[7] has been changed to “SIPI_RXP” (was SIPI_RXN) and
“Interprocessor Bus LFAST, LVDS Receive Positive Terminal” (was “Interprocessor
Bus LFAST, LVDS Receive Negative Terminal”). This change affects port pins PD[7],
PF[13], PA[14], PD[6], PA[7], PA[8], PD[2], PD[3], PD[0], PD[1], PF[10], PF[9], PF[11],
PF[12], PQ[8], PQ[9], PQ[10], PQ[11], PI[14], and PI[15].
• Added package ball locations
Electrical characteristics—Miscellaneous
Section 3, Electrical characteristics:
• Thermal characteristics section has been moved to Package characteristics section.
• Following note removed: “All parameter values in this document are tested with
nominal supply voltage values (VDD_LV = 1.25 V, VDD_HV = 5.0 V ± 10%,
VDD_HV_IO = 5.0 V ± 10% or 3.3 V ± 10%) and TA = –40 to 125 °C unless otherwise
specified.”. Operating conditions will appear elsewhere in the data sheet.
• Added VDD_HV_IO_FLEX before VDD_HV_FLA in the second note on the page
Electrical characteristics—Absolute maximum ratings
Table 6 (Absolute maximum ratings):
• IMAXD specification now given by pad type (Medium, Strong, and Very Strong)
• IMAXA specification deleted.
• New specification: IINJD (Maximum DC injection current for digital pad)
• New specification: IINJA (Maximum DC injection current for analog pad)
• New specification: IMAXSEG (Maximum current per power segment)
• New specification: VFERS (Flash erase acceleration supply)
• New specification: VDD_HV_IO_EBI (External Bus Interface supply)
• Changed “Emulation module supply” to “BD supply” in the VDD_LV_BD – BDD_LV row
• Maximum junction temperature changed from 125 °C to 165 °C in cumulative time
limits on voltage levels for VDD_LV and VDD_LV_BD
• Footnote added to VFERS: VFERS is a factory test supply pin that is used to reduce the
erase time of the flash. It is only available in bare die devices. There is no VFERS pin in
the packaged devices. The VFERS supply pad can be bonded to ground (VSS_HV) to
disable, or connected to 5.0 V ± 5% to use the flash erase acceleration feature. Pad
can be left at 5 V ± 5% in normal operation.
• Footnote added to VIN: “The maximum input voltage on an I/O pin tracks with the
associated I/O supply maximum. For the injection current condition on a pin, the
voltage will be equal to the supply plus the voltage drop across the internal ESD diode
from I/O pin to supply. The diode voltage varies greatly across process and
temperature, but a value of 0.3V can be used for nominal calculations.“
• Footnote VDD_LV changed: “1.32 – 1.375 V range allowed periodically for supply with
sinusoidal shape and average supply value below 1.288 V at maximum TJ = 165 °C”
(was 1.275)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
137
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—Operating conditions
Table 8 (Device operating conditions)
• Changed VSTBY_BO minimum from 0.7V to 0.8V.
Electrical characteristics—DC electrical specifications
Table 10 (DC electrical specifications)
• Replaced table; significant changes throughout, including parameter names,
descriptions, and values.
MPC5777M Microcontroller Data Sheet, Rev. 6
138
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—I/O pad specification
Table 11 (I/O pad specification descriptions)
• Revised “Very strong configuration” description to include EBI data bus.
• Added “EBI configuration” row.
• Changed “Input only pads” description to “These pads, which ensure low input leakage,
are associated with the ADC channels” (was “These pads are associated with the ADC
channels and 32 kHz low power external crystal oscillator providing low input leakage”)
• Changed note following table to “Each I/O pin on the device supports specific drive
configurations. See the signal description table in the device reference manual for the
available drive configurations for each I/O pin” (was “All pads can be configured in all
configurations”)
Table 12 (I/O input DC electrical characteristics)
• New specification: VDRFTTTL (Input VIL/VIH temperature drift TTL)
• New specification: VDRFTAUT (Input VIL/VIH temperature drift)
• New specification: VDRFTCMOS (Input VIL/VIH temperature drift CMOS)
• Conditions for VIHCMOS_H, VIHCMOS, VILCMOS_H, VILCMOS, VHYSCMOS, VDRFTCMOS are
now 3.0 V < VDD_HV_IO < 3.6 V and 4.5 V < VDD_HV_IO < 5.5 V (was 2.7 V < VDD_HV_IO
< 3.6 V and 4.0 V < VDD_HV_IO < 5.5 V)
• New specification: ILKG_MED (Digital input leakage for MEDIUM pad)
• Footnotes give formulas for approximation of the variation of the minimum value with
supply of VIHAUT and VHYSAUT (previously stated formulas approximated upper value
instead of minimum value). Changed formula for VIHAUT to “0.69 x VDD_HV_IO” (was
“0.69 supply”). Changed formula for VHYSAUT to “0.11 x VDD_HV_IO” (was “0.11
supply”).
• Footnote gives formula for approximation of the variation of the maximum value with
supply of VILAUT (previously stated formula approximated upper value instead of
maximum value). Changed formula for VILAUT to “0.49 x VDD_HV_IO” (was “0.49
supply”).
• Added footnote: “In a 1 ms period, assuming stable voltage and a temperature
variation of ±30°C, VIL/VIH shift is within ±50 mV.”
• VHYSAUT conditions column: replaced dash with 4.5V < VDD_HV_IO < 5.5V
• CIN row, changed GPIO input pins conditions Max value from “10” to 7pF and EBI input
pins Max value from “8” to “7pF”
Table 13 (I/O pull-up/pull-down DC electrical characteristics)
• Significant revisions throughout this table, including new conditions for IWPU and
IWPD
• New specification: RWPU (Weak pull-up resistance)
• New specification: RWPD (Weak pull-down resistance)
• New figure: Figure 8 (Weak pull-up electrical characteristics definition)
• New figure: Figure 18 (I/O output DC electrical characteristics definition)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
139
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—I/O pad specification (con’t)
Table 14 (WEAK configuration output buffer electrical characteristics)
• ROH_W (PMOS output impedance weak configuration) condition is now 4.5 V <
VDD_HV_IO < 5.9 V, Push pull IOH < 0.5 mA (was 4.0 V < VDD_HV_IO < 5.9 V). Removed
3.0 V < VDD_HV_IO < 4.0 V condition.
• ROL_W (NMOS output impedance WEAK configuration) condition is now 4.5 V <
VDD_HV_IO < 5.9 V, Push pull IOL < 0.5 mA (was 4.0 V < VDD_HV_IO < 5.9 V). Removed
3.0 V < VDD_HV_IO < 4.0 V condition.
• tTR_W (Transition time output pin WEAK configuration) conditions changed for CL = 25
pF, CL = 50 pF, CL = 200 pF: 4.5 V < VDD_HV_IO < 5.9 V (was 4.0 V < VDD_HV_IO <
5.9 V)
• Specification change: tTR_W, CL = 200 pF, 4.5 V < VDD_HV_IO < 5.9 V max value is
820 ns (was 1000)
• Specification change: tTR_W, CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 50 ns
(was TBD)
• Specification change: tTR_W, CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 100 ns
(was TBD)
• Specification change: tTR_W, CL = 200 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is
350 ns (was TBD) and max value is 1050 ns (was TBD)
• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to
5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
Table 15 (MEDIUM configuration output buffer electrical characteristics)
• ROH_M (PMOS output impedance MEDIUM configuration) condition is now 4.5 V <
VDD_HV_IO < 5.9 V, Push pull IOH < 2 mA (was 4.0 V < VDD_HV_IO < 5.9 V). Removed
3.0 V < VDD_HV_IO < 4.0 V condition.
• ROL_M (NMOS output impedance MEDIUM configuration) condition is now 4.5 V <
VDD_HV_IO < 5.9 V, Push pull IOL < 2 mA (was 4.0 V < VDD_HV_IO < 5.9 V). Removed
3.0 V < VDD_HV_IO < 4.0 V condition.
• tTR_M (Transition time output pin MEDIUM configuration) conditions changed for CL =
25 pF, CL = 50 pF, CL = 200 pF: 4.5 V < VDD_HV_IO < 5.9 V (was 4.0 V < VDD_HV_IO
< 5.9 V)
• Specification change: tTR_M, CL = 200 pF, 4.5 V < VDD_HV_IO < 5.9 V max value is
200 ns (was 240)
• Specification change: tTR_M, CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 12 ns
(was TBD)
• Specification change: tTR_M, CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 24 ns
(was TBD)
• Specification change: tTR_M, CL = 200 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 70 ns
(was TBD) and max value is 300 ns (was TBD)
• New specification: IDCMAX_M (Maximum DC current)
• New specification: tSKEW_M(Difference between rise and fall time)
• Formula given for transition time typical value changed to: tTR_M(ns) = 5.6 ns+CL(pF)
x 1.11 ns/pF (when 0 pF < CL < 50 pF) and tTR_M(ns) = 13 ns+CL(pF) x 0.96 ns/pF
(when 50 pF < CL < 200 pF)
• Footnote added: ROX_M(min) may decrease by 10% at TJ = 165 °C.
• Footnote added: ROX_M(max) may increase by 10% at TJ = 165 °C.
• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to
5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
MPC5777M Microcontroller Data Sheet, Rev. 6
140
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—I/O pad specification (con’t)
Table 16 (STRONG configuration output buffer electrical characteristics)
• New specification: IDCMAX_S (Maximum DC current)
• Renamed: ROH_F (PMOS output impedance STRONG configuration) is now ROH_S
• Renamed: ROL_F (NMOS output impedance STRONG configuration) is now ROL_S
• Renamed: fMAX_M (Output frequency STRONG configuration) is now fMAX_S
• ROH_S condition is now 4.5 V < VDD_HV_IO < 5.9 V, Push pull IOH < 8 mA (was 4.0 V <
VDD_HV_IO < 5.9 V). Removed 3.0 V < VDD_HV_IO < 4.0 V condition.
• ROL_S condition is now 4.5 V < VDD_HV_IO < 5.9 V, Push pull IOH < 8 mA (was 4.0 V <
VDD_HV_IO < 5.9 V). Removed 3.0 V < VDD_HV_IO < 4.0 V condition.
• tTR_S conditions changed for CL = 25 pF, CL = 50 pF, CL = 200 pF: 4.5 V < VDD_HV_IO
< 5.9 V (was 4.0 V < VDD_HV_IO < 5.9 V)
• Specification change: fMAX_S, CL = 200 pF max value is 5 MHz (was “—”)
• Specification change: tTR_S, CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 4 ns
(was TBD) and max value is 15 ns (was TBD)
• Specification change: tTR_S, CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 6 ns
(was TBD) and max value is 27 ns (was TBD)
• Specification change: tTR_S, CL = 200 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 20 ns
(was TBD) and max value is 83 ns (was TBD)
• Footnote added: ROX_S(min) may decrease by 10% at TJ = 165 °C.
• Footnote added: ROX_S(max) may increase by 10% at TJ = 165 °C.
• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to
5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
Table 17 (VERY STRONG configuration output buffer electrical characteristics)
• New specification: IDCMAX_M (Maximum DC current)
• New condition added to tTR_V: VDD_HV_IO = 5.0 V ± 10%, CL = 200 pF
• Footnote added: ROX_V(min) may decrease by 10% at TJ = 165 °C.
• Footnote added: ROX_V(max) may increase by 10% at TJ = 165 °C.
• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to
5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
Table 18 (EBI pad output electrical specification)
• Replaced this table “EBI output driver electrical characteristics” with new table “EBI pad
electrical specification”
Electrical characteristics—I/O pad current specification
New section
Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics
Section 3.8, Reset pad (PORST, ESR0) electrical characteristics:
• Added note on PORST and active control
Figure 11 (Noise filtering on reset signal):
• Replaced; significant detail added
• Clarification: VESR0 is also described by VPORST behavior shown in illustration.
• Figure prefaced with more detailed PORST description.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
141
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics
(con’t)
Table 20 (Reset electrical characteristics)
• New specification: WFNMI (ESR1 input filtered pulse)
• New specification: WNFNMI (ESR1 input not filtered pulse)
• New specification: VDD_POR (Minimum supply for strong pull-down activation)
• IOL_R condition changed (VDD_HV_IO = 1.0 V is now VDD_HV_IO = VDD_POR, VDD_HV_IO
= 4.0 V is now 3.0 V < VDD_HV_IO < 5.5 V, and VOL = 0.35*VDD_HV_IO is now VOL >
0.9 V)
• Specification change: IOL_R (3.0 V < VDD_HV_IO < 5.5 V, VOL > 0.9 V) min value is
11 mA (was 15)
• Added footnote: An external 4.7 K pull-up resistor is recommended to be used with
the PORST and ESR0 pins for fast negation of the signals.
• Added footnote: IOL_R applies to both PORST and ESR0: Strong pull-down is active on
PHASE0 for PORST. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and
the beginning of PHASE3 for ESR0.
• Added note on reset signal slew rate restrictions
Electrical characteristics—Oscillator and FMPLL
Section 3.12, Oscillator and FMPLL
Table 21 (PLL0 electrical characteristics)
• New specification: fPLL0PHI0 (PLL0 output frequency)
• Specification change: tPLL0LOCK (PLL0 lock time) maximum is 100 µs (was
100–110 µs)
• PLL0LTJ specification parameter and conditions change: “PLL0 output long term jitter,
fPLL0IN = 20 MHz (resonator), VCO frequency = 800 MHz” (was “PLL0 output long term
jitter, fPLL0IN = 20 MHz (resonator)”). Conditions significantly revised.
• Revised footnote: “VDD_LV noise due to application in the range VDD_LV = 1.25 V ±5%
with frequency below PLL bandwidth (40 KHz) will be filtered” (was “1.25 V ±5%
application noise below 40kHz at VDD_LV pin”)
• Removed “F” from “FXOSC” in footnote 1
Table 22 (PLL1 electrical characteristics)
• Specification change: fPLL1PHI (PLL1 output clock PHI) is now fPLL1PHI0 (PLL1 output
clock PHI0)
• Specification change: fPLL1PHI0 (PLL1 output clock PHI0) max is 200 MHz (was
625 MHz)
• fPLL1PHI parameter, Max column, changed 200MHz to 300MHz.
• Removed “F” from “FXOSC” in footnote 1
MPC5777M Microcontroller Data Sheet, Rev. 6
142
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—Oscillator and FMPLL (con’t)
Table 23 (External Oscillator electrical specifications):
• New specification: VHYS (Comparator Hysteresis)
• New specification: VEXTAL (Oscillation Amplitude on the EXTAL pin after startup)
• Specification change: fXTAL range values changed: fXTAL ranges are 4–8 MHz,
>8–20 MHz, and >20–40 MHz (previously stated as 4–8 MHz, 8–16 MHz, and
20–40 MHz
• Specification change tcst (Crystal start-up time) is now specified by temperature range
• Specification change: VIHEXT specified at VREF = 0.28 * VDD_HV_IO_JTAG (previously
specified at VDDOSC = 3.0 V and VDDOSC = 5.5 V)
• Specification change: VILEXT specified at VREF = 0.28 * VDD_HV_IO_JTAG (previously
specified at VDDOSC = 3.0 V and VDDOSC = 5.5 V)
• Specification change: CS_EXTAL values specified by package (was previously based on
selected load capacitance value)
• Specification change: CS_XTAL values specified by package (was previously based on
selected load capacitance value)
• Specification change: gm (Oscillator Transconductance) is now specified by
temperature and frequency range conditions (was previously specified without
conditions)
• Footnote added: “All oscillator specifications are valid for
VDD_HV_IO_JTAG = 3.0 V – 5.5 V.“
• Footnote added to CS_EXTAL, CS_XTAL to refer to crystal manufacturer's specifications
for load capacitance values.
• Footnote added: “Amplitude on the EXTAL pin after startup is determined by the ALC
block, i.e., the Automatic Level Control Circuit. The function of the ALC is to provide
high drive current during oscillator startup, but reduce current after oscillation in order
to reduce power, distortion, and RFI, and to avoid over-driving the crystal. The
operating point of the ALC is dependent on the crystal value and loading conditions.”
• Footnote added: “IXTAL is the oscillator bias current out of the XTAL pin with both
EXTAL and XTAL pins grounded. This is the maximum current during startup of the
oscillator. The current after oscillation is typically in the 2–3 mA range and is dependent
on the load and series resistance of the crystal.”
• VILEXT parameter, changed “External Reference” to “External Clock Input”
• VILEXT parameter, added footnote: This parameter is guaranteed by design rather than
100% tested.
Table 24 (Selectable load capacitance):
• Changed footnote 2 from “Values in this table do not include 8 pF routing and ESD
structure on die and package trace capacitance.” to "Values in this table do not include
the die and package capacitances given by Cs_xtal/Cs_extal in Table 23 (External
Oscillator electrical specifications).”
Electrical characteristics—ADC specifications
Section 3.10.1, ADC input description
Table 26 (ADC pin specification)
• ILK_IN specification change: removed TA = 125 °C row from (TA = 125 °C)
• ILK_INUD, ILK_INUSD, ILK_INREF, and ILK_INOUT specification changes to parameters,
conditions, and values.
• Specification change: IINJ min value is –3 mA (was –1)
• Specification change: CS max value is 8.5 pF (was 7)
• Specification change: RSWn max value for SARn channels is 1.1 k (was 0.6)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
143
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—ADC specifications (con’t)
Section 3.10.1, ADC input description
Table 26 (ADC pin specification):
• Specification change: RSWn max value for SARB channels is 1.7 k (was 1.2)
• Specification change: RCMSW max value is 2.6 k(was 2)
• Removed VREF_BG specification
• Added VREF_BG_LR and VREF_BG_TC specifications
• Added footnote: Specifications in this table apply to both packaged parts and Known
Good Die (KGD) parts, except where noted.
• Added footnote: The temperature coefficient and line regulation specifications are
used to calculate the reference voltage drift at an operating point within the specified
voltage and temperature operating conditions.
• Parameter ILK_INOUT description column, changed MEDIUM output buffer with GPIO
output buffer.
Table 27 (SARn ADC electrical specification)
• Replaced table
Section 3.13.3, S/D ADC electrical specification
• Revised sentence to indicate that the ADCs are 14-bit (was 16-bit)
Table 28 (SDn ADC electrical specification)
• New specification: fPASSBAND (Pass band)
• Removed VDD and VSS specifications
• Removed fIN specification
• Throughout table, appended _D to change to VDD_HV_ADV_D (was VDD_HV_ADV),
VSS_HV_ADV_D (was VSS_HV_ADV), VDD_HV_ADR_D (was VDD_HV_ADR), and
VSS_HV_ADR_D (was VSS_HV_ADR).
• VIN_PK2PK (Input range peak to peak VIN_PK2PK= VINP – VINM): single ended
specification extended to include multiple conditions
• Multiple condition changes for the GAIN and SNRDIFF150 parameters
• GAIN: changed maximum value for Before calibration condition to “1.5 %” (was 1 %).
• SFDR conditions revised to include different GAIN settings
• Specification change: VBIAS min value is –2.5% (was –10) and the max value is +2.5%
(was +10)
• Significant revisions to footnotes, including one added to voltage range conditions in
all SNR specs: “In the range 3.6 V< VDD_HV_ADV<4.0 V and
<3.0 V<VDD_HV_ADR_D<4.0 V, SNR parameter degrades by 9 dB”
• fADCD_M, changed “S/D clock 3(4)” to “S/D Modulator Input Clock” and replaced “—”
with “4” in Min column
• fADCD_S changed “conversion rate'” to “output conversion rate”
• Changed SNR specifications Unit column from “dB” to “dBFS”
• Changed SFDR specification Unit column from “dB” to “dBc”
• Add to footnote: Input impedance is calculated in megaohms by the formula 25.6/(Gain
Fadcd_m)
• Changed Group delay, OSR = 75, Max value from “546” to “596”
• Added new specifications: SINADDIFF150, SINADDIFF333, SINADSE150, THDDIFF150,
THDDIFF333, THDSE150
Electrical characteristics—Temperature sensor specifications
Table 29 (Temperature sensor electrical characteristics)
• TSENS, TACC, and ITEMP_SENS added to Symbol column.
• Condition change for TACC (Accuracy): added 150 °C and 165 °C conditions
• Specification change: TACC min value for TJ < 165°C is 7 °C (was –3) and max value
is 7 °C (was 3)
• Specification change: ITEMP_SENS max value is 700 µA (was 600).
MPC5777M Microcontroller Data Sheet, Rev. 6
144
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—LFAST electrical specifications
Formerly named “DigRF interface electrical characteristics”; renamed to “LVDS Fast
Asynchronous Serial Transmission (LFAST) pad electrical characteristics. The change
from “DigRF” to “LFAST” applies throughout.
Figure 16 (LFAST and MSC/DSPI LVDS timing definition). Figure updated.
Section Table 30., LVDS pad startup and receiver electrical characteristics,
• Specification change: added ILVDS_BIAS
• TRANSMITTER parameters moved to separate table: VOS_DRF (Common mode
voltage), |DVOD_DRF| (Differential output voltage swing (terminated)), tTR_DRF
(Rise/Fall time (10%–90% of swing)), ROUT_DRF (Terminating resistance), COUT_DRF
(Capacitance)
• Receiver requirement VICOM_DRF renamed to VICOM
• Receiver requirement |VI_DRF| renamed to |VI|
• Receiver specification VHYS_DRF renamed to VHYS
• Receiver specification RIN_DRF renamed to RIN
• Receiver specification CIN_DRF renamed to CIN
• Receiver specification LIN_DRF deleted
• Extensive changes throughout table footnotes.
Table 31 (LFAST transmitter electrical characteristics,):
Differential output voltage swing parameter:
• Removed the delta symbol from |VOD|
• Changed Min = 100, Typ = 171, Max = 285. removed the “+/-” from each value.
Rise/Fall time parameter:
• Changed “(10%–90% of swing)” to (absolute value of the differential output voltage
swing
Table 32 (MSC/DSPI LVDS transmitter electrical characteristics ,):
Differential output voltage swing parameter:
• Removed the delta symbol from |VOD|
• Changed Min +/- 150 to 150
• Changed Typ +/- 200 to 214
• Changed Max +/- 400 to 400
Rise/Fall time parameter:
• Changed “(10%–90% of swing)” to (absolute value of the differential output voltage
swing)
Table 33 (LFAST PLL electrical characteristics)
• Changed footnote 2, from “320” to “640” MHz frequency
Table 34 (Aurora LVDS electrical characteristics,)
• Extensive changes throughout table
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
145
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—Power management: PMC, POR/LVD, sequencing
Table 40 (PMC operating conditions and external regulators supply voltage)
• Specification change: VDD_HV_PMC, Reduced internal regulator output capacity max
value is 3.5 V (was 5.5)
• Specification change: VDD_HV_PMC, Monitoring activity only min value is 2.7 V (was
3.0) and max value is 3.15 V (was 5.5)
Section 3.14.2, Power management integration
• Entire section replaced
Table 36 (Flash power supply):
• New
Section 3.14.4, Device voltage monitoring
• Added Figure 24 (Voltage monitor threshold definition)
Table 37 (Voltage monitor electrical characteristics)
• VPORUP_LV Added footnote2, “Hysteresis is only true with the High voltage Supplies for
the I/O Main and the ADC are connected together. (There is actually around 1V of
Hysteresis using these two supplies.)”
• New specification: VPOR240 (HV supply power-on reset voltage monitoring)
• New specification: tVDASSERT (Voltage detector threshold crossing assertion)
• New specification: tVDRELEASE (Voltage detector threshold crossing deassertion)
• Specification change: VPORUP_LV, Rising voltage max value is 1180 mV (was 1170)
• Specification change: VPORUP_LV Falling voltage max value is 1100 mV
• Significant changes to footnotes for this table.
• VLVD096 (LV internal supply low voltage monitoring). Footnote added: “LV internal
supply levels are measured on device internal supply grid after internal voltage drop.“
• VLVD108 (LV internal supply low voltage monitoring). Footnote added: “LV internal
supply levels are measured on device internal supply grid after internal voltage drop.“
• Specification change: VLVD112 max value is 1180 mV (was 1190)
• Specification change: VHVD140 is 1440 mV (was 1420)
• Specification change: VPORUP_HV Rising voltage max value is 4480 mV (was 4200);
min value is 4040. in addition, the Falling voltage min value is 2830 mV (was 2700) and
the max value of 3210 mV was added
• Specification change: VLVD270 max value is 2950 mV (was 2980)
• Specification change: VLVD400 max value is 4410 mV (was 4400); min value added for
Rising voltage. Also, changed min value for Falling voltage is 3970 mV (was 3980)
Specification change: VHVD600 min value is 5560 mV (was 5520) and max value is
6000 mV (was 5960)
Table 39 (Functional terminals state during power-up and reset)
• Corrected ESR1 RESET pad state to “Weak pull-up” (was “pull-down”) and DEFAULT
pad state to “Weak pull-up” (was “pull-down”)
• Corrected TMS RESET pad state to “Weak pull-up” (was “pull-down”) and DEFAULT
pad state to “Weak pull-up” (was “pull-down”)
• Changed TDO RESET pad state to “High impedance” (was “Weak pull-up”)
• Revised TESTMODE footnote: “An internal pull-down is implemented on the
TESTMODE pin to prevent the device from entering test mode if the package
TESTMODE pin is not connected. It is recommended to connect the TESTMODE pin
to VSS_HV_IO on the board for maximum robustness, but not required. The value of
TESTMODE is latched at the negation of reset and has no affect afterward. The device
will not exit functional reset with the TESTMODE pin asserted during power-up. The
TESTMODE pin can be connected externally directly to ground without any other
components.”
MPC5777M Microcontroller Data Sheet, Rev. 6
146
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—Flash memory electrical characteristics
Section 3.15, Flash memory electrical characteristics
• This section completely revised.
Electrical characteristics—AC specifications—Debug and Calibration
Table 46 (JTAG pin AC electrical characteristics,):
• Specification change: tJCYC (TCK cycle time) now consists of a single
specification—minimum value is 100 ns. Footnotes from previous entries have been
removed.
• Specification change: tTDOHZ (TCK low to TDO high impedance) is now 15 ns (was 16)
• Classification change: All specifications are “D” (were “P” and “C”)
Table 47 (Nexus debug port timing)
• New specification: tEVTIPW (EVTI pulse width)
• New specification: tEVTOPW (EVTO pulse width)
• Clarification: footnote added to TCYC, defining it as the system clock period
• Specification change: TDO propagation delay from falling edge of TCK max is 16 ns
(was 12.5 ns)
• Specification change: TCK cycle time is min value is 2 tCYC (was 4)
• Specification change: Absolute minimum TCK cycle time min value is 40 ns (was 25)
• Specification change: TDI Data Hold Time min value is 5 ns (was 17.5)
• Specification change: TMS Data Hold Time min value is 5 ns (was 17.5)
• TDO propagation delay from falling edge of TCK max value is 16 ns (was 12.5)
• Specification change: tTCYC (absolute minimum TCK cycle time) now consists of two
specifications—one with TDO sampled on posedge of TCK and one sampled with TDO
sampled on negedge of TCK.
Table 48 (Aurora LVDS interface timing specifications)
• Specification change: Data rate typ. value is undefined (was 1200 Mbps)
• Specification change: Data rate max. value is 1250 Mbps (was “Typ+1%”)
Table 49 (Aurora debug port timing)
• Specification change: tREFCLK (Reference clock frequency) max value is 1250 MHz
(was 1200)
• Specification change: OUI (Aurora lane unit interval) is now specified by data rate
• Characteristic vs. Requirement change: JD (Transmit lane deterministic jitter) is “SR”
(was “CC”)
• Characteristic vs. Requirement change: JT (Transmit lane total jitter) is “SR” (was “CC”)
Electrical characteristics—AC specifications—DSPI
Section 3.19.2, DSPI timing with CMOS and LVDS pads: Substantive changes to entire
section, including reclassification of content as:
• Table 51 (DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0,
CPHA = 0 or 1)
• Table 52 (DSPI CMOS master modified timing (full duplex and output only) –
MTFE = 1, CPHA = 0 or 1)
• Table 54 (DSPI LVDS slave timing – full duplex – modified transfer format
(MTFE = 0/1))
• Table 55 (DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or
ITSB = 1, CPOL = 0 or 1, continuous SCK clock,)
• Table 56 (DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or
ITSB = 1, CPOL = 0 or 1, continuous SCK clock,)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
147
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—AC specifications—Fast Ethernet Controller (FEC)
Section 3.16.3, “FEC timing
Table 58 (MII receive signal timing)
• Column added: SR/CC (system requirement or controller characteristic)
• Column added: Classification (parameters are guaranteed by design)
Table 59 (MII transmit signal timing)
• Column added: SR/CC (system requirement or controller characteristic)
• Column added: Classification (parameters are guaranteed by design)
• Footnote added to max and min values columns: “Output parameters are valid for
CL = 25 pF, where CL is the external load to the device. The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF
value.”
Table 60 (MII async inputs signal timing)
• Column added: SR/CC (system requirement or controller characteristic)
• Column added: Classification (parameters are guaranteed by design)
Table 61 (MII serial management channel timing):
• Column added: SR/CC (system requirement or controller characteristic)
• Column added: Classification (parameters are guaranteed by design)
Table 62 (RMII receive signal timing):
• Column added: SR/CC (system requirement or controller characteristic)
• Column added: Classification (parameters are guaranteed by design)
Table 63 (RMII transmit signal timing,):
• Column added: SR/CC (system requirement or controller characteristic)
• Column added: Classification (parameters are guaranteed by design)
• Specification change: REF_CLK to TXD[1:0], TX_EN valid max value is 16 ns (was 14)
• Added footnote 2 to value column “Output parameters are valid for CL = 25 pF, where
CL is the external load to the device. The internal package capacitance is accounted
for, and does not need to be subtracted from the 25 pF value.”
Electrical characteristics—AC specifications—FlexRay
Section 3.16.4, FlexRay timing
Table 64 (TxEN output characteristics):
• Column added: SR/CC (system requirement or controller characteristic)
• Column added: Classification (parameters are guaranteed by design)
Table 65 (TxD output characteristics,):
• tTR20-80 specification for VDD_HV_IO = 5.0 V ± 10%, Transmission line Z = 50 ohms,
tdelay = 1 ns, CL = 10 pF, moved from Table 17 (VERY STRONG configuration output
buffer electrical characteristics)
• tTR20-80 specification combined with dCCTxDRISE25+dCCTxDFALL25 specification.
Footnotes added for conditions. 3.3V specification added.
• Footnote added: “Specifications valid according to FlexRay EPL 3.0.1 standard with
20%-80% levels and a 10pF load at the end of a 50ohm, 1ns stripline. Please refer to
the Very Strong I/O pad specifications.“
• Column added: SR/CC (system requirement or controller characteristic)
• Column added: Classification (parameters are guaranteed by design)
MPC5777M Microcontroller Data Sheet, Rev. 6
148
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—AC specifications—FlexRay (con’t)
Table 66 (RxD input characteristics):
• New specification: dCCRxAsymAccept15 (Acceptance of asymmetry at receiving CC
with 15 pF load)
• New specification: dCCRxAsymAccept25 (Acceptance of asymmetry at receiving CC
with 25 pF load)
• Column added: SR/CC (system requirement or controller characteristic)
• Column added: Classification (parameters are guaranteed by design)
Electrical characteristics—AC specifications—PSI5
Section 3.19.6, PSI5 timing
Table 67 (PSI5 timing):
• Specification description for tMSG_DLY changed to, “Delay from last bit of frame (CRC0)
to assertion of new message received interrupt“ (was, “Delay from last bit of frame (end
of idle time) ...”)
• Specification description for tMSG_JIT changed to, “Delay jitter from last bit of frame
(CRC0) to assertion of new message received interrupt“ (was, “Delay from last bit of
frame (end of idle time) ...”)
• Maximum value for tSYNC_JIT changed to ±(1 PSI5_1µs_CLK + 1 PBRIDGEn_CLK);
was 1 cycle
• Footnote 2 (“Measured in PSI5 1 MHz clock cycles (PSI5_1us_CLK on the device).”)
on the unit for tSYNC_JIT deleted
• Classification change: tMSG_DLY (Delay from last bit of frame (CRC0) to assertion of
new message received interrupt) is “D” (was “C”)
• Classification change: tSYNC_DLY (Delay from internal sync pulse to sync pulse trigger
at the SDOUT_PSI5_n pin) is “D” (was “C”)
• Classification change: tMSG_JIT (Delay jitter from last bit of frame (CRC0) to assertion
of new message received interrupt) is “D” (was “C”)
• Classification change: tSYNC_JIT (Delay jitter from internal sync pulse to sync pulse
trigger at the SDOUT_PSI5_n pin) is “D” (was “C”)
Electrical characteristics—AC specifications—UART
Section 3.18.7, UART timing
• New
Electrical characteristics—AC specifications—EBI
Section 3.16.7, External Bus Interface (EBI) Timing:
• New
Package characteristics
• 292 MAPBGA case drawing Rev. A included.
• 416 TEPBGA case drawing Rev. 0 included.
Electrical characteristics—Thermal Characteristics
Table 74 (Thermal characteristics)
• This table consolidates what were formerly separate thermal specifications tables for
each package. All values have been updated.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
149
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Ordering Information
Section 4, Ordering information:
• New
3
3/2014
Throughout
• Changed document ID to “MPC5777M.”
• Updated the “e200_z720n3” cores to “e200_z710n3” and the “e200_z719” core to
“e200_z709.”
• Removed references to the 292 MAPBGA and LFBGA292 packages.
• Editorial (non-technical) changes and improvements.
• Removed references to KGD and 165oC ratings.
Introduction
Table 1 (Family comparison):
• SPC5744K column, ADC (SD) feature, changed “3” to “2”.
• MPC5777M column, removed 292 MAPBGA.
• Changed feature from “SIPI/LFAST7 bus” to “Zipwire(SIPI / LFAST7) Interprocessor
Communication Interface”.
• Removed “To be confirmed for final silicon” footnote from Local RAM row for
SPC5744K.
• Removed “Only on the I/O processor core” footnote from LSP row for all devices.
• Changed System SRAM for MPC5777M to “404 KB” (was 384 KB).
• Changed Flash memory for MPC5777M to “8640 KB” (was 7.9 MB).
• Changed DMA Nexus Class for SPC5744K, MPC5746M, and MPC5777M to “3+” (was
3).
• Changed GTM RAM for MPC5777M to “58 KB” (was 52 KB).
• Changed Interrupt Controller entry for MPC5777M to “727 sources” (was 930 sources).
• Removed “Integrated switch mode voltage regulator” row.
• Removed “Degraded performance below 4.0 V” footnote from 5 V value in External
power supplies row.
Figure 1 (Block diagram):
• Updated the “e200_z720n3” cores to “e200_z710n3” and the “e200_z719” core to
“e200_z709”.
Section 1.5, Feature overview
• Changed item describing main CPUs to “single issue” (was “dual issue).
• Changed item describing on-chip flash memory to “8640 KB” (was “8528 KB”).
• Removed FlexRay as an option for BAM serial port.
MPC5777M Microcontroller Data Sheet, Rev. 6
150
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Package pinouts and signal descriptions
Section 2.1, Package pinouts:
• Removed “292” from the first sentence.
• Removed figure “292-ball BGA production device pinout (top view)” and figure
“292-ball BGA production device pinout (bottom view)”.
Table 2 (Power supply and reference pins) and Table 3 (System pins):
• Removed the “292PD” and 292ED” BGA ball columns.
• VSS_LV: Added K13 and K14 for 416PD/416ED. Added M15 and M16 for
512PD/512ED.
• VDD_LV_BD: R1/R4 now applies only to 416ED (416PD changed to “—”). M13/N12 now
applies only to 512ED (512PD changed to “—”).
• Removed VDD_HV_OSC row.
• Changed VDD_HV_JTAG Description to "JTAG/Oscillator power supply."
• VDDSTBY: removed "Input" from descripion.
• Significantly revised VSS_HV_ADV_S, VDD_HV_ADV_S, VSS_HV_ADV_D, and
VDD_HV_ADV_D rows. Added rows for VSS_HV_ADR_S, VDD_HV_ADR_S, VSS_HV_ADR_D,
VDD_HV_ADR_D.
Table 4 (LVDS pin descriptions):
• Changed title to “LVDS pin descriptions” (was “LVDSM”).
• Removed the “292 PD, 292 ED” BGA ball column.
• In the BGA ball (416 PD,416 ED) column, added ball locations.
• In the BGA ball (512 PD, 512 ED) column, added ball locations.
• Changed SIPI_TXP to P25 for 512BGA (was T25).
• DSPI 4: Changed SCK_N to G17 for 512BGA (was G18).
• DSPI 2: Changed SIN_P to G23 for 416BGA (was D17).
• DSPI 5: For SCK_P, changed PI[15] to PF[10], G26 to J24, and P22 to W24.
• DSPI 5: For SCK_N, changed PI[15] to PF[9], J23 to K23, and R22 to W25.
• Added another pair of SIN_P/SIN_N rows for DSPI_5.
Electrical characteristics—Absolute maximum ratings
Section 3.1, Introduction:
• Added VDD_HV_IO_FLEXE and VDD_HV_IO_EBI to list in supply pins note.
Table 7 (Parameter classifications):
• Changed Tag description for C classification to “Parameters are guaranteed. . .” (was
“Those parameters are achieved. . .”
• Changed Tag description for T classification to “Parameters are guaranteed. . .” (was
“Those parameters are achieved. . .”
Table 6 (Absolute maximum ratings):
• Changed VSS to VSS_HV.
• Removed “VSS – VSS_HV_ADV” parameter row.
• Removed VFERS row.
• Removed “VFERS is a factory test supply pin . . .” footnote.
• VSS_HV_ADR: Added "Reference to VSS_HV" to Conditions field.
• Removed VSS–VSS_HV_ADR_D and VSS–VSS_HV_ADR_S rows.
• In VDD_HV_IO footnote, added VDD_HV_IO_JTAG to list of power supplies to which
VDD_HV_IO applies.
• In ADC grounds footnote, removed VSS_HV_ADV_D2.
• In ADC supplies footnote, changed VDD_HV_ADV to VDD_HV_ADV_S.
• In ADC low and high references footnote, removed VSS_HV_ADR_D2 and
VDD_HV_ADR_D2.
• In ADC supplies footnote, removed VDD_HV_ADV_D2.
Table 7 (ESD ratings,):
• Changed ESD for Human Body Model (HBM) parameter classification to “T” (was SR)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
151
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Electrical characteristics—Electromagnetic Compatibility (EMC)
• Removed section.
Electrical characteristics—Operating conditions
Table 8 (Device operating conditions):
• VDDSTBY added new footnote: The VDDSTBY pin should be connected to ground in
the application when the standby RAM feature is not used.'
• Added “Vin” specification, Min = 0V, Max = 5.5 V.
• VDD_HV_ADV changed Min value from 3.6 V to 3.7 V.
• VDD_HV_IO_MAIN, LVD400/HVD 600 disabled and LVD360/HVD600 disabled
conditions: changed max to “5.5 V” (was “5.9 V”).
• VDD_HV_IO_MAIN: Added footnote "VDD_HV_IO_MAIN range limited to 4.75–5.25 V
when FERS = 1 to enable the fast erase time of the flash memory."
• VDD_HV_ADR_D: Changed Typ value from VDD_HV_ADV to VDD_HV_ADV_D.
• Changed "VDD_HV_ADR_D–VDD_HV_ADV" parameter to
"VDD_HV_ADR_D–VDD_HV_ADV_D."
• VSS_HV_ADR_D: Changed VSS_HV_ADV to VSS_HV_ADV_D.
• Changed "VSS_HV_ADR_D–VSS_HV_ADV" parameter to
"VSS_HV_ADR_D–VSS_HV_ADV_D."
• VDD_HV_ADR_S: Added typ value of VDD_HV_ADV_S
• Added VSS_HV_ADR_S parameter.
• Changed "VDD_HV_ADR_S–VDD_HV_ADV" parameter to "VDD_HV_ADR_S–VDD_HV_ADV_S"
• Changed "VSS_HV_ADR_S–VSS_HV_ADV" parameter to "VSS_HV_ADR_S–VSS_HV_ADV_S"
• For VDD_HV_ADV specification, changed parameter to “SARADC, SDADC,
Temperature Sensor, and Bandgap Reference supply voltage” (was SARADC and
SDADC). For LVD400 disabled and LVD360 disabled conditions, referenced new
footnote: “VDD_HV_ADV_S is required to be between 4.5V and 5.5V to read to read the
internal Temp Sensor and Bandgap Reference.”
• Changed VRAMP to VRAMP_LV, and changed parameter to “slew rate on core power
supply pins”.
• Added VRAMP_HV specification, parameter “Slew rate on HV power supply pins”, max
value 500 V/ms.
• Changed VDD_HV_IO_JTAG, VDD_HV_IO_FLEX, and VDD_HV_IO_EBI values from 4.0 V Min
to 4.5 V Min, and changed “5.9 V” Max to “5.5 V” Max.
• Moved VREF_BG_T, VREF_BG_TC and VREF_BG_LR specifications from ADC pin
specification table to Device operating conditions table.
• Removed footnote “Maximum frequency for the 292BGA is TBD, and may be lower
due to package thermal considerations.” from fSYS specification, Max value “300” MHz.
• VDD_HV_ADV changed “LVD400 disabled” condition to “LVD360 disabled” for the
3.7V-5.9 V case.
• VDD_HV_IO_FLEXE added specification.
• VSTBY_BO and VDD_LV_STBY_SW removed from the Device operating conditions table
and added to the DC electrical specifications table.
• Vpor_rel and Vpor_hys specifications added.
• Removed VFERS row and associated footnote.
Table 9 (Emulation (buddy) device operating conditions):
• Changed VDD_LV_BD minimum value from blank to “1.2” V.
• VDD_LV_BD: Maximum changed to 1.365 V (was 1.32 V).
• Changed VRAMP_BD to VRAMP_LV_BD and added specification VRAMP_HV_BD.
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Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Electrical characteristics—DC electrical specification
Table 10 (DC electrical specifications):
• Changed footnote 11, to “The standby RAM regulator current is present on the
VDDSTBY pin whenever a voltage is applied to the pin. This also applies to normal
operation where the RAM is powered by the VDD_LV supply. Connecting the
VDDSTBY pin to ground when not using the standby RAM feature will remove the
leakage current on the VDDSTBY pin.”
• Moved VREF_BG_T, VREF_BG_TC and VREF_BG_LR specifications from ADC pin
specification table to DC electrical specifications table.
• Removed IFERS row.
• VSTBY_BO and VDD_LV_STBY_SW removed from the Device operating conditions table
and added to the DC electrical specifications table.
• Changed IDD_LV maximum value to 850 mA (was 910).
Electrical characteristics—DC electrical specification (con’t)
Table 10 (DC electrical specifications):
• Changed IDD_LV maximum value to 850 mA (was 910).\
• IDD_LV_BD, changed “250” to “290” mA.
• IDD_BD_STBY, 150 oC condition, changed “120” to “230” mA.
• IDD_MAIN_CORE_AC: Added footnote "There is an additional 25mA when FERS=1 to
enable the fast erase time of the flash memory."
• In VDD_HV_PMC availability footnote, changed “QFP” to “416 BGA” and “BGA” to “512
BGA.”
• Revised footnote “If Aurora and JTAGM/LFAST not used, VDD_LV_BD current is reduced
by ~20mA.”
• Removed silicon characterization footnote.
Table 12 (I/O input DC electrical characteristics):
• VDRFTAUT specification, conditions column, added “4.5 V < VDD_HV_IO < 5.5 V”.
• VDRFTCMOS specification, added 3.0 V < VDD_HV_IO < 3.6 V and 4.5 V < VDD_HV_IO <
5.5 V conditions.
• ILKG specification, entire row revised.
• Changed footnote 6 “n the range 4.5 V < VDD_HV_IO < 5.9 V.” to “in the range 4.5 V <
VDD_HV_IO < 5.5 V.
• VHYSAUT conditions column: replaced dash with 4.5 V < VDD_HV_IO < 5.5 V.
• CIN row, changed GPIO input pins conditions Max value from “10” to “7” pF and EBI
input pins Max value from “8” to “7” pF.
• ILKG_EBI removed “Vin = 10%/90%” from parameter column.
Figure 18 (I/O output DC electrical characteristics definition): Replaced figure.
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Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Electrical characteristics—I/O pad specification
Table 13 (I/O pull-up/pull-down DC electrical characteristics):
• IWPU, IWPD: substantially revised these specifications.
Table 14,Table 15,Table 16,Table 17:
• Added footnote to “C” classification header: "Once device characterization is
correlated to production I/O testing, the test classification of output resistance
parameters may be subject to change in future revisions of this document."
• ROH_W, ROL_W, ROH_M, ROL_M, ROH_S, ROL_S, ROH_V, ROL_V: Changed classification to
C (was P).
• Removed all VSIO conditions (VSIO[VSIO_xx] = 1 and VSIO[VSIO_xx] = 0) from
conditions column and added footnote: “All VDD_HV_IO conditions for 4.5 V to 5.9 V are
valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0 V to 3.6 V are valid for
VSIO[VSIO_xx] = 0.”
• Removed TPHL/PLH specification from WEAK, MEDIUM, and STRONG configuration
output buffer electrical characteristics.
• Removed characterization and validation footnotes (total 2) for each table.
Table 14, Table 15, Table 16:
• ROH_, ROL_, tTR_: Changed 5.9 V conditions to 5.5 V.
Table 15,Table 16,Table 17:
• Added tTPD10-90 specification.
Table 16, Table 17:
• In footnotes, changed 5.9 V to 5.5 V.
Table 18 (EBI pad output electrical specification):
• Replaced this table “EBI output driver electrical characteristics” with new table “EBI pad
electrical specification”.
Table 19 (I/O consumption)
• IRMS_EBI: In Conditions column, changed 66MHz references to 66.7MHz. Removed
CDRV = 6 pF condition row.
• IDYN_EBI: revised specification.
Electrical characteristics—I/O pad current specification
Section 3.7, I/O pad current specification: Changed the first note: from “In order to ensure
correct functionality for SENT, the sum of all pad usage ratio within the SENT segment
should remain below 50%.” to “In order to maintain the required input thresholds for the
SENT interface, the sum of all I/O pad output percent IR drop as defined in the I/O Signal
Description table, must be below 50 %. See the I/O Signal Description attachment.”
Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics
Table 20 (Reset electrical characteristics):
• |IWPU| parameter, changed Min value from “25” to “23” and Max value from “100” to “82”
uA.
• |IWPD| parameter, changed Min value from “25” to “40” and Max value from “100” to
“130” uA.
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Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Electrical characteristics—Oscillator and FMPLL
Section 3.12, Oscillator and FMPLL
• Updated text to reflect that there is one FMPLL on the chip.
Table 22 (PLL1 electrical characteristics)
• fPLL1PHI parameter, changed Max freq from “200” MHz to “600” MHz.
• First footnote, changed “FXOSC” to “XOSC”.
Table 23 (External Oscillator electrical specifications):
• Added footnote to both VIHEXT and VILEXT parameter column “Applies to an external
clock input and not to crystal mode”.
• Added footnote to VILEXT parameter column “This parameter is guaranteed by design
rather than 100% tested.”
• VILEXT parameter, changed “External Reference” to “External Clock Input”.
• Combined CS_XTAL and CS_EXTAL parameters into one specification CS_xtal, updated
Min and Max values and removed the “BG292” condition.
Table 24 (Selectable load capacitance):
• Removed last 16 rows “10000” to “11111”.
• Changed footnote 2 from “Values in this table do not include 8 pF routing and ESD
structure on die and package trace capacitance.” to “Values in this table do not include
the die and package capacitances given by Cs_xtal/Cs_extal in Table 23 (External
Oscillator electrical specifications).”
• Table 25 (Internal RC Oscillator electrical specifications): fvar_SW parameter added
footnote “IRC software trimmed accuracy is performed either with the CMU_0 clock
monitor, using the XOSC as a reference or through the CCCU (CAN clock control Unit),
extracting reference clock from CAN master clock. Software trim must be repeated as
the device operating temperature varies in order to maintain the specified accuracy.”
Electrical characteristics—ADC specifications
Table 36 (ADC pin specification,):
• ILK_INUD, ILK_INUSD, ILK_INREF, ILK_INOUT: Removed footnote “Leakage current is a
parameter potentially showing variation with process maturity. This table is based on
current process model, and will be validated when preliminary silicon data of ADC
modules and I/O module is available.”
• Parameter ILK_INOUT description column, changed “MEDIUM” output buffer with
“GPIO” output buffer.
Table 27 (SARn ADC electrical specification):
• Added new condition for “VPRECH” - “VPRECH = VDD_HV_ADR/2 TJ < 150 °C
CTRn[PRECHG] > 2”
• IADCREFL specification: added VDD_HV_ADR_S <= 5.5 V to all modes in condition
column.
• DNL, “Differential non-linearity” parameter, conditions column, replaced “—” with
“VDD_HV_ADV > 4V, VDD_HV_ADR_S > 4V”.
• INL: Conditions column, first row, removed TJ < 150C and added 4.0V <
VDD_HV_ADV_S < 5.5V. Conditions column, second row, removed TJ < 150C and added
VDD_HV_ADV_S = 2V.
MPC5777M Microcontroller Data Sheet, Rev. 6
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Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Electrical characteristics—ADC specifications (con’t)
Table 28 (SDn ADC electrical specification):
• Removed the ILK_IN specification from table.
• For SNRDIFF150, SNRDIFF333, and SNRSE150 specifications, added reference to “S/D
ADC is functional in the range 3.0 V < VDD_HV_ADR_D , 4.0 V. . .” footnote.
• Moved VREF_BG_T, VREF_BG_TC and VREF_BG_LR specifications from ADC pin
specification table to Device operating table.
• Removed IBG specification as it is already provided in the DC electrical table.
• Maximum value of parameter “GAIN” changed from “16” to “15”
Table 28 (SDn ADC electrical specification):
• Changed footnote from “The ±1% passband ripple specification is equivalent to 20 *
log10 (0.99) = 0.87 dB.” to “The ±1% passband ripple specification is equivalent to 20
* log10 (0.99) = 0.087 dB.”
• Max value of GROUP modified for all values of OSR.
• tLATENCY, tSETTLING and tODRECOVERY: “HPF = ON” and “HPF = OFF” conditions added.
New max values.
• Added SINAD and THD specifications.
• RESOLUTION specification, added footnote “When using a GAIN setting of 16, the
conversion result will always have a value of zero in the least significant bit. The gives
an effective resolution of 15 bits.”
• GAINspecification, changed Max value from ”1” % to “1.5” %, “0.1” % to “5” mV, “0.25”
% to “7.5” mV, and “0.5 %” to 10” mV”.
• VOFFSETspecification, added 3 “After calibration” conditions, VDD_HV_ADR_D < 5%
VDD_HV_ADV_D < 10% TJ < 50 °C, Max value of “5” mV, VDD_HV_ADR_D < 5%
VDD_HV_ADV_D < 10% TJ < 100 °C, Max value of “7.5” mV and “After calibration”
conditions, VDD_HV_ADR_D < 5% VDD_HV_ADV_D < 10% TJ < 150 °C, Max value of
“10” mV.
• Changed all SNR specification “Unit”s from “dB” to “dBFS”.
• Changed SFDR specification “Unit” from “dB” to “dBc”.
• ZIN specification, changed footnote to “Input impedance is valid over the full input
frequency range.Input impedance is calculated in megaohms by the formula
25.6/(Gain * fADCD_M).
• Common mode rejection ratio parameter changed symbol from “—” to “Vcmrr”.
• Anti-aliasing filter parameter, changed symbol “—” to “RCaaf”.
• Stop band attenuation parameter, changed symbol “—” to “Frolloff”.
• Changed footnote in 13 “full input range (specified by Vin)” to “full input frequency
range.”
• Changed in footnote 15 “0.873” dB to “0.087” dB.
• fADCD_M, changed “S/D clock 3(4)” to “S/D Modulator Input Clock” and replaced “—”
with “4” in Min column.
• fADCD_S changed “conversion rate'” to “output conversion rate”.
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Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Electrical characteristics—LFAST electrical specifications
Table 30 (LVDS pad startup and receiver electrical characteristics,):
• |VI| specification, Differential input voltage parameter, added footnote 12 “The
LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to
ensure proper LFAST receive timing.”
Table 31 (LFAST transmitter electrical characteristics,):
• |VOD|: removed the delta from symbol. Changed values to Min = 110, Typ = 171, Max
= 285 and removed the “+/-” from each value.
• tTR: changed “(10%–90% of swing)” to “(absolute value of the differential output
voltage swing).”
Table 32 (MSC/DSPI LVDS transmitter electrical characteristics ,):
• |VOD|: removed the delta from symbol. Changed values to Min = 150, Typ = 214, Max
= 400 and removed the “+/-” from each value.
• tTR: Changed “(10%–90% of swing)” to “(absolute value of the differential output
voltage swing).”
Table 33 (LFAST PLL electrical characteristics):
• |VI| specification, Differential input voltage parameter, added footnote 12 “The
LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to
ensure proper LFAST receive timing.”
Table 32 (MSC/DSPI LVDS transmitter electrical characteristics ,), Rise/Fall time
parameter:
• Changed “(10%–90% of swing)” to (absolute value of the differential output voltage
swing).
Table 33 (LFAST PLL electrical characteristics):
• Changed footnote 2, from “320” to “640” MHz frequency.
Electrical characteristics—Aurora LVDS electrical characteristics
Table 34 (Aurora LVDS electrical characteristics,):
• Removed VDD_HV_IO_BD and VDD_LV specifications as they are supplied in the device
operating conditions table.
• Changed “CAC” specification name to “Cac_clk”.
• Added specification “Cac_tx”.
MPC5777M Microcontroller Data Sheet, Rev. 6
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Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Electrical characteristics—Power management: PMC, POR/LVD, sequencing
Figure 20 (Recommended supply pin circuits):
• For VDD_LV supply: Changed "nxClv" to "Clv."
Table 35 (Device power supply integration):
• CHV_IO removed footnote.
• CHV_FLA parameter, added footnote “Start-up time of the internal flash regulator from
release of the LVD360 is worst case 500 us. This is based on the typical CHV_FLA bulk
capacitance value.”
• CLV: Changed the 3 for Bypass capacitance at pin to "Note3." Changed parameter
"Bypass capacitance at pin" to "Total bypass capacitance at external pin."
• Significantly revised CHV_PMC_BYP, including changing spec name to CHV_PMC, min
value to 2.2 µF (was 200 nF), and typ value to 4.7 µF (was “—”). Added footnote "For
noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF
between VDD_HV_PMC and VSS_HV."
Table 36 (Flash power supply):
• VDD_HV_FLA, after trimming, Min value “3.2” changed to “3.15”. Added two notes.
• Removed IREG_FLA specification.
Table 39 (Functional terminals state during power-up and reset):
• Changed “TRST” to “JCOMP.”
MPC5777M Microcontroller Data Sheet, Rev. 6
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Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Electrical characteristics—Device voltage monitoring electrical characteristics
Table 37 (Voltage monitor electrical characteristics):
• VPORUP_LV Rising voltage (power up) condition, changed Min value “1040” to “1111”
and Max value “1180” to “1235”.
• VPORUP_LV Falling voltage (power down) condition, changed Min value “960” to “1015”
and Max value “1100” to “1125”. Added footnote.
• VLVD096 “960” to “1015” and Max value “1100” to “1145”.
• VLVD108 changed Min value “1080” to “1125” and Max value “1140” to “1235”.
• VLVD112 changed Min value “1110” to “1175 and Max value “1180” to “1235”.
• VHVD140 changed Min value “1320” to “1385” and Max value “1440” to “1475”.
• Added new specification VHVD145.
• Added “HVD140 does not cause reset” at end of footnote “HVD is released after
tVDRELEASE temporization when lower threshold is crossed, HVD is asserted
tVDASSERT after detection when upper threshold is crossed.”
• ]VPORUP_HV, added footnote “the PMC supply also needs to be below 5472 mV
(untrimmed HVD600)”. Added new conditions: Rising voltage (power up) on IO JTAG,
and Osc supply, Rising voltage (power up) on ADC supply, and Hysteresis on
Power-up.
• VPORUP_HV: Changed Falling voltage (power down) minimum value to “2850” (was
“2680”) and maximum value to 3162 (was “2980”).
• Revised Falling voltage footnote to read “Untrimmed LVD300_A will be asserted first
on power down” (was “Assume all LVDs except LVD270 on HV supplies disabled”).
• VLVD295 Rising voltage condition changed Max value “3100” to “3120”.
• VLVD295 Falling voltage condition changed Min value “2950” to “2920” and Max value
“3080” to “3100”.
• VHVD360 Rising voltage condition changed Min value “3420” to “3435” and Max value
“3610” to “3650”.
• VHVD360 Falling voltage condition changed Min value “3400” to “3415”.
Electrical characteristics—Flash memory electrical characteristics
Section 3.15, Flash memory electrical characteristics:
• This section completely revised.
Electrical characteristics—AC specifications—Debug and Calibration
Table 46 (JTAG pin AC electrical characteristics,):
• Added footnote “JTAG timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and
maximum loading per pad type as specified in the I/O section of the data sheet.”
Table 47 (Nexus debug port timing)
• Footnote 1 changed to “Nexus timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and
maximum loading per pad type as specified in the I/O section of the data sheet.”
• Changed “TDI” to “TDI/TDIC,” “TMS” to “TMS/TMSC,” and “TDO” to “TDO/TDOC.”
Figure 27 (Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing):
• Changed “TDI” to “TDI/TDIC,” “TMS” to “TMS/TMSC,” and “TDO” to “TDO/TDOC.”
MPC5777M Microcontroller Data Sheet, Rev. 6
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Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Electrical characteristics—AC specifications—Fast Ethernet Controller (FEC)
Table 61 (MII serial management channel timing):
• Added footnote to “Value” column: “Output parameters are valid for CL = 25 pF, where
CL is the external load to the device. The internal package capacitance is accounted
for, and does not need to be subtracted from the 25 pF value.”
Table 63 (RMII transmit signal timing,):
• Added footnote to “Value” column “Output parameters are valid for CL = 25 pF, where
CL is the external load to the device. The internal package capacitance is accounted
for, and does not need to be subtracted from the 25 pF value.”
• Added footnote to table title: “RMII timing is valid only up to a maximum of 150 oC
junction temperature.”
Electrical characteristics—AC specifications—FlexRay
Section 3.16.4, FlexRay timing:
• Removed reference to “292 MAPBGA”.
• Removed “ . . . and subject to change per the final timing analysis of the device” from
FlexRay specification sentence.
Table 66 (RxD input characteristics):
• Added footnote: “FlexRay RxD timing is valid for all input levels and hysteresis
disabled."
Electrical characteristics—AC specifications—EBI
Table 69 (Bus Operation Timing):
• Changed bus frequency in table heading to “66.7 MHz” (was “66 MHz”).
• Footnote 1, added "with DSC = 0b10 for ADDR/CTRL and DSC = 0b11 for
CLKOUT/DATA."
• Footnote 3, changed “[Clock Register TBD]” TO “CGM_SC_DC4 register”.
• Footnote 4, changed "VDDE" to "VDD_HV_IO_EBI or VDD_HV_IO_FLEXE."
• Spec 5, Characteristic column, added “ADDR[8:11]/WE[0:3]/BE[0:3],” “BDIP,” and
overbar on CS, OE, and TS. Changed "ADDR[8:31]" to "ADDR[12:31]."
• Spec 6, Characteristic column, added “ADDR[8:11]/WE[0:3]/BE[0:3]”, “BDIP,” overbar
on CS, OE, TS, and footnote “One wait state must be added to the output signal valid
delay for external writes.” Changed "ADD[8:31]" to "ADDR[12:31]."
• Spec 7, change Min value from “6.0” to “7.0” ns.
• Spec 8, Characteristic column, changed to “DATA[0:31]”.
• Removed cut 1 footnotes associated with output delay and setup time (total 2).
Figure 50 (D_CLKOUT Timing)
Figure 51 (Synchronous Output Timing)
Figure 52 (Synchronous Input Timing):
• Changed “VDDE” to “VDD_HV_IO_EBI” throughout.
Electrical characteristics—AC specifications—I2C
Section 3.16.8, “I2C timing:
New section.
Electrical characteristics—AC specifications—GPIO delay
Section 3.19.10, GPIO delay timing
• New section
MPC5777M Microcontroller Data Sheet, Rev. 6
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Table 76. Revision history (continued)
Revision
Date
Description of changes
3
3/2014
Package characteristics
Section 4, Package characteristics:
• Removed the “292 MAPBGAcase drawing” figures.
• Table 73 (Package case numbers): Removed the 292MAPBGA row.
Electrical characteristics—Thermal Characteristics
Table 74 (Thermal characteristics):
• Removed “292 Value” column.
Ordering Information
Table 75 (Orderable part number summary)
• Changed Freescale part numbers: 416 MAPBGA PD to TEPBGA
“PPC5777MK0MVU8A” (was PPC5777MQK0MVU8), 512 TEPBGA PD to
“PPC5777MK0MVA8A” (was PPC5777MQK0MVA8), 416 MAPBGA ED to TEPBGA
“PPC5777M2K0MVU8A” (was PPC5777M2K0MVU8), and 512 TEPBGA ED to
“PPC5777M2K0MVA8A” (was PPC5777M2K0MVA8)
• Removed KGD and Production PD rows.
• Removed “Flash/SRAM,” “Emulation RAM,” and “Frequency” columns.
Figure 61 (Product code structure):
• Package Code, added “VA = 512 TEPBGA Pb-Free”.
• Package Code, added “VU = 416 TEPBGA Pb-Free”.
• Miscellaneous, added “2 = Emulation Device”.
• Changed “Tape and Reel” to “Suffix” and added “A = cut2.0 revision”.
• In “Fab and Mask Revision” codes, changed “K = TBD” to “K = TSMC.”
4
9/2014
Throughout
• Removed parameter classifications from specification tables.
• Editorial changes and improvements.
Introduction
• In Figure 1 (Block diagram), added “LFAST & SIPI” block to 50 MHz concentrator.
• In Figure 2 (Periphery allocation), changed block to “2 x SIPI” (was “SIPI_0)” and
removed double arrow on its right side.
Electrical characteristics—Operating conditions
• Extensive revisions to Table 8 (Device operating conditions).
MPC5777M Microcontroller Data Sheet, Rev. 6
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Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
4
9/2014
Electrical characteristics—DC electrical specification
• In Section 3.1, Introduction, added the following to note text: "VDD_HV_ADV refers to
ADC supply pins VDD_HV_ADV_S and VDD_HV_ADV_D. VDD_HV_ADR refers to ADC
reference pins VDD_HV_ADR_S and VDD_HV_ADR_D. VSS_HV_ADV refers to ADC ground
pins VSS_HV_ADV_S and VSS_HV_ADV_D. VSS_HV_ADR refers to ADC reference pins
VSS_HV_ADR_S and VSS_HV_ADR_D."
• In Table 10 (DC electrical specifications), changed IDD_HV_PMC maximum for PMC only
condition (was 5 mA, is 25 mA). Added “This includes PMC consumption, LFAST PLL
regulator current, and Nwell bias regulator current” to footnote associated with this
value.
• In Table 10 (DC electrical specifications), changed IDD_LV maximum to 1140 mA (was
600 mA) and added “VDD_LV = 1.325 V” to conditions.
• In Table 10 (DC electrical specifications), added IDDAPP_LV specification.
• In Table 10 (DC electrical specifications), changed the conditions for IDDSTBY_RAM and
IDDSTBY_REG (were “...to 6 V...”, are “...to 5.5 V...”).
• In Table 10 (DC electrical specifications), IDDSTBY_RAM specification: changed max
value for 40°C condition to 60 µA (was 40). Changed max value for 85°C condition to
100 µA (was 60).
• In Table 10 (DC electrical specifications), VSTBY_BO specification: changed min value
to 0.9 V (was 0.8).
Electrical characteristics—I/O pad current specification
• Table 12 (I/O input DC electrical characteristics), Table 13 (I/O pull-up/pull-down DC
electrical characteristics), Table 14 (WEAK configuration output buffer electrical
characteristics), Table 15 (MEDIUM configuration output buffer electrical
characteristics), Table 16 (STRONG configuration output buffer electrical
characteristics), Table 17 (VERY STRONG configuration output buffer electrical
characteristics), Table 19 (I/O consumption) added the following footnote to Conditions
heading: “During power up operation, the minimum required voltage to come out of
reset state is determined by the VPORUP_HV monitor, which is defined in the voltage
monitor electrical characterstics table. Note that the VPORUP_HV monitor is connected
to the VDD_HV_IO_MAIN0 physical I/O segment.”
• Table 12 (I/O input DC electrical characteristics): VHYSTTL specification: changed min
value to 0.275 (was 0.3). VHYSAUT specification: changed min value to 0.4 (was 0.5).
• Table 12 (I/O input DC electrical characteristics), changed VIHCMOS_H min value to
“0.70 * VDD_HV_IO” (was 0.65 * VDD_HV_IO).
• In Table 12 (I/O input DC electrical characteristics), changed VIHAUT min value to 3.9 V
(was 3.8).
• Table 12 (I/O input DC electrical characteristics), revised ILKG and ILKG_EBI rows.
MPC5777M Microcontroller Data Sheet, Rev. 6
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Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
4
9/2014
Electrical characteristics—I/O pad current specification
• Table 14 (WEAK configuration output buffer electrical characteristics), ROH_W and
ROL_W: changed min value to 517 (was 560) and max value to 1052 (was 1040).
• Table 15 (MEDIUM configuration output buffer electrical characteristics), ROH_M and
ROL_M: changed min value to 135 (was 140).
• Table 16 (STRONG configuration output buffer electrical characteristics), ROH_S and
ROL_S: changed min value to 30 (was 35) and max value to 77 (was 65).
• Table 17 (VERY STRONG configuration output buffer electrical characteristics),
revised ROH_V and ROL_V conditions.
• Table 17 (VERY STRONG configuration output buffer electrical characteristics), ROH_V
and ROL_V: changed max values to 72 (was 60) and 90 (was 75).
• Table 18 (EBI pad output electrical specification), ROH_EBI_GPIO and ROL_EBI_GPIO:
changed max value to 400 (was 260).
• In Table 18 (EBI pad output electrical specification): VIHCMOS_H_EBI specification:
changed max value to “VDD_HV_IO_EBI + 0.3” (was “VDD_HV_IO + 0.3”). ROH_EBI_GPIO
specification: changed condition to “4.5 V < VDD_HV_IO_EBI < 5.5 V” (was “3.0 V <
VDD_HV_IO < 3.6 V”). ROL_EBI_GPIO specification: changed condition to “4.5 V <
VDD_HV_IO_EBI < 5.5 V” (was “3.0 V < VDD_HV_IO < 3.6 V”).
Electrical characteristics—Oscillator and FMPLL
• In Table 23 (External Oscillator electrical specifications), deleted the transconductance
specification (gm).
Electrical characteristics—ADC specifications
• Table 26 (ADC pin specification), ILK_INUD specification: changed TJ < 40 °C condition
max value to 50 nA (was 70). Changed TJ< 150 °C condition max value to 150 nA (was
220).
• In Table 27 (SARn ADC electrical specification): added condition rows for full and fast
precharge to tADCPRECH, revised condition entries for VPRECH.
• In Table 28 (SDn ADC electrical specification), changed the max value for tLATENCY at
HPF = OFF (was 2*GROUP,, is GROUP).
• In Table 28 (SDn ADC electrical specification), changed the max value for GAIN (was
15, is 16).
• Table 28 (SDn ADC electrical specification), SNRSE150: changed GAIN=1 min value to
72 (was 74), GAIN=2 min value to 69 (was 71), GAIN=4 min value to 66 (was 68),
GAIN=8 min value to 63 (was 65), and GAIN=16 min value to 60 (was 62).
• Table 28 (SDn ADC electrical specification), GROUP specification: changed OSR = 75
max value to 696 Tclk (was 746), changed OSR = 96 max value to 946.5 Tclk (was
946.4).
• In Table 28 (SDn ADC electrical specification), added footnote to parameter column for
tLATENCY.
Electrical characteristics—Power management: PMC, POR/LVD, sequencing
• In Section 3.16, Power management: PMC, POR/LVD, sequencing, replaced PMC
operating conditions and external regulators supply voltage table with a cross
reference to Table 8 (Device operating conditions).
• In Table 35 (Device power supply integration), changed minimum VDD_LV external
capacitance footnote to “variation over voltage, temperature, and aging” (was
“variation over process, voltage, temperature, and aging.”)
• In Table 36 (Flash power supply), revised table footnotes and added new “After
trimming; 25°C < TJ  150°C” condition to VDD_HV_FLA.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
163
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
4
9/2014
Electrical characteristics—Device voltage monitoring electrical characteristics
• In Table 37 (Voltage monitor electrical characteristics), revised the entries for VLVD108
and VLVD145.
Electrical characteristics—Flash memory electrical characteristics
• Multiple changes throughout Section 3.15, Flash memory electrical characteristics.
Electrical characteristics—AC specifications—GPIO delay
• In Table 72, changed parameter to “Delay from SIUL2 MSCR register bit update to pad
function enable at the input of the I/O pad” (was “Delay from MSCR bit update to pad
function enable”).
Electrical characteristics—Thermal Characteristics
• Updated Table 74 (Thermal characteristics).
Ordering Information
• Revised Table 75 (Orderable part number summary).
5
6/2015
Electrical characteristics—Absolute maximum ratings
Table 6 (Absolute maximum ratings)
• VDD_LV_BD: corrected footnote numbering.
• Revised footnote (“Allowed 1.38– 1.45 V...”) text to 1.38 (was 1.375). Revised footnote
(“1.32 – 1.38 V range...”) text to 1.38 (was 1.375) and “1.326 V at maximum” (was
“1.288 V at maximum”).
Electrical characteristics—Operating conditions
Table 8 (Device operating conditions)
• Consolidated duplicate footnotes throughout table.
• VDD_HV_ADV: added footnote (“SAR ADC only...”) to LVD disabled conditions.
• Revised VDD_HV_ADR_D row.
• Changed VRAMP_LV max value to 100 V/mx (was 500).
• Revised footnote (“RAM data retention is guaranteed at a voltage...”) (was “RAM data
retention is not guaranteed below...”).
Table 9 (Emulation (buddy) device operating conditions)
• Changed VRAMP_LV_BD max value to 100 V/ms (was 500).
Electrical characteristics—DC electrical specification
Table 10 (DC electrical specifications)
• IDD_MAIN_CORE_AC: changed max value to 115 mA (was 105).
• IDD_CHKR_CORE_AC: changed max value to 80 mA (was 45).
• IDDSTBY_REG: changed max value to 50 µA (was 30).
• VSTBY_BO specification: changed minimum to no value (was 0.9 V) and maximum to
0.9 V (was no value) with footnote (“VSTBY_BO is the maximum voltage...”).
• VDD_LV_STBY_SW: changed min value to 0.93 V (was 0.95).
Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics
Table 20 (Reset electrical characteristics)
• Changed VIH min value to 2.2 V (was 2.0).
• Changed WFNMI max value to 15 ns (was 20).
MPC5777M Microcontroller Data Sheet, Rev. 6
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NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
5
6/2015
Electrical characteristics—I/O pad current specification
Replaced Figure 18 (I/O output DC electrical characteristics definition).
Table 12 (I/O input DC electrical characteristics)
• VIHAUT specification: changed min value to 3.8 V.
• VHYSTTL: Changed min value to 0.250 V (was 0.275). Removed footnote (“Minimum
hysteresis...”) from min value.
Table 13 (I/O pull-up/pull-down DC electrical characteristics)
• Added “AUTO” and “CMOS” designations to conditions for |IWPU| and |IWPD|.
• |IWPU| specification: changed final condition row to “VIN = 0.35*VDD_HV_IO” (was “VIN =
0.65*VDD_HV_IO”).
Table 14 (WEAK configuration output buffer electrical characteristics)
• ROH_W specification: changed min value to 520  (was 517).
• ROL_W specification: changed min value to 520  (was 517).
Table 15 (MEDIUM configuration output buffer electrical characteristics), Table 16
(STRONG configuration output buffer electrical characteristics), and Table 17 (VERY
STRONG configuration output buffer electrical characteristics)
• Changed specification to tTPD50-50 and revised row.
Table 16 (STRONG configuration output buffer electrical characteristics)
• Added tSKEW_S specification.
Table 17 (VERY STRONG configuration output buffer electrical characteristics)
• Added IDCMAX_VS specification.
Table 18 (EBI pad output electrical specification)
• Removed all specifications in Input Specifications section and changed table title to
“EBI Pad Output Electrical Specifications.”
• tPD_EBI: changed parameter to “50% – 50% threshold...” (was “50% - 10% 90%
threshold...”) and changed max value to 4.0 ns (was 5.5).
• ROH_EBI_GPIO specification: change min value to 100  (was 150).
Electrical characteristics—Oscillator and FMPLL
Table 21 (PLL0 electrical characteristics)
• Added footnote (“fPLL0IN frequency must be...”) to fPLL0IN parameter.
• Changed footnote text to “Noise on the VDD_LV supply...” (was “VDD_LV noise due...”).
• Added footnote (“PLL jitter is guaranteed when...”) to PLL0PHISPJ|, PLL0PHI1SPJ|, and
PLL0LTJ specifications.
• Added fPLL0VCOFR specification.
Table 22 (PLL1 electrical characteristics),
• Added fPLL1VCOFR specification.
Table 24 (Selectable load capacitance)
• Significant changes throughout table.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
165
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
5
6/2015
Electrical characteristics—ADC specifications
In Table 27 (SARn ADC electrical specification)
• IADCREFH specification: changed min value for Run mode tconv  5 µs condition to 7 µA
(was 3.5). Changed max value for Power Down mode condition to 6 µA (was 1).
• IADV_S specification, Power Down mode: changed max value to 1.0 mA (was 0.04).
• INL and DNL rows: removed injection current footnote.
• TUE12 row: changed footnote text to “This parameter is guaranteed...” (was “TUE, INL,
and DNL are granted...”). Removed TJ < 150 °C, VDD_HV_ADV_S > 4 V,
VDD_HV_ADR_S > 4 V condition row.
In Table 28 (SDn ADC electrical specification)
• VOFFSET: Changed parameter name to “Input Referred Offset Error” (was “Conversion
Offset”) and added footnote (“Conversion offset error must be...”).
• SNRDIFF150, SNRDIFF333, SNRSE150: removed footnote (“SNR degraded by 3dB...”)
and changed conditions range to 4.5 (was 4.0).
• SNRSE150 specification: revised min values for each condition. Added footnote (“This
parameter is guaranteed...”).
• For first footnote “S/D ADC is functional in the range...” changed voltage range to
3.6 V–4.5 V (was 3.6 V < VDD_HV_ADV_D < 4.0 V) and added “Degraded SNR value
based on simulation.”
• For second footnote “S/D ADC is functional in the range...” changed voltage range to
3.0 V–4.5 V and added “Degraded SNR value based on simulation.”
• Vcmrr specification: changed min value to 54 dB (was 20 dB).
• GROUP specification: increased the max value for each condition by 3 Tclk.
• IADR_D specification: changed max value to 30 µA (was 20). Added “fADCD_M =
14.4 MHz” to condition.
Electrical characteristics—LFAST electrical specifications
Table 30 (LVDS pad startup and receiver electrical characteristics,)
• Revised entire RIN specification row.
Table 31 (LFAST transmitter electrical characteristics,)
• fDATA: Changed max value to "312/320" (was 320) and added footnote.
Table 33 (LFAST PLL electrical characteristics)
• Changed ERRREF and DCREF parameter descriptions to “PLL input reference clock”
(was “PLL reference clock”).
Electrical characteristics—Power management: PMC, POR/LVD, sequencing
Table 36 (Flash power supply)
• Removed VDD_HV_PMC row (this specification documented in Table 8 (Device
operating conditions).
Electrical characteristics—Flash memory electrical characteristics
• Added Section 3.15.7, Flash read wait state and address pipeline control settings.
Electrical characteristics—AC specifications—DSPI
• Substantial revisions to Section 3.16.2, DSPI timing with CMOS and LVDS pads.
Electrical characteristics—AC specifications—FlexRay
Table 66 (RxD input characteristics)
• Revised footnote (“FlexRay RxD timing is valid . . .”).
MPC5777M Microcontroller Data Sheet, Rev. 6
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NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
5
6/2015
Ordering Information
Table 75 (Orderable part number summary)
• Revised ED footnote (“‘ED’ refers to . . .”).
6
6/2016
Introduction
Section 1.3, Device feature
• Changed the name of the section to Device feature.
• Table 1 (MPC5777M feature) Changed the name of the table to MPC5777M feature.
Figure 1
• Removed the 50 MHz from the concentrator box and added 50 MHz and 100 Mhz to
the connection arrows.
Electrical characteristics—I/O pad specification
Section 3.7, I/O pad current specification
• Added paragraph (In order to ensure device reliability....., and In order to ensure device
functionality....).
• Removed the entries IRMS_SEG and IDYN_SEG in Table 19 (I/O consumption).
Table 12 (I/O input DC electrical characteristics)
• VHYSTTL specification: Changed min value to 0.275 V (was 0.250 V)
Electrical characteristics—Oscillator and FMPLL
Table 25 (Internal RC Oscillator electrical specifications)
• Added fTRIM specification.
Electrical characteristics—ADC Specifications
Table 28 (SDn ADC electrical specification),
• ZDIFF, ZCM and VINTCM specifications added. RBIAS specification has been updated.
Electrical characteristics—AC specifications—FlexRay
Table 66 (RxD input characteristics)
• Changed footnote (“FlexRay RxD timing is valid . . .”).
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
167
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Document Number: MPC5777M
Rev. 6
06/2016
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