Freescale Semiconductor Product Preview Document Number: MC33772SM Rev. 1.0, 9/2015 Battery Cell Controller IC The 33772 is a SMARTMOS lithium ion Battery Cell Controller IC designed for automotive applications, such as hybrid electric (HEV) and electric vehicles (EV) along with industrial applications, such as energy storage systems (ESS), and uninterruptible power supply (UPS) systems. The device performs ADC conversions of the differential cell voltages and current, as well as battery Coulomb counting and battery temperature measurements. The information is digitally transmitted through SPI or transformer isolation to a microcontroller for processing. Features • 5.0 V ≤ VPWR ≤ 30 V operation, 40 V transient • 3 to 6 cells management • Isolated 2.0 Mbps differential communication or 4.0 Mbps SPI • Addressable on initialization • Synchronized cell voltage/current measurement with Coulomb count • Total stack voltage measurement • Seven GPIO/temperature sensor inputs • 5.0 V at 5.0 mA reference supply output • Automatic over/undervoltage & temperature detection routable to fault pin • Integrated Sleep mode over/undervoltage & temperature monitoring • Onboard 300 mA passive cell balancing with diagnostics • Hot plug capable • Detection of internal and external faults, as open lines, shorts, and leakages • Single chip ASIL C capable • Fully compatible with the MC33771 for max 14 cells 33772 BATTERY CELL CONTROLLER IC AE SUFFIX (PB-FREE) 98ASA00173D 48-PIN LQFP-EP Applications • Automotive: 12 V and high-voltage battery packs • E-bikes, e-scooters • Energy storage systems • Uninterruptible power supply (UPS) MC33772 VPWR1 VPWR2 RDTX _OUT+ RDTX_OUTVCOM CT6 VCOM CB6 CB6:5_C CT5 VANA AGND DGND CTn 6 Cell Voltage Measure CBn CT1 CB2:1_C CB1 CTREF ISENSE+ Battery Reference CGND VPRE FAULT SDA SDL SPI_COM_EN VCP GNDCP RESET CSB SO SI/RDTX _IN+ SCLK/RDTX _IN- Battery Reference EEPROM GPIOx CSB MISO MOSI SCLK VCOM Current Measure ISENSE- Battery Reference GNDSUB GNDFLG GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 Battery Reference Figure 1. Simplified Application Diagram of SPI Communication Context * This document contains certain information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2015. All rights reserved. MCU VPRE MC33772 VPWR1 VPWR2 CT6 CB6 CB6:5_C CT5 CTn 6 Cell Voltage Measure CBn CT1 CB2:1_C CB1 VCOM VCOM CGND VPRE VANA AGND DGND FAULT SDA SDL SO CSB SPI_COM_EN RESET SI/RDTX _IN+ Battery Reference Battery Reference EEPROM Battery Reference T1 1:1 CTREF ISENSE+ ISENSE- Battery Reference RDTX _OUT+ RDTX_OUT- GNDSUB GNDFLG SCLK/RDTX _INVCP GNDCP GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 VCOM Battery Reference MC33772 VPWR1 VPWR2 CT6 CB6 CB6:5_C CT5 CTn 6 Cell Voltage Measure CBn CT1 CB2:1_C CB1 CTREF ISENSE+ Current Measure ISENSE- Battery Reference GNDSUB GNDFLG RDTX _OUT+ RDTX_OUT- VCOM VCOM CGND VPRE VANA AGND DGND FAULT SDA SDL SO CSB SPI_COM_EN RESET SI/RDTX _IN+ Battery Reference Battery Pack Controller Battery Reference EEPROM MCU Battery Reference T1 T1 SPI1 1:1 1:1 SCLK/RDTX _INVCP GNDCP GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 MC33664 SPI2 VCOM Battery Reference Figure 2. Simplified Application Diagram of Twisted Pair Line Communication with Isolation Transformers 33772 2 Analog Integrated Circuit Device Data Freescale Semiconductor Table 1. Orderable Part Variations Part Number (1) Communication Type PC33772ASP1 SPI version PC33772ATP1 TPL version PC33772ASP3 SPI version PC33772ATP3 TPL version PC33772ASP5 SPI version PC33772ATP5 TPL version Calibration Type Temperature Number of Cells Package Type N Type F -40 °C to 125 °C Three to six cells 48 Pin LQFP-EP Type T Notes 1. To order parts in Tape & Reel, add the R2 suffix to the part number. VPRE VDDIO VCP GNDCP DGND VANA AGND VCOM CGND RESET MC33772 VPRE VPWR1 VPWR2 VPWR OV/LV/UV/POR TSD VPRE, VCP, VDDIO VCP 100kHz Osc VCOM, VANA, Vbg_HP Stack Voltage 6MHz Osc VANA TEMP Vbg 100kO CT_6 CB_6 CB Control & Diagnostics SPI_COM_EN VCP_CNTL CB_6:5_C 100kO CB Control & Diagnostics CB_5 CT_5 RDTX_OUTRDTX_OUT+ Digital Control CT_4 CB_4 Mux CB Control & Diagnostics Data RegistersSI ADC1-A 14 Bit S? CB_4:3_C & SI/+ SI/RDTX_IN+ SCLK/RDTX_IN- SO SCLK CB Control & Diagnostics Communication CB_3 CT_3 Interface CLK/VCOM CS ADC1-B 14 Bit S? CT_2 CB_2 VCOM CSB SO CB Control & Diagnostics CB_2:1_C CB Control & Diagnostics CB_1 CT_1 CT_REF AN0_GPIO0 AN1_GPIO1 AN2_GPIO2 AN3_GPIO3 AN4_GPIO4 AN5_GPIO5 AN6_GPIO6 VPRE FAULT 100kO GPIO Port Control VCOM 100kO 100kO SDA SCL Auto Input Swap ISENSE + Zero PGA ADC2 ISENSE GNDSUB GNDFLAG Figure 3. Simplified Internal Block Diagram 33772 Analog Integrated Circuit Device Data Freescale Semiconductor 3 GNDSUB VANA DGND AGND ISENSE- ISENSE+ AN6/GPIO6 AN5/GPIO5 AN4/GPIO4 AN3/GPIO3 AN2GPIO2 AN1/GPIO0 48 47 46 45 44 43 42 41 40 39 38 37 Transparent Top View VPWR2 1 36 AN1/GPIO1 VPWR1 2 35 RDTX_OUT+ FAULT 3 34 SI/RDTX_IN+ VPRE 4 33 SCLK/RDXT_IN- VCP 5 32 RDTX_OUT- GNDCP 6 31 CGND CT_6 7 30 VCOM CB_6 8 29 CSB CB_6:5_C 9 28 VDDIO CB_5 10 27 SO CT_5 11 26 SCL CT_4 12 25 SDA 19 20 21 CB_2:1_C CB_1 CT_1 24 18 CB_2 RESET 17 CT_2 23 16 CT_3 SPI_COM_EN 15 CB_3 22 14 CT_REF 13 CB_4 CB_4:3_C 48 GNDFLAG Figure 4. 33772 Pinout Diagram Table 2. 33772 Pin Definitions Pin Number Pin Name 1 VPWR2 Power input to the 33772 Definition 17 CT_2 Cell pin 2 input. Terminate to LPF resistor 2 VPWR1 Power input to the 33772 18 CB_2 Cell balance driver. Terminate to cell 2 cell balance load resistor 3 FAULT Fault output dependent on user defined internal or external faults. If not used, it must be left open. 19 CB_2:1_C 4 VPRE Pre-regulator voltage. Connect to a 470 nF capacitor 20 CB_1 5 VCP Charge pump capacitor. Connect to a 10 nF 21 CT_1 6 GNDCP Charge pump capacitor ground 22 CT_REF 7 CT_6 Cell pin 6 input. Terminate to LPF resistor 23 SPI_COM_EN 8 CB_6 Cell balance driver. Terminate to cell 6 cell balance load resistor 24 RESET 9 CB_6:5_C Cell balance 6:5 common. Terminate to cell 6 & 5 common pin 25 SDA I2C data 10 CB_5 Cell balance driver. Terminate to cell 5 cell balance load resistor 26 SCL I2C clock 11 CT_5 Cell pin 5 input. Terminate to LPF resistor 27 SO SPI serial output 12 CT_4 Cell pin 4 input. Terminate to LPF resistor 28 VDDIO 13 CB_4 Cell balance driver. Terminate to cell 4 cell balance load resistor 29 CSB 14 CB_4:3_C Cell balance 4:3 common. Terminate to cell 4 & 3 common pin 30 VCOM Communication regulator output, decouple with 2.2 μF ceramic 15 CB_3 Cell balance driver. Terminate to cell 3 cell balance load resistor 31 CGND Communication decoupling ground, terminate to GNDSUB 16 CT_3 Cell pin 3 input. Terminate to LPF resistor 32 RDTX_OUT- Cell Balance 2:1 common. Terminate to cell 2 & 1 common pin Cell balance driver. Terminate to cell 1 cell balance load resistor Cell pin 1 input. Terminate to LPF resistor Cell pin REF input. Terminate to LPF resistor SPI communication enable, pin must be high for SPI to be active. RESET is an active high input. RESET has an internal pull-down. If not used, it can be tied to GND. IO voltage for I2C and SPI interfaces. Voltage level corresponding to Logic 1 are the same as VDDIO SPI chip select Receive/transmit output negative 33772 4 Analog Integrated Circuit Device Data Freescale Semiconductor Table 2. 33772 Pin Definitions(continued) Pin Number 33 Pin Name Definition SCLK/RDTX_IN- SPI clock or receive/transmit input negative 42 AN6/GPIO6 43 ISENSE+ Receive/transmit output positive 44 ISENSE- General purpose analog input or GPIO 45 AGND Analog ground, terminate to GNDSUB General purpose analog input or GPIO 46 DGND Digital ground, terminate to GNDSUB AN2/GPIO2 General purpose analog input or GPIO 47 VANA Precision ADC analog supply. Decouple with ceramic 47 nF ceramic capacitor to AGND 39 AN3/GPIO3 General purpose analog input or GPIO 48 GNDSUB Ground reference for device, terminate to reference of battery cluster. Note: GNDREF is an alias of it. 40 AN4/GPIO4 General purpose analog input or GPIO 49 GNDFLAG Device flag, terminate to lowest potential of battery cluster 41 AN5/GPIO5 General purpose analog input or GPIO 34 SI/RDTX_IN+ 35 RDTX_OUT+ 36 AN0/GPIO0 37 AN1/GPIO1 38 SPI serial input or receiver/transmit input positive General purpose analog input or GPIO Current measurement input+ Current measurement input– Table 3. Key Parameters Characteristics noted under SPI mode conditions 5.0 V ≤ VPWR ≤ 30 V, TPL mode: 7.0 V ≤ VPWR ≤ 30 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Before starting any development, it is recommended to request a copy of the full 33772 data sheet. Symbol Characteristic Typ Unit Supply Current (base value) • Normal mode, Cell Balance OFF, ADC Inactive, Communication Inactive, IVCOM = 0 mA 5.8 mA IVPWR(CBON) Supply Current adder to set all 6 Cell Balance switches ON 0.97 mA IVPWR(ADC) Delta Supply Current to perform ADC conversions (addend) • ADC1-A,B continuously converting • ADC2 continuously converting 2.9 1.17 mA Supply Current in Sleep mode, Communication Inactive, Cell Balance OFF, Oscillator Monitor ON • SPI mode • TPL mode 32 50 μA VPWR OV, LV, UV Filter 50 μs 4.25 V 1.5 V VCOM Output Voltage 5.0 V VCOM(UV) VCOM Undervoltage Fault Threshold 4.5 V VCOM_HYS VCOM Undervoltage Hysteresis 100 mV 10 μs VCOM Fault Retry Timer 10 ms VCOM Sleep Mode Pull-down Resistor 2.0 kΩ Notes POWER MANAGEMENT IVPWR IVPWR(SS) tVPWR(FILTER) VPRE POWER SUPPLY VVPRE(UV_TH) Undervoltage Threshold for VCP minus VPRE VCP POWER SUPPLY VCP(UV_TH) Undervoltage Threshold for VCP minus VPRE VCOM POWER SUPPLY VCOM VDDIO POWER SUPPLY (CONTINUED) tVCOM(FLT_TIMER) tVCOM(RETRY) RVCOM(SS) VCOM Undervoltage Fault Timer 33772 Analog Integrated Circuit Device Data Freescale Semiconductor 5 Table 3. Key Parameters (continued) Characteristics noted under SPI mode conditions 5.0 V ≤ VPWR ≤ 30 V, TPL mode: 7.0 V ≤ VPWR ≤ 30 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Before starting any development, it is recommended to request a copy of the full 33772 data sheet. Symbol Characteristic Typ Unit VANA Output Voltage (NOT USED BY EXTERNAL CIRCUITS) • Decouple with 47 nF X7R 0603 or 0402 2.65 V VANA(UV) VANA Undervoltage Fault Threshold 2.4 V VANA_HYS VANA Undervoltage Hysteresis 50 mV tVANA(FLT_TIMER) VANA Undervoltage Fault Timer 11 μs VANA Overvoltage Fault Threshold 2.8 V VANA Fault Retry Timer 10 ms VANA Sleep Mode Pull-down Resistor 1.0 kΩ Cell Terminal Input Leakage Current 10 nA Cell Terminal Input Current - Functional Verification 1.0 mA CTN Cell Terminal Input Current During Conversion 100 nA RPD Cell Terminal Open Load Detection Pull-down Resistor 950 Ω 2.4415 mV/LSB 152.5925 μV/LSB Notes VANA POWER SUPPLY VANA VANA (OV) tVANA(RETRY) RVANA_RPD ADC1-A, ADC1-B CTn(LEAKAGE) CTn(FV) VVPWR_RES VCT_ANx_RES tVCONV VV_NOISE VPWR Terminal Measurement Resolution Cell Voltage and ANx Resolution in 15-bits MEAS_xxxx registers Single Channel Net Conversion Time • 16-Bit Resolution • 16-Bit Resolution 25.36 μs 400 μVrms ADC2/CURRENT SENSE MODULE IISENSE_OL ISENSE Open Load injected current 130 μA VISENSE_OL ISENSE Open Load detection threshold 460 mV ADC Resolution 0.6 μV/LSB V2RES VPGA_SAT PGA saturation half-range • Gain = 256 • Gain = 64 • Gain = 16 • Gain = 4 4.9 19.5 78.1 150.0 VPGA_ITH Voltage threshold for PGA gain increase • Gain = 256 • Gain = 64 • Gain = 16 • Gain = 4 2.344 9.375 37.50 VPGA_DTH Voltage threshold for PGA gain decrease • Gain = 256 • Gain = 64 • Gain = 16 • Gain = 4 4.298 17.188 68.750 - tPGA_SETTLE tICONV VI_NOISE PGA settling time after a chopper event 14.0 ADC Conversion Time including PGA settling time • 16-Bit Resolution 37.67 Noise at 16-bit Conversion 3.01 mV mV mV μs μs μVrms 33772 6 Analog Integrated Circuit Device Data Freescale Semiconductor Table 3. Key Parameters (continued) Characteristics noted under SPI mode conditions 5.0 V ≤ VPWR ≤ 30 V, TPL mode: 7.0 V ≤ VPWR ≤ 30 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Before starting any development, it is recommended to request a copy of the full 33772 data sheet. Symbol Characteristic Typ Unit Notes ADC2/CURRENT SENSE MODULE (CONTINUED) VI_NOISE Noise Error at 13-bit Conversion 8.33 μVrms ADCCLK ADC2 and ADC1-A,B Clocking Frequency 6.0 MHz 11 V Output Fault Detection Voltage Threshold • Balance OFF (Open Load) • Balance ON (Shorted Load) 0.55 V Output OFF Open Load Detection Pull-down Resistor • Balance OFF, Open Load Detect Disabled 2.0 kΩ CELL BALANCE DRIVERS VDS(CLAMP) VOUT(FLT_TH) RPD_CB RDS(on) Cell Balance Driver VDS Active Clamp Voltage • Clamp Energy tbd Drain-to-Source ON Resistance • IOUT = 300 mA, TJ = 105 °C • IOUT = 300 mA, TJ = 25 °C • IOUT = 300 mA, TJ = -40 °C – 0.5 0.4 Ω tON Cell Balance Driver Turn On • RL = 15 Ω 350 μs tOFF Cell Balance Driver Turn Off • RL = 15 Ω 200 μs Short/Open Detect Filter Time 20 μs tBAL_DEGLICTH INTERNAL TEMPERATURE MEASUREMENT IC_TEMP1_RES 0.032 K/LSB TSD_TH IC Temperature Resolution Thermal Shutdown 170 °C TSD_HYS Thermal Shutdown Hysteresis 10 °C Analog Input Open Pin Detect Threshold 0.15 V Internal Open detection Pull-down Resistor 5.0 kΩ GPIO0 WU De-glitch Filter 50 μs GPIO0 Daisy Chain De-glitch Filter both edges 20 μs GPIO2 Convert Trigger De-glitch Filter 2.0 μs tRESETFLT RESET De-glitch Filter 100 μs RRESET_PD Input Logic Pull-down (RESET) 100 kΩ Input Hysteresis 125 mV Input Pull-down Resistor (SPI_COM_EN) 100 kΩ 300 Ω GENERAL PURPOSE INPUT/OUTPUT GPIOX VOL(TH) ROPENPU RESET INPUT SPI_COM_EN INPUT VHYS RSPI_COM_EN_PD BUS SWITCH FOR TPL COMMUNICATION RXTERM Bus Termination Resistor (open resistor when bus switch is closed) Remark: if the bus switch is closed, the termination resistor is open, else the termination resistor is connected. At the end of the daisy chain the switch must be open, so the transmission line is properly terminated. 33772 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Table 3. Key Parameters (continued) Characteristics noted under SPI mode conditions 5.0 V ≤ VPWR ≤ 30 V, TPL mode: 7.0 V ≤ VPWR ≤ 30 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Before starting any development, it is recommended to request a copy of the full 33772 data sheet. Symbol Characteristic Typ Unit FAULT Output (High Active, IOH = 1.0 mA) 4.9 V FAULT Output Pull-down Resistance 100 kΩ Input Hysteresis • SI/RDTX_IN+, SCLK/RDTX_IN-, CSB, SDA, SCL 80 mV Input Logic Pull-down Resistance (SCLK/RDTX_IN-, SI/RDTX+) 20 kΩ Input Logic Pull-up Resistance to VCOM (CSB, SDA, SCL) 100 kΩ CSB Wake-up De-glitch Filter, Low to High Transition 50 μs Time needed to acquire all 6 cell voltages and the current after an on demand conversion • 16-Bit Resolution 208 V/I time synchronization • ADC1-A,B at 16-Bit, ADC2 at 16-Bit 113 Time between wake pulses 600 μs Idle time out after POR 60 s Wake-up signaling time out after POR 0.75 s tDIAG Diagnostic Mode Time-out 1.0 s tEOC SOC to Data Ready (includes post processing of data) • 16-Bit Resolution 520 Notes DIGITAL INTERFACE VHYS RSCLK_PD R_PU CSBWU_FLT SYSTEM TIMING tCELL_CONV tSYNC tWAKE_DELAY tIDLE tWAKE_INIT tSETTLE tCLST_TPL Time after SOC to begin converting with ADC1-A,b 12.28 Time needed to send a SOC command and read back 6 cell voltages, 7 temperatures, 1 current, 1 Coulomb counter with TPL communication working at 2.0 Mbps and ADC1-A,B configured as follows: • 16-Bit Resolution μs μs μs μs ms 1.16 Time needed to send a SOC command and read back 6 cell voltages, 7 temperatures, 1 current, 1 Coulomb counter with SPI communication working at 4.0 Mbps and ADC1-A,B configured as follows: • 16-Bit Resolution 0.86 EEPROM Access Time, EEPROM Write (depends on device selection) 5.0 ms tWAVE_DC_BITx Daisy Chain Duty Cycle OFF Time • tWAVE_DC_BITx = 00 500 μs tWAVE_DC_BITx Daisy Chain Duty Cycle OFF Time • tWAVE_DC_BITx = 01 1.0 ms tWAVE_DC_BITx Daisy Chain Duty Cycle OFF Time • tWAVE_DC_BITx = 10 10 ms tWAVE_DC_BITx Daisy Chain Duty Cycle OFF Time • tWAVE_DC_BITx = 11 100 ms tWAVE_DC_ON Daisy Chain Duty Cycle ON Time 500 μs Time out to enter Sleep Mode in the absence of TPL communication 1024 ms tCLST_SPI tI2C_ACCESS tSLEEP ms 33772 8 Analog Integrated Circuit Device Data Freescale Semiconductor Table 3. Key Parameters (continued) Characteristics noted under SPI mode conditions 5.0 V ≤ VPWR ≤ 30 V, TPL mode: 7.0 V ≤ VPWR ≤ 30 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Before starting any development, it is recommended to request a copy of the full 33772 data sheet. Symbol Characteristic Typ Unit 2.35 μs Time Between Slave Response Messages (Q) 1.5 μs Start of Message (S) 500 ns Start of Message Delay (T) 250 ns Bit Time (U) 250 ns Notes TRANSFORMER INTERFACE tRES Slave Response After Write Command (echo) Bit Delay (V) 250 ns Message Duration (R) 21.25 μs VRDTXINTH Differential Receiver Threshold 0.74 V VRDTXINHYS Differential Receiver Threshold Hysteresis 130 mV Amplifier Differential Output Voltage 2.5 V Transformer Bias Voltage • Driver tri-state 2.5 V VRDTX(PK_DIFF) VRDTX_BIAS 33772 Analog Integrated Circuit Device Data Freescale Semiconductor 9 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no on the information in this document. warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2015 Freescale Semiconductor, Inc. Document Number: MC33772SM Rev. 1.0 9/2015