Data Sheet

NXP Semiconductors
Data Sheet: Technical Data
Document Number SAC57D54H
Rev. 5, 05/2016
SAC57D54H
SAC57D54H
Features
• ARM™ Cortex-A5, 32-bit CPU
– Supports ARMv7- ISA
– 32 KB Instruction cache, 32 KB Data cache
– NEON SIMD Media Processing Engine
– FPU supporting double precision floating point
operations
– Memory Management Unit
– GIC Interrupt Controller
– Up to 320 MHz
• ARM™ Cortex-M4, 32-bit CPU
– Supports ARMv7 - ISA
– 16 KB Instruction cache, 16 KB Data cache
– 64 KB Tightly-Coupled Memory (TCM)
– Single Precision FPU
– NVIC Interrupts Controller
– 1.25 DMIPS per MHz integer performance
– Up to 160 MHz
• I/O Processor
– ARM™ Cortex-M0+, 32-bit CPU
– Intelligent Stepper Motor Drive
• Debug functionality
– Run-time debug control of cores and visibility of
system resources using the Debug Access Port
(DAP)
– IEEE 1149.1/ IEEE 1149.7 System JTAG Controller
(SJTAG)
– Program and Data Trace support (16-bit data width)
implemented by the ARM Trace Port Interface Unit
(TPIU) Trace capture
• Timer
– Four 8-channel Flextimer modules (FTM)
– Two 4 channel System Timer Module (STM)
– Three Software WatchDog Timers (SWT)
– One 8 channel Periodic Interrupt Timer (PIT)
– Autonomous Real Time Counter (RTC)
• Analog
– 1 x 24 channel, 12-bit analog-to-digital converter
(ADC)
– 2 analog comparators (CMP)
• Security
– Cryptographic Services Engine (CSE)
• Memory subsystem
– System Memory Protection Unit
– 4 MB on-chip flash supported with the flash
controller
– 1 MB on-chip SRAM with ECC
– 1.3 MB on-chip Graphics SRAM with FlexECC
• Safety
– ISO26262 ASIL-B compliance
– Password and Device Security (PASS) supporting
advanced censorship and life-cycle management
– One Fault Collection and Control Unit (FCCU) to
collect faults and issue interrupts
• Supports wake-up from low power modes via the
WKPU controller
• Multiple operating modes
– Includes enhanced low power operation
• On-chip voltage regulator
– External 3.3 V input supply
– Option for direct, external supply of core voltage
– Low Voltage Detect (LVD) and High Voltage
Detect (HVD) on various supplies and regulators
• Memory interfaces
– 2 x Dual QuadSPI Serial flash controllers
– Supports SDR and DDR serial flash
– Support for 3.3 V Hyperflash (Spansion)
– DRAM controller supporting SDR and DDR2
• Clock interfaces
– 8-40 MHz external crystal (FXOSC)
– 16 MHz IRC (FIRC)
– 128 kHz IRC (SIRC)
– 32 kHz external crystal (SXOSC)
– Clock Monitor Unit (CMU)
– Frequency modulated phase-locked loop (FMPLL)
– Real Time Counter (RTC)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
© 2016 NXP B.V.
• Graphics interfaces
– Vivante GC355 GPU supporting OpenVG 1.1
– 2 x 2D-ACE Display Controllers (with inline Head-Up-Display warping)
– Digital RGB, TCON_0 (RSDS), TCON_1 and OpenLDI/LVDS output options
– Digital Video Input (VIU4)
– RLE Decoder for memory-memory decompression
– 40x4 segment LCD driver, reconfigurable as 38x6 or 36x8
• Cluster peripherals
– Sound Generator Module (SGM)
– 6 Stepper Motor Drivers with Stepper Stall Detect
• Communication
– Ethernet 10/100 + AVB (ENET)
– MLB50
– FlexCAN x 3
– DSPI x 5
– LINFlexD x 3 (1 x Master/Slave, 2 x Master only)
– I2C x 2
• eDMA controller with multiple transfer request sources using DMAMUX
• Boot Assist Flash (BAF) supports internal flash programming
SAC57D54H, Rev. 5, 05/2016
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NXP Semiconductors
Table of Contents
1
Block diagram.................................................................................... 5
6.2.2
Slow Oscillator (SXOSC) electrical specifications .. 33
2
Family comparison.............................................................................6
6.2.3
Fast internal RC Oscillator (FIRC) electrical
3
Ordering parts.....................................................................................8
4
3.1
Determining valid orderable parts ..........................................8
3.2
Ordering information ..............................................................8
6.2.4
4.1
Absolute maximum ratings..................................................... 9
4.2
Recommended operating conditions....................................... 10
4.3
Voltage regulator electrical specifications.............................. 11
Slow internal RC oscillator (SIRC) electrical
specifications ............................................................ 33
General............................................................................................... 9
4.3.1
5
specifications............................................................. 33
6.2.5
6.3
PLL electrical specifications .................................... 34
Memory interfaces...................................................................35
6.3.1
Flash memory specifications..................................... 35
6.3.1.1
Recommended decoupling capacitor values............. 12
4.4
Voltage monitor electrical specifications................................13
4.5
Power consumption................................................................. 14
4.6
Electrostatic discharge (ESD) specifications.......................... 15
4.7
Electromagnetic Compatibility (EMC) specifications............ 16
specifications......................................... 35
6.3.1.2
Flash memory Array Integrity and
Margin Read specifications................... 36
6.3.1.3
Flash memory module life
specifications......................................... 37
I/O parameters....................................................................................16
6.3.1.4
Data retention vs program/erase cycles. 37
5.1
AC specifications @ 3.3 V range............................................16
6.3.1.5
Flash memory AC timing
5.2
DC electrical specifications @ 3.3 V range............................ 17
5.3
AC specifications @ 5 V range...............................................18
5.4
DC electrical specifications @ 5 V range............................... 18
5.5
DDR2 pads IO specifications..................................................19
5.5.1
5.5.2
5.6
specifications......................................... 38
6.3.1.6
5.6.2
6.3.2
QuadSPI AC specifications....................................... 39
DDR2 pads AC specifications @ 1.8V
6.3.2.1
SDR mode..............................................40
VDDE_DDR..............................................................19
6.3.2.2
DDR mode............................................. 41
SSTL_18 Class II 1.8 V DDR2 DC specifications....20
6.3.2.3
HyperFlash mode...................................43
6.3.3
SMC 5V pads IO specifications................................ 21
5.6.1.1
SMC 5V pads IO DC specifications...... 21
5.6.1.2
SMC 5V pads IO AC specifications...... 22
SDR AC specifications..............................................44
6.3.3.1
6.3.4
6.4
DDR2 SDRAM AC specifications............................ 46
Communication modules.........................................................49
6.4.1
SPI electrical specifications.......................................49
5.6.2.1
SMC 3.3 V pads IO DC specifications.. 22
6.4.2
Ethernet AC specifications........................................ 55
5.6.2.2
SMC 3.3 V pads IO AC specifications.. 23
6.4.3
MediaLB (MLB) electrical specifications.................56
RSDS pads electrical specifications........................................23
5.8
LVDS pads electrical specifications....................................... 25
5.9
Functional reset pad electrical specifications..........................26
6.4.3.1
Peripheral operating requirements and behaviors.............................. 27
MLB 3-wire interface DC
specifications......................................... 56
6.4.3.2
5.10 PORST electrical specifications..............................................27
6.2
SDR DC specifications.......................... 46
SMC 3.3 V pads IO specifications............................ 22
5.7
6.1
Flash read wait state and address
pipeline control settings ........................ 39
SMC pads IO specifications....................................................21
5.6.1
6
Flash memory program and erase
MLB 3-wire interface electrical
specifications......................................... 57
6.5
Display modules......................................................................59
Analog modules.......................................................................27
6.5.1
LCD driver electrical specifications.......................... 59
6.1.1
ADC electrical specifications.................................... 27
6.5.2
2D-ACE electrical specifications.............................. 59
6.1.2
Analog Comparator (CMP) electrical specifications 30
Clocks and PLL interfaces modules........................................31
6.2.1
6.5.2.1
Interface to TFT LCD Panels (2DACE)...................................................... 59
Fast Oscillator (FXOSC) electrical specifications.... 31
SAC57D54H, Rev. 5, 05/2016
NXP Semiconductors
3
6.5.2.2
6.5.2.3
6.6
6.7.1
JTAG interface timing .............................................. 66
level timings...........................................60
6.7.2
Debug trace timing specifications............................. 68
Interface to TFT LCD panels—access
6.7.3
Wakeup Unit (WKPU) AC specifications.................69
level........................................................62
6.7.4
External interrupt timing (IRQ pin)...........................69
6.5.3
Video input unit (VIU4) electrical specifications..... 63
6.5.4
TCON electrical specifications..................................64
6.5.4.1
TCON RSDS electrical specifications...64
6.5.4.2
TCON TTL electrical specifications......64
Motor control modules............................................................ 65
6.6.1
6.7
Interface to TFT LCD Panels—pixel
Stepper Stall Detect (SSD) specifications................. 65
Debug specifications............................................................... 66
7
Thermal attributes.............................................................................. 70
7.1
8
Dimensions.........................................................................................72
8.1
9
Thermal attributes................................................................... 70
Obtaining package dimensions ...............................................72
Pinouts................................................................................................72
9.1
Package pinouts and signal descriptions................................. 72
10 Revision History.................................................................................72
SAC57D54H, Rev. 5, 05/2016
4
NXP Semiconductors
Block diagram
1 Block diagram
RGB
RSDS / RGB
64
64
64
32
32
64
64
64
64
MLB50
32
AHB
AHB
AXI
AXI
AXI
AHB
2D-ACE
HUD Warping
2D-ACE
Tiny UI
ENET-AVB
LDB
OpenVG 1.1
64
64
TCON_1
TCON_0
AHB
16ch eDMA_1
SECURITY
(CSE)
FPU
32KB L1 32KB L1
D-Cache I-Cache
AXI
System
AHB
MBIST
AHB
Code
Temp Sensor
GC355
GPU
NEON
AHB
FPU
16KB L1 16KB L1
D-Cache I-Cache
64KB
TCM
AHB
INT Router
DAP
I/O Ctrl
Reset Ctrl
AHB
16ch eDMA_0
GIC
DMAMUX (64:16)
ARM
Cortex M4
OpenLDI/LVDS
RSDS
ARM
Cortex A5
NVIC
VIU4
System Modules
LVDS
32
Clocking
4-40MHz/32KHz
XOSC
System Bus
Memory Protection
Power
1.2V Regulator
LVD / HVD
64
AHB
Flash memory BIU
64
AHB
64
AHB
AHB
64
AXI
Pixel
Converter
AHB
64
64
AHB
Port Splitter
512kB
System
SRAM (ECC)
512kB
System
SRAM (ECC)
2 - 4MB
Flash memory (ECC)
64
Boot ROM
1.3MB
GRAM
(FlexECC)
EE Emulation
OTP
CA5 GIC
SGM (I2S)
SMC & SSD (6)
Autonomous RTC
Timer/PWM (8ch)
Timer/PWM (8ch)
Timer/PWM (8ch)
Timer/PWM (8ch)
12-bit ADC (24)
CMP (2)
LCD
SWT (3)
PIT (8CH)
STM (4CH)
CRC
SEMA42
UART/LIN (3)
I2C (2)
DSPI (5)
FlexCAN (3)
4k & 2k ETBs
64
AHB
64
AXI
64 AHB 64
DRAM Controller
16/32-bit
SDR
AIPS
Debug
TPIU
AHB
DDR2
Low Power Ctrl
SJTAG
64
QuadSPI
Clock Monitor
AHB
QuadSPI
64
IOP
ARM
CortexM0+
CM4 NVIC
AHB
PLLs
RLE
Decoder
16MHz/128KHz
IRC
Interrupt
Router
Peripheral
Interrupts
32k SRAM
(ECC)
Figure 1. High level block diagram
SAC57D54H, Rev. 5, 05/2016
NXP Semiconductors
5
Family comparison
320MHz Domain
ARM
Cortex A5
64
64
2D-ACE & HUD
NEON
FPU
64
GC355
OpenVG GPU
AXI
AXI
DAP
32KB L1 32KB L1
D-Cache I-Cache
AXI
AXI
AXI
AXI
64
AXI
64
2D-ACE
ENET-AVB
16CH eDMA
VIU4
System
AHB
Code
AHB
16KB L1 16KB L1
D-Cache I-Cache
MLB50
64KB
TCM
64:16 mux
FPU
SECURITY
(CSE)
ARM
Cortex M4
16CH eDMA
160MHz Domain
64
64
64
64
AHB
AHB
AHB
AHB
M1
64
64
64
64
M0
AHB
RDC - 8 domain, 1MDAC per master, 2x MDAC per CPU.,
32
M3
M2
AHB 64
AHB 64
M4
M5
M7
M13
M8 M9
M14
M10
M11
QoS301
AMBA AXBS
S0
S7
S3
S4
S6 S5
S8 S9 S10 S11
S12
Port Splitter
AIPS 0
AIPS 1
PDAC
PDAC
AHB 64
AHB
64
AHB
64
512kB
System
SRAM (ECC)
AHB
64
AHB
64
AHB
64
S14
S15
Flash Memory
BIU
512kB
System
SRAM (ECC)
4MB
Flash memory (ECC)
S16
SDAC2 [0..3] (AXI)
AHB 64
AHB 64
AHB
64
RLE
Decoder
Boot ROM
S13
SDCAC1 [0..15] (AHB)
SDAC0 [0..15] (AHB)
QuadSPI
S2
QuadSPI
S1
M12
M16
M15
S17
SDAC5 [0..3] (AXI)
AXI 64
Pixel
Converter
1.3MB
GRAM
(FlexECC)
SDAC4 [0..7] (AXI)
Priority Manager
DRAM Controller
16/32-bit
SDR & DDR2
EE Emulation
Secure Flash
memory
OTP
ARM
Cortex M0+
SDAC3 [0..7] (AHB)
AXBS
32kB
SRAM (ECC)
I/O Processor
Figure 2. Detailed block diagram
2 Family comparison
The table below provides a summary of the different members of the SAC57D5xx Low/
Mid-Line Instrument Cluster family and their features. Note that not all features are
available simultaneously on all packages.
Table 1. Feature sets
Product Features
Cores
SAC57D54H
SAC57D53M
SAC57D52L
Cortex-A5 (320 MHz,
32 KB/32 KB L1
Caches, FPU, MMU,
NEON)
Yes
Yes
Yes
Cortex-M4 (160 MHz,
16 KB/16 KB L1
Caches, FPU)
Yes
Yes
Yes
Table continues on the next page...
SAC57D54H, Rev. 5, 05/2016
6
NXP Semiconductors
Family comparison
Table 1. Feature sets (continued)
Product Features
Internal Memory
SAC57D54H
SAC57D53M
SAC57D52L
Cortex - M0+ I/O
Processor (IOP) (80
MHz)
Yes
Yes
Yes
ECC Flash Memory
4 MB
3 MB
2 MB
1.3 MB
1.3 MB
1.3 MB
System SRAM (ECC)
2 x 512 KB
2 x 512 KB
2 x 512 KB
IOP local SRAM (ECC)
32 KB
32 KB
32 KB
Graphics
External Memory
Interfaces
System and General
Purpose
Graphics/Video/Display/
Audio
System Connectivity
Analog Connectivity
Timer/PWM
Package Options
SRAM1
Dual DDR QuadSPI
2 x Dual DDR QuadSPI 2 x Dual DDR QuadSPI 2 x Dual DDR QuadSPI
16 bit SDR DRAM
(160MHz)
Yes
Yes
Yes
32-Bit DDR2 DRAM
(320MHz)2
Yes
Yes
-
Memory / Peripheral
Protection (xDRC Extended Resource
Domain Controller)
Yes
Yes
Yes
Security (CSE)
Yes
Yes
Yes
eDMA
16ch x 2
16ch x 2
16ch x 2
2D-ACE
x2
x2
x2
HUD Warping Engine
Yes
Yes
Yes
TCON_0/RSDS
Yes
Yes
Yes
TCON_1
Yes
Yes
Yes
OpenLDI/LVDS
Yes
Yes
-
GPU
GC355 : OpenVG 1.1 /
TinyUI
GC355 : OpenVG 1.1 /
TinyUI
GC355 : OpenVG 1.1 /
TinyUI
Video Input Unit
Yes
Yes
Yes
Sound Generator
Yes
Yes
Yes
Segment LCD
Yes
Yes
Yes
FlexCAN
x3
x3
x3
I2C
x2
x2
x2
LINFlexD
x3
x3
x3
SPI
x5
x5
x5
MLB50
Yes
Yes
Yes
10/100 Ethernet + AVB
Yes
Yes
Yes
SMC/SSD
x6
x6
x6
12 Bit ADC
Yes
Yes
Yes
Analog Comparator
2 x 8ch
2 x 8ch
2 x 8ch
PIT
8ch
8ch
8ch
SWT
3
3
3
ARTC
Yes
Yes
Yes
FlexTimer
4 x 8ch
4 x 8ch
4 x 8ch
LQFP
208 LQFP
208 LQFP
208 LQFP
Table continues on the next page...
SAC57D54H, Rev. 5, 05/2016
NXP Semiconductors
7
Ordering parts
Table 1. Feature sets (continued)
Product Features
BGA
SAC57D54H
SAC57D53M
SAC57D52L
516 MAPBGA
516 MAPBGA
-
1. GRAM can be reconfigured as ECC RAM
2. DDR2 interface only available in BGA package option
3 Ordering parts
3.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web.
1. To determine the orderable part numbers for this device, go to www.nxp.com and
perform a part number search for the following device number: SAC57D5xx.
3.2 Ordering information
SAC57D54H, Rev. 5, 05/2016
8
NXP Semiconductors
General
4 General
4.1 Absolute maximum ratings
NOTE
Functional operating conditions appear in the DC electrical
characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maximum values is not
guaranteed.
Stress beyond the listed maximum values may affect device
reliability or cause permanent damage to the device.
Table 2. Absolute maximum ratings
Symbol 1
VDDE_A, VDDE_B,
VDDE_SDR
VDD_LP_DEC
VDDA
VDDEH_ADC
VSSA
Parameter
Conditions
Min
Max
Unit
Input/output supply voltage2
—
–0.3
3.6
V
Decoupling pin for low power regulators3
—
–0.32
1.32
V
ADC supply voltage
—
–0.3
6.0
V
ADC I/O supply voltage
—
–0.3
6.0
V
ADC supply ground
—
–0.3
0.3
V
VDDA_REF
4
ADC supply voltage
—
–0.3
6.0
V
VDDM_SMD
SMD supply voltage
—
–0.3
6.0
V
VSSM_SMD
SMD supply ground
—
–0.3
0.3
V
VDDE_DDR
DDR2 DRAM supply voltage
—
–0.3
2.3
V
DDR_VREF
DDR I/O Reference Voltage
—
–0.3
1.15
V
Core logic supply voltage
—
–0.3
1.32
V
Relative to
VDDE_A,
VDDE_B,
VDDE_SDR
–0.3
VDDE_ADC + 0.3
V
–0.3
VDDE_A + 0.3
V
Relative to
VDDE_A,
VDDE_B,
VDDE_SDR
–0.3
VDDE_x + 0.3
V
Always
–5
5
mA
5
VDD12
VINA
Voltage on ADC analog pin with respect to
VSSA
Voltage on Analog comparator pin (CMP)
with respect to VSS
VIN
Voltage on any digital pin with respect to
ground (VSS)
IINJPAD
Injected input current on any pin during
overload condition
IINJSUM
Absolute sum of all injected input currents
during overload condition
—
–50
50
mA
Tramp
Supply ramp rate
—
0.5 V / min
100 V/ms
—
Ta 6
Ambient temperature
—
–40
105
°C
TSTG
Storage temperature
—
–55
165
°C
SAC57D54H, Rev. 5, 05/2016
NXP Semiconductors
9
General
1. All parameters are with reference to Vss unless otherwise specified.
2. A crossover current of up to 2 mA may be experienced if VDD12 is ramped up before VDDE_A supply. This current is only an
electrical crossover but has no functional implications, and should be removed when VDDE_A ramps up to its functional
operating range.
3. Not available for input voltage, only for decoupling internal regulators.
4. VDDA_REF is only available on the 516 BGA package.
5. DDR_VREF is expected to be equal to 0.5 × VDDE_DDR and to track VDDE_DDR DC variations as measured at the device
pins. Ensure VDD_LV supply ramps up before VDDE_DDR. In Standby mode, it should be ensured that VDDE_DDR supply
should be cut off.
6. Tj=125°C. Assumes Ta=105°C. Assumes maximum θJA of 2s2p board. See Thermal attributes section for details.
4.2 Recommended operating conditions
The following table describes the operating conditions for the device, and for which all
specifications in the data sheet are valid, except where explicitly noted. The device
operating conditions must not be exceeded in order to guarantee proper operation and
reliability. The ranges in this table are design targets and actual data may vary in the
given range.
For normal device operations, VDDE_A, VDDA, VDDA_REF, VDDEH_ADC and VDD12
supplies must be within operating range corresponding to the range mentioned in
following tables. This is required even if some of the features are not used. If using the
ADC to convert SSD channels then VDDA should always be >= VDDM_SMC.
VDD12 should be supplied externally. VDDA_REF, the supply port to 516 BGA is shorted to
VDDA inside lower pin packages. Stepper Stall Detect module (SSD) should only be
operated in the 4.5 V to 5.5 V range and so cannot be used if VDDM_SMD is in 3.3 V
range.
Design may experience up to 30 mA additional crossover current (on VDDE_A) if the
high voltage flash supply is powered before the low voltage core supply. This additional
current will be removed once VDD12 supply rises to its operating range. There is no
reliability concern to the device due to this additional current.
Table 3. Recommended operating conditions
Symbol 1
Parameter
Conditions
Min2
Max
Unit
VDDE_A
Input/output supply voltage
—
3.15
3.6
V
VSSA
ADC supply ground, relative to
VSS
—
-0.1
0.1
V
VDDA
ADC supply voltage
3.15
5.5
V
VDDEH_ADC
ADC I/O supply voltage
3.15
5.5
V
VDDA_REF
ADC reference voltage
VDDA,VDDA_REF and VDDEH_ADC
should be within +/-25 mV of
each other
3.15
5.5
V
VDDM_SMD
SMD supply voltage
—
3.15
5.5
V
VDDE_B3
VDDE_SDR3
Table continues on the next page...
SAC57D54H, Rev. 5, 05/2016
10
NXP Semiconductors
General
Table 3. Recommended operating conditions (continued)
Symbol 1
Parameter
Conditions
Min2
Max
Unit
VDDE_DDR
DDR2 supply voltage
—
1.7
1.9
V
DDR_VREF
DDR I/O Reference Voltage
—
VDDE_DDR
(min)/2
VDDE_DDR
(max)/2
V
VDD124
Core logic supply voltage
—
1.20
1.32
V
VSSEH_ADC
ADC supply ground, relative to
VSS
—
-0.3
0.3
V
IINJPAD
Injected input current on any
pin during overload condition
—
-3.0
3.0
mA
Ta5
Ambient temperature under
bias
–40
105
°C
1. All parameters are with reference to Vss, unless otherwise specified.
2. Device will be functional (and electrical specifications as per various datasheet parameters will be guaranteed) until one of
the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.
3. VDDE_A, VDDE_B and VDDE_SDR are all independent supplies and can each be set to 3.3 V. However, care must be taken
over LCD inputs that operate across the IO segments.
4. Only applicable when supplying from external source. VDD12 supply pins should never be grounded (through a small
impedance). If not driven, these should only be left floating.
5. Tj=125°C. Assumes Ta=105°C. Assumes maximum θJA of 2s2p board. See Thermal attributes section for details.
4.3 Voltage regulator electrical specifications
The voltage regulator is composed of the following blocks:
• Connect an external 1.25 V nominal directly
• Low voltage detector - low threshold (LVD_HV_A) for VDDE_A supply
• Low voltage detector (LVD_FLASH) for 3.3 V flash supply
• Various low voltage detectors (LVD_LV_x) for digital core supply (VDD12)
• High voltage detector (HVD_LV) for digital core supply (VDD12)
• Power on Reset (POR_LV) for 1.25 V digital core supply (VDD12)
• Power on Reset (POR_HV) for VDDE_A
SAC57D54H, Rev. 5, 05/2016
NXP Semiconductors
11
General
LPPREG
VDD_LP_DEC
ULPPREG
CLP/ULPREG
Vss
V DD12
Vss
DEVICE
Figure 3. Voltage regulator capacitance connection
Table 4. Voltage regulator electrical specifications
Symbol
Clp/ulp_reg
Parameter
Conditions
External decoupling / stability
Min, max values shall be
capacitor for internal low power granted with respect to
regulators
tolerance, voltage, temperature,
and aging variations
Combined ESR of external
capacitor
—
Min
Typ1
Max
Unit
0.8
1
1.4
µF
0.001
—
0.1
Ohm
1. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum and
maximum values.
4.3.1 Recommended decoupling capacitor values
Following are the recommendations for supply decoupling on various power domains:
• For VDDE_A, VDDE_B, VDDE_SDR, VDDM_SMD, VDDE_DDR, VDDA,
VDDEH_ADC,VDDA_REF, DDR_VREF supplies:
• 0.1 μF close to each VDD/VSS pin pair.
• 1 μF on each side of the chip for each supply domain.
• 10 μF near for each power supply source (except for VDDM_SMD pins where a
higher capacitance value may be needed depending upon motor characteristics).
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12
NXP Semiconductors
General
• For VDD12, 0.1 μF close to each VDD/VSS pin pair is required.
4.4 Voltage monitor electrical specifications
Table 5. Voltage monitor electrical specifications
Symbol
Parameter
State Conditions
Configuration
Power
Up 1
VPOR_LV
LV supply
power on reset
detector
Fall
Rise
Typ
Max
0.9300
0.9790
1.0280
V
Trimmed
-
-
-
V
Untrimmed
0.9800
1.0290
1.0780
V
-
-
-
V
1.3750
V
Yes
No
Reset Type
Destructive
Trimmed
VHVD_LV_cold
VLVD_LV_PD2_hot
VLVD_LV_PD1_hot
VLVD_LV_PD0_hot
VPOR_HV
VLVD_IO_A_LO
LV supply high Fall
voltage
monitoring,
detecting at the Rise
device pin
Untrimmed
LV supply low Fall
voltage
monitoring,
detecting in the Rise
PD2 core (hot)
area
Untrimmed
LV supply low Fall
voltage
monitoring,
detecting in the Rise
PD1 core (hot)
area
Untrimmed
LV supply low Fall
voltage
monitoring,
detecting in the Rise
PD0 core (hot)
area
Untrimmed
HV supply
power on reset
detector
Untrimmed
Fall
Rise
HV IO_A supply Fall
low voltage
monitoring - low
Rise
range
VLVD_LV_PD2_COL LV supply low Fall
voltage
D
monitoring,
detecting at the Rise
device pin
Unit
Min
Untrimmed
Mask
Opt
Threshold
No
Yes
Functional
Disabled at Start
Trimmed
1.3250
Untrimmed
Disabled at Start
Trimmed
1.3450
1.3650
1.3950
V
1.0800
1.1200
1.1600
V
Trimmed
1.1250
1.1425
1.1600
V
Untrimmed
1.1000
1.1400
1.1800
V
Trimmed
1.1450
1.1625
1.1800
V
Yes
1.0800
1.1200
1.1600
V
1.1140
1.1370
1.1600
V
Untrimmed
1.1000
1.1400
1.1800
V
Trimmed
1.1340
1.1570
1.1800
V
1.0800
1.1200
1.1600
V
Trimmed
1.1140
1.1370
1.1600
V
Untrimmed
1.1000
1.1400
1.1800
V
Trimmed
1.1340
1.1570
1.1800
V
2.7000
2.8500
3.0000
V
Trimmed
-
-
-
V
Untrimmed
2.7500
2.9000
3.0500
V
Trimmed
-
-
-
V
2.7500
2.9230
3.0950
V
Trimmed
2.9780
3.0390
3.1000
V
Untrimmed
2.7800
2.9530
3.1250
V
Trimmed
3.0080
3.0690
3.1300
V
1.1750
V
1.1950
V
Untrimmed
Yes
Yes
Yes
No
No
Destructive
Trimmed
Untrimmed
Yes
No
No
No
No
Yes
Destructive
1.3450
Destructive
Destructive
Destructive
Functional
Disabled at Start
Trimmed
1.1400
1.1550
Untrimmed
Disabled at Start
Trimmed
1.1600
1.1750
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NXP Semiconductors
13
General
1. All monitors that are active at power up will gate the power up recovery and prevent exit from POWERUP phase until the
minimum level is crossed. These monitors can in some cases be masked during normal device operation, but when active
will always generate a destructive reset.
4.5 Power consumption
The following table shows the power consumption for the device in the various modes of
operation.
Table 6. Power consumption
Mode
Configuration
Typ
Max
Unit
Run Mode
CA5 320 MHz, CM4
160 MHz, DDR2 320
MHz, Dual Display (516
BGA)
800
1500
mA
Run Mode
CA5 320 MHz, CM4
160 MHz, SDR 160
MHz, Single Display
(208 QFP)
600
1200
mA
IOP Run Mode
CM0+ 16 MHz, PD1/0
domains powered,
remainder of device
power gated off.
31
35
mA
IOP Stop Mode
CM0+ halted, PD1/0
domains powered, all
module enabled and
LCD running in IOP
domain, remainder of
device power gated off.
0.252
20
mA
Stop Mode
Cores halted, Device
fully powered.
240
700 3
mA
Standby Mode4, 5
ARTC/32 KHz + 32 KB
SRAM powered
μA
ARTC/32 KHz + 8 KB
SRAM powered
50 (25 °C)
70 (25 °C)
500 (55 °C)
900 (55 °C)
1500 (85 °C)
2500 (85 °C)
2000 (105 °C)
4000 (105 °C)
45 (25 °C)
65 (25 °C)
500 (55 °C)
900 (55 °C)
1500 (85 °C)
2500 (85 °C)
2000 (105 °C)
4000 (105 °C)
μA
IOP_Run typical is measured at 25oC.
IOP_Stop typical is measured at 25oC.
There could be 10% variation based on the characterization.
Weak pull functionality provided in I/O pads must be used to configure I/Os in a known state (that does not cause
contention with external connection on the pin) to avoid floating input to cause crow-bar currents and hence increased
leakage during low power modes.
5. During STANDBY/IOP modes, it is recommended to keep VDDE_A, VDDEH_ADC, VDDAand VDDA_REF powered to their
respective functional levels to obtain best power performance of the device. All other supplies are recommended be kept
unpowered in these low power modes.
1.
2.
3.
4.
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NXP Semiconductors
General
The following diagrams show the supply configuration of the device.
Figure 4. Supply configuration
4.6 Electrostatic discharge (ESD) specifications
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
NOTE
A device will be defined as a failure if after exposure to ESD
pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing
shall be performed per applicable device specification at room
temperature followed by hot temperature, unless specified
otherwise in the device specification.
Table 7. ESD ratings
Symbol
VESD(HBM)
Conditions1
Parameter
Electrostatic discharge
TA = 25 °C
Class
Max value2
Unit
H1C
2000
V
(Human Body Model)
Table continues on the next page...
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NXP Semiconductors
15
I/O parameters
Table 7. ESD ratings (continued)
Symbol
Conditions1
Parameter
Class
Max value2
Unit
C3A
500
V
conforming to AECQ100-002
VESD(CDM)
Electrostatic discharge
TA = 25 °C
(Charged Device Model)
conforming to AECQ100-011
750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. Data based on characterization results, not tested in production.
4.7 Electromagnetic Compatibility (EMC) specifications
EMC measurements to IC-level IEC standards are available from NXP on request.
5 I/O parameters
5.1 AC specifications @ 3.3 V range
Table 8. Functional Pad AC Specifications @ 3.3 V range
Symbol
Rise/Fall Edge (ns)
Min
pad_sr_hv
(output)
Drive Load (pF)
Max
1.75/1.5
MSB, LSB
25
0.8/0.8
3.25/3
50
3.5/2.5
12/12
200
0.6/0.8
3.75/3.5
25
1/1
7/6.5
50
7.7/5
25/21
200
4/3.5
25/25
50
6.3/6.2
30/30
200
6.8/6
40/40
50
11/11
Drive/Slew Rate Select
11 (Recommended setting)
10
01
001
51/51
200
0.5/0.5
0.5
NA
1.5/1.5
30
11
2.4/2.4
50
0.6/0.6
1.5/1.5
20
10
0.6/0.6
1.85/1.85
10
01
12/11
36/45
50
00
pad_i_hv/pad_sr_hv
(input)2
pad_fc_hv
(output)
0.6/0.6
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16
NXP Semiconductors
I/O parameters
1. Slew rate control modes
2. Input slope = 2 ns
5.2 DC electrical specifications @ 3.3 V range
Table 9. DC electrical specifications @ 3.3 V range
Symbol
Vdde
Parameter
I/O Supply Voltage
Value
Unit
Min
Max
3.15
3.63
V
Vih
CMOS Input Buffer High Voltage (with
hysteresis disabled)
0.55 x Vdde
Vdde + 0.3
V
Vil
CMOS Input Buffer Low Voltage (with
hysteresis disabled)
Vss − 0.3
0.40 x Vdde
V
Vih_hys
CMOS Input Buffer High Voltage (with
hysteresis enabled)
0.65 x Vdde
Vdde + 0.3
V
Vil_hys
CMOS Input Buffer Low Voltage (with
hysteresis enabled)
Vss − 0.3
0.35 x Vdde
V
CMOS Input Buffer Hysteresis
0.1 x Vdde
Vhys
V
Pull_Ioh_vil_hys
Weak Pullup Current measured when
pad = 0.35 x Vdde
25
80
µA
Pull_Ioh_vih_hys
Weak Pulldown Current measured when
pad = 0.65 x Vdde
25
80
µA
Iinact_d
Digital Pad Input Leakage Current (weak
pull inactive)
−2.5
2.5
µA
0.8 x Vdde
—
V
—
0.2 x Vdde
V
Voh
Output High Voltage1
Vol
Voltage2
Output Low
Vih_ttl
TTL High Level Input Voltage
Vil_ttl
TTL Low Level Input Voltage
Vhyst_ttl
TTL Input Hysteresis Voltage
Vih_auto
Automotive High Level Input Voltage
Vil_auto3
Vhyst_auto
1.8
V
0.6
0.25
V
V
0.75 x Vdde
Vdde + 0.3
V
Automotive Low Level Input Voltage
−0.3
0.35 ✕ Vdde
V
Automotive Input Hysteresis Voltage
0.11 x Vdde
V
1. Measured when pad is sourcing 2 mA.
2. Measured when pad is sinking 2 mA.
3. Auto levels are applicable to the ‘input only' channels (CH0-7) of the ADC pins
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NXP Semiconductors
17
I/O parameters
5.3 AC specifications @ 5 V range
Table 10. Functional pad AC specifications @ 5 V range
Symbol
Rise/Fall Edge (ns)
Min
pad_sr_hv
Drive Load (pF)
Max
MSB, LSB
1.2/1.2
(output)
pad_fc_hv
(output)
Drive/Slew Rate Select
25
11 (Recommended setting)
2.5/2
50
8/8
200
3/2
25
5/4
50
18/16
200
13/13
50
24/24
200
24/24
50
10
01
001
50/50
200
1.8/1.7
50
6.6/6.1
200
2.7/2.5
50
10.3/9.3
200
5.6/4.8
50
21/19
200
41/41
50
151/151
200
11
10
01
00
1. Slew rate control modes
5.4 DC electrical specifications @ 5 V range
Table 11. DC electrical specifications @ 5 V range
Symbol
Vdde
Parameter
I/O Supply Voltage
Value
Unit
Min
Max
4.5
5.5
V
Vih
CMOS Input Buffer High Voltage (with hysteresis
disabled)
0.55 × Vdde
Vdde + 0.3
V
Vil
CMOS Input Buffer Low Voltage (with hysteresis
disabled)
Vss − 0.3
0.40 × Vdde
V
Vih_hys
CMOS Input Buffer High Voltage (with hysteresis
enabled)
0.65 × Vdde
Vdde + 0.3
V
Vil_hys
CMOS Input Buffer Low Voltage (with hysteresis
enabled)
Vss − 0.3
0.35 × Vdde
V
Table continues on the next page...
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18
NXP Semiconductors
I/O parameters
Table 11. DC electrical specifications @ 5 V range (continued)
Symbol
Parameter
Value
Min
Vhys
CMOS Input Buffer Hysteresis
Unit
Max
0.1 × Vdde
V
Pull_Ioh_vil_h ys
Weak Pullup Current measured when pad = 0.35 x Vdde
(Vil_hys)
40
120
µA
Pull_Ioh_vih_hys
Weak Pulldown Current measured when pad = 0.65 x
Vdde (Vih_hys)
40
120
µA
Iinact_d
Digital Pad Input Leakage Current (weak pull inactive)
−2.5
2.5
µA
Voltage1
Voh
Output High
0.8 x Vdde
—
V
Vol
Output Low Voltage2
—
0.2 x Vdde
V
Vih_ttl
TTL High Level Input Voltage
2.0
Vil_ttl
TTL Low Level Input Voltage
Vhyst_ttl
TTL Input Hysteresis Voltage
0.3
Vih_auto
Automotive High Level Input Voltage
3.8
Vdde + 0.3
V
Automotive Low Level Input Voltage
−0.3
2.2
V
Vhyst_auto
Automotive Input Hysteresis Voltage
0.5
Vih_auto3
Automotive High Level Input Voltage
0.7 × Vdde
Vdde + 0.3
V
Vil_auto3
Automotive Low Level Input Voltage
−0.3
0.47 × Vdde
V
Automotive Input Hysteresis Voltage
0.11 × Vdde
3
Vil_auto
3
V
0.8
V
V
V
Automotive Levels with Expanded VDDE Range: 4 V - 5.5 V
3
Vhyst_auto
V
1. Measured when pad is sourcing 2 mA.
2. Measured when pad is sinking 2 mA.
3. Auto levels are applicable to the ‘input only' channels (CH0-7) of the ADC pins
5.5 DDR2 pads IO specifications
5.5.1 DDR2 pads AC specifications @ 1.8V VDDE_DDR
Table 12. DDR2 pads AC electrical specifications at 1.8 V VDDE_DDR
Name
pad_dq_18
Rise/Fall Edge (V/ns)
Drive Load (pF)
Drive Strength
Select (Refer
SIUL_MSCR[SRE]
description in the
device reference
manual)
Min
Max
Half/Full
1
—
5
Half
1
—
20
Half
1
—
5
Full
Table continues on the next page...
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NXP Semiconductors
19
I/O parameters
Table 12. DDR2 pads AC electrical specifications at 1.8 V VDDE_DDR (continued)
Name
Rise/Fall Edge (V/ns)
pad_acc_18
pad_clk_18
Drive Load (pF)
Drive Strength
Select (Refer
SIUL_MSCR[SRE]
description in the
device reference
manual)
Min
Max
Half/Full
1
—
20
Full
1
—
5
Half
1
—
20
Half
1
—
5
Full
1
—
20
Full
1
—
5
Half
1
—
20
Half
1
—
5
Full
1
—
20
Full
5.5.2 SSTL_18 Class II 1.8 V DDR2 DC specifications
Table 13. SSTL_18 Class II 1.8 V DDR2 DC specifications
Symbol
Parameter
Conditio
n
Min
Typ
Max
Uni
t
Notes
VDDE_DDR
DDR 1.8 V I/O
Supply voltage
—
1.7
1.8
1.9
V
VDD12
Core Supply
Voltage
—
1.20
1.26
1.32
V
A5.15
DDR_REF
I/O Reference
Voltage
—
0.51 x
VDDE_DDR
V
A5.16
Vih(dc)
DC Input Logic
High
—
Vil(dc)
DC Input Logic
Low
—
Vih(ac)
AC Input Logic
High
—
Vil(ac)
AC Input Logic
Low
Iin
0.49 x VDDE_DDR 0.50 x VDDE_DDR
DDR_VREF +
0.125
—
JESD8-15
A
SpecI
D
A5.14
V
JESD8-15
A
A5.18
—
DDR_VREF −
0.125
V
JESD8-15
A
A5.19
DDR_VREF +
0.25
—
—
V
JESD8-15
A
A5.20
—
—
—
DDR_VREF −
0.25
V
JESD8-15
A
A5.21
Pad input
Leakage Current
—
-50
—
50
μA —
A5.22
Voh
Output High
Voltage Level
—
VDDE_DDR − 0.28
—
—
V
—
A5.23
Vol
Output Low
Voltage Level
—
—
—
0.28
V
—
A5.24
Table continues on the next page...
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20
NXP Semiconductors
SMC pads IO specifications
Table 13. SSTL_18 Class II 1.8 V DDR2 DC specifications (continued)
Symbol
Parameter
Conditio
n
Min
Typ
Max
Uni
t
Notes
SpecI
D
Ioh(dc)
Output min
Vout = Voh
source dc current
−12.86
—
—
mA JESD8-15
A VDDE_DDR
= 1.7V Voh
= 1.42V
A5.25
Iol(dc)
Output min sink
dc current
12.86
—
—
mA JESD8-15
A VDDE_DDR
= 1.7 V Vol
= 0.28 V
A5.26
Vout= Vol
Table 14. Current-draw Characteristics for DDR_VREF
Symbol
DDR_VREF
Parameter
Current-draw characteristics for DDR_VREF
Min
Max
Unit
-
5
mA
5.6 SMC pads IO specifications
5.6.1 SMC 5V pads IO specifications
NOTE
In Table 15, Table 16, "VDDE" is the VDDM_SMD supply
5.6.1.1
SMC 5V pads IO DC specifications
Table 15. SMC 5V IO DC specifications(4.5V<vdde<5.5V)
Symbol
Characteristic
Min
Typ
Max
Unit
Vil
Low level input voltage
−0.3
0.35 × vdde
V
Vih
High level input voltage
0.65 × vdde
vdde + 0.3
V
Schmitt trigger hysteresis
0.1 × vdde
V
−130
μA
Vhyst
Ipu
Internal pull up device current
(Vin=Vil)
Ipu
Internal pull up device current
(Vin=Vih)
Ipd
Internal pull down device current
(Vin=Vil)
Ipd
Internal pull down device current
(Vin=Vih)
Iin
Input leakage current (ipp_pue=0)
Vol
Low level output voltage (Iol=+20
mA)
−10
10
−2.5
μA
μA
130
μA
2.5
μA
0.32
V
Table continues on the next page...
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NXP Semiconductors
21
SMC pads IO specifications
Table 15. SMC 5V IO DC specifications(4.5V<vdde<5.5V) (continued)
Symbol
Characteristic
Min
Voh
High level output voltage (Ioh=-20
mA)
Vsum
Vsum ( | Vol | + | Voh | ) (Iol=+40
mA and Ioh=-40 mA)
Voh delta / Vol
delta
Delta Voh across one motor
segment and Delta Vol across one
motor segment
Typ
Max
Unit
vdde − 0.32
V
1.0
V
−50
50
mV
Rdsonh
Pad drive active high impedance
(test load Ioh = 30 mA)
4
13
Ω
Rdsonl
Pad drive active low impedance
(test load Iol = 30 mA)
2.75
9
Ω
5.6.1.2
SMC 5V pads IO AC specifications
Table 16. SMC 5V IO functional pad AC specifications (4.5V<vdde<5.5V)
Name
Symbol
Symbol
Rise/Fall Edge (ns)
Min
CMOS input
Drive Load
(pF)
Max
0.5/0.5
Drive/Slew
Rate Select
ipp_sre_lv
0.5
NA
5.6.2 SMC 3.3 V pads IO specifications
NOTE
In Table 17, Table 18, the "VDDE" refers to the VDDM_SMD
supply.
5.6.2.1
Symbol
SMC 3.3 V pads IO DC specifications
Table 17. SMC 3.3 V pads IO DC specifications (3.0V<vdde<3.6V)
Characteristic
Min
Typ
Max
Unit
Vil
Low level input voltage
-0.3
0.35 × vdde
V
Vih
High level input voltage
0.65 × vdde
vdde + 0.3
V
Schmitt trigger hysteresis
0.1 × vdde
V
-130
μA
Vhyst
Ipu
Internal pull up device current
(Vin=Vil)
Ipu
Internal pull up device current
(Vin=Vih)
Ipd
Internal pull down device current
(Vin=Vil)
-10
10
μA
μA
Table continues on the next page...
SAC57D54H, Rev. 5, 05/2016
22
NXP Semiconductors
SMC pads IO specifications
Table 17. SMC 3.3 V pads IO DC specifications (3.0V<vdde<3.6V) (continued)
Symbol
Characteristic
Min
Ipd
Internal pull down device current
(Vin=Vih)
Iin
Input leakage current (ipp_pue=0)
Vol
Low level output voltage (Iol=+10
mA)
Voh
High level output voltage (Ioh=-10
mA)
5.6.2.2
Typ
-2.5
Max
Unit
130
μA
+2.5
μA
0.32
V
vdde − 0.32
V
SMC 3.3 V pads IO AC specifications
Table 18. SMC 3.3 V functional pads IO DC specifications (3.0V<vdde<3.6V)
Name
Symbol
Symbol
Rise/Fall Edge (ns)
Min
CMOS input
Drive Load
(pF)
Max
0.5/0.5
Drive/Slew
Rate Select
ipp_sre_lv
0.5
NA
5.7 RSDS pads electrical specifications
Table 19. RSDS pads electrical specifications
Symbol
Parameter
Min
Typ
Max
Unit
3.3
-
V
Supply Voltages
Vdde
1
3
RSDS_Tx
Normal mode (Vdde)
-
3
-
mA
Power down mode
-
1
-
µA
RSDS reference
Normal mode
-
400
-
μA
Power down mode
-
0.1
-
µA
50
50
MHz
Data rate
Data Frequency
Driver specs
Vod
Differential o/p voltage
100
200
400
mV
Vos
Common mode voltage
(VOS)
-
1.2
-
V
Rise/Fall time
-
500
-
ps
Startup Time (RSDS_ref)
-
6
-
µs
Startup time (RSDSTx)
-
6
-
µs
tR/tF
Termination
Table continues on the next page...
SAC57D54H, Rev. 5, 05/2016
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23
SMC pads IO specifications
Table 19. RSDS pads electrical specifications (continued)
Termination Resistance
-
100
-
ohm
Trans. Line (differential Zo)
95
100
105
ohm
382
-
ps
Skew
tskew
2
Skew between different
RSDS lines
-
1. vdde is the VDDE_B supply
2. This value is derived from simulation assuming default register setting of all 1’s for skew. There are 8 programmable bits to
provide 256 different skew numbers with various combinations of these bits. See the TCON chapter of the device
Reference Manual for details. All "0" combination of 8 bits is not valid.
Pad_p
pad_n
80%
80%
Crossover point
pad_p
Differential
Data Lines
20%
pad_n
20%
Fall
Time
Rise
Time
(tf)
(tr)
Figure 5. Rise/Fall transition
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NXP Semiconductors
SMC pads IO specifications
Pad_p
Crossover point
Vos
Valid outputs
Differential
outputs
pad_n
Enable time
(tdz)
ipp_obe
Figure 6. Enable time
Figure 7. Rise/Fall transition of differential output
5.8 LVDS pads electrical specifications
Table 20. LVDS pads electrical specifications
Symbol
Parameter
Min
Typ
Max
Unit
Supply Voltages
Table continues on the next page...
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25
SMC pads IO specifications
Table 20. LVDS pads electrical specifications (continued)
V DDE , 1
3
3.3
-
V
Current consumption
LVDS Tx
Normal mode
(VDDE1 )
—
5
—
mA
Switching currents
—
±1.5 (during output
transition)
—
mA
Power down mode
—
1
—
µA
LVDS Reference
Normal mode
—
400
—
µA
Power down mode
—
0.1
—
µA
—
560
Mbps
Data Rate
Data Frequency
—
Driver specs
Vod
Differential o/p
voltage 2
247
—
454
mV
Vos
Common mode
voltage (VOS)
1.125
—
1.375
V
tr/tf
Rise/Fall time 3
—
—
800
ps
Startup Time
(lvds_ref)
—
5
—
µs
Startup time
(lvds_Tx)
—
5
—
µs
Termination
Termination
Resistance
—
100±1%
—
Ω
Trans. Line
(differential Zo)
95
100
105
Ω
1. VDDE is the VDDE_B supply.
2. The limit applies to the default drive current.
3. Rise/fall time is assumed to be measured with 20%-80% levels.
5.9 Functional reset pad electrical specifications
The device implements a dedicated bidirectional RESET pin.
Table 21. Functional reset pad electrical specifications
Symbol
Parameter
Conditions
Value
Min
Typ
Max
Unit
VIH
Input high level TTL (Schmitt Trigger)
—
2.0
—
VDDE_A+0.4 V
VIL
Input low level TTL (Schmitt Trigger)
—
–0.4
—
0.65
V
VHYS
Input hysteresis TTL (Schmitt Trigger)
—
300
—
—
mV
Table continues on the next page...
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 21. Functional reset pad electrical specifications (continued)
Symbol
Parameter
Conditions
Value
Min
Unit
Typ
Max
VDD_POR
Minimum supply for strong pull-down
activation
—
—
—
1.2
V
IOL_R
Strong pull-down current
Device under power-on reset
0.2
—
—
mA
VDDE_A=VDD_POR
VOL = 0.35 x VDDE_A
WFRST
RESET input filtered pulse
—
—
—
500
ns
WNFRST
RESET input not filtered pulse
—
2000
—
—
ns
|IWPU|
Weak pull-up current absolute value
RESET pin VIN = VDD
23
—
82
µA
5.10 PORST electrical specifications
Table 22. PORST electrical specifications
Symbol
Parameter
Value
Min
WFPORST
PORST input filtered pulse
WNFPORST
PORST input not filtered pulse
VIH
VIL
Typ
Unit
Max
—
—
200
ns
1000
—
—
ns
Input high level
—
0.65 x VDDE_A
—
V
Input low level
—
0.35 x VDDE_A
—
V
6 Peripheral operating requirements and behaviors
6.1 Analog modules
6.1.1 ADC electrical specifications
The device provides a 12-bit Successive Approximation Register (SAR) Analog-toDigital Converter.
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Analog modules
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
( 2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out
7
( 1)
6
5
(5)
4
(4)
3
(3)
2
1
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
1 LSB (ideal)
0
1
2
3
Offset Error OSE
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Figure 8. ADC characteristics and error definitions
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NXP Semiconductors
Analog modules
6.1.1.1
Input impedance and ADC accuracy
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD_IO
Source
Filter
RS
Current Limiter
RF
Sampling
RSW1
RAD
RL
CF
VA
Channel
Selection
CP1
CP2
CS
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL
Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 9. Input equivalent circuit
Table 23. ADC conversion characteristics
Symbol
fCK
Parameter
Conditions
Min
Typ
Max
Unit
15.2
80
80
MHz
—
—
1
MHz
80 MHz@ 100 ohm source
impedance
250
800
—
ns
80 MHz
700
—
—
ns
80 MHz
1.54
—
—
µs
1
—
—
ADC Clock frequency (depends on —
ADC configuration) (The duty cycle
depends on AD_CK1 frequency)
fs
Sampling frequency
tsample
tconv
ttotal_conv
Sample
80 MHz
time2
Conversion time3
Total Conversion time tsample +
tconv (for standard and extended
channels)
Total Conversion time tsample +
tconv (for precision channels)
CS
ADC input sampling capacitance
—
—
3
5
pF
5
ADC input pin capacitance 1
—
—
—
5
pF
CP2
5
ADC input pin capacitance 2
—
—
—
0.8
pF
RSW15
Internal resistance of analog
source
VREF range = 4.5 to 5.5 V
—
—
0.3
kΩ
VREF range = 3.15 to 3.6 V
—
—
875
Ω
Internal resistance of analog
source
—
—
—
825
Ω
Max leakage
125°C
—
—
250
nA
—
5
mA
CP1
5
RAD
ADC Analog Pad
(pad going to one
ADC)
Max positive/negative injection
–5
Table continues on the next page...
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Analog modules
Table 23. ADC conversion characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ADC (12-bit mode)
INL
Integral non-linearity
—
–2
—
2
LSB
DNL
Differential non-linearity
—
–1
—
1
LSB
OFS
Offset error
—
–6
—
6
LSB
GNE
Gain error
—
–4
—
4
LSB
–6
+/- 4
6
LSB
—
+/- 5
—
LSB
—
—
<1
μs
TUEprecision channels Total unadjusted error for precision Without current injection
channels
With current injection
Trecovery
Differential non-linearity
—
ADC (10-bit
mode)6
INL
Integral non-linearity
—
–1
—
1
LSB
DNL
Differential non-linearity
—
–0.7
—
0.7
LSB
OFS
Offset error
—
–4
—
4
LSB
GNE
Gain error
—
–4
—
4
LSB
–5
+/- 3
5
LSB
—
+/- 4
—
LSB
—
—
<1
μs
TUEprecision channels Total unadjusted error for precision Without current injection
channels
With current injection
Trecovery
Differential non-linearity
—
1. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheral
clock based on register configuration in the ADC.
2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the
sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tsample depend on programming.
3. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
4. Apart from tsample and tconv, few cycles are used up in ADC digital interface and hence the overall throughput from the
ADC is lower.
5. See Figure 2.
6. Measurements taken with same ADC accuracy settings as for 12bit. ADC data is read from CDR with last 2-LSBs ignored.
6.1.2 Analog Comparator (CMP) electrical specifications
Table 24. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
250
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
5
11
μA
VAIN
Analog input voltage
VSS
—
VDDE_A
V
-42
—
42
mV
—
1
25
mV
—
20
50
mV
—
40
70
mV
VAIO
VH
Analog input offset voltage
1
Analog comparator hysteresis
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
2
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Clocks and PLL interfaces modules
Table 24. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
60
105
mV
—
—
250
ns
—
5
14
μs
Analog comparator initialization delay, High speed
mode4
—
4
μs
Analog comparator initialization delay, Low speed
mode 4
—
100
μs
3.3V Reference Voltage
—
6
9
μA
INL
6-bit DAC integral non-linearity
–1
—
1
LSB5
DNL
6-bit DAC differential non-linearity
–0.8
—
0.8
LSB
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
tDHS
tDLS
IDAC6b
Propagation Delay, High Speed Mode (Full Swing) 1, 3
Propagation Delay, Low power Mode (Full Swing)
1, 3
6-bit DAC current adder (when enabled)
1.
2.
3.
4.
Measured with hysteresis mode of 00
Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_HV_A-0.6V
Full swing = VIH, VIL
Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
5. 1 LSB = Vreference/64
6.2 Clocks and PLL interfaces modules
6.2.1 Fast Oscillator (FXOSC) electrical specifications
This device provides a driver for oscillator in pierce configuration with amplitude
control. Controlling the amplitude allows a more sinusoidal oscillation, reducing in this
way the EMI. Other benefits arises by reducing the power consumption. This Loop
Controlled Pierce (LCP mode) requires good practices to reduce the stray capacitance of
traces between crystal and MCU.
An operation in Full Swing Pierce (FSP mode), implemented by an inverter is also
available in case of parasitic capacitances and cannot be reduced by using crystal with
high equivalent series resistance. For this mode, a special care needs to be taken
regarding the serial resistance used to avoid the crystal overdrive.
Other two modes called External (EXT Wave) and disable (OFF mode) are provided. For
EXT Wave, the drive is disabled and an external source of clock within CMOS level
based in analog oscillator supply can be used. When OFF, EXTAL is pulled down by 240
Kohms resistor and the feedback resistor remains active connecting XTAL through
EXTAL by 1M resistor.
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Clocks and PLL interfaces modules
Figure 10. Oscillator connections scheme
Table 25. Fast Oscillator electrical characteristics
Symbol
Parameter
Mode
fXOSCHS
Oscillator
frequency
FSP/LCP
TXOSCHSSU
Startup time
FSP/LCP
Supply current FSP
LCP
Conditions
Min
Typ
8
Max
40
Unit
MHz
8-40 MHz
1
ms
8 MHz
2.2
mA
16 MHz
2.2
40 MHz
3.2
8 MHz
141
16 MHz
252
µA
40 MHz
518
VIH
Input High
EXT Wave
level CMOS
Schmitt trigger
Oscillator
supply=3.3
1.84
V
VIL
Input low level EXT Wave
CMOS
Schmitt trigger
Oscillator
supply=3.3
1.48
V
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Clocks and PLL interfaces modules
6.2.2 Slow Oscillator (SXOSC) electrical specifications
Table 26. Slow Oscillator (SXOSC) electrical
specifications
Symbol
Parameter
fosc_lo
Oscillator crystal
or resonator
frequency
tcst
Crystal Start-up
Time1, 2
Vpp
Peak-to-Peak
XTAL Amplitude
Condition
Min
Typ
32
Max
Unit
40
kHz
2
s
0.53
V
1. This parameter is characterized before qualification rather than 100% tested.
2. Proper PC board layout procedures must be followed to achieve specifications.
3. RF is integrated and may not be attached externally.
6.2.3 Fast internal RC Oscillator (FIRC) electrical specifications
Table 27. Fast internal RC Oscillator electrical specifications
Symbol
Parameter
Conditions
Value
Unit
Min
Typ
Max
—
16
—
MHz
—
1.51
µs
FTarget
IRC target frequency
—
Tstartup
Startup time
—
TSTJIT
Cycle to cycle jitter
—
—
1.5
%
TLTJIT
Long term jitter
—
—
0.2
%
IVDDHV
Current consumption on 3.3 V power
supply
After Tstartup
—
—
75
µA
IVDDLV
Current consumption on 1.2 V power
supply
After Tstartup
—
—
25
µA
1. The start-up time is generally 16 clock cycles of FIRC untrimmed clock.
6.2.4 Slow internal RC oscillator (SIRC) electrical specifications
Table 28. Slow internal RC oscillator electrical specifications
Symbol
Fosc
Parameter
Oscillator
frequency
Condition
Calibrated
Min
119
Typ
128
Temperature
dependence
Max
Unit
136.5
kHz
600
ppm/C
Table continues on the next page...
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Clocks and PLL interfaces modules
Table 28. Slow internal RC oscillator electrical specifications
(continued)
Symbol
Parameter
Condition
Min
Typ
Max
Supply
dependence
Supply current
Unit
18
%/V
Clock running
2.75
µA
Clock stopped
200
nA
6.2.5 PLL electrical specifications
Table 29. PLL electrical specifications
Parameter
Min
Typ
Max
Unit
Input Frequency
8
40
MHz
VCO Frequency Range
600
1280
MHz
Duty Cycle at pllclkout
48%
52%
Period Jitter
See Table 30
TIE
See Table 30
Modulation Depth (Center Spread)
+/- 0.25%
Comments
This specification is guaranteed
at PLL IP boundary
ps
NON SSCG mode
at 960 M Integrated over 1MHz
offset not valid in SSCG mode
+/- 3.0%
Modulation Frequency
32
KHz
Lock Time
60
µs
Calibration mode
Table 30. Jitter calculation
Type of jitter
Jitter due to
Supply
Noise (ps)
JSN1
Jitter due to
Fractional Mode
(ps) JSDM2
Jitter due to
Fractional Mode
JSSCG (ps) 3
1 Sigma
Random
Jitter JRJ
(ps) 4
Total Period Jitter (ps)
0.1% of
pllclkout1,2
+/-(JSN+JSDM+JSSCG+N[4]
×JRJ)
Long Term Jitter
(Integer Mode)
40
+/-(N x JRJ)
Long Term jitter
(Fractional Mode)
100
+/-(N x JRJ)
Period Jitter
60 ps
3% of pllclkout1,2
Modulation depth
1. This jitter component is due to self noise generated due to bond wire inductances on different PLL supplies. The jitter value
is valid for inductor value of 5nH or less each on avdd, avss, dvdd, dvss.
2. This jitter component is added when the PLL is working in the fractional mode.
3. This jitter component is added when the PLL is working in the Spread Spectrum Mode. Else it is 0.
4. The value of N is dependent on the accuracy requirement of the application. See Percentage of sample exceeding
specified value of jitter table
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NXP Semiconductors
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Table 31. Percentage of sample exceeding specified value of jitter
N
Percentage of samples exceeding specified value of jitter
(%)
1
31.73
2
4.55
3
0.27
4
6.30 × 1e-03
5
5.63 × 1e-05
6
2.00 × 1e-07
7
2.82 × 1e-10
6.3 Memory interfaces
6.3.1 Flash memory specifications
NOTE
Flash specs defined in this section at 150°C are also valid for
the maximum temperature specifications of the device.
6.3.1.1
Flash memory program and erase specifications
NOTE
All timing, voltage, and current numbers specified in this
section are defined for a single embedded flash memory within
an SoC, and represent average currents for given supplies and
operations.
Table 32 shows the estimated Program/Erase times.
Table 32. Flash memory program and erase specifications
Characteristic1
Symbol
Typ2
Factory
Programming3, 4
Field Update
Initial
Max
Initial
Max, Full
Temp
Typical
End of
Life5
20°C ≤TA
≤30°C
-40°C ≤TJ
≤150°C
-40°C ≤TJ
≤150°C
Unit
Lifetime Max6
≤ 1,000
cycles
≤ 250,000
cycles
tdwpgm
Doubleword (64 bits) program time 43
100
150
55
500
μs
tppgm
Page (256 bits) program time
200
300
108
500
μs
73
Table continues on the next page...
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Memory interfaces
Table 32. Flash memory program and erase specifications (continued)
Characteristic1
Symbol
Typ2
Factory
Programming3, 4
Field Update
Initial
Max
Initial
Max, Full
Temp
Typical
End of
Life5
20°C ≤TA
≤30°C
-40°C ≤TJ
≤150°C
-40°C ≤TJ
≤150°C
Unit
Lifetime Max6
≤ 1,000
cycles
≤ 250,000
cycles
tqppgn
Quad-page (1024 bits) program
time
268
800
1,200
396
2,000
μs
t16kers
16 KB Block erase time
168
290
320
250
1,000
ms
t16kpgn
16 KB Block program time
34
45
50
40
1,000
ms
t32kers
32 KB Block erase time
217
360
390
310
1,200
ms
t32kpgm
32 KB Block program time
69
100
110
90
1,200
ms
t64kers
64 KB Block erase time
315
490
590
420
1,600
ms
t64kpgm
64 KB Block program time
138
180
210
170
1,600
t256kers
256 KB Block erase time
884
1,520
2,030
1,080
4,000
—
ms
t256kpgm
256 KB Block program time
552
720
880
650
4,000
—
ms
ms
1. Program times are actual hardware programming times and do not include software overhead. Block program times
assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 150 cycles, nominal voltage.
4. Plant Programing times provide guidance for timeout limits used in the factory.
5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
6. Conditions: -40°C ≤ TJ ≤ 150°C, full spec voltage.
6.3.1.2
Flash memory Array Integrity and Margin Read specifications
Table 33. Flash memory Array Integrity and Margin Read specifications
Symbol
Characteristic
Min
Typical
Max1
Units
tai16kseq
Array Integrity time for sequential sequence on 16KB block.
—
—
512 x
Tperiod x
Nread
—
tai32kseq
Array Integrity time for sequential sequence on 32KB block.
—
—
1024 x
Tperiod x
Nread
—
tai64kseq
Array Integrity time for sequential sequence on 64KB block.
—
—
2048 x
Tperiod x
Nread
—
tai256kseq
Array Integrity time for sequential sequence on 256KB block.
—
—
8192 x
Tperiod x
Nread
—
tmr16kseq
Margin Read time for sequential sequence on 16KB block.
73.81
—
110.7
μs
tmr32kseq
Margin Read time for sequential sequence on 32KB block.
128.43
—
192.6
μs
2
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Table 33. Flash memory Array Integrity and Margin Read specifications (continued)
Min
Typical
Max1
Units
Margin Read time for sequential sequence on 64KB block.
237.65
—
356.5
μs
Margin Read time for sequential sequence on 256KB block.
893.01
—
1,339.5
μs
Symbol
Characteristic
tmr64kseq
tmr256kseq
2
1. Array Integrity times need to be calculated and is dependant on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires
6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the
address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
6.3.1.3
Flash memory module life specifications
Table 34. Flash memory module life specifications
Symbol
Array P/E
cycles
Data
retention
Characteristic
Conditions
Min
Typical
Units
Number of program/erase cycles per block
for 16 KB, 32 KB and 64 KB blocks.1
—
250,000
—
P/E
cycles
Number of program/erase cycles per block
for 256 KB blocks.2
—
1,000
250,000
P/E
cycles
Minimum data retention.
Blocks with 0 - 1,000 P/E
cycles.
50
—
Years
Blocks with 100,000 P/E
cycles.
20
—
Years
Blocks with 250,000 P/E
cycles.
10
—
Years
1. Program and erase supported across standard temperature specs.
2. Program and erase supported across standard temperature specs.
6.3.1.4
Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the
following figure. The spec window represents qualified limits. The extrapolated dotted
line demonstrates technology capability, however is beyond the qualification limits.
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37
Memory interfaces
6.3.1.5
Symbol
Flash memory AC timing specifications
Table 35. Flash memory AC timing specifications
Characteristic
Min
Typical
Max
Units
Time from setting the MCR-PSUS bit until MCR-DONE bit is set
to a 1.
—
7
9.1
μs
plus four
system
clock
periods
plus four
system
clock
periods
Time from setting the MCR-ESUS bit until MCR-DONE bit is set
to a 1.
—
16
20.8
plus four
system
clock
periods
plus four
system
clock
periods
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low.
—
—
100
ns
tdone
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared.
—
—
5
ns
tdones
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1.
—
16
20.8
μs
plus four
system
clock
periods
plus four
system
clock
periods
Time to recover once exiting low power mode.
16
—
45
tpsus
tesus
tres
tdrcv
μs
μs
Table continues on the next page...
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Table 35. Flash memory AC timing specifications (continued)
Symbol
Characteristic
Min
Typical
plus seven
system
clock
periods.
Max
Units
plus seven
system
clock
periods
taistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin Read
or Array Integrity until the UT0-AID bit is cleared. This time also
applies to the resuming from a suspend or breakpoint by
clearing AISUS or clearing NAIBP
—
—
5
ns
taistop
Time from 1 to 0 transition of UT0-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also applies
to the UT0-AISUS to UT0-AID setting in the event of a Array
Integrity suspend request.
—
—
80
ns
Time from 1 to 0 transition of UT0-AIE initiating a Margin Read
abort until the UT0-AID bit is set. This time also applies to the
UT0-AISUS to UT0-AID setting in the event of a Margin Read
suspend request.
10.36
tmrstop
6.3.1.6
plus fifteen
system
clock
periods
—
plus four
system
clock
periods
20.42
μs
plus four
system
clock
periods
Flash read wait state and address pipeline control settings
The following table describes the recommended RWSC and APC settings at various
operating frequencies based on specified intrinsic flash access times of the flash module
controller array at 150 °C.
Table 36. Flash read wait state and address pipeline control guidelines
Flash Frequency
RWSC setting
APC setting
0 MHz < fFLASH ≤ 33 MHz
0
0
33 MHz < fFLASH ≤ 100 MHz
2
1
100 MHz < fFLASH ≤ 133 MHz
3
1
133 MHz < fFLASH ≤ 167 MHz
4
1
167 MHz < fFLASH ≤ 200 MHz
5
2
6.3.2 QuadSPI AC specifications
• Measurements are with a load of 35 pF on output pins. Input slew: 1ns, DSE[1:0]=11
• QuadSPI input timing is with 15pF load on flash output
The following table lists various QuadSPI modes and their corresponding configurations.
These DDR configurations are applicable when used without learning. Please see the
device reference manual for register and bit descriptions.
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Table 37. QuadSPI read/write settings
QuadSPI Modes
QuadSPI_MCR[D QuadSPI_MCR[D QuadSPI_MCR
QS_EN]
[SCLKCFG]
DR_EN]
QuadSPI_SOCCR QuadSPI_FLSH
[SOCCFG]
CR[TDH]
SDR
mode
Internal DQS 0
mode
1
07h
002F_002Fh
00
DDR
mode
(without
learning
)
4x Sampling
mode
1
0
Don't care
Don't care
10
Internal DQS 1
mode
1
03h
002F_002Fh
10
HyperFlash
mode
1
02h
0000_0000h
10
6.3.2.1
1
SDR mode
1
2
3
Clock
Tck
SCK
Tcsh
Tcss
CS
Tih
Tis
Data in
Figure 11. QuadSPI input timing (SDR mode) diagram
NOTE
• A negative time indicates the actual capture edge inside the
device is earlier than clock appearing at pad.
• All board delays need to be added appropriately
• Input hold time being negative does not have any
implication or max achievable frequency
Table 38. QuadSPI input timing (SDR mode) specifications
Symbol
Parameter
Value
Min
Unit
Max
Tis
Setup time for incoming data
5.5
-
ns
Tih
Hold time for incoming data
1.5
-
ns
FSCK
SCK clock frequency
-
80
MHz
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NOTE
For SDR mode, QuadSPI_MCR[DQS_EN] must be set as '1'.
The delay chain settings for this mode is mentioned Table 37.
1
2
3
Clock
Tck
SCK
Tcsh
Tcss
CS
Toh
Tov
Data out
Figure 12. QuadSPI output timing (SDR mode) diagram
Table 39. QuadSPI output timing (SDR mode) specifications
Symbol
Parameter
Value
Min
Unit
Max
Tov
Output Data Valid
-
2.8
ns
Toh
Output Data Hold
-1.5
-
ns
Tck
SCK clock period
-
80
MHz
Tcss
Chip select output setup time
1
-
ns
Tcsh
Chip select output hold time
-1
-
ns
6.3.2.2
DDR mode
1
2
3
Clock
Tck
SCK
CS
Tis
Tih
Data in
Figure 13. QuadSPI input timing (DDR mode) diagram
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Table 40. QuadSPI input timing (DDR mode) specifications without learning (valid across
PVT)
Symbol
Parameter
Value
Min
Unit
Configuration
Max
Tis
Setup time for incoming 5.5
data
—
ns
Tih
Hold time for incoming
data
—
ns
FSCK
SCK Clock Frequency
1.5
—
45 (Internal DQS)
—
35 (4x sampling)
MHz
Refer Table 37
QSPI_SMPR[DDRS
MP]=1
Table 41. QuadSPI input timing (DDR mode) specifications with learning
Symbol
Parameter
Value
Min
FSCK
SCK Clock Frequency
Unit
Note
Max
—
80 (Internal DQS) 1
—
66 (4x sampling)
MHz
Flash data valid window must be >
3.5 ns
Flash data valid window must be >
3.5 ns, Flash max access time must
be < = 6.5 ns
1. Multiple (dynamic) calibration across voltage/temperature on board required.
1
2
3
Clock
Tck
SCK
Tcss
Tcsh
CS
Tov
Toh
Data out
Figure 14. QuadSPI output timing (DDR mode) diagram
Table 42. QuadSPI output timing (DDR mode) specifications
Symbol
Parameter
Value
Min
Unit
Max
Tov
Output Data Valid
-
4.5
ns
Toh
Output Data Hold
1.5
-
ns
Tcss
Chip select output setup time
1
-
ns
Table continues on the next page...
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Table 42. QuadSPI output timing (DDR mode) specifications (continued)
Symbol
Parameter
Value
Min
Tcsh
Chip select output hold time
6.3.2.3
-1
Unit
Max
-
ns
HyperFlash mode
NOTE
In HyperFlash mode, the read/write maximum frequency is 90
MHz.
RDS
TsMIN ThMIN
DI[7:0]
Figure 15. QuadSPI input timing (Hyperflash mode) diagram
Table 43. QuadSPI input timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Min
Unit
Configurations
Max
Tis
Setup time for incoming data
2
-
ns
Tih
Hold time for incoming data
2
-
ns
Refer Table 37
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CK
CK 2
Tclk SKMAX
Tclk SKMIN
THO
TDVO
Output Invalid Data
Figure 16. QuadSPI output timing (Hyperflash mode) diagram
Table 44. QuadSPI output timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Min
Unit
Max
TDVO
Output Data Valid
-
3
ns
THO
Output Data Hold
1.3
-
ns
TclkSKMAX
CK to CK2 skew max
-
T/4 + 0.5
ns
TclkSKMIN
CK to CK2 skew min
T/4 - 0.5
-
ns
6.3.3 SDR AC specifications
For details on read timings with and without the external capacitor and capacitance value,
refer the "Chip-specific MDDRC information" section of the device Reference Manual.
For SDRAM operating frequencies above 80 MHz the SDR_A12 pin cannot be used for
the SDRAM address. At higher operating frequencies this pin requires an external
capacitor connected with VSS to adjust the read timing.
Round trip delay (consisting of board trace delay of SDCK and DQ(READ)) should not
be more than 450 ps.
NOTE
1. All transitions measured at mid-supply (VDDE_SDR/2).
2. Data signal which are driven from ATE are given a swing
of 20%/80% of full signal swing.
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3. The DQS Config Offset Count register
(MDDRC_DQS_CFG) would need to be programmed with
value 0x0000_16h in the initialization code when operating
SDR at 160 MHz.
4. The SRE settings for SDR_CLK pad going to the external
memory should be 2'b11 (as noted in the "Section 15.3.2.1
Recommended settings for SRE pads" in the Reference
Manual). SRE settings for loopback clock A12 has been
reduced to 2'b01 in CZ to help with EMC improvement.
Table 45. SDR @ 160 MHz AC timing specification
ID
Symbol
—
tSDCK
DD1
DD21
Parameter
Min
Typ
Max
Unit
Clock Period
—
6.25
—
ns
tQVS
Data output Valid (Write transaction)
—
—
(0.5 × tSDCK) + 1.125
ns
tQH
Data output Hold (Write transaction)
1.5
—
—
ns
DD3
tIS
Data Input Setup (Read transaction)
-0.4
—
DD4
tIH
Data input Hold (Read transaction)
3.7
—
—
ns
—
tCH
CK HIGH pulse width
0.43
—
0.57
tCK
—
tCL
CK LOW pulse width
0.43
—
0.57
tCK
—
—
Series termination (Data/CLK/
Address/Command)
—
50
—
ohms
—
—
Trans. line impedance (Zo)
—
50
—
ohms
ns
1. Applies to command and address buses also.
Table 46. SDR @ 80 MHz AC timing specification
ID
Symbol
—
tSDCK
DD1
Parameter
Min
Typ
Max
Unit
Clock Period
—
12.5
—
ns
tQVS
Data output Valid (Write
transaction)
—
—
(0.5 × tSDCK) + 1.25
ns
DD21
tQH
Data output Hold (Write
transaction)
3.0
—
—
ns
DD3
tIS
Data Input Setup (Read
transaction)
2.2
—
DD4
tIH
Data input Hold (Read transaction)
2.0
—
—
ns
—
tCH
CK HIGH pulse width
0.43
—
0.57
tCK
—
tCL
CK LOW pulse width
0.43
—
0.57
tCK
—
—
Series termination (Data/CLK/
Address/Command)
—
50
—
ohms
—
—
Trans. line impedance (Zo)
—
50
—
ohms
ns
1. Applies to command and address buses also.
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Figure 17. SDR (@ 160 MHz and @ 80 MHz) AC read and write timings
6.3.3.1
SDR DC specifications
The SDR DC specifications are same as pad_fc_hv specs described in this document.
6.3.4 DDR2 SDRAM AC specifications
NOTE
DDR2-800 (-25E speed grade) is the lowest speed grade
supported. If self-refresh mechanism needs to be supported, an
external pull-down resistance needs to be connected to the DDR
CKE pin.
NOTE
Specified values in the table are at recommended operating
conditions with VDDE_DDR of 1.8±5.5%
Table 47. DDR2 SDRAM timing specifications1, 2, 3, 4, 5
ID
Symbol
—
F
—
VIX-AC
Parameter
Min
Typ
Max
Unit
Frequency of operation
(Clock Period)
—
—
320
MHz
MCK AC differential
crosspoint voltage
0.5 × VDDE_DDR —
0.175
—
0.5 × VDDE_DDR + 0.175 V
DD1
tDDR_CLK
Clock period
3.125
—
—
ns
DD2
tDDR_CLKH
High pulse width6
0.47
—
0.53
tCK
DD3
tDDR_CLKL
Low pulse width
0.47
—
0.53
tCK
DD4
tCMS
Address/Command
Output Setup
0.5 × tDDR_CLK–0.75
—
—
ns
DD5
tCMH
Address/Command
Output Hold
0.5 × tDDR_CLK–0.75
—
—
ns
DD6
tDQSS
First DQS latching
transition to associated
clock edge
-0.18 × tDDR_CLK
—
0.18 × tDDR_CLK
ns
Table continues on the next page...
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Table 47. DDR2 SDRAM timing specifications1, 2, 3, 4, 5 (continued)
ID
DD7
Symbol
tOS
Parameter
Min
Typ
Max
Unit
Data and Data Mask
Output Setup relative to
DQS (DDR Write Mode)
tDDR_CLK/4 − 0.4
—
—
ns
Data and Data Mask
Output Hold relative to
DQS (DDR Write Mode)
tDDR_CLK/4 − 0.4
—
—
ns
—
0.24
ns
8, 9
DD8
tOH
7, 10
DD9
tIS
Input Data Skew relative
to DQS11
—
—
Parallel termination
address lines
—
50
—
Ohms
—
—
Differential clock lines
—
100
—
Ohms
—
—
Trans. Line (differential
Zo)
—
50
—
Ohms
1.
2.
3.
4.
5.
6.
7.
8.
VDDE_DDR value is 1.8 V for DDR2 mode
CZ at -40 to 125 °C.
Measured with clock pin loaded with differential 100 ohm termination resistor.
All transitions measured at mid-supply (VDDE_DDR/2).
Measured with all outputs except the clock loaded with 50 ohm termination resistor to VDDE_DDR/2.
Pulse width high + pulse width low cannot exceed minimum and maximum clock period.
The losses for IO and package are 190 ps and are already included in the 400 ps budget taken by the device.
This specification relates to the required input setup time of DDR memories. The chip output setup should be larger than
the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation. DDR_DQ[31:24]
is relative to DDR_DQS[3]; DDR_DQ[23:16] is relative to DDR_DQS[2], DDR_DQ[15:8] is relative to DDR_DQS[1] and
DDR_DQ[7:0] is relative to DDR_DQS[0].
9. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
are valid for each subsequent DQS edge.
10. This specification relates to the required hold time of DDR memories. DDR_DQ[31:24] is relative to DDR_DQS[3];
DDR_DQ[23:16] is relative to DDR_DQS[2], DDR_DQ[15:8] is relative to DDR_DQS[1] and DDR_DQ[7:0] is relative to
DDR_DQS[0].
11. Data input skew is derived from each DDR_DQS clock edge. It begins with a DDR_DQS transition and ends when the last
data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to
routing or other factors).
Figure 18 shows the DDR2 SDRAM write timing.
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DD1
DD2
DDR_CLK
DD4
DD3
DDR_CLK
DD5
DDR_CSn , DDR_WE
DDR_RAS ,DDR_CAS
CMD
DDR_A[15:0]
ROW
COL
DDR_DQS
DD7
DDR_D[31:0]
WD1 WD2 WD3 WD4
DD7
DQS
DD6
DQ, DM(out)
tDS
tDH
Figure 18. DDR2 write timing
Figure 19 shows the DDR2 SDRAM read timing.
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DD1
DD2
DDR_CLK
DD3
DDR_CLK
CL= 4
DD5
n DDR_WE
DDR_CS::,
DDR_RAS, DDR_CAS
CMD
CL= 5
DD4
DDR_A[15:0]
ROW
COL
DQS Read
Preamble
DD9
CL= 4
DDR_DQS
DQS Read
Postamble
DDR_D[7:0]
CL = 5
RD1 RD2 RD3 RD4
DQS Read
Postamble
DQS Read
Preamble
DDR_DQS
DDR_D[7:0]
RD1 RD2 RD3 RD4
Figure 19. DDR2 read timing
6.4 Communication modules
6.4.1 SPI electrical specifications
Table 48. SPI electrical specifications
No
Symbol
Parameter
Conditions
Master (MTFE = 0)
High Speed Mode
low Speed mode
Min
Max
Min
Max
25
—
50
—
Unit
1
tSCK
SPI cycle time
Slave (MTFE = 0)
40
—
60
—
2
tCSC
PCS to SCK
delay
—
16
—
—
—
ns
3
tASC
After SCK delay
—
16
—
—
—
ns
4
tSDC
SCK duty cycle
—
tSCK/2 - 1
tSCK/2 + 1
—
—
ns
5
tA
Slave access
time
SS active to SOUT
valid
—
40
—
—
ns
6
tDIS
Slave SOUT
disable time
SS
inactive to SOUT
High-Z or invalid
—
25
—
—
ns
7
tPCSC
PCSx to PCSS
time
13
—
—
—
ns
—
ns
Table continues on the next page...
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Table 48. SPI electrical specifications (continued)
No
Symbol
8
tPASC
9
tSUI
10
11
12
tHI
tSUO
tHO
Parameter
High Speed Mode
low Speed mode
Min
Max
Min
Max
13
—
—
—
ns
Data setup time Master (MTFE = 0)
for inputs
Slave
NA
—
20
—
ns
4
—
4
—
Master (MTFE = 1,
CPHA = 0)
15
—
8
—
Master (MTFE = 1,
CPHA = 1)
15
—
20
—
Master (MTFE = 0)
NA
—
–2
—
Slave
4
—
4
—
—
PCSS to PCSx
time
Data hold time
for inputs
Conditions
—
Master (MTFE = 1,
CPHA = 0)
0
—
111
Master (MTFE = 1,
CPHA = 1)
0
—
-2
—
Data valid (after Master (MTFE = 0)
SCK edge)
Slave
—
NA
—
7
—
15
—
23
Master (MTFE = 1,
CPHA = 0)
—
7
—
19.51
Master (MTFE = 1,
CPHA = 1)
—
7
—
7
Master (MTFE = 0)
NA
—
–2
—
Slave
2
—
2
—
—
—
Data hold time
for outputs
Master (MTFE = 1,
CPHA = 0)
-2
—
101
Master (MTFE = 1,
CPHA = 1)
–2
—
–2
Unit
ns
ns
ns
1. SMPL_PTR should be set to 1
NOTE
Restriction for high speed modes:
• Maximum of one SPI will support 40 MHz Master mode
SCK
• 4 SPIs will support 20 MHz master SCK frequency.
• Maximum of one SPI will support 25 MHz Slave SCK
frequency.
• SIN(GPIO_20, PB[4]), DATAOUT(GPIO_19, PB[3]),
SCK(GPIO_27, PB[11]) groups support high frequency
mode.
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NOTE
For numbers shown in the following figures, see Table 48
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Figure 20. SPI classic SPI timing — master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
SIN
Data
First Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Figure 21. SPI classic SPI timing — master, CPHA = 1
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3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
First Data
SOUT
9
6
Data
Last Data
Data
Last Data
10
First Data
SIN
11
12
Figure 22. SPI classic SPI timing — slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Figure 23. SPI classic SPI timing — slave, CPHA = 1
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3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
11
First Data
Last Data
Data
Figure 24. SPI modified transfer format timing — master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Data
Last Data
11
Last Data
Figure 25. SPI modified transfer format timing — master, CPHA = 1
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3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
5
First Data
SOUT
Data
Last Data
10
9
Data
First Data
SIN
6
Last Data
Figure 26. SPI modified transfer format timing – slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Figure 27. SPI modified transfer format timing — slave, CPHA = 1
8
7
PCSS
PCSx
Figure 28. SPI PCS strobe (PCSS) timing
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6.4.2 Ethernet AC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.4.2.1
MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 49. MII signal switching specifications
Symbol
—
MII1
Description
RXCLK frequency
RXCLK pulse width high
Min.
Max.
Unit
—
25
MHz
35%
65%
RXCLK
period
MII2
RXCLK pulse width low
35%
65%
RXCLK
period
MII3
RXD[3:0], RXDV, RXER to RXCLK setup
5
—
ns
MII4
RXCLK to RXD[3:0], RXDV, RXER hold
5
—
ns
TXCLK frequency
—
25
MHz
35%
65%
TXCLK
—
MII5
TXCLK pulse width high
period
MII6
TXCLK pulse width low
35%
65%
TXCLK
period
MII7
TXCLK to TXD[3:0], TXEN, TXER invalid
2
—
ns
MII8
TXCLK to TXD[3:0], TXEN, TXER valid
—
25
ns
MII6
MII5
TXCLK (input)
MII8
MII7
TXD[n:0]
Valid data
TXEN
Valid data
TXER
Valid data
Figure 29. RMII/MII transmit signal timing diagram
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MediaLB (MLB) electrical specifications
MII2
MII1
MII3
MII4
RXCLK (input)
RXD[n:0]
Valid data
RXDV
Valid data
RXER
Valid data
Figure 30. RMII/MII receive signal timing diagram
6.4.2.2
RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 50. RMII signal switching specifications
Symbol
—
Description
EXTAL frequency (RMII input clock RMII_CLK)
Min.
Max.
Unit
—
50
MHz
RMII1
RMII_CLK pulse width high
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
4
—
ns
RMII4
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
2
—
ns
RMII7
RMII_CLK to TXD[1:0], TXEN invalid
4
—
ns
RMII8
RMII_CLK to TXD[1:0], TXEN valid
—
15
ns
6.4.3 MediaLB (MLB) electrical specifications
6.4.3.1
MLB 3-wire interface DC specifications
The section lists the MLB 3-wire interface electrical specifications.
Table 51. MediaLB 3-wire interface DC specifications
Parameter
Symbol
Test Conditions
Min
Max
Unit
Maximum input voltage
—
—
—
3.6
V
Low level input threshold
VIL
—
—
0.7
V
Table continues on the next page...
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MediaLB (MLB) electrical specifications
Table 51. MediaLB 3-wire interface DC specifications (continued)
Parameter
Symbol
Test Conditions
Min
Max
Unit
High level input threshold
VIH
See Note1
1.8
—
V
Low level output threshold
VOL
IOL = –6 mA
—
0.4
V
High level output threshold
VOH
IOH = –6 mA
2.0
—
V
Input leakage current
IL
0 < Vin < VDD
—
±10
μA
1. Higher VIH thresholds can be used; however, the risks associated with less noise margin in the system must be evaluated
and assumed by the customer.
6.4.3.2
MLB 3-wire interface electrical specifications
This section describes the timing electrical information of the MLB module.
Figure 31. MediaLB 3-wire Timing
Ground = 0.0 V; Load Capacitance = 60 pF, input transition= 1 ns ; MediaLB speed =
256/512 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold
as listed below; unless otherwise noted.
Table 52. MLB 3-wire 256/512 Fs Timing Parameters
Symbol
Parameter
Min
Max
Unit
Comment
fmck
MLBCLK operating frequency
11.264
25.6
MHz
256xFs at 44.0 kHz,
512xFs at 50.0 kHz
tmckr
MLBCLK rise time
−
1
ns
VIL to VIH
tmckf
MLBCLK fall time
−
1
ns
VIH to VIL
Table continues on the next page...
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MediaLB (MLB) electrical specifications
Table 52. MLB 3-wire 256/512 Fs Timing Parameters (continued)
Symbol
Parameter
Min
MLBCLK low time1
tmckl
tmckh
MLBCLK high time
Max
30
−
14
−
30
−
14
−
Unit
ns
Comment
256xFs
512xFs
ns
256xFs
512xFs
tdsmcf
MLBSIG/MLBDAT receiver input setup to
MLBCLK falling
3
−
ns
−
tdhmcf
MLBSIG/MLBDAT receiver input hold from
MLBCLK low
2
−
ns
−
tmcfdz
MLBSIG/MLBDAT output valid from
MLBCLK low2
0
16
ns
256xFs
0
12.5
Bus output hold from MLBCLK low
2
−
tmdzh
512xFs3
ns
−
1. MLBCLK low/high time includes the pluse width variation.
2. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final
driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the
maximum load capacitance listed.
3. Only 1 pair of MLB pads support 512 Fs:
PK[11] - MLB Signal Output
PK[12] - MLB Data Output
PK[13] - MLB clock input
Ground = 0.0 V; Load Capacitance = 40 pF, input transition= 1 ns; MediaLB speed =
1024 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as
listed below; unless otherwise noted.
Table 53. MLB 3-wire 1024 Fs Timing Parameters
Symbol
fmck
Parameter
MLBCLK Operating
Frequency1
Min
Max
45.056
−
−
51.2
Unit
MHz
Comment
1024 x fs at 44.0 kHz
1024 x fs at 50.0 kHz
fmckr
MLBCLK rise time
−
1
ns
VIL to VIH
fmckf
MLBCLK fall time
−
1
ns
VIH to VIL
tmckl
MLBCLK low time
6.1
−
ns
tmckh
MLBCLK high time
9.3
−
ns
tdsmcf
MLBSIG/MLBDAT receiver input setup
to MLBCLK falling
3
−
ns
tdhmcf
MLBSIG/MLBDAT receiver input hold
from MLBCLK low
2
−
ns
tmcfdz
MLBSIG/MLBDAT output valid from
MLBCLK low
−
16
ns
tmdzh
Bus Hold from MLBCLK low
2
−
ns
1. The controller can shut off MLBCLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a
runt pulse can occur on MLBCLK.
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Display modules
6.5 Display modules
6.5.1 LCD driver electrical specifications
NOTE
When using the LCD segment display module in the 208LQFP
package options the VDDE_B and VDDE_SDR supply pins should
be shorted together if LCD signal pins are used in both I/O
supply domains.
Table 54. LCD driver specifications
Symbol
1.
2.
3.
4.
Value1
Parameter
Unit
Min
Typ
Max
ZBP/FP
LCD output impedance (BP[n-1:0],
FP[m-1:0]) for output levels VLCD, VSS
-
-
10
kΩ
IBP/FP
LCD output current (BP[n-1:0],
FP[m-1:0]) for outputs charge/discharge
voltage levels VLCD2/3, VLCD1/2,
VLCD1/3) 2,3
-
2-180
-
µA
Offset
Offset of outputs with capacitive load
-
-
50 4
mV
VDD = 5.0 V ± 10%, TA = –40 to 105 °C, unless otherwise specified.
Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
With PWR = 0-3, BSTEN = 0-1, BSTAO = 0-1.
50 mV offset is only guaranteed across temperature with BSTEN=1 / BSTAO=1 up to 85oC.
6.5.2 2D-ACE electrical specifications
6.5.2.1 Interface to TFT LCD Panels (2D-ACE)
The following figure depicts the LCD interface timing for a generic active matrix color
TFT panel. In this figure signals are shown with positive polarity. The sequence of events
for active matrix interface timing is:
• PCLK latches data into the panel on its positive edge (when positive polarity is
selected). In active mode, PCLK runs continuously. This signal frequency could be
from 5 to 80 MHz depending on the panel type.
• HSYNC causes the panel to start a new line. It always encompasses at least one
PCLK pulse.
• VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DE acts like an output enable signal to the LCD panel. This output enables the data
to be shifted onto the display. When disabled, the data is invalid and the trace is off.
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2D-ACE electrical specifications
VSYNC
LINE 1
HSYNC
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
HSYNC
DE
1
2
3
m-1
m
PCLK
LD[23:0]
Figure 32. TFT LCD interface timing
6.5.2.2
Interface to TFT LCD Panels—pixel level timings
The following figure depicts depicts the horizontal timing (timing of one line), including
both the horizontal sync pulse and data. All parameters shown in the diagram are
programmable. This timing diagram corresponds to positive polarity of the PCLK signal
(meaning the data and sync signals change on the rising edge) and active-high polarity of
the HSYNC, VSYNC and DE signals. The user can select the polarity of the HSYNC and
VSYNC signals via the SYN_POL register, whether active-high or active-low. The
default is active-high. The DE signal is always active-high.
Pixel clock inversion and a flexible programmable pixel clock delay are also supported.
They are programmed via the DCU Clock Confide Register (DCCR) in the system clock
module.
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register.
The PW_H, BP_H and FP_H parameters are programmed via the HSYN PARA register.
The PW_V, BP_V and FP_V parameters are programmed via the VSYN_PARA register.
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2D-ACE electrical specifications
tHSP
tPWH
Start of line
tFPH
tSW
tBPH
tPCP
PCLK
Invalid Data
LD[23:0]
2
1
3
DELTA_X
Invalid Data
HSYNC
DE
Figure 33. Vertical sync pulse
tVSP
Start of Frame
tSH
tBPV
tPWV
tFPV
tHCP
HSYNC
LD[23:0]
(Line Data)
1
Invalid Data
2
3
DELTA_Y
Invalid Data
HSYNC
DE
Figure 34. Horizontal sync timing
Table 55. TFT LCD interface timing parameters—horizontal and vertical
Symbol
Parameter
Value
Unit
tPCP
Display pixel clock period
12.5
ns
tPWH
HSYNC pulse width
PW_H × tPCP
ns
tBPH
HSYNC back porch width
BP_H × tPCP
ns
tFPH
HSYNC front porch width
FP_H × tPCP
ns
tSW
Screen width
DELTA_X × tPCP
ns
tHSP
HSYNC (line) period
(PW_H + BP_H + FP_H + DELTA_X ) × tPCP
ns
tPWV
VSYNC pulse width
PWV × tHSP
ns
Table continues on the next page...
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2D-ACE electrical specifications
Table 55. TFT LCD interface timing parameters—horizontal and vertical (continued)
Symbol
Parameter
Value
Unit
tBPV
VSYNC back porch width
BP_V × tHSP
ns
tFPV
VSYNC front porch width
FP_V × tHSP
ns
tSH
Screen height
DELTA_Y × tHSP
ns
tVSP
VSYNC (frame) period
(PW_V + BP_V + FP_V + DELTA_Y ) × tHSP
ns
6.5.2.3
Interface to TFT LCD panels—access level
1
2
3
4
5
6
7
8
9
10
Pixel Clock
Data Bus
t HO
t DV
Valid Data
Figure 35. Display timing diagram
Table 56. Interface to TFT LCD panels—access level
Symbol
Parameter
Min
Max
Unit
Tpix
Pixel clock frequency
-
80
MHz
TDV
Data valid after pixel
clock for Data/Hysnc/
Vsync/DE
-
4.5
ns
THO
Output hold time for
data and control bits
0
-
ns
Tskew
Relative skew between data bits
3
ns
NOTE
The timing diagram is on the assumption that timing path
between this device and external display is full cycle.
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2D-ACE electrical specifications
6.5.3 Video input unit (VIU4) electrical specifications
Clock
fPIX_CLK
tDHD
tDSU
Data
Figure 36. VIU4 timing diagram
Table 57. VIU4 timing parameters
Symbol
Parameter
Min
Typ
Max
Unit
fPIX_CK
VIU4 pixel clock frequency
—
—
53
MHz
tDSU
VIU4 data setup time
4
—
—
ns
tDHD
VIU4 data hold time
1
—
—
ns
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TCON electrical specifications
6.5.4 TCON electrical specifications
6.5.4.1
TCON RSDS electrical specifications
1
2
3
4
5
6
7
8
9
10
PixelClock
Pixel Data
TCON
Clock In
TCON Divided
Clock Out
(50 MHz)
Pixel Data Out
TOV
TOV
TOH
TOH
Figure 37. TCON RSDS timing diagram
Table 58. TCON RSDS timing parameters
Symbol
Parameter
Value
Unit
Min
Max
TOV
Output data valid time
2
-
ns
TOH
Output data hold time
2
-
ns
6.5.4.2
TCON TTL electrical specifications
1
2
3
4
5
6
7
8
9
10
Pixel Clock
Data Bus and
Timing Signals
t HO
t DV
Valid Data
Figure 38. TCON TTL timing diagram
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Motor control modules
Table 59. TCON TTL timing parameters
Symbol
Parameter
Min
Max
Unit
Tpix
Pixel clock frequency
-
80
MHz
TDV
Data valid after pixel clock for data and timing
signals
-
5.5
ns
THO
Output hold time for data and control bits
0
-
ns
Tskew
Relative skew between data bits
-
3
ns
6.6 Motor control modules
6.6.1 Stepper Stall Detect (SSD) specifications
Table 60. SSD electrical specifications
Symbol
Value1
Parameter
Min
Typ
Max
VDDM/22 + 0.03
V
—
—
mA
0.8
1.0
1.2
MΩ
Input common
mode range
VSSM
—
VDDM
V
SSDCONST
SSD constant 3
0.539
0.574
0.610
—
SSDOFFSET
SSD offset
(unipolar, Nsample =
1024)
–53
—
45
counts
SSD offset (bipolar,
Nsample = 1024)
-40
—
40
SSD offset (bipolar
with offset cellation,
Nsample = 1024)
-5
—
5
SSD cmpout
sample rate
0.5
—
2.0
VVREF
Reference voltage
(IVREF = 0)
VDDM/2 – 0.03
IVREF
Reference voltage
output current
1.85
RIN
Input resistance
(against VDDM/2)
VIN
fSSDSMP
VDDM
/22
Unit
MHz
1. VDDM_SMD = 5.0 V ±10%, Tj = –40 to +125 °C.
2. VDDM is the voltage level of VDDM_SMD supply
3. If offset cancellation is enable, OFFCNC must equal 0b01 and the integration window must be greater than or equal to 2
ms. The integration window = fSSDSMP x Nsample.
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65
Debug specifications
6.7 Debug specifications
6.7.1 JTAG interface timing
Table 61. JTAG pin AC electrical characteristics 1
#
Symbol
Characteristic
Min
Max
Unit
1
tJCYC
TCK Cycle Time
62.5
—
ns
2
tJDC
TCK Clock Pulse Width
40
60
%
3
tTCKRISE
TCK Rise and Fall Times (40% - 70%)
—
3
ns
4
tTMSS, tTDIS
TMS, TDI Data Setup Time
5
—
ns
5
tTMSH, tTDIH
TMS, TDI Data Hold Time
5
—
ns
6
tTDOV
TCK Low to TDO Data Valid
—
20
ns
7
tTDOI
TCK Low to TDO Data Invalid
0
—
ns
8
tTDOHZ
TCK Low to TDO High Impedance
—
15
ns
9
tJCMPPW
JCOMP Assertion Time
100
—
ns
10
tJCMPS
JCOMP Setup Time to TCK Low
40
—
ns
11
tBSDV
TCK Falling Edge to Output Valid
—
600
ns
12
tBSDVZ
TCK Falling Edge to Output Valid out of High
Impedance
—
600
ns
13
tBSDHZ
TCK Falling Edge to Output High Impedance
—
600
ns
14
tBSDST
Boundary Scan Input Valid to TCK Rising Edge
15
—
ns
15
tBSDHT
TCK Rising Edge to Boundary Scan Input Invalid
15
—
ns
1. These specifications apply to JTAG boundary scan only.
TCK
2
3
2
1
3
Figure 39. JTAG test clock input timing
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Debug specifications
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 40. JTAG test access port timing
TCK
10
JCOMP
9
Figure 41. JTAG JCOMP timing
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Debug specifications
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 42. JTAG boundary scan timing
6.7.2 Debug trace timing specifications
Table 62. Debug trace operating behaviors
Symbol
Description
Tcyc
Clock period
Twl
Low pulse width
Twh
tDV
tHO
Min.
Max.
40
Unit
MHz
2
—
ns
High pulse width
2
—
ns
Data output valid
7.5
—
ns
Data output hold
0.5
—
ns
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Debug specifications
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 43. TRACE_CLKOUT specifications
trace output clock
trace output data
tHO
tDV
Figure 44. Trace data specifications
6.7.3 Wakeup Unit (WKPU) AC specifications
Table 63. WKPU glitch filter specifications
No.
Symbol
Parameter
Min
Typ
Max
Unit
1
WF
2
WNF
Pulse width that is rejected
—
—
20
ns
Pulse width that is passed
400
—
—
ns
6.7.4 External interrupt timing (IRQ pin)
Table 64. External interrupt timing specifications
No.
Symbol
Parameter
Conditions
Min
Max
Unit
1
tIPWL
IRQ pulse width low
—
3
—
tCYC
2
tIPWH
IRQ pulse width high
—
3
—
tCYC
3
tICYC
IRQ edge to edge time
—
6
—
tCYC
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Thermal attributes
These values applies when IRQ pins are configured for rising edge or falling edge events,
but not both.
IRQ
1
2
3
Figure 45. External interrupt timing
7 Thermal attributes
7.1 Thermal attributes
Board type
Symbol
Description
208LQFP
Unit
Notes
Single-layer (1s)
RθJA
Thermal
19.1
resistance, junction
to ambient (natural
convection)
°C/W
1,2
Four-layer (2s2p)
RθJA
Thermal
16.4
resistance, junction
to ambient (natural
convection)
°C/W
1,2,3
Single-layer (1s)
RθJMA
Thermal
12.4
resistance, junction
to ambient (200 ft./
min. air speed)
°C/W
1,3
Four-layer (2s2p)
RθJMA
Thermal
12.4
resistance, junction
to ambient (200 ft./
min. air speed)
°C/W
1,3
—
RθJB
Thermal
7.4
resistance, junction
to board
°C/W
4
—
RθJC
Thermal
5.3
resistance, junction
to case
°C/W
5
—
ΨJT
Thermal
0.2
characterization
parameter, junction
to package top
°C/W
6
Table continues on the next page...
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Thermal attributes
Board type
Symbol
ΨJB
—
Description
208LQFP
Thermal
0.3
characterization
parameter, junction
to package bottom
Unit
°C/W
Notes
7
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package. With provided Theta-JB, Max junction temperature must be 125
degreeC.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12.
Board type
Symbol
Description
516MAPBGA
Unit
Notes
Single-layer (1s)
RθJA
Thermal
23.2
resistance, junction
to ambient (natural
convection)
°C/W
1,2
Four-layer (2s2p)
RθJA
Thermal
16.2
resistance, junction
to ambient (natural
convection)
°C/W
1,2,3
Single-layer (1s)
RθJMA
Thermal
15.9
resistance, junction
to ambient (200 ft./
min. air speed)
°C/W
1,3
Four-layer (2s2p)
RθJMA
Thermal
12.2
resistance, junction
to ambient (200 ft./
min. air speed)
°C/W
1,3
—
RθJB
Thermal
7.0
resistance, junction
to board
°C/W
4
—
RθJC
Thermal
3.7
resistance, junction
to case
°C/W
5
—
ΨJT
Thermal
0.1
characterization
parameter, junction
to package top
°C/W
6
—
ΨJB
Thermal
2.7
characterization
parameter, junction
to package bottom
°C/W
7
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71
Dimensions
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package. With provided Theta-JB, Max junction temperature must be 125
degreeC.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12.
8 Dimensions
8.1 Obtaining package dimensions
Package dimensions are provided in package drawing.
To find a package drawing, go to http://www.nxp.com and perform a keyword search for
the drawing’s document number:
Package
Body Size
Pitch
NXP Document Number
208 LQFP
28 mm x 28 mm
0.5 mm
98ASA00649D
516 MAPBGA
27 mm x 27 mm
1.0 mm
98ASA00623D
9 Pinouts
9.1 Package pinouts and signal descriptions
For package pinouts and signal descriptions, refer to the Reference Manual.
10 Revision History
The following table provides a revision history for this document.
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Revision History
Table 65. Revision History
Rev. No.
Date
Substantial Changes
1
30 Jan
2014
•
•
•
•
•
•
•
2
20 May
2014
•
•
•
•
•
•
•
•
•
20 May
2
(continue 2014
d)
3
13 March
2015
Updated family comparison table
Updated Ordering information
Updated Absolute Maximum Ratings and Recommended Operating Conditions tables
Updated Power consumption table
Revised parameter classifications in several tables
Updated Main oscillator electrical characteristics table
Added DDR2 Read timing figure in the DDR2 SDRAM AC specifications section and revised the
parameter values
• Updated QuadSPI Input timing (RPC mode) table
Updated device part number to MAC57D54H
"Feature list", updated Program and Data Trace support from "32-bit" to "16-bit"
Updated block diagram, added detailed block diagram.
Revised "Feature Sets" table.
Removed parameter classifications throughout the document.
Revised "Ordering information" section.
Removed "Key electrical parameter" section.
Revised "Absolute maximum ratings" table.
In the "Recommended operating conditions (VDDE_x = 3.3 V)", revised note, added VDDA_REF,
updated footnote with VDD_HV_FLA.
• In the "Recommended operating conditions (VDDE_x = 3.3 V)", revised note, added VDDA_REF,
updated footnote with VDD_HV_FLA.
• Added Voltage monitor electrical specifications
• In the "Voltage regulator electrical specifications", renamed VDD_PMC to VDDE_A, removed
CHV_VDD_A, CHV_ADC, CHV_ADR, added a new section, "Recommended decoupling capacitor
value".
• In the "Voltage monitor electrical specifications", updated VLVD_FLASH configuration and threshold.
• In the "Power consumption" table, updated Target Typ and Target Max for IOP Run Mode, IOP
Stop Mode, Standby Mode. Added footnote for Standby Mode parameter.
• Added note below Figure 6.
• Revised "Electromagnetic Compatibility (EMC) specifications".
• In the "Functional Pad AC Specifications @ 3.3 V Range table", added recommended settings,
removed asymmetry drive load, added footnote: "Auto levels are applicable only to the ADC pins"
• In the "DC electrical specifications @ 3.3 V Range table", removed footnote showing ramp rate.
• In the "Functional Pad AC Specifications @ 5 V Range table", added recommended settings,
removed asymmetry drive load.
• In the "DDR2 pads AC electrical specifications at 1.8 V VDDE_DDR table",updated Prop. Delay
(ns) L>H/ H>L.
• In the "SSTL_18 Class II 1.8 V DDR2 DC specifications table", updated VDD12, removed
JESD8-15 A notes from VDD0P9_DDR.
• In the "SMC 5 V IO DC specifications", added Rdsonh, Rdsonl.
• In the "SMC 5V pads IO AC specifications", updated pad_smc_io _hv values.
• In the "SMC 3.3 V pads IO DC specifications", added Rdsonh, Rdsonl
• In the "SMC 3.3 V functional pads IO DC specifications", updated pad_smc_io _hv values.
• Updated High Level Block Diagram
• Updated Family Comparison table
• In Absolute maximum ratings table
• Removed Vss and Tj spec. Added footnote, "Tj=125°C. Assumes Ta=105°C. Assumes
maximum θJA of 2s2p board. See Thermal attributes section for details." Updated
description of VINA spec.
• Removed VDD_HV_FLA parameter.
• In Recommended operating conditions section, added the following paragraph: The following
table describes .... in the given range.
• In Recommended operating conditions (VDDE_x = 3.3 V)
Table continues on the next page...
SAC57D54H, Rev. 5, 05/2016
NXP Semiconductors
73
Revision History
Table 65. Revision History (continued)
Rev. No.
Date
Substantial Changes
• removed the footnote "This supply should be shorted on board with VSSA.VDDA_REF Min
voltage changed to 3.15V from -3.15V
• Recommended operating conditions (VDDE_x = 5 V) table:
• Clarified parameter description for several paramters
• Removed Vss
• VSSEH_ADC: Updated min to -0.1 and max to 0.1V.
• Added footnote: All parameters are with reference to Vss, unless otherwise
specified.
• Added Tj condition in the footnote.
• Added a footnote in VDD12 pin description in Recommended operating
conditions (VDDE_x = 3.3 V) table: VDD_LV supply pins should never be
grounded (through a small impedance). If these are not driven, they should only
be left floating.
• In Voltage regulator electrical specifications section,
• Changed the text "Supports up to 800 mA load internal generation of the 3.3 V flash supply
when device connected in 5 V applications" into following bullet:
• Supports up to 800mA current (on VDD12 supply) when using external NPN ballast
transistor for generating core supply
• Updated Voltage regulator capacitance connection figure to remove Flash voltage
regulator, VDD_HV_FLA and CFLASH_REG
• In block description, changed low range to low threshold and high range to high threshold.
In Voltage regulator electrical specifications table, added Combined ESR of external
capacitor parameter for Clp/ulp_reg. Added a foonote in the Cflash_reg
• Added VDD_HV_BALLAST options section
In Voltage monitor electrical specifications table,
• Updated parameter description to remove the term internal/external from LV supply.
• Removed VLVD_IO_A_HI parameter, added parameter description for "VLVD_FLASH
during low power mode using LPBG as reference", in footnote 3, renamed VDD_HV_FLA to
flash HV supply.
In Power consumption table,
• removed reference to "5 V Vreg Supply, External Ballast, 5 V only IO" figure, updated 3.3 V
Vreg Supply, External Ballast. DDR2, Mixed 3.3 V / 5 V IO figure and 1.2 V External Supply,
DDR2, Mixed 3.3 V / 5 V IO figure.
13 March
3
(continue 2015
d)
• In DC electrical specifications @ 3.3 V Range,
• Updated Pull_Ioh with Pull_Ioh_vil_hys data and its values, updated Pull_Iol with
Pull_Iol_vil_hys data and its values
• In DC electrical specifications @ 5 V Range,
• Updated Pull_Ioh with Pull_Ioh_vil_hys data and its values, updated Pull_Iol with
Pull_Iol_vil_hys data and its values
• In DDR2 pads AC electrical specifications at 1.8V VDDE_DDR,added reference to
SIUL_MSCR[SRE] in the Drive Strength Select cell.
• In RSDS pads electrical specifications, updated Data rate TYP and MAX to 50 MHz, added
Tskew value
• In LVDS pads electrical specifications, updated Rise/Fall time specification for open LDI LVDS
pads from 1.5 ns to 800 ps.
• In ADC conversion characteristics (for 12-bit) table,
• renamed TUEIS1WINJ to TUE for precision channels
• added parameter name as Trecovery for STOP mode to Run mode recovery time
• added parameter - ADC Analog Pad
Table continues on the next page...
SAC57D54H, Rev. 5, 05/2016
74
NXP Semiconductors
Revision History
Table 65. Revision History (continued)
Rev. No.
Date
Substantial Changes
• aded Total unadjusted error with current injection
• removed footnote in "Conditions" column
• Revised the whole section "Comparator and 6-bit DAC electrical specifications table"
• In Fast Oscillator electrical characteristics table, removed FOSC VIH/VIL Min and Max spec and
replaced with TYP specs: VIH as 1.84V, VIL as 1.48V .
• In Fast internal RC Oscillator electrical specifications table, removed FUntrimmed spec
• In Slow internal RC oscillator electrical specifications table, removed Foscu spec.
• Revised PLL electrical specifications table
• Revised the whole section "Flash Read Wait State and Address Pipeline Control Guidelines"
• In LCD driver electrical specifications, added offset, IBP/FP, ZBP/FP
• In 208LQFP and 516BGA thermal attribute tables, for RθJB updated footnote to add, "With
provided Theta-JB, Max junction temperature must be 125 degreeC".
13 March
3
(continue 2015
d)
•
•
•
•
•
•
•
•
4
• In "Recommended operating conditions", removed phrase, "VDDE_A (4.5 V to 5.5 V) configuration
is only supported in 176 LQFP".
• In "LVDS pads electrical specifications",
• Vdde parameter, updated foonote, from "VDDE is the VDDE_OLDI supply" to "VDDE is the
VDDE_B supply"
• "Differential o/p voltage" parameter, added foonote, "The limit applies to the default drive
current".
• "Rise/Fall time" parameter, added footnote, "Rise/fall time is assumed to be measured with
20%-80% levels".
• In "Analog Comparator (CMP) electrical specifications", updated min VAIO from -35 mV to -42 mV
and max VAIO from 35 mV to 42 mV.
• Editorial changes in "Memory Interfaces" section.
• In "QuadSPI electrical specifications",
• updated table title from "QuadSPI delay chain read/write settings" to "QuadSPI read/write
settings" and revised the content.
• revised notes in the "SDR mode" section.
• "QuadSPI input timing (SDR mode)" diagram, renamed SFCK to SCK
• "QuadSPI output timing (SDR mode)" diagram, renamed SFCK to SCK
• "QuadSPI input timing (SDR mode) specifications" table, added "FSCK" parameter
• removed notes in the "DDR mode" section.
• added new table, "QuadSPI input timing (DDR mode) specifications with learning".
• "QuadSPI output timing (DDR mode) specifications" table, removed "Tck ".
• "QuadSPI output timing (Hyperflash mode) specifications" table, renamed "TdvMAX" to "TDVO
".
• In "SDR AC specifications",
• SDR @ 160 MHz AC timing specification table, moved value of tSDCK from Min to Typ
• SDR @ 80 MHz AC timing specification table, moved value of tSDCK from Min to Typ
• In "DDR2 SDRAM AC specifications", added a note, "If self-refresh mechanism needs to be
supported, an external pull-down resistance needs to be connected to the DDR CKE pin".
• Revised "TCON RSDS timing diagram"
• In "TCON RSDS timing parameters" table, updated TDS to TOV and updated TH to TOH.
17 Jun
2015
Revised Voltage monitor electrical specifications
Revised Voltage regulator electrical specifications
Revised Power consumption specifications
Revised SSD electrical specifications
Updated SAR-ADC electrical specifications by providing values for both 12-bit and 10-bit modes
Revised QuadSPI, VIU and TCON specifications
Updated Debug trace operating behaviors
Renamed VDD_0P9_DDR to DDR_VREF throughout the document
Table continues on the next page...
SAC57D54H, Rev. 5, 05/2016
NXP Semiconductors
75
Revision History
Table 65. Revision History (continued)
Rev. No.
5
Date
05 May
2016
Substantial Changes
• Updated part number from MAC57D5xx to SAC57D5xx throughout the document.
• Changed Freescale to NXP:
• In Determining valid orderable parts : web link address changed to NXP
• In Electromagnetic Compatibility (EMC) specifications : changed Freescale to NXP.
• Removed CAN-FD references from:
• system connectivity row of Table 1,
• communication bullet in "Features".
• In the feature list, removed the phrase 'using external ballast transistor' from 'External 3.3 V input
supply'.
• Removed reference to 176 LQFP package from the following sections:
• Table 1
• Ordering information
• LCD driver electrical specifications
• Thermal attributes
• Obtaining package dimensions
• In Recommended operating conditions,
• removed phrase, "....and internal regulator cannot be used if peak application demand is
more than 800 mA".
• added a phrase, 'Design may experience up to 30 mA.........additional current'.
• In Voltage regulator electrical specifications,
• removed VRC_CTL and all connection to FPREG, RC_BALLAST and HDD_HV_BALLAST
related content in the Voltage regulator capacitance connection figure and Voltage regulator
electrical specifications table,
• removed VDD_HV_BALLAST options section,
• updated Recommended decoupling capacitor values.
• In Table 5,
• removed 'VLVD_FLASH' and 'VLVD_FLASH during low power mode using LPBG as reference'
parameters.
• updated VHVD_LV_cold fall trimmed typical value.
• In Power consumption section,
• updated Table 6 for standby current specs for 25oC,
• removed VDDE_B supply name from footnote 5,
• removed figure, "3.3 V Vreg Supply, External Ballast. DDR2, Mixed 3.3 V / 5 V IO",
• renamed Figure 4 title from '1.2 V External Supply, DDR2, Mixed 3.3 V / 5 V IO' to 'Supply
configuration', removed VRC_CTL block from the figure.
• In Table 11, added Vol and Voh specs.
• In Table 13 updated Ioh(dc) and Iol(dc) minimum values.
• In Table 17, removed 'Vsum', 'Voh delta / Vol delta', 'Rdsonh' and 'Rdsonl' parameters.
• Removed the column for 'Prop. Delay' parameter from the following tables:
• Table 8
• Table 10
• Table 12
• Table 16
• Table 18
• Removed reference to 5V Typ and 5.5V max in Table 19 and Table 20.
• In Table 24,
• updated min and max values for 'INL' parameter.
• removed '5V Reference Voltage' row in IDAC6b parameter.
• In Table 28,
• updated 'Temp Dependence' value as 600 ppm/C,
• updated 'Supply Dependence' as 18%V,
• updated 'Oscillator Frequency' as 119 KHz (min) and 136.5 KHz (max),
• added 'Supply Current (Run)' as 2.75 uA and 'Supply Current (Stop)' as 200 nA.
• In Table 27, updated TSTJIT value to '1.5%' and TLTJIT value to '0.2%'
• In Table 29 updated Modulation Depth (Center Spread), max value updated to +/- 3.0%.
• In SDR AC specifications,
SAC57D54H, Rev. 5, 05/2016
76
NXP Semiconductors
Revision History
Table 65. Revision History
Rev. No.
Date
Substantial Changes
•
•
•
•
• added note, 'All transitions measured at mid-supply ..........with EMC improvement'.
• added footnotes for DD1 and DD2 specs of Table 45 and Table 46 that these parameters
also apply to command and address buses.
In Table 47, updated DD2 and DD3 values and unit.
In Table 54, in footnote 4, added phrase '..up to 85oC'.
In Table 55 updated 'Display pixel clock period' (tPCP) value to 12.5 ns.
In Table 60, updated the values for all parameters of SSDOFFSET and added footnote 3.
SAC57D54H, Rev. 5, 05/2016
NXP Semiconductors
77
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Document Number SAC57D54H
Revision 5, 05/2016
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