SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge

SubLVDS to MIPI CSI-2 IP Image Sensor
Interface Bridge
User Guide
IPUG125 Version 1.0
May 2016
SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
Contents
Acronyms in This Document ................................................................................................................................................. 4
1. Introduction ................................................................................................................................................................... 5
1.1.
Quick Facts .......................................................................................................................................................... 5
1.2.
Features ............................................................................................................................................................... 5
1.3.
Conventions......................................................................................................................................................... 5
1.4.
Signal Names ....................................................................................................................................................... 5
2. Functional Description .................................................................................................................................................. 6
2.1.
Interface and Timing Diagram ............................................................................................................................. 6
2.1.1. SubLVDS Interface ..........................................................................................................................................6
2.1.2. MIPI DPHY Interface .......................................................................................................................................8
2.2.
Clocking and Reset .............................................................................................................................................. 9
2.3.
Module Descriptions ......................................................................................................................................... 10
2.3.1. sublvds_rx_wrapper .....................................................................................................................................12
2.3.2. cmos_2_dphy_ip ..........................................................................................................................................12
2.3.3. imx_framer ...................................................................................................................................................12
3. Parameter Settings ..................................................................................................................................................... 13
4. IP Generation and Evaluation ..................................................................................................................................... 14
4.1.
Licensing the IP .................................................................................................................................................. 14
4.2.
Getting Started .................................................................................................................................................. 14
4.3.
Creating IP in Clarity Designer ........................................................................................................................... 15
4.4.
Generated IP Directory Structure and Files ....................................................................................................... 19
4.5.
Instantiating the IP ............................................................................................................................................ 20
4.6.
Synthesizing and Implementing the IP in a Top-Level Design ........................................................................... 20
4.7.
Hardware Evaluation ......................................................................................................................................... 20
4.7.1. Enabling Hardware Evaluation in Diamond ..................................................................................................20
4.8.
Updating/Regenerating the IP........................................................................................................................... 21
4.8.1. Regenerating an IP in Clarity Designer .........................................................................................................21
References .......................................................................................................................................................................... 22
Appendix A. Resource Utilization ....................................................................................................................................... 23
LIF-MD6000 Utilization ................................................................................................................................................... 23
Appendix B. What is Not Supported ................................................................................................................................... 24
Technical Support Assistance ............................................................................................................................................. 22
Revision History .................................................................................................................................................................. 25
Figures
Figure 2.1. SubLVDS input data, clock and sync signal timing (4k2k, 10-bit data, 10-lanes) IPUG124-1.0 ...........................7
Figure 2.2. High-speed Data Transmission............................................................................................................................8
Figure 2.3. SubLVDS to CSI-2 Clock Domains ........................................................................................................................9
Figure 2.4. Top level block diagram ....................................................................................................................................10
Figure 4.1. Clarity Designer Window ..................................................................................................................................14
Figure 4.2. Starting Clarity Designer from Diamond Design Environment .........................................................................15
Figure 4.3. Configuring SubLVDS to MIPI CSI-2 IP in Clarity Designer .................................................................................16
Figure 4.4. SubLVDS to MIPI CSI-2 IP Configuration GUI in Clarity Designer ......................................................................17
Figure 4.5. Configuring Video Packet in SubLVDS to CSI-2 IP configuration GUI in Clarity Designer ..................................18
Figure 4.6. SubLVDS to MIPI CSI-2 IP Directory Structure...................................................................................................19
Figure 4.7. IP Regeneration in Clarity Designer ..................................................................................................................21
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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IPUG125-1.0
SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
Tables
Table 1.1. SubLVDS to MIPI CSI-2 IP Quick Facts ................................................................................................................. 5
Table 2.1. Sync Code Details ................................................................................................................................................. 8
Table 2.2. Top Level Ports ................................................................................................................................................... 11
Table 2.3. Indicator States .................................................................................................................................................. 12
Table 3.1. SubLVDS to CSI-2 IP Parameters ........................................................................................................................ 13
Table 4.1. Files Generated in Clarity Designer .................................................................................................................... 19
Table A. 1. Resource Utilization* ........................................................................................................................................ 23
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG125-1.0
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SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
ISP
Image Signal Processor
AP
Application Processors
CSI-2
Camera Serial Interface 2
MIPI
Mobile Industry Processor Interface
HS
High Speed
LP
Low Power
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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IPUG125-1.0
SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
1. Introduction
Many Image Signal Processor (ISP) or Application Processors (AP) use the MIPI® CSI-2 standard for image sensor inputs.
However, some high resolution CMOS image sensors use a proprietary SubLVDS output format. The Lattice
Semiconductor SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge IP for Lattice Semiconductor CrossLinkTM solves
the interface mismatch between subLVDS output image sensor and an ISP/AP using MIPI CSI-2 interface.
1.1.
Quick Facts
Table 1.1 provides quick facts about the SubLVDS to CSI-2 IP for CrossLink devices.
Table 1.1. SubLVDS to MIPI CSI-2 IP Quick Facts
SubLVDS to MIPI CSI-2 IP Configuration
10-lane Configuration
Core
Requirements
Resource
Utillization
Design Tool
Support
1.2.



FPGA Families Supported
CrossLink
Targeted Device
Data Path Width
LIF-MD6000-6MG81I
10-bit (RAW10) or 12-bit (RAW12) input data to DPHY serial data
LUTs
sysMEM EBRs
5242
12
Registers
Lattice Implementation
Synthesis
2250
Lattice Diamond® 3.8
Lattice Synthesis Tool (LSE)
Simulation
Aldec® Active HDL™ 10.3 Lattice Edition
Features
Supports four, six, eight or ten data lanes from an image sensor in 10-bit (RAW10) or 12-bit (RAW12) pixel widths
Can generate XVS and XHS for image sensors in slave mode
Interfaces to MIPI CSI-2 Receiving Devices with four data lanes up to 6 Gb/s total bandwidth
1.3.
Conventions
The nomenclature used in this document is based on the Verilog language. This includes radix indications and logical
operators.
1.4.
Signal Names
Signal names that end with:
 “_i” are input pins.

“_o” are output pins.
 “_io” are bi-directional pins.
 “_n_i” are active low.
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG125-1.0
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SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
2. Functional Description
The SubLVDS to MIPI CSI-2 Interface Bridge converts, serialized, source synchronous SubLVDS data from an Image
Sensor to MIPI CSI-2. It consists of one SubLVDS differential clock lane and up to 10 SubLVDS differential data lanes.
The output from the chip is a MIPI DPHY interface supporting HS (High Speed) and LP (Low Power) modes during
vertical and horizontal blanking.
The SubLVDS data received at the input is deserialized using iDDRx4 (1:8 gearing) or iDDRx8 (1:16 gearing) gearbox.
This converts each double data rate lane to a single data rate 8-bit or 16-bit bus for slower operating speeds within the
system. The data from each lane is forwarded to a word alignment module which converts the deserialized data to 10bit pixels. The output of this module is a large data bus of pixels (pixdata_o) with a width dependent on the number of
data lanes being used, dvalid_o, fv_o and lv_o signals. The dvalid_o control signal goes active high on clock cycles that
have valid pixel data. The fv_o goes high at the beginning of an active video frame and low at the end of the frame.
Similarly, the lv_o goes active high or low at the beginning or end of an active video line respectively.
The multi-pixel bus is then routed to the MIPI CSI-2 module. This module contains several modules to perform the pixel
to MIPI CSI-2 conversion. The first module is the pixel to byte module. This module’s function is to convert pixel data
into HS byte packets. The module creates a frame start or frame end MIPI HS short packet when the fv_o goes high or
low respectively. The module additionally creates HS long packets based on the lv_o going high and pixel data being
seen as valid based on dvalid_o. There are two more modules, the packet header and packet footer, which handle
appending the MIPI packet header and footer and calculating the appropriate, included checksums.
The TX global operations controller provides all data control for the MIPI output data. This module allows the user to
set delay controls for when LP and HS modes start and end on the clock and data lanes as these delays changed based
on the speed of data transfer. Delay controls include the number of clocks difference between when the clock lane
goes from LP to HS mode and when the data lanes go from LP to HS mode. All parameters are based on the MIPI byte
clock which operates at a ¼ the speed of the MIPI bit clock output. The MIPI DPHY TX channels are put into low power
(LP) mode when not sending out packets, and when sending packets, the MIPI DPHY TX channels are in high speed (HS)
mode. However, there is a wait time needed between any LP and HS transition (and vice versa) as specified by the MIPI
DPHY Specification. Because of this wait time requirement on the MIPI DPHY TX side of the bridge, the 1 st line of each
frame is dropped through the bridge. The wait time (horizontal blanking period) between start of FV (frame valid) and
start of LV (line valid), end of LV and end of FV and end of LV and start of LV can be as long as 200 byte clock cycles or
650 input clock cycles depending on the lane rate.
In addition, the MIPI DPHY TX can only handle pixels that consist of a number of bytes that is divisible by 8. In order to
support all input resolutions, the received data will be cropped to be divisible by 8 bytes and by 5 bytes (CSI-2 protocol
for RAW10). The Word Count (WC) provided by the user must include the EAV (4*no. of lanes pixels). EAV is the end of
sync code. The cropping will only affect the EAV if cropped pixels are less than or equal to 4*no. of lanes pixels. It will
only affect the ignored region of active pixels if cropped pixels is more than 4*no. of lanes pixels.
Lastly, the design includes the IMX framer module. Some image sensors require a method for controlling XVS (vertical)
and XHS (horizontal) indication signals. For these image sensors, the SubLVDS-to-CSI-2 Soft IP in the CrossLink FPGA can
provide the XVS and XHS controls using the IMX Framer module.
2.1.
Interface and Timing Diagram
2.1.1. SubLVDS Interface
Figure 2.1 shows the sync signal and data output timing during 10-bit length serial received from the image sensor. The
horizontal and vertical timing of the data are controlled by the XVS and XHS sync signals. The sync code is added before
and after the pixel data. See Table 2.1 for the sync code details.
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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IPUG125-1.0
SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
1[XVS] = 2200[XHS]
Front dummy [Communication
period + sensor clamp]
User clamp
8H[8XHS]
Margin for Color
processing
4H[4XHS]
Ignored area of effective pixel
6H[6XHS]
Margin for Color
processing
4H[4XHS]
Effective pixels
2160H[2160XHS]
VBLK period
XVS
XHS
0
DO
7
13
8
17
18
19
2176
2177
2181
See next diagram for details
1[H] = 1[XHS] = 546[INCK] = 2184 [DCK]
Number of
DCK clock
HBLK period
348 to 353
Sync code
20
HOPB ignored
15
HOPB
ignored
10
HOPB
25
Ignored
area of Margin for
effective Color
pixel processing
5
10
Ignored
Margin for area of
Color effective
processing pixel
10
5
Effective pixels
2045
Sync code
20
XHS
DCK
EAV2
EAV3
EAV4
EAV1
EAV2
EAV3
EAV4
4242
EAV1
EAV2
EAV3
EAV4
4243
EAV1
EAV2
EAV3
EAV4
4244
EAV1
EAV2
EAV3
EAV4
4245
EAV1
EAV2
EAV3
EAV4
4246
EAV1
EAV2
EAV3
EAV4
4247
EAV1
EAV2
EAV3
EAV4
EAV1
EAV2
EAV3
EAV4
EAV1
EAV2
EAV3
EAV4
123
DOD
124
SubLVDS output 10ch 10bit serial
EAV1
4241
4232
4231
112
72
4240
111
71
4230
4220
4210
4200
4190
150
140
130
120
110
SAV1[5]
90
SAV1[6]
100
9
SAV1[7]
80
8
SAV4
SAV1[8]
70
7
SAV4
SAV3
SAV1[0]
6
SAV4
SAV3
60
24
5
SAV4
SAV3
SAV1[1]
23
4
SAV4
SAV3
50
3
SAV4
SAV3
SAV1[2]
2
SAV4
SAV3
40
1
SAV4
SAV3
30
0
SAV4
SAV3
20
SAV4
SAV3
SAV1[9]
10
SAV3
SAV2
EAV4
SAV1
EAV3
SAV2
EAV4
EAV2
SAV1
EAV3
EAV1
SAV2
EAV4
EAV2
SAV1
EAV3
EAV1
SAV2
EAV4
EAV2
SAV1
EAV3
EAV1
SAV2
EAV4
EAV2
SAV1
EAV3
EAV1
SAV2
EAV4
EAV2
SAV1
EAV3
EAV1
SAV2
EAV4
EAV2
SAV1
EAV3
EAV1
SAV2
EAV4
EAV2
SAV1
EAV3
EAV1
SAV2
EAV4
EAV2
SAV1
EAV3
EAV1
SAV2
EAV4
EAV2
SAV1
EAV3
EAV1
DOC
EAV2
DOB
EAV1
DOA
DOE
DOH
95
DOG
95
DOF
DOI
4219
DOJ
5 DCK clock
SAV1[3]
SAV1[4]
Figure 2.1. SubLVDS input data, clock and sync signal timing (4k2k, 10-bit data, 10-lanes) IPUG125-1.0
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG125-1.0
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SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
Table 2.1. Sync Code Details
LVDS output bit No.
Sync code
12-bit output
10-bit output
1st word
2nd word
3rd word
4th word
11
9
1
0
0
1
10
8
1
0
0
0
9
7
1
0
0
V
1: Blanking line
0: Except blanking line
8
6
1
0
0
H
1: End sync code
2: Start sync code
7
5
1
0
0
P3
6
4
1
0
0
P2
5
3
1
0
0
P1
4
2
1
0
0
P0
3
1
1
0
0
0
2
0
1
0
0
0
1
—
1
0
0
0
0
—
1
0
0
0
Protection bits
Protection bits
V
H
P3
P2
P1
P0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
1
0
1
1
1
1
0
1
1
0
2.1.2. MIPI DPHY Interface
Figure 2.2. High-speed Data Transmission
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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IPUG125-1.0
SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
Figure 2.2 is taken from the MIPI DPHY specification. It shows that prior to the HS mode data transfer all clock and data
lanes are in the LP11 state (1.2 V on the P and N channel). The clock lane goes to the LP01 state (0 V on the P channel
and 1.2 V on the N channel) then the LP00 state (0 V on the P channel and 0 V on the N channel). After that, the clock
lane goes into HS mode with SLVS200 signaling (Vcm=200 mV, Vdiff=±100 mV) and holds an HS0 state (differential 0
state of P channel=100 mV and N channel=300 mV when termination of the receiver is turned on). Then the clock starts
shortly after. Once the HS clock is running the data lanes follow a similar procedure going from LP11 to LP01, LP00, and
HS0 states. Then the HS-SYNC sequence is driven on the line followed by the packet header and data payload. At the
end of the transfer the data lanes first go back into LP mode by going to LP00 then LP11 states. The clock lane follows
shortly after.
2.2.
Clocking and Reset
The RX clock input is from an external source (i.e. image sensor) and should be connected to a dedicated SubLVDS edge
clock pin. The DPHY PLL reference clock will be from the SubLVDS RX (pixclk_i) and it will generate a byte clock for the
cmos_2_dphy modules. Clock source of the IMX framer will also be external and typically be the same clock source of
the image sensor.
sublvds_2_csi2_ip.v
reset_n_i
sublvds_rx_wrapper.v
Deserializer
cmos_2_dphy_ip.v
SubLVDS
Word
Alignment
Pixel to Byte
Packet Formatter
TX Global
Operations
Controller
DPHY Common
Interface
Wrapper
DPHY PLL
clk_p/n_i
imx_framer.v
inck_i
Figure 2.3. SubLVDS to CSI-2 Clock Domains
Active low reset is used in the system and it is connected to reset ports of all modules. Resets for each clock domains
are synced to their respective clock domains.
Initialization sequence for this soft IP is the following:
1.
Assert reset signal for 500ns.
2.
The design will wait for Hard D-PHY to lock (pll_lock_o).
3.
Wait for tinit_done_o to assert (The design will drive the DPHY to a Stop State (LP-11) for a period longer than Tinit.
The Hard D-PHY can force the lane module into transmit mode and generate stop state.)
4.
High-speed data transmission will now follow
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG125-1.0
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SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
2.3.
Module Descriptions
The top level design (sublvds_2_csi2_ip_wrapper.v) instantiates the soft IP module (sublvds_2_csi2_ip.v). The
sublvds_2_csi2_ip.v consists of three main modules:
 sublvds_rx_wrapper.v — It is composed of a deserializer and word alignment module.
 cmos_2_dphy_ip.v — It consists of the Pixel to byte, Packet Footer, Packet Header, TX Global Operations Controller
and D-PHY Common Interface Wrapper
 imx_framer.v — It provides control mechanism (XVS and XHS) for the rate at which line and frame is read out. This
is used for image sensors that operate in slave mode.
sublvds_2_csi2_ip.v
reset_n_i
sublvds_rx_wrapper.v
cmos_2_dphy_ip.v
pixclk_o
byte_clk_o
Deserializer
SubLVDS
Word
Alignment
Pixel to Byte
Packet Formatter
TX Global
Operations
Controller
DPHY Common
Interface
Wrapper
clk_o
clk_p/n_i
d*_p/n_i
d0_p/n_o
dvalid_o
d1_p/n_o
lv_o
d2_p/n_o
fv_o
d3_p/n_o
To the Image Processor
From the Image Sensor
DPHY PLL
pixdata_o[lane_width*bus_width-1:0]
imx_framer.v
From external
oscillator
inck_i
V_TOTAL[11:0]
To the Image Sensor
operating in slave mode
H_TOTAL[11:0]
V_H_BLANK[11:0]
xvs_o
xhs_o
Figure 2.4. Top level block diagram
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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IPUG125-1.0
SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
Table 2.2 lists the IO ports of the SubLVDS to CSI-2 block:
Table 2.2. Top Level Ports
Port Name
Direction
Description
Resets/Clocks
reset_n_i
Input
Asynchronous reset; resets all modules within top level (active low).
SubLVDS Interface
clk_p_i
clk_n_i
Input
SubLVDS serial input clock
d0_p_i
d0_n_i
Input
SubLVDS RX data0
d1_p_i2,3
d1_n_i2,3
Input
SubLVDS RX data1
d2_p_i2,3
d2_n_i2,3
Input
SubLVDS RX data2
d3_p_i2,3
d3_n_i2,3
Input
SubLVDS RX data3
d4_p_i3,4
d4_n_i3,4
Input
SubLVDS RX data4
d5_p_i3,4
d5_n_i3,4
Input
SubLVDS RX data5
d6_p_i4,5
d6_n_i4,5
Input
SubLVDS RX data6
d7_p_i4,5
d7_n_i4,5
Input
SubLVDS RX data7
d8_p_i5
d8_n_i5
Input
SubLVDS RX data8
d9_p_i5
d9_n_i5
Input
SubLVDS RX data9
CSI-2 Interface
clk_p_o
clk_n_o
Output
d0_p_io
d0_n_io
Bi-directional
MIPI CSI-2 TX data0
d1_p_o
d1_n_o
Output
MIPI CSI-2 TX data1
d2_p_o
d2_n_o
Output
MIPI CSI-2 TX data2
d3_p_o
d3_n_o
Output
MIPI CSI-2 TX data2
inck_i1
xvs_o1
xhs_o1
Input
IO
IO
MIPI CSI-2 seraial HS clock lane
IMX Framer
Input clock for IMX Framer. This clock is shared as the input clock to the image sensor.
Image sensor slave readout vertical control signal
Image sensor slave readout horizontal control signal
Notes:
1. Used only when mode = slave; when mode = master, xvs_o and xhs_o are driven to high-impedance
2. Used only when LANE_WIDTH = 4
3. Used only when LANE_WIDTH = 6
4. Used only when LANE_WIDTH = 8
5. Used only when LANE_WIDTH = 10
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG125-1.0
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SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
User Guide
2.3.1. sublvds_rx_wrapper
The SubLVDS RX wrapper is composed of a deserializer and a word alignment module.
The deserializer converts each double data rate lane to a single data rate 8-bit or 16-bit bus at slower operating speeds
within system. The word alignment module receives the 8-bit (1:8 gearing) or 16-bit (1:16 gearing) deserialized data
and converts it to 10-bit or 12-bit pixel data according to the set configuration of data type (RAW10 or RAW12). The
output of the module is a multi-pixel bus, a dvalid_o, fv_o and lv_o control signal. The dvalid_o control signal goes
active high on clock cycles that have valid pixel data. There is also a parser inside that will look at the recognition codes
from the beginning (SAV) and the end (EAV) of each data packet if they are part of an active video line or not. The fv_o
goes high at the beginning of an active video frame and low at the end of the frame. Similarly, the lv_o goes active high
or low at the beginning or end of an active video line respectively.
Table 2.3. Indicator States
Sync code
SAV (valid line)
fv state
1
lv state
1
EAV (valid line)
SAV (invalid line
EAV (invalid line)
1
0
0
0
0
0
2.3.2. cmos_2_dphy_ip
The CMOS2DPHY is a Soft IP block that is reused in the SubLVDS-to-CSI-2 IP. This module accepts the large multiplepixel bus from the SubLVDS RX and serializes it into HS data packets following the MIPI CSI-2 specification. It consists of
the Pixel2byte, Packet Footer, Packet Header, TX Global Operations Controller and D-PHY Common Interface Wrapper.
The Pixel2byte block converts the pixel data to MIPI byte data based on the number of bits per pixel, the data type and
the number of MIPI D-PHY lanes that are to be used. This module should also be able to handle cases of sending in
multiple pixels per clock cycle for cases where the pixel clock will be too fast for the fabric.
The packet footer block generates the CRC16 checksum based on the byte data coming in and an enable. The packet
header block generates and appends the packet header and footer to the data payload.
The TX global operations controller controls HS request path and timing using parameters. Currently LP-request,
escape mode and turnaround path are not supported. This block should follow the requirement from D-PHY
Specification v1.2 section 6 – operating modes for control and high-speed data transmission.
The DCI (DPHY Common Interface) wrapper is used as the wrapper of the MIPI DPHY IP. This is used to serialize the
incoming byte data and transmits to DPHY receiver. The DCI is used to make a connection between the PHY hard IP and
higher protocol layers. Based on the Tx global operation state, it determines how to enable HS or LS mode for data
transfer.
2.3.3. imx_framer
The IMX Framer module is for image sensors that operate in “Slave” mode. Image Sensors that use this mode must
have their XHS and XVS driven by another component. For this scenario, the SubLVDS-to-CSI-2 IP will drive the signals in
a similar manner to frame valid and line valid indicators. It provides a control mechanism for the rate at which each
line and frame is read out. Timing of these two signals is defined in the Image Sensor datasheet. Timing of the XHS and
XVS is in Figure 2.1.
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3. Parameter Settings
Table 3.1 shows the user parameters used to generate the SubLVDS to MIPI CSI-2 IP.
Table 3.1. SubLVDS to CSI-2 IP Parameters
Parameter
Attribute
User Input
4
6
Number of RX lane
User-input
8
10
8
RX Gear
User-input
16
Minimum: 320 Mb/s
Maximum:
TX Line Rate
User-input
4 & 6 RX lane – 900 Mb/s
8 RX lane
– 1440 Mb/s
10 RX lane
– 1500 Mb/s
tINIT_SLAVE Value
User-input
1 — 32767
Miscellaneous
User-input
DataType
User-input
Word count
User-input
1 — 65536
Virtual Channel ID
User-input
0—3
Image Sensor Mode
User-input
Master
Slave
V_TOTAL
User-input
Decimal value
H_TOTAL
User-input
Decimal value
V_H_BLANK
User-input
Decimal value
Enable
Disable
RAW10
RAW12
Description
Selects the number of RX SubLVDS data lanes.
Select gearing of RX side.
Target TX line rate in Mb/s. RX line rate is not
the same with the TX.
RX line rate will depend on the number of RX
lanes.
This parameter can be configured by the user
to ensure that the initialization period of the DPHY slave is met. The D-PHY specification
places a minimum period of 100us, but this
parameter may be increased depending on the
receiver requirement. During this period, all
incoming data is ignored by the bridge.
If enabled, it will probe out internal signals for
debug purposes.
Selects desired data type.
Specify the number of bytes within the
payload.
Virtual channel ID assignment for packets from
channel 1
Set the mode of the image sensor. When in
slave mode, it will enable the IMX framer.
Set the number of lines XVS will be driven high.
This parameter is needed in slave mode. When
in master mode, please disregard this entry.
Set the number of INCK clocks XHS will be
driven high. This parameter is needed in slave
mode. When in master mode, please disregard
this entry.
Set the number of INCK clocks XVS and XHS will
be driven low. This parameter is needed in
slave mode. When in master mode, please
disregard this entry.
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4. IP Generation and Evaluation
This Chapter provides information on how to generate the Lattice SubLVDS to CSI-2 IP code using the Diamond Clarity
Designer, and how to include the IP in a top-level design.
4.1.
Licensing the IP
An IP license is required to enable full, unrestricted use of the SubLVDS to CSI-2 IP in a complete, top level design. The
SubLVDS to CSI-2 IP is available free of charge. Please request your free IP license at:
http://www.latticesemi.com/licenseprocessing/ipcore_lic_req.cfm?api=true
You may download or generate the SubLVDS to CSI-2 IP and fully evaluate the through functional simulation and
implementation (synthesis, map, place and route) without the IP license. The SubLVDS to CSI-2 IP also supports
Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP that operate in
hardware for a limited time (approximately four hours) without requiring an IP license. See Hardware Evaluation for
further details. However, a license is required to enable timing simulation, to open the design in Diamond EPIC tool, or
to generate bitstreams that do not include the hardware evaluation timeout limitation.
4.2.
Getting Started
The SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge is available for download from the Lattice IP Server using the
Clarity Designer. After the IP has been installed, the IP will be available in the Clarity Designer GUI as shown in Figure
4.1.
Figure 4.1. Clarity Designer Window
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4.3.
Creating IP in Clarity Designer
Clarity Designer is a tool used to customize modules and IPs and place them into the device’s architecture. Besides
configuration and generation of modules and IPs, Clarity Designer can also create a top module template in which all
generated modules and IPs are instantiated.
The following describes the procedure for generating SubLVDS to MIPI CSI-2 in Clarity Designer.
Clarity Designer can be started from the Diamond design environment.
To start Clarity Designer:
1.
Create a new empty Diamond project for LIFMD family devices.
2.
From the Diamond main window, choose Tools > Clarity Designer, or click
Designer project dialog box is displayed.
3.
Select and or fill out the following items as shown in Figure 4.2:
 Create new Clarity design — Choose to create a new Clarity Design project directory in which the SubLVDS to
CSI-2 IP will be generated.
 Design Location — Clarity Design project directory path.
 Design Name — Clarity Design project name.
 HDL Output — Hardware Description Language Output Format (Verilog).
in Diamond toolbox. The Clarity
The Clarity Designer project dialog box also allows you to open an existing Clarity Designer project by selecting the
following:
 Open Clarity design — Open an existing Clarity Design project.
 Design File — Name of existing Clarity Design project file with .sbx extension.
Figure 4.2. Starting Clarity Designer from Diamond Design Environment
4.
Click the Create button. A new Clarity Designer project is created.
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To configure the SubLVDS to MIPI CSI-2 IP in Clarity Designer:
1.
Double-click SubLVDS to MIPI CSI-2 in the IP list of the System/Planner view. The sublvds_to_csi2 dialog box is
displayed as shown in Figure 4.3.
Figure 4.3. Configuring SubLVDS to MIPI CSI-2 IP in Clarity Designer
2.
Enter the Instance Name.
3.
Click the Customize button. An IP configuration interface is displayed as shown in Figure 4.4. From this dialog box,
you can select the IP parameter options specific to your application.
4.
Input valid values in required fields in the Configuration tab.
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Figure 4.4. SubLVDS to MIPI CSI-2 IP Configuration GUI in Clarity Designer
5.
To configure data type, virtual channel ID, word count and IMX Framer settings (when image sensor is in slave
mode) click the Video tab as shown in Figure 4.5.
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Figure 4.5. Configuring Video Packet in SubLVDS to CSI-2 IP configuration GUI in Clarity Designer
6.
Click the Configure button after the required parameters are selected.
7.
Click Close.
For detailed instructions on how to use the Clarity Designer, refer to the Lattice Diamond software user guide.
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4.4.
Generated IP Directory Structure and Files
The IP and supporting files generated in Clarity Designer and IP Express have similar folder architecture and files. The
directory structure of the generated files is shown in Figure 4.6.
Figure 4.6. SubLVDS to MIPI CSI-2 IP Directory Structure
The design flow for the IP created with Clarity Designer and IPexpress uses a post-synthesized module (NGO) for
synthesis and uses a protected model for simulation. The post-synthesized module and protected model are
customized when you configure the IP and created automatically when the IP is generated.
Table 4.1 provides a list of key files and directories created by Clarity Designer and how they are used. Besides the postsynthesized module (NGO) and protected simulation model, all other files are also generated based on your
configuration and provided as examples to use or evaluate the IP.
Table 4.1. Files Generated in Clarity Designer
File
Description
<instance_name>.v
Verilog top-level module of SubLVDS to MIPI CSI-2 IP used for both synthesis and
simulation
<instance_name>_*.v
Verilog submodules for simulation. Files that do not have equivalent black box modules
are also used for synthesis.
<instance_name>_*_beh.v
Protected Verilog models for simulation
<instance_name>_*_bb.v
Verilog black box modules for synthesis
<instance_name>_*.ngo
GUI configured and synthesized modules for synthesis
<instance_name>_params.v
Verilog parameters file which contains required compiler directives to successfully
configure IP during synthesis and simulation
<instance_name>.lpc
Lattice Parameters Configuration file. This file records all the IP configuration options
set through Clarity Designer. It is used by IP generation script to generate configurationspecific IP. It is also used to reload parameter settings in the IP GUI in Clarity Designer
when it is being reconfigured.
Besides the files listed in the tables, most of the files required to evaluate the SubLVDS to MIPI CSI-2 IP reside under
the directory \<sublvds2csi2_eval>. This includes the simulation model, testbench and simulation script files for
running the simulation in Active HDL.
The \<username> folder contains files/folders with content specific to the <username> configuration. This directory is
created by Clarity Designer each time the IP is generated and regenerated with the same file name. A separate
\<username> directory is generated for IPs with different names, such as \<my_IP_0>,\<my_IP_1>, and others.
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Aside from the folder\<username>, the \sublvds2csi2_eval and subtending directories provide files supporting SubLVDS
to CSI-2 IP evaluation that includes files/folders with content that is constant for all configurations of the SubLVDS to
MIPI CSI-2 IP. The \sublvds2csi2_eval directory is created by Clarity Designer the first time the IP is generated when
multiple SubLVDS to MIPI CSI-2 IP are generated in the same root directory and updated each time the IPis
regenerated.
The simulation part of the user evaluation provides testbench and test cases supporting RTL simulation for Active-HDL
simulators under <project root>\testbench.
Separate directories located at \<project_dir>\sublvds2csi2_eval\<username>\sim\Aldec\rtl are provided and contrain
pre-built simulation script files.
4.5.
Instantiating the IP
The core modules of SubLVDS to CSI-2 IP are synthesized and provided in NGO format with black box Verilog source
files for synthesis. A Verilog source file named <instance_name>_sublvds_2_csi2_ip.v instantiates the black box of core
modules. The top-level file <instance_name>.v instantiates <instance_name>_sublvds_2_csi2_ip.v.
The user does not need to instantiate the IP instances one by one manually. The top-level file along with the other
Verilog source files are provided in \<project_dir>. These files are refreshed each time the IP is regenerated.
For example, if the Clarity Designer project file is cdprj.sbx, the automatically generated wrapper file is cdprj.v in which
all generated IPs are instantiated. The user does not need to instantiate the IP instances one by one manually. The
cdprj.v is refreshed each time the IPs in the design are regenerated.
4.6.
Synthesizing and Implementing the IP in a Top-Level Design
In Clarity Designer, the Clarity Designer project file (.sbx) is added to Lattice Diamond as a source file after all IPs are
generated. Note that default Diamond strategy (.sty) and default Diamond preference file (.lpf) are used. When using
.sbx approach, import the recommend strategy and preferences from
\<project_dir>\sublvds2csi2_eval\<instance_name>\impl\lifmd\[lse | synplify] directories. All required files are
invoked automatically. You can directly synthesize, map and place/par the design in the Diamond design environment
after the IPsare generated.
To use the project files in Diamond:
1.
Choose File > Open > Project.
2.
Browse to \<project_dir>\sublvds2csi2_eval\<username>\impl\lifmd\[lse|synplify]\ in the Open Project dialog box.
3.
Select and open <username>_top.ldf. At this point, all of the files needed to support top-level synthesis and
implementation will be imported to the project.
4.
Select the Process tab in the left-hand GUI window.
5.
Implement the complete design via the standard Diamond GUI flow.
4.7.
Hardware Evaluation
The SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge IP supports Lattice’s IP hardware evaluation capability, which
makes it possible to create versions of the IP that operate in hardware for a limited period of time (approximately four
hours) without requiring the request of an IP license. It may also be used to evaluate the IP in hardware in user-defined
designs.
4.7.1. Enabling Hardware Evaluation in Diamond
Choose Project > Active Strategy > Translate Design Settings. The hardware evaluation capability may be
enabled/disabled in the Strategy dialog box. It is enabled by default.
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4.8.
Updating/Regenerating the IP
The Clarity Designer interface allows you to update the local IPs from the Lattice IP server. You can use the updated IP
to regenerate the IPin the design.
To change the parameters of the IP used in the design, the IP must also be regenerated.
4.8.1. Regenerating an IP in Clarity Designer
To regenerate IP in Clarity Designer:
1.
In the Builder or Planner tab, right-click the IP instance to be regenerated and select Config in the menu as shown
in Figure 4.6.
2.
The IP Configuration GUI is displayed. Change the parameters as required and click the Configure button.
3.
Update the pin connection in Builder tab for configuration changes.
4.
Click
in the toolbox. Clarity Designer regenerates all the instances which are reconfigured.
Figure 4.7. IP Regeneration in Clarity Designer
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References
For more information, refer to the following document:
 DS1055, CrossLink Family Data Sheet
For further information on interface standards refer to:
 MIPI Alliance Specification for D-PHY, version 1.1, November 7, 2011, www.mipi.org
 MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2) version 1.1, July 18, 2012, www.mipi.org
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
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Appendix A. Resource Utilization
This appendix gives resource utilization information for Lattice FPGAs using theSubLVDS to MIPI CSI-2 Image Sensor
Interface Bridge.
LIF-MD6000 Utilization
Table A.1 lists resource utilization for LIF-MD6000 FPGAs using the SubLVDS to MIPI CSI-2 Image Sensor Interface
Bridge.
Table A.1. Resource Utilization*
IP User-Configurable
Parameters (1:8 gearing)
Slices
LUTs
Registers
sysMEME EBRs
Actual fMAX (MHz)
Target fMAX
(MHz)
10-lane configuration
2967
5242
2250
8-lane configuration
2480
3875
1927
12
99.364
93.75
10
123.870
90
6-lane configuration
2234
3559
4-lane configuration
1861
2889
1583
8
119.503
112.5
1271
6
140.726
112.5
*Note: Fmax shown is the byte clock. The target Fmax for this design is 93.75 MHz.
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Appendix B. What is Not Supported
The IP does not support the following features:
 Back-to-back transition from low power (LP) mode to high speed (HS) mode and vice versa. There is a wait time
needed between any LP and HS transition. Because of this wait time requirement on the MIPI DPHY TX side of the
bridge, the 1st line of each frame is dropped through the bridge. The wait time (horizontal blanking period)
between start of FV (frame valid) and start of LV (line valid), end of LV and end of FV and end of LV and start of LV
can be as long as 200 byte clock cycles or 650 input clock cycles depending on the lane rate.
 ECC error detection and correction
 Checksum error detection
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Revision History
Date
Version
May 2016
1.0
Change Summary
Initial release.
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