Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MPC17511
Rev. 3.0, 10/2013
1.0 A 6.8 V H-Bridge Motor
Driver IC
The 17511 is a monolithic H-Bridge designed to be used in portable
electronic applications to control small DC motors or bipolar step
motors. End applications include head positioners (CDROM or disk
drive), camera focus motors, and camera shutter solenoids.
The 17511 can operate efficiently with supply voltages as low as
2.0 V to as high as 6.8 V. Its low RDS(ON) H-Bridge output MOSFETs
(0.46 Ω typical) can provide continuos motor drive currents of 1.0 A
and handle peak currents up to 3.0 A. It is easily interfaced to low-cost
MCUs via parallel 3.0 V or 5.0 V compatible logic. The device can be
pulse width modulated (PWMed) at up to 200 kHz.
This device contains an integrated charge pump and level shifter (for
gate drive voltages), integrated shoot-through current protection
(cross-conduction suppression logic and timing), and undervoltage
detection and shutdown circuitry.
The 17511 has four operating modes: Forward, Reverse, Brake, and
Tri-state (high-impedance).
Features
• 2.0 to 6.8 V continuous operation
• Output current 1.0 A(DC), 3.0 A (peak)
• MOSFETs < 600 mΩ RDS(ON) @ 25 °C guaranteed
• 3.0 V/ 5.0 V TTL/ CMOS compatible logic inputs
• PWM frequencies up to 200 kHz
• Undervoltage shutdown
• Low power consumption
• Integrated charge pump
• Shoot-through current protection
• External MOSFET control circuit
17511
H-BRIDGE MOTOR DRIVER IC
ORDERING INFORMATION
Device
© Freescale Semiconductor, Inc., 2013. All rights reserved.
Temperature
Range (TA)
MPC17511EP/R2
Package
24 QFN
-20 to 65 °C
MPC17511EV/EL
Figure 1. 17511 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
EP SUFFIX
98ARL10577D
24-PIN QFN
EV SUFFIX)
98ASA10614D
16-Pin VMFP
16 VMFP
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Charge Pump
C2L
C2H
C1H
C1L
CRES
GOUT
Low-voltage
Shutdown
VDD
VM
IN1
OUT1
Level
Shifter
Predriver
IN2
VDD
OUT2
Control
Logic
GIN
VDD
PGND
LGND
EN
Figure 2. 17511 Simplified Internal Block Diagram
17511
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
C2L
1
16
C2H
C1H
2
15
CRES
C1L
3
14
GOUT
VM
4
13
OUT2
VDD
5
12
PGND
IN1
6
11
OUT1
IN2
7
10
GIN
EN
8
9
LGND
Figure 3. VMFP Pin Connections
Table 1. 17511 VMFP Pin Function Description
Pin
Number
Pin Name
Formal Name
1
C2L
Charge Pump 2L
Charge pump bucket capacitor 2 (negative pole).
2
C1H
Charge Pump 1H
Charge pump bucket capacitor 1 (positive pole).
3
C1L
Charge Pump 1L
Charge pump bucket capacitor 1 (negative pole).
4
VM
Motor Drive Power Supply
5
VDD
Logic Supply
6
IN1
Input Control 1
Control signal input 1
7
IN2
Input Control 2
Control signal input 2.
8
EN
Enable Control
Enable control signal input pin.
9
LGND
Logic Ground
10
GIN
Gate Driver Input
LOW True control signal for GOUT pin.
11
OUT1
H-Bridge Output 1
Driver output 1 (right half of H-Bridge).
12
PGND
Power Ground
13
OUT2
H-Bridge Output 2
Driver output 2 (left half of H-Bridge).
14
GOUT
Gate Driver Output
Output gate driver signal to external MOSFET switch.
15
CRES
Charge Pump Output Capacitor
Connection
16
C2H
Charge Pump 2H
Definition
Driver power supply voltage input pin.
Control circuit power supply pin.
Logic ground pin.
Driver ground pin.
Charge pump reservoir capacitor pin.
Charge pump bucket capacitor 2 (positive pole).
17511
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
GOUT
CRES
C2H
C2L
C1H
C1L
PIN CONNECTIONS
24 23 22 21 20 19
NC
VM
2
17
OUT2
VM
3
16
PGND
VM
4
15
PGND
NC
5
14
OUT1
NC
6
13
NC
GIN
9 10 11 12
LGND
8
EN
7
IN2
18
IN1
1
VDD
VM
Figure 4. QFN Pin Connections
Table 2. 17511 QFN Pin Function Description
Pin
Number
Pin Name
Formal Name
1, 2, 3, 4
VM
Motor Drive Power Supply
5, 6, 13, 18
NC
No Connect
This pin is not used.
7
VDD
Logic Supply
Control circuit power supply pin.
8
IN1
Logic Input Control 1
Control signal input 1.
9
IN2
Logic Input Control 2
Control signal input 2.
10
EN
Enable Control
11
LGND
Logic Ground
12
GIN
Gate Driver Input
14
OUT1
Output 1
15, 16
PGND
Power Ground
17
OUT2
Output 2
19
GOUT
Gate Driver Output
20
CRES
Pre-Driver Power Supply
21
C2H
Charge Pump 2H
Charge pump bucket capacitor 2 (positive pole).
22
C2L
Charge Pump 2L
Charge pump bucket capacitor 2 (negative pole).
23
C1H
Charge Pump 1H
Charge pump bucket capacitor 1 (positive pole).
24
C1L
Charge Pump 1L
Charge pump bucket capacitor 1 (negative pole).
Definition
Driver power supply voltage input pin.
Enable control signal input pin.
Logic ground pin.
LOW = True control signal for GOUT pin.
Driver output 1 (right half of H-Bridge).
Driver ground pin.
Driver output 2 (left half of H-Bridge).
Output gate driver signal to external MOSFET switch.
Pre-driver circuit power supply pin.
17511
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent
damage to the device.
Rating
Symbol
Value
Unit
VM
-0.5 to 8.0
V
-0.5 to 14.0
V
Motor Supply Voltage
V
Charge Pump Output Voltage
CRES
Logic Supply Voltage
VDD
-0.5 to 7.0
V
Signal Input Voltage (EN, IN1, IN2, GIN)
VIN
-0.5 to VDD + 0.5
V
IO
1.0
IOPK
3.0
Human Body Model
VESD1
±1800
Machine Model
VESD2
± 100
TSTG
-55 to 150
°C
TJ
-20 to 150
°C
Driver Output Current
A
Continuous
Peak (1)
ESD Voltage (2)
V
Storage Temperature Range
Operating Junction Temperature
Thermal Resistance
(3)
°C/W
RθJA
24 Pin QFN
50
16 Pin VMFP
150
Power Dissipation (4)
PD
24 Pin QFN
16 Pin VMFP
Soldering Temperature
mW
2500
830
(5)
Peak Package Reflow Temperature During Reflow
(6), (7)
TSOLDER
245
°C
TPPRT
Note 7
°C
Notes
1. TA = 25 °C, 10 ms pulse width at 200 ms intervals.
2.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
3.
QFN24: 45 x 30 x 1 [mm] glass EPOXY board mount. (See: recommended heat pattern) VMFP16: 37 x 50 x 1.6 [mm] glass EPOXY
board mount. When the exposed pad is bonded, Rsj is not performed.
Maximum at TA = 25 °C. When the exposed pad is bonded, Rsj is not performed.
4.
5.
6.
7.
Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
17511
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions TA = 25 °C, VM = VDD = 5.0 V, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Driver Circuit Power Supply Voltage
VM
2.0
5.0
6.8
V
Logic Supply Voltage
VDD
2.7
5.0
5.7
V
C1, C2, C3
0.01
0.1
1.0
μF
VMSTBY
–
–
1.0
μA
VDDSTBY
–
–
1.0
mA
DD
–
–
3.0
mA
RES
–
–
0.7
mA
VDDDET
1.5
2.0
2.5
V
RDS(ON)
–
0.46
0.60
Ω
12
13
13.5
10
11.2
–
POWER
Capacitor for Charge Pump
Standby Power Supply Current
I
Motor Supply Standby Current
Logic Supply Standby Current
(8)
I
Operating Power Supply Current
IV
Logic Supply Current (9)
IC
Charge Pump Circuit Supply Current
Low VDD Detection Voltage
(10)
Driver Output ON Resistance
(11)
GATE DRIVE
Gate Drive Voltage (12)
V
V
CRES
No Current Load
Gate Drive Ability (Internally Supplied)
V
V
CRESLOAD
IC
RES = -1.0 mA
Gate Drive Output
V
V
V
IOUT = -50 μA
VGOUTHIGH
lIN = 50 μA
VGOUTLOW
LGND
VIN
0
–
High-level Input Voltage
VIH
VDD x 0.7
Low-level Input Voltage
VIL
–
High-level Input Current
IIH
Low-level Input Current
IIL
Pull-Up Resistance (EN, GIN)
RPU
50
CRES- 0.5
CRES- 0.1
V
CRES
LGND + 0.1 LGND + 0.5
CONTROL LOGIC
Logic Input Voltage
VDD
V
–
–
V
–
VDD x 0.3
V
–
–
1.0
μA
-1.0
–
–
μA
100
200
kΩ
Logic Input Function (2.7 V < VDD < 5.7 V)
Notes
8.
9.
10.
I
I
VDDSTBY includes current to the predriver circuit.
VDD includes current to the predriver circuit.
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the
gate voltage VCRES is applied from an external source, VCRES = 7.5 V.
11.
IO = 1.0 A source + sink.
12.
Input logic signal not present.
17511
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions TA = 25 °C, VM = VDD = 5.0 V, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
fIN
–
–
200
kHz
INPUT (EN, IN1, IN2, GIN)
Pulse Input Frequency
Input Pulse Rise Time (13)
tR
Input Pulse Fall Time (15)
–
–
1.0
(14)
μs
1.0
(14)
μs
tF
–
–
Turn-ON Time
tPLH
–
0.55
1.0
Turn-OFF Time
tPHL
–
0.55
1.0
OUTPUT
μs
Propagation Delay Time
μs
GOUT Propagation Delay Time
Turn-ON Time
tSON
–
0.15
0.5
Turn-OFF Time
tSOFF
–
0.15
0.5
–
0.1
3.0
–
–
10
Charge Pump Circuit
(16)
tV
CRESON
ms
Rise Time (17)
t
Low-Voltage Detection Time
Notes
13.
14.
15.
16.
17.
VDDDET
ms
Time is defined between 10% and 90%.
That is, the input waveform slope must be steeper than this.
Time is defined between 90% and 10%.
When C1 = C2 = C3 = 0.1 μF.
Time to charge CRES to 11 V after application of VDD.
TIMING DIAGRAMS
VDDDETON
EN, IN1, IN2
(GIN)
50%
tPLH
(tSON)
OUT1, OUT2
(GOUT)
tPHL
VDD
0.8 V/
1.5 V
Figure 5. tPLH, tPHL, and tPZH Timing
t
VDDDET
90%
VDDDETOFF
50%
t
(tSOFF)
10%
2.5 V/3.5 V
VDDDET
90%
0%
(<1.0 μA)
IM
Figure 6. Low-Voltage Detection
17511
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Table 6. Truth Table
INPUT
OUTPUT
EN
IN1
IN2
GIN
OUT1
OUT2
GOUT
H
H
H
X
L
L
X
H
H
L
X
H
L
X
H
L
H
X
L
H
X
H
L
L
X
Z
Z
X
L
X
X
X
L
L
L
H
X
X
H
X
X
L
H
X
X
L
X
X
H
H = High.
L = Low.
Z = High-impedance.
X = Don’t care.
17511
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17511 is a monolithic H-Bridge power IC applicable to
small DC motors used in portable electronics. The 17511 can
operate efficiently with supply voltages as low as 2.0 V to as
high as 6.8 V, and it can provide continuos motor drive
currents of 1.0 A while handling peak currents up to 3.0 A. It
is easily interfaced to low-cost MCUs via parallel 3.0 V or
5.0 V compatible logic. The device can be pulse width
modulated (PWM-ed) at up to 200 kHz. The 17511 has four
operating modes: Forward, Reverse, Brake, and Tri-State
(high-impedance).
Basic protection and operational features (direction,
dynamic braking, PWM control of speed and torque, main
power supply undervoltage detection and shutdown, logic
power supply undervoltage detection and shutdown), in
addition to the 1.0 A rms output current capability, make the
17511 a very attractive, cost-effective solution for controlling
a broad range of small DC motors. In addition, a pair of 17511
devices can be used to control bipolar step motors. The
17511 can also be used to excite transformer primary
windings with a switched square wave to produce secondary
winding AC currents.
As shown in Figure 2, the 17511 is a monolithic H-Bridge
with built-in charge pump circuitry. For a DC motor to run, the
input conditions need to be set as follows: enable input logic
HIGH, one Input logic LOW, and the other input logic HIGH
(to define output polarity). The 17511 can execute dynamic
braking by setting both IN1 and IN2 logic HIGH, causing both
low side MOSFETs in the output H-Bridge to turn ON.
Dynamic braking can also implemented by taking the enable
logic LOW. The output of the H-Bridge can be set to an opencircuit high-impedance (Z) condition by taking both IN1 and
IN2 logic LOW. (refer to Table 6).
The 17511 outputs are capable of providing a continuous
DC load current of up to 1.2 A. An internal charge pump
supports PWM frequencies to 200 kHz. The EN pin also
controls the charge pump, turning it off when EN = LOW, thus
placing the 17511 in a power-conserving sleep mode.
FUNCTIONAL PIN DESCRIPTION
OUT1 AND OUT2
The OUT1 and OUT2 pins provide the connection to the
internal power MOSFET H-Bridge of the IC. A typical load
connected between these pins would be a small DC motor.
These outputs connect to either VM or PGND, depending on
the states of the control inputs (refer to Table 6).
VM has an undervoltage threshold. If the supply voltage
drops below the undervoltage threshold, the output power
stage switches to a tri-state condition. When the supply
voltage returns to a level above the threshold, the power
stage automatically resumes normal operation according to
the established condition of the input pins.
PGND AND LGND
IN1, IN2, AND EN
The power and logic ground pins (PGND and LGND)
should be connected together with a very low-impedance
connection.
The IN1, IN2, and EN pins are input control pins used to
control the outputs. These pins are 5.0 V CMOS-compatible
inputs with hysteresis. The IN1, IN2, and EN work together to
control OUT1 and OUT2 (refer to Table 6).
CRES
The CRES pin provides the connection for the external
reservoir capacitor (output of the charge pump). Alternatively
this pin can also be used as an input to supply gate-drive
voltage from an external source via a series current-limiting
resistor. The voltage at the CRES pin is approximately three
times the VDD voltage, as the internal charge pump utilizes a
voltage tripler circuit. The VCRES voltage is used by the IC to
supply gate drive for the internal power MOSFET H-Bridge.
VM
The VM pins carry the main supply voltage and current into
the power sections of the IC. This supply then becomes
controlled and/or modulated by the IC as it delivers the power
to the load attached between OUT1 and OUT2. All VM pins
must be connected together on the printed circuit board with
as short as possible traces offering as low-impedance as
possible between pins.
GIN
The GIN input controls the GOUT pin. When GIN is set
logic LOW, GOUT supplies a level-shifted high side gate
drive signal to an external MOSFET. When GIN is set logic
HIGH, GOUT is set to GND potential.
C1L AND C1H, C2L AND C2H
These two pairs of pins, the C1L and C1H and the C2L and
C2H, connect to the external bucket capacitors required by
the internal charge pump. The typical value for the bucket
capacitors is 0.1 μF.
GOUT
The GOUT output pin provides a level-shifted, high side
gate drive signal to an external MOSFET with CISS up to
500 pF.
17511
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
VDD
The VDD pin carries the 5.0 V supply voltage and current
into the logic sections of the IC. VDD has an undervoltage
threshold. If the supply voltage drops below the undervoltage
threshold, the output power stage switches to a tri-state
condition. When the supply voltage returns to a level that is
above the threshold, the power stage automatically resumes
normal operation according to the established condition of
the input pins.
17511
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
FUNCTIONAL PIN DESCRIPTION
TYPICAL APPLICATIONS
Figure 7 shows a typical application for the 17511. When
applying the gate voltage to the CRES pin from an external
source, be sure to connect it via a resistor equal to, or greater
than, RG = VCRES / 0.02 Ω.
5.0 V
17511
VDD
VCRES < 14 V
RG > VCRES /0.02 Ω
RG
NC
NC
NC
NC
0.01 μF
MCU
C1L
C1H
C2L
C2H
CRES
VM
GOUT
OUT1
Motor
EN
GIN
IN1
IN2
Solenoid
OUT2
GND
NC = No Connect
Figure 7. 17511 Typical Application Diagram
CEMF SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially
damaging CEMF spikes induced when commutating currents
in inductive loads. Typical practice is to provide snubbing of
voltage transients via placing a capacitor or zener at the
supply pin (VM) (see Figure 8).
5.0 V
5.0 V
17511
VM
VDD
5.0 V
5.0 V
17511
VM
VDD
C1L
C1H OUT1
C2L
C2H
CRES
C1L
C1H OUT1
C2L
C2H
CRES
GND
GND
OUT2
OUT2
Figure 8. CEMF Snubbing Techniques
17511
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit
www.freescale.com and perform a keyword search using
the “98A” listed below.
EV (PB-FREE) SUFFIX
16-PIN VMFP
98ASA10614D
ISSUE B
17511
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
EV (PB-FREE) SUFFIX
16-PIN VMFP
98ASA10614D
ISSUE B
17511
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
PACKAGING
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
EP (PB-FREE) SUFFIX
24-PIN QFN
98ARL10577D
ISSUE B
17511
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
EP (PB-FREE) SUFFIX
24-PIN QFN
98ARL10577D
ISSUE B
17511
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
PACKAGING
PACKAGE DIMENSIONS
EP (PB-FREE) SUFFIX
24-PIN QFN
98ARL10577D
ISSUE B
17511
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
1.0
7/2006
• Implemented Revision History page
• Converted to Freescale format
2.0
5/2010
• Updated Figures 1 and 2 to reflect correct pin names
3.0
10/2013
•
•
•
•
•
Corrected Ordering information to MPC17511EP and MPC17511EV/EL
Corrected packaging drawings to 98ASA10614D and 98ARL10577D
Corrected Figure 1 and some text for GIN
Corrected page footers to 17511
Corrected Table 6 - now on 1 page.
17511
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
REVISION HISTORY
17511
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
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© 2013 Freescale Semiconductor, Inc.
Document Number: MPC17511
Rev. 3.0
10/2013
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