Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MC34931
Rev. 4.0, 9/2015
5.0 A H-Bridge
34931
Industrial
The 34931 is a monolithic H-Bridge Power IC in a robust thermally
enhanced package. It is designed for any low voltage DC servo motor
control application within the current and voltage limits stated in this
specification. This device is powered by SMARTMOS technology.
The 34931 H-Bridge is able to control inductive loads with currents up
to 5.0 A peak. RMS current capability is subject to the degree of
heatsinking provided to the device package. Internal peak current
limiting (regulation) is activated at load currents above 6.5 A ±1.5 A.
Output loads can be pulse-width modulated (PWMed at frequencies up
to 20 kHz. A load current feedback feature provides a proportional
(0.24% of the load current) current output suitable for monitoring by a
microcontroller’s A/D input. A status flag output reports undervoltage,
overcurrent, and overtemperature fault conditions.
Two independent inputs provide polarity control of two half-bridge
totem-pole outputs. The disable inputs are provided to force the
H-Bridge outputs to tri-state (high-impedance off-state).
H-BRIDGE
EK SUFFIX (PB-FREE)
98ARL10543D
32-PIN SOICW-EP
Applications
• DC motor control
• DC brushed and servo motor driver
• Copiers, printers
• Factory automation
• POS, ATM, vending kiosks
• Robotics
• Security camera control
• Ticketing, toll systems
Features
• 5.0 V to 36 V continuous operation with 24 V nominal operating
voltage (transient operation from 5.0 V to 40 V)
• 235 m maximum RDS(on) at TJ = 150 °C (each H-Bridge
MOSFET)
• 3.0 V and 5.0 V TTL/CMOS logic compatible inputs
• Overcurrent limiting (regulation) via internal constant-off-time
PWM
• Output short-circuit protection (short to VPWR or GND)
• Temperature-dependant current-limit threshold reduction
• All inputs have an internal source/sink to define the default
(floating input) states
• Sleep mode with current draw < 20 µA
VPWR
VDD
34931
SF
VPWR
FB
CCP
OUT1
MCU
IN1
MOTOR
IN2
OUT2
D1
EN/D2
PGND
AGND
Figure 1. MC34931 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2013-2015. All rights reserved.
1
Orderable Parts
Table 1. Orderable Part Variations
Part Number
PWM Frequency
MC34931EK
11 kHz
MC34931SEK
20 kHz
Temperature (TA)
Package
Notes
- 40 °C to 85 °C
32 SOICW-EP
(1)
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
34931
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
Internal Block Diagram
VPWR
LOGIC SUPPLY
CCP
VDD
VCP CHARGE
PUMP
HS1
HS2
OUT1
TO GATES
OUT2
HS1
IN1
LS1
IN2
HS2
EN/D2
D1
GATE DRIVE
AND
PROTECTION
LOGIC
SF
LS1
PGND
LS2
VSENSE
ILIM PWM
FB
LS2
CURRENT MIRROR
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
AGND
PGND
Figure 2. 34931 Simplified Internal Block Diagram
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
3
Pin Connections
3.1
Pinout Diagram
AGND
1
32
D1
2
31
IN1
FB
3
30
N/C
SF
N/C
4
29
IN2
EN/D2
5
28
CCP
N/C
6
27
N/C
VPWR
7
26
VPWR
VPWR
8
25
VPWR
N/C
9
24
N/C
OUT1
10
23
OUT2
OUT1
11
22
OUT2
N/C
12
21
N/C
N/C
13
20
N/C
N/C
14
19
N/C
PGND
15
18
PGND
PGND
16
17
PGND
EP
32 SOICW-EP
Transparent Top View
Figure 3. 34931 Pin Connections
A functional description of each pin can be found in the Functional Description section beginning on page 12.
Table 2. 34931 Pin Definitions
Pin
Number
Pin
Name
Pin
Function
Formal Name
Definition
2
D1
Logic Input
Disable Input 1
(Active High)
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger
input with ~ 80 A source so default condition = disabled.
3
FB
Analog
Output
Feedback
The load current feedback output provides ground referenced 0.24% of the
high-side output current. (Tie to GND through a resistor if not used.)
5
EN/D2
Logic Input
Enable Input
When EN/D2 is logic HIGH the H-Bridge is operational. When EN/D2 is logic
LOW, the H-Bridge outputs are tri-stated and placed in Sleep mode. (logic
input with ~ 80 A sink so default condition = Sleep mode.)
7, 8, 25, 26
VPWR
Power Input
Positive Power
Supply
These pins must be connected together physically as close as possible and
directly soldered down to a wide, thick, low resistance supply plane on the
PCB.
10, 11
OUT1
Power
Output
H-Bridge Output 1
15-18
PGND
Power
Ground
Power Ground
22, 23
OUT2
Power
Output
H-Bridge Output 2
Source of HS1 and drain of LS1
High-current power ground pins must be connected together physically as
close as possible and directly soldered down to a wide, thick, low resistance
ground plane on the PCB.
Source of HS2 and drain of LS2
34931
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 2. 34931 Pin Definitions (continued)
Pin
Number
Pin
Name
Pin
Function
Formal Name
28
CCP
Analog
Output
Charge Pump
Capacitor
29
IN2
Logic Input
Input 2
Logic input control of OUT2;e.g., when IN2 is logic HIGH, OUT2 is set to
VPWR, and when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger
Input with ~ 80 A source so default condition = OUT2 HIGH.)
31
IN1
Logic Input
Input 1
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to
VPWR, and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger
Input with ~ 80 A source so default condition = OUT1 HIGH.)
32
SF
Logic
Output Open Drain
Status Flag
(Active Low)
Open drain active LOW Status Flag output (requires an external pull-up
resistor to VDD. Maximum permissible load current < 0.5 mA. Maximum
VSFLOW < 0.4 V at 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)
1
AGND
Analog
Ground
Analog Signal
Ground
4, 6, 9, 12-14,
19-21, 24, 27,
30
N/C
None
No Connect
EP
EP
Thermal
Pad
Exposed Pad
Definition
External reservoir capacitor connection for the internal charge pump;
connected to VPWR. Allowable values are 30 nF to 100 nF. Note: This
capacitor is required for the proper performance of the device.
The low-current analog signal ground must be connected to PGND via lowimpedance path (<10 m, 0 Hz to 20 kHz).
Pin is not used
Exposed TAB is also the main heatsinking path for the device and must be
connected to GND.
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
4
Electrical Characteristics
4.1
Maximum Ratings
Table 3. Maximum Ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device. These parameters are not production tested.
Ratings
Symbol
Value
Unit
VPWR(SS)
VPWR(T)
- 0.3 to 36
- 0.3 to 40
V
Logic Input Voltage(2)
VIN
- 0.3 to 7.0
V
(3)
V SF
- 0.3 to 7.0
V
IOUT(CONT)
5.0
A
ELECTRICAL RATINGS
Power Supply Voltage
• Normal Operation (Steady-state)
• Transient Overvoltage(1)
SF Output
Continuous Output
ESD
•
•
•
•
•
Current(4)
Voltage(5)
Human Body Model
Machine Model
Charge Device Model
Corner Pins
All Other Pins
VESD1
VESD2
± 2000
± 200
V
±750
±500
THERMAL RATINGS
Storage Temperature
TSTG
- 65 to 150
C
TA
TJ
- 40 to 85
- 40 to 150
C
TPPRT
Note 8
°C
RJC
< 1.0
C/W
Temperature(6)
Operating
• Ambient
• Junction
Peak Package Reflow Temperature During Reflow(7),(8)
Approximate Junction-to-Case Thermal Resistance(9)
Notes
1. Device survives repetitive transient overvoltage conditions for durations not to exceed 500 ms at duty cycle not to exceed 5.0%. External
protection is required to prevent device damage in case of a reverse power condition.
2. Exceeding the maximum input voltage on IN1, IN2, EN/D2 or D1 may cause a malfunction or permanent damage to the device.
3. Exceeding the pull-up resistor voltage on the open drain SF pin may cause permanent damage to the device.
4. Continuous output current capability is dependent on sufficient package heatsinking to keep junction temperature  150C.
5. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), Machine Model (CZAP = 200 pF,
RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
6.
7.
8.
9.
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
non-repetitive excursions of junction temperature above 150C can be tolerated, provided the duration does not exceed 30 seconds
maximum. (Non-repetitive events are defined as not occurring more than once in 24 hours.)
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RJB (junction-to-PC board)
values varies depending on solder thickness and composition and copper trace thickness and area. Maximum current at maximum die
temperature represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RJA must be 
< 5.0 C/W for maximum current at 70 C ambient. Module thermal design must be planned accordingly.
34931
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
4.2
Static Electrical Characteristics
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 5.0 V VPWR  36 V, - 40 C  TA  85 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min.
Typ.
Max.
Unit
VPWR(SS)
VPWR(t)
5.0
–
–
–
36
40
V
IPWR(SLEEP)
–
15
20
IPWR(STANDBY)
–
–
18
mA
VUVLO(ACTIVE)
VUVLO(INACTIVE)
VUVLO(HYS)
4.15
–
150
–
–
200
–
5.0
350
V
V
mV
Charge Pump Voltage (CP Capacitor = 33 nF), No PWM
• VPWR = 5.0 V
• VPWR = 36 V
VCP - VPWR
3.5
–
–
–
–
12
V
Charge Pump Voltage (CP Capacitor = 33 nF), PWM = 11 kHz for
MC34931EK and 20 kHz for MC34931SEK
• VPWR = 5.0 V
• VPWR = 36 V
VCP - VPWR
3.5
–
–
–
–
12
V
VI
–
–
5.5
V
VIH
VIL
VHYS
2.0
–
250
–
–
400
–
1.0
–
V
V
mV
IIN
20
-200
80
-80
200
-20
A
POWER INPUTS (VPWR)
Operating Voltage Range(10)
• Steady-state
• Transient (t < 500 ms)(11)
Sleep State Supply Current(12)
• EN/D2 = Logic [0], IN1, IN2, D1 = Logic [1], and IOUT = 0A
Standby Supply Current (Part Enabled)
• IOUT = 0 A, VEN = 5.0 V
Undervoltage Lockout Thresholds
• VPWR(FALLING)
• VPWR(RISING)
• Hysteresis
A
CHARGE PUMP
CONTROL INPUTS
Operating Input Voltage (IN1, IN2, D1, EN/D2)
Input Voltage (IN1, IN2, D1, EN/D2)
• Logic Threshold HIGH
• Logic Threshold LOW
• Hysteresis
Logic Input Currents, VPWR = 5.0 V
• Input EN/D2 (internal pull-downs), VIH = 5.0 V
• Inputs IN1, IN2, D1 (internal pull-ups), VIL = 0 V
Notes
10. Device specifications are characterized over the range of 8.0 V  VPWR  36 V. Continuous operation above 36 V may degrade device
reliability. Device is operational down to 5.0 V, but below 8.0 V the output resistance may increase by 50 percent.
11. Device survives the transient overvoltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once
every 10 seconds.
12. IPWR(SLEEP) is with Sleep Mode activated and EN/ D2, = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating. Typical
value characterized under the following conditions: TA = 85 C and VPWR = 36 V.
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.0 V VPWR  36 V, - 40 C  TA  85 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min.
Typ.
Max.
–
–
–
120
–
–
–
235
325
Unit
POWER OUTPUTS OUT1, OUT2
Output-ON Resistance(14), ILOAD = 3.0 A
• VPWR = 8.0 V, TJ = 25 C
• VPWR = 8.0 V, TJ = 150 C
• VPWR = 5.0 V, TJ = 150 C
RDS(ON)
m
Output Current Regulation Threshold
• TJ < TFB
• TJ  TFB (Foldback Region - see Figure 9 and Figure 11)(13)
ILIM
5.2
–
6.5
4.2
8.0
–
A
High-side Short-circuit Detection Threshold (Short Circuit to Ground)(13)
ISCH
11
13
16
A
ISCL
9.0
11
14
A
IOUTLEAK
–
-140
–
–
100
–
A
VF
–
–
2.0
V
TLIM
THYS
175
–
–
12
200
–
C
TFB
165
–
185
C
TSEP
10
–
15
C
0.0
0.0
0.35
2.86
5.71
11.43
–
270
0.775
3.57
7.14
14.29
50
750
1.56
4.28
8.57
17.15
A
A
mA
mA
mA
mA
Low-side Short-circuit Detection Threshold (Short Circuit to VPWR
)(13)
(15)
Output Leakage Current , Outputs off, VPWR = 36 V
MC34931EK and MC34931SEK
• VOUT = VPWR
• VOUT = Ground
Output MOSFET Body Diode Forward Voltage Drop, IOUT = 3.0 A
Shutdown(13)
Overtemperature
• Thermal Limit at TJ
• Hysteresis at TJ
Current Foldback at TJ(13)
Current Foldback to Thermal Shutdown Separation
(13)
HIGH SIDE CURRENT SENSE FEEDBACK
Feedback Current (pin FB sourcing current)(16)
• I OUT = 0 mA
• I OUT = 300 mA
• I OUT = 500 mA
• I OUT = 1.5 A
• I OUT = 3.0 A
• I OUT = 6.0 A
I FB
STATUS FLAG(17)
Status Flag Leakage Current(18)
• V SF = 5.0 V
ISFLEAK
–
–
5.0
Status Flag SET Voltage(19)
• I SF = 300 µA
VSFLOW
–
–
0.4
Notes
13.
14.
15.
16.
A
V
This parameter is Guaranteed By Design.
Output-ON resistance as measured from output to VPWR and from output to GND.
Outputs switched OFF via D1.
Accuracy is better than 20% from 0.5 A to 6.0 A. Recommended terminating resistor value: RFB = 270 
17.
Status Flag output is an open drain output requiring a pull-up resistor to logic VDD.
18.
19.
Status Flag Leakage Current is measured with Status Flag HIGH and not SET.
Status Flag Set Voltage measured with Status Flag LOW and SET with I SF = 300 A. Maximum allowable sink current from this pin is
< 500 A . Maximum allowable pull-up voltage < 7.0 V.
34931
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
4.3
Dynamic Electrical Characteristics
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.0 V  VPWR  36 V, - 40 C  TA 85 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min.
Typ.
Max.
Unit
PWM Frequency(20)
• MC34931EK
• MC34931SEK
f PWM
–
–
–
–
11
20
kHz
Maximum Switching Frequency During Current Limit Regulation(21)
f MAX
–
–
20
kHz
Output ON Delay
• VPWR = 24 V
t DON
–
–
18
Output OFF Delay(22)
• VPWR = 24 V
t DOFF
–
–
12
ILIM Output Constant-OFF Time(23),(25)
tA
15
20.5
32
s
Time(24),(25)
tB
12
16.5
27
s
t DDISABLE
–
–
8.0
s
t F, t R
1.9
0.2
3.9
1.1
8.0
1.5
s
t FAULT
–
–
8.0
s
Power-ON Delay Time(29)
t POD
–
1.0
5.0
ms
Output MOSFET Body Diode Reverse Recovery Time(29)
t RR
75
100
150
ns
Charge Pump Operating Frequency(29)
fCP
–
7.0
–
MHz
TIMING CHARACTERISTICS
(22)
ILIM Blanking
Disable Delay
Time(26)
Output Rise and Fall
• MC34931EK
• MC34931SEK
s
s
Time(27)
Short-circuit / Overtemperature Turn-OFF (Latch-OFF) Time(28),(29)
Notes
20. The maximum PWM frequency should be limited to frequencies < 11 kHz for MC34931EK and < 20 kHz for MC34931SEK in order to
allow the internal high-side driver circuitry time to fully enhance the high-side MOSFETs at a duty cycle range of 15 to 85%.
21. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s
inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM
frequency during current limit.
22. * Output Delay is the time duration from 1.5 V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5 V on the input signal to the 80% point of
the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5 V on the input signal to the 20% point of the
output response signal. See Figure 4, page 10.
23. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
24. The time during which the current regulation threshold is ignored so the short-circuit detection threshold comparators may have time to
act.
25. Parameter is Guaranteed By Characterization.
26. * Disable Delay Time measurement is defined in Figure 5, page 10.
27. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with VPWR = 24 V, 
RLOAD = 3.0 ohm. See Figure 6, page 10.
28.
29.
Load currents ramping up to the current regulation threshold become limited at the ILIM value (see Figure 7). The short-circuit currents
possess a di/dt which ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short-circuit event detection
and causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit
mode may cause junction temperatures to rise. Junction temperatures above ~160 C causes the output current limit threshold to “fold
back”, or decrease, until ~175 C is reached, after which the TLIM thermal latch-OFF occurs. Permissible operation within this fold back
region is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).
Parameter is Guaranteed By Design.
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
VIN1, IN2 (V)
Timing Diagrams
5.0
VOUT1, 2 (V)
4.4
VPWR
1.5 V
1.5 V
0
t DON
t DOFF
80%
20%
0
TIME
5.0 V
1.5 V
0V
IO = 100 mA
VOUT1, 2
VD1, EN/D2 (V)
Figure 4. Output Delay Time
tDDISABLE
90%

TIME
Figure 5. Disable Delay Time
VOUT1, 2 (V)
.
tF
VPWR
tR
90%
90%
10%
0
10%
TIME
Figure 6. Output Switching Time
Overload Condition
IOUT, CURRENT (A)
9.0
ISC Short-circuit Detection Threshold
tB
6.5
0.0
5.0
tB = ILIM Blanking Time
tA = Constant-OFF Time (OUT1 and OUT2 Tri-Stated)
tA
ILIM
t ON
TIME
Figure 7. Current Limit Blanking Time and Constant-OFF Time
34931
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
Short-circuit Condition
t FAULT
IOUT, CURRENT (A)
9.0
ISC Short-circuit Detection Threshold
Hard Short Occurs
tB
6.5
OUT1, OUT2 Tri-stated,
SF set Low
ILIM
0.0
5.0
t B (~16 s)
TIME
Figure 8. Short-circuit Detection Turn-OFF Time tFAULT
.
Current Limit Threshold Foldback.
Operation within this region must be
limited to non-repetitive events not to
exceed 30 s per 24 hr.
ILIM, CURRENT (A)
6.5
4.2
tSEP
tLIM
Thermal Shutdown
tHYS
tFB
tLIM
Figure 9. Output Current Limiting Foldback Region
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
5
Functional Description
5.1
Introduction
Numerous protection and operational features (speed, torque, direction, dynamic breaking, PWM control, and closed-loop
control) make the 34931 a very attractive, cost-effective solution for controlling a broad range of small DC motors. The 34931
outputs are capable of supporting peak DC load currents of up to 5.0 A from a 36 V VPWR source. An internal charge pump and
gate drive circuitry which can support external PWM frequencies up to 11 kHz in MC34931EK and 20 kHz in MC34931SEK.
The 34931 has an analog feedback (current mirror) output pin (the FB pin) which provides a constant-current source ratioed to
the active high-side MOSFETs’ current. This can be used to provide monitoring of output current to facilitate closed-loop
operation for motor speed/torque control, or for the detection of open load conditions.
Two independent inputs, IN1 and IN2, provide control of the two totem-pole half-bridge outputs. Two independent disable inputs,
D1 and EN/D2, provide the means to force the H-Bridge outputs to a high-impedance state (all H-Bridge switches OFF). The EN/
D2 pin also controls an enable function allowing the IC to be placed in a power-conserving Sleep mode.
The 34931 has output current limiting (via constant OFF-time PWM current regulation), output short-circuit detection with latchOFF, and overtemperature detection with latch-OFF. Once the device is latched-OFF due to a fault condition, either of the Disable
inputs (D1 or EN/D2), or VPWR must be toggled to clear the status flag.
Current limiting (Load Current Regulation) is accomplished by a constant-OFF time PWM method using current limit threshold
triggering. The current limiting scheme is unique in that it incorporates a junction temperature-dependent current limit threshold.
This means the current limit threshold is reduced to around 4.2 A as the junction temperature increases above 160 °C. When the
temperature is above 175 °C, overtemperature shutdown (latch-OFF) occurs. This combination of features allows the device to
continue operating for short periods of time (< 30 seconds) with unexpected loads, while still retaining adequate protection for
both the device and the load.
5.2
Functional Pin Description
5.2.1
Power Ground and Analog Ground (PGND and AGND)
The power and analog ground pins should be connected together with a very low-impedance connection.
5.2.2
Positive Power Supply (VPWR)
VPWR pins are the power supply inputs to the device. All VPWR pins must be connected together on the printed circuit board
with as short as possible traces, offering as low an impedance as possible between pins.
5.2.3
Status Flag (SF)
This pin is the device fault status output. This output is an active LOW open drain structure requiring a pull-up resistor to VDD.
The maximum VDD is < 7.0 V. Refer to Table 6 for the SF Output status definition.
5.2.4
Input 1,2 and Disable Input 1 (IN1, IN2, and D1)
These pins are input control pins used to control the outputs. These pins are 3.0 V/ 5.0 V CMOS-compatible inputs with
hysteresis. IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 input is used to tri-state disable the H-Bridge
outputs.
When D1 is SET (D1 = logic HIGH) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest
of the device circuitry is fully operational and the supply IPWR(STANDBY) current is reduced to a few mA. Refer to Table 4, page 7.
34931
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
5.2.5
H-Bridge Output (OUT1, OUT2)
These pins are the outputs of the H-Bridge with integrated free-wheeling diodes. The bridge output is controlled using the IN1,
IN2, D1, and EN/D2 inputs. The outputs have PWM current limiting above the ILIM threshold. The outputs also have thermal
shutdown (tri-state latch-OFF) with hysteresis as well as short-circuit latch-OFF protection.
A disable timer (time t B) is incorporated to distinguish between load currents which are higher than the ILIM threshold and shortcircuit currents. This timer is activated at each output transition.
5.2.6
Charge Pump Capacitor (CCP)
This pin is the charge pump output pin and connection for the external charge pump reservoir capacitor. The allowable value is
from 30 nF to 100 nF. This capacitor must be connected from the CCP pin to the VPWR pin. The device cannot operate properly
without the external reservoir capacitor.
5.2.7
Enable Input/Disable Input 2 (EN/D2)
The EN/D2 pin performs the same function as D1 pin, when it goes to a logic LOW the outputs are immediately tri-stated. It is
also used to place the device in a Sleep mode so as to consume very low currents. When the EN/D2 pin voltage is a logic LOW
state, the device is in the Sleep mode. The device is enabled and fully operational when the EN pin voltage is logic HIGH. An
internal pull-down resistor maintains the device in Sleep mode in the event EN is driven through a high-impedance I/O or an
unpowered microcontroller, or the EN/D2 input becomes disconnected.
5.2.8
Feedback (FB)
The 34931 has a feedback output (FB) for monitoring of H-Bridge high-side output currents to facilitate closed-loop operation for
motor speed and torque control.
The FB pin provides current sensing feedback of the H-Bridge high-side drivers. When running in the forward or reverse direction,
a ground-referenced 0.24% of load current is output to this pin. Through the use of an external resistor to ground, the proportional
feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can measure the
current proportional voltage with its analog-to-digital converter (ADC). This is intended to provide the user with only first-order
motor current feedback for motor torque control. The resistance range for the linear operation of the FB pin is 100  < RFB
< 300 .
If PWM-ing is implemented using the disable pin input (only D1), a small filter capacitor (~1.0 µF) may be required in parallel with
the RFB resistor to ground for spike suppression.
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
5.3
Functional Internal Block Description
34931
CURRENT SENSE
VOLTAGE
REGULATION
TEMPERATURE
CHARGE
SENSE
PUMP
ANALOG CONTROL AND PROTECTION
INPUT LOGIC CONTROL
MCU
INTERFACE
H-BRIDGE
OUTPUT DRIVERS
OUT1 - OUT2
FAULT LOGIC
PROTECTION LOGIC CONTROL
GATE CONTROL LOGIC
Figure 10. Functional Internal Block Diagram
5.3.1
Analog Control and Protection Circuitry
An on-chip voltage regulator supplies the internal logic. The charge pump provides gate drive for the H-Bridge MOSFETs. The
current and temperature sense circuitry provides detection and protection for the output drivers. Output undervoltage protection
shuts down the MOSFETS.
5.3.2
Gate Control Logic
The 34931 is a monolithic H-Bridge Power IC designed primarily for any low-voltage DC servo motor control application within
the current and voltage limits stated for the device. Two independent inputs provide polarity control of two half-bridge totem-pole
outputs. Two independent disable inputs are provided to force the H-Bridge outputs to tri-state (high-impedance off-state).
5.3.3
H-bridge Output Drivers: OUT1 and OUT2
The H-Bridge is the power output stage. The current flow from OUT1 to OUT2 is reversible and under full control of the user by
way of the Input Control Logic. The output stage is designed to produce full load control under all system conditions. All protective
and control features are integrated into the control and protection blocks. The sensors for current and temperature are integrated
directly into the output MOSFET for maximum accuracy and dependability.
34931
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device operation
6.1
Operational Modes
SF LOGIC OUT
EN/D2 LOGIC IN
D1 LOGIC IN
INn LOGIC IN
ILOAD OUTPUT CURRENT (A)
6
9.0
Typical Short-circuit Detection Threshold
6.5
Typical Current Limit Threshold
PWM
Current
Limiting
High Current Load Being Regulated via Constant-OFF-Time PWM
Moderate Current Load
Hard Short Detection and Latch-OFF
0
[1]
[0]
IN1 IN2
IN1 or IN2
IN1 or IN2
IN2 or IN1
IN2 or IN1
[1]
[0]
[1]
[0]
[1]
Outputs
[0]
Tri-stated
Outputs Operation
(per Input Control Condition)
Outputs
Tri-stated
Time
Figure 11. Operating States
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
6.2
Logic Commands
Table 6. Truth Table
The tri-state conditions and the status flag are reset using D1 or EN/D2. The truth table uses the following notations: L = LOW,
H = HIGH, X = HIGH or LOW, and Z = High-impedance. All output power transistors are switched off.
Input Conditions
Device State
EN/D2
D1
Status
IN1
IN2
Outputs
SF
OUT1
OUT2
Forward
H
L
H
L
H
H
L
Reverse
H
L
L
H
H
L
H
Freewheeling Low
H
L
L
L
H
L
L
Freewheeling High
H
L
H
H
H
H
H
Disable 1 (D1)
H
H
X
X
L
Z
Z
IN1 Disconnected
H
L
Z
X
H
H
X
IN2 Disconnected
H
L
X
Z
H
X
H
D1 Disconnected
H
Z
X
X
L
Z
Z
Undervoltage Lockout(30)
H
X
X
X
L
Z
Z
Overtemperature(31)
H
X
X
X
L
Z
Z
Short-circuit(31)
H
X
X
X
L
Z
Z
Sleep Mode EN/D2
L
X
X
X
H
Z
Z
EN/D2 Disconnected
Z
X
X
X
H
Z
Z
Notes
30. In the event of an undervoltage condition, the outputs tri-state and status flag is SET logic LOW. Upon undervoltage
recovery, status flag is reset automatically or automatically cleared and the outputs are restored to their original operating
condition.
31. When a short-circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of
the input signals and the status flag is latched to logic LOW. To reset from this condition requires the toggling of either D1,
EN/D2, or VPWR.
Forward
Load
Current
OFF
OUT2
ON
OFF
ON
ON
OUT1
OUT1
OFF
LOAD
OUT2
ON
OUT2
LOAD
ON
OFF
PGND
VPWR
VPWR
Load
Current
ON
LOAD
Low-Side Recirculation
(Forward)
V PW R
V PW R
VPWR
VPWR
Load
Current
OUT1
Reverse
High-Side Recirculation
(Forward)
V PW R
V PW R
LOAD
OUT2
Load
Current
ON
PGND
PGND
OFF
OUT1
OFF
OFF
PGND
OFF
ON
PGND
PGND
PGND
PGND
Figure 12. 34931 Power Stage Operation
34931
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
6.3
Protection and Diagnostic Features
6.3.1
Short-circuit Protection
If an output short-circuit condition is detected, the power outputs tri-state (latch-OFF) independent of the input (IN1 and IN2)
states, and the fault status output flag (SF) is SET to logic LOW. If the D1 input changes from logic HIGH to logic LOW, or if the
EN/D2 input changes from logic LOW to logic HIGH, the output bridge becomes operational again and the fault status flag resets
(cleared) to a logic HIGH state.
The output stage always switches into the mode defined by the input pins (IN1, IN2, D1, and EN/D2), provided the device junction
temperature is within the specified operating temperature range.
6.3.2
Internal PWM Current Limiting
The maximum current flow under normal operating conditions should be less than 5.0 A. The instantaneous load currents is
limited to ILIM via the internal PWM current limiting circuitry. When the ILIM threshold current value is reached, the output stages
are tri-stated for a fixed time (T A) of 20 µs typical. Depending on the time constant associated with the load characteristics, the
output current decreases during the tri-state duration until the next output ON cycle occurs.
The PWM current limit threshold value is dependent on the device junction temperature. When - 40 °C < TJ < 160 °C, ILIM is
between the specified minimum/maximum values. When TJ exceeds 160 °C, the ILIM threshold decreases to 4.2 A. Shortly above
175 °C the device overtemperature circuit detects tLIM and an overtemperature shutdown occurs. This feature implements a
graceful degradation of operation before thermal shutdown occurs, thus allowing for intermittent unexpected mechanical loads
on the motor’s gear-reduction train to be handled.
Important:
Die temperature excursions above 150 C are permitted only for non-repetitive durations < 30 seconds. Provision must be made
at the system level to prevent prolonged operation in the current-foldback region.
6.3.3
Overtemperature Shutdown and Hysteresis
If an overtemperature condition occurs, the power outputs are tri-stated (latched-OFF) and the fault status flag (SF) is SET to
logic LOW.
To reset from this condition, D1 must change from logic HIGH to logic LOW, or EN/D2 must change from logic LOW to logic
HIGH. When reset, the output stage switches ON again, provided the junction temperature is now below the overtemperature
threshold limit minus the hysteresis fault has cleared. When the junction temperature is below the overtemperature threshold
limit, EN/D2 clears the fault. When the junction temperature is below the overtemperature threshold limit minus the hysteresis,
D1 clears the fault.
Important:
Resetting from the fault condition clears the fault status flag. Powering down and powering up the device resets the 34931 from
the fault condition.
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
6.3.4
Output Avalanche Protection
If VPWR were to become an open circuit, the outputs would likely tri-state simultaneously due to the disable logic. This could
result in an unclamped inductive discharge. The VPWR input to the 34931 should not exceed 40 V during this transient condition,
to prevent electrical overstress of the output drivers.This can be accomplished with a zener clamp or MOV, and/or an
appropriately valued input capacitor with sufficiently low ESR (see Figure 13).
VPW R
VPW R
Bulk
Low ESR
Cap.
100nF
OUT1
M
9
I/Os
OUT2
AGND
PGND
Figure 13. Avalanche Protection
34931
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
Typical Applications
7.1
Introduction
A typical application schematic is shown in Figure 14. For precision high-current applications in harsh, noisy environments, the
VPWR by-pass capacitor may need to be substantially larger.
VPWR
100 F
100 nF
VPWR
33nF
LOGIC SUPPLY
CCP
VDD
VCP CHARGE
PUMP
HS1
HS2
OUT1
M
TO GATES
OUT2
HS1
IN1
D1
+5.0 V
STATUS
FLAG
TO
ADC RFB
270 
LS2
LS1
IN2
EN/D2
LS1
HS2
GATE DRIVE
AND
PROTECTION
LOGIC
PGND
LS2
VSENSE
ILIM PWM
SF
FB
CURRENT MIRRORS
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
1.0 F
AGND
PGND
Figure 14. 34931 Typical Application Schematic
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
8
Packaging
8.1
Package Dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to
www.freescale.com and perform a keyword search for the drawing’s document number.
34931
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
34931
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
9
Thermal Addendum
9.1
Introduction
This thermal addendum is provided as a supplement to the MC34931 technical datasheet. The addendum provides thermal
performance information which may be critical in the design and development of system applications. All electrical, application,
and packaging information is provided in the datasheet.
9.2
Package and Thermal Considerations
The MC34931 is offered in a 32-pin SOICW-EP single die package. There is a single heat source (P), a single junction
temperature (TJ), and thermal resistance (RJA).
TJ
=
RJA
.
P
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to, and does not predict the performance of a package in an application-specific environment.
Stated values were obtained by measurement and simulation according to the standards listed below.
Table 7. Table of Thermal Resistance Data
Rating
Value
Unit
Notes
Junction to Ambient
Natural Convection
Single Layer board (1s)
RJA
92.0
°C/W
(32),(33)
Junction to Ambient
Natural Convection
Four layer board (2s2p)
RJA
26.6
°C/W
(32),(34)
Junction to Board
RJB
7.0
°C/W
(35)
Junction to Case (bottom / flag)
RJC (bottom)
0.62
°C/W
(38)
Junction to Case (top)
RJC (top)
23.3
°C/W
(36)
JT
2.7
°C/W
(37)
Junction to Package Top
Natural Convection
Notes
32. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
33. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
34. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
35. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
36. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
37. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
38. Thermal resistance between the die and the case bottom / flag surface (simulated) (flag bottom side fixed to ambient temperature).
34931
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
100
Thermal Resistance [°C/W]
]
W
/C 10
° [
e
c
n
at
si
se
R
l a
m
r
1
e
h
T
0.1
0.001
0.01
0.1
1
10
100
1000
10000
Time [s]
Figure 15. Transient Thermal Resistance RJA MC34931EK on 2s2p Test Board
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
Figure 16. Typical Duty Cycle Linearity over Frequency at 36 V for MC34932SEK
Operating the part continuously at more than 24 V and up to 36 V while switching the outputs at high frequencies causes
additional power dissipation on the die due to high switching losses. This could result in junction temperature (TJ) exceeding the
thermal foldback temperature (TFB) and even thermal shutdown (TLIM) threshold. Hence, while operating the part at such
conditions, it is important to consider methods to keep the junction temperature (TJ) below 165 °C to prevent the part exceeding
the thermal foldback temperature threshold (TFB) and limit the current internally.
34931
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
REFERENCE SECTION
REFERENCE SECTION
Table 8. Thermal Analysis Reference Documents
Reference
Description
AN4146
Thermal Modeling and Simulation of 12 V Gen3 eXtreme Switch Devices with SPICE
BASICTHERMALWP
Basic Principles of Thermal Analysis for Semiconductor Systems
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
REFERENCE SECTION
10
Revision History
REVISION
DATE
1.0
7/2013
•
Initial Release based on the MC33931 Data sheet
2.0
10/2013
•
Reduced the sleep mode current specifications
•
•
•
•
•
Updated as per PCN # 16555
Added new part number MC34931SEK with higher slew rate to support PWM frequency up to 20 kHz
Updated the operating voltage up to 36 V (max.) after characterization and testing
Changed the rise/fall time, sleep current, output leakage current, sleep and stand-by current based on test and
characterization data
Added performance curves of key parameters to show operation up to 36 V
7/2015
•
•
Changed the document classification from Advance Information to Technical Data
Corrected typo in Table 1
9/2015
•
Added a column for PWM frequency to Table 1
2/2015
3.0
4.0
DESCRIPTION
34931
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
How to Reach Us:
Information in this document is provided solely to enable system and software implementers to use Freescale products.
Home Page:
freescale.com
There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based
Web Support:
freescale.com/support
Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no
on the information in this document.
warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by
customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.
Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:
freescale.com/SalesTermsandConditions.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their
respective owners.
© 2015 Freescale Semiconductor, Inc.
Document Number: MC34931
Rev. 4.0
9/2015
Similar pages