HI3300 TM Data Sheet March 2000 3V 10-Bit, 20MSPS A/D Converter with Internal Voltage Reference The HI3300 is a monolithic, 10-bit analog-to-digital converter fabricated in an advanced CMOS process. It is designed for high speed applications where integration, bandwidth and accuracy are essential. The HI3300 features a 2-step parallel architecture to allow the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. The HI3300 has excellent dynamic performance while consuming less than 40mW power at 20MSPS. The A/D only requires a single +3.0V power supply. • Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .20MSPS • Low Power at 20MSPS. . . . . . . . . . . . . . . . . . . . . . .40mW • Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3mW • Wide Full Power Input Bandwidth. . . . . . . . . . . . . 100MHz • On-Chip Sample and Hold Amplifiers • Single Supply Voltage Operation . . . . . . . . . .+2.7V - 3.3V Applications • Wireless Local Loop PACKAGE -40 to 85 48 Ld LQFP SAMPLING RATE PKG. NO. (MSPS) Q48.7x7-S 20 • Medical Imaging • Wireless Communications Systems • Battery Powered Instruments Pinout TSTR AVDD TS VIN CAL AVSS AvDD AVSS AVDD AT 48 47 46 45 44 43 42 41 40 39 38 37 36 BE AVSS 4 33 5 32 6 7 31 VRBS VRB VRBC 30 VRMC D5 8 29 D6 D7 9 28 VRTC VRT 10 27 VRTS 11 12 26 AVDD 25 13 14 15 16 17 18 19 20 21 22 23 24 AVSS D4 DVSS DVDD D8 D9 CE 34 OE AVDD AvDD CLK 35 LINV MINV 2 3 AvDD D1 TEST 1 RESET AVSS DO D2 D3 1 DVDD DVSS HI3300 48 LEAD LQFP TOP VIEW TO HI3300IN Features TIN PART NUMBER 4822.1 • PSK and QAM I&Q Demodulators Ordering Information TEMP. RANGE (oC) File Number CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HI3300 Block Diagram S/H AMP VIN 38 VRT 28 + x8 12 D9 COARSE CORRECTION AND LATCH + - VRTC 29 VRTS 27 11 D8 10 D7 9 D6 8 D5 5 D4 4 D3 3 D2 2 D1 1 D0 (LSB) DAC COARSE COMPARATE AND ENCODE VRMC 30 BE 36 FINE FIN3 COMPARATE AND ENCODE FIND LATCH VRBS 33 CALIBRATION UNIT VRB 32 + - 20 MINV VRBC 31 19 LINV 18 TEST MODE CLK 22 TIMING GEN OE 23 CE 24 2 AUTO CALIBRATION PULSE GENERATOR 42 CAL 15 RESET HI3300 Absolute Maximum Ratings Thermal Information Supply Voltage (AVDD) . . . . . . . . . . . . . . . . . . . AVSS -0.5V to 4.5V (DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DVSS -0.5V to 4.5V Reference Voltage (VRT, VRB) . . . . . . . . AVDD +0.5V to AVSS -0.5V Input Voltage (Analog) (VIN) . . . . . . . . . . . . . . AVDD +0.5V to -0.5V Input Voltage (Digital) (VIH, VIL) . . . . . . AVDD +0.5V to AVSS -0.5V Output Voltage (Digital) (VOH, VOL). . . . DVDD +0.5V to DVSS -0.5V Thermal Resistance (Typical, Note 1) θJA (oC/W) 48 Ld LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage Range (AVDD, AVSS) . . . . . . . . . . . . 3.0V to ±0.3V (DVDD, DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to ±0.3V DVSS - AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . 0mV to 100mV Reference Input Voltage (VRB). . . . . . . . . 0.3 AVDD to 0.5 AVDDV (VRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 AVDD to 0.8 AVDDV Analog Input (VIN) . . . . . . . . . . . . . . . . . . . . . . . 0.9 Vp-p or More Clock Pulse Width (tPW1), (tPW0) . . . . . . . . . . . . . . . . 25ns (Min) Operating Ambient Temperature (TOPR) . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. fC = 20MSPS, AVDD = 3V, DVDD = 3V, VRB = 1V, VRT = 2V, TA = 25oC Electrical Specifications PARAMETER SYMBOL CONDITIONS fIN = 1.0kHz Triangular Wave Input MIN. TYP. MAX. UNIT 20 - - MSPS - - 0.5 Maximum Conversion Rate fC max Minimum Conversion Rate fC min Supply Voltage Analog IADD fIN = 1.0kHz Triangular Wave Input - 12 - Digital IDDD BE = High - 1.0 - IAST CE = AVDD - 1.0 - mA - 1.0 - µA - 100 - µA - -100 - - 2 - - -2 - - TBD - MHz - 10 - pF Standby Current Analog Digital IDST Reference Pin Current 1 IRT1 VRTS, VRBS: Open Between VRT and VRB IRB1 Reference Pin Current 2 IRT2 BE = AVDD Between VRTC and VRBC IRB2 Analog Input Band BW Analog Input Capacitance CIN -1dB mA mA Reference Resistance Value 1 RREF1 Between VRTS and VRT, VRT and VRB, VRB and VRBS - 10k - Ω Reference Resistance Value 2 RREF2 Between VRTC and VRBC - 500 - Ω EOT EOT = Theoretical Value - Measured Value - TBD - mV EOB EOB = Measured Value - Theoretical Value - TBD - VIH AVDD = 2.7 to 3.3V 0.7 - - - - 0.2 Offset Voltage Digital Input Voltage VIL Analog Input Current Digital Input Current AIH VIN = 2V - 20 - AIL VIN = 1V - -20 - IIH AVDD = 3.3V VIH - AVDD - - 5 VIL = AVSS - - 5 IIL 3 V µA µA HI3300 fC = 20MSPS, AVDD = 3V, DVDD = 3V, VRB = 1V, VRT = 2V, TA = 25oC (Continued) Electrical Specifications PARAMETER SYMBOL Digital Output Current IOH IOL Digital Output Current IOZH IOZL CONDITIONS MIN. TYP. MAX. UNIT mA OE = AVSS DVDD = 2.7V VOH = DVDD -0.4V 1.0 - - VOL = 0.4V 1.0 - - OE = AVDD DVDD = 3.3V VOH = DVDD - - 1.0 VOL = 0V - - 1.0 µA Three-State Output Disable time tPEZ Clock not Synchronized for Active → High Impedance - 2 - ns Three-State Output Enable Time tPEZ Clock not Synchronized For High Impedance → Active - 2 - ns Integral Nonlinearity Error EL - ±1.0 - LSB Differential Nonlinearity Error ED - ±0.5 - LSB Differential Gain Error DG - TBD - % Differential Phase Error DP - TBD - Deg Output Data Delay tDL - 3 - ns Sampling Delay tSD - 2 - ns SNR SNR fIN = 100kHz - TBD - dB fIN = 500kHz - TBD - dB fIN = 1MHz - TBD - dB fIN = 3MHz - TBD - dB fIN = 7MHz - TBD - dB fIN = 10MHz - TBD - dB fIN = 100kHz - TBD - dB fIN = 500kHz - TBD - dB fIN = 1MHz - TBD - dB fIN = 3MHz - TBD - dB fIN = 7MHz - TBD - dB fIN = 10MHz - TBD - dB SFDR SFDR 4 NTSC 40 IRE Mod Ramp, fC = 14.3MSPS CL = 20pF HI3300 Timing Diagrams tPW0 tPW1 1.5V CLOCK tSD N +1 ANALOG INPUT N N +2 N +3 tDL DATA OUTPUT N -3 N +4 N -1 N -2 N 1.5V NOTE: : Indicates point at which analog data is sampled. FIGURE 1. TIMING CHART 1 tPZE tPEZ 1.5V 1.5V OUTPUT ENABLE (OE) 1.5V DATA OUTPUT ACTIVE HIGH IMPEDANCE FIGURE 2. TIMING CHART 2 5 ACTIVE HI3300 S Pin Description PIN NO. SYMBOL 1 to 5 8 to 12 D0 to D9 EQUIVALENT CIRCUIT DESCRIPTION D0 (LSB) to D9 (MSB) output. DVDD DVSS 6, 48 DVSS Digital Ground. 7, 47 DVDD Digital Power. 13 TO Test signal output. High impedance when TS = high. 14 TIN Test signal input. Normally fixed to AVDD or AVSS . 15 RESET AVDD Calibration circuit reset and startup calibration restart. 15 AVSS 16, 25, 34, 4, 46 AVSS Analog Ground. 17, 21, 26, 35, 40, 43, 45 AVDD Analog Power. 18 TEST MODE AVDD N/C Do not use. 18 AVSS 19 LINV AVDD 19 AVSS 6 Output Inversion. High: D0 to D8 are inverted and output. Low: D0 to D8 are normal output. HI3300 Pin Description (Continued) PIN NO. SYMBOL 20 MINV EQUIVALENT CIRCUIT AVDD DESCRIPTION Output Inversion. High: D9 is inverted and output. Low: D9 is Normal output. 20 AVSS 22 CLK Clock Input. AVDD 22 AVSS 23 OE AVDD D0 to D9 Output Enable. Low: Output Active. High: High Impedance state. 23 AVSS 24 CE AVDD 24 AVSS 7 Chip Enable. Low: Active state. High: Standby state. HI3300 Pin Description (Continued) PIN NO. SYMBOL 27 VRTS 28 VRT 29 VRTC 30 VRMC 31 VRBC 32 EQUIVALENT CIRCUIT Self bias (Reference top). AVDD VRBS 36 BE Reference top. Reference top output. 27 Reference middle output. Reference bottom output. AVSS VRB 33 DESCRIPTION Reference bottom. AVDD Self bias (reference bottom). Bias enable. 28 + - AVSS AVDD 29 AVSS AVDD 30 AVSS AVDD 31 AVSS AVDD 32 + - AVSS AVDD 33 AVSS AVDD 36 AVSS 37 TSTR Test signal input. Tie to AVDD or AVSS . 8 HI3300 Pin Description (Continued) PIN NO. SYMBOL 44 AT 38 VIN EQUIVALENT CIRCUIT DESCRIPTION No Connect Analog input. AVDD 38 AVSS 42 CAL Calibration pulse input. AVDD 42 AVSS 39 TS Test signal input. Normally fixed to AVDD. 9 HI3300 Digital Output The following table shows the correlation between the analog input voltage and the digital output code (TESTMODE = 1, LINV, MINV = 0). TABLE 1. DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE STEP VRT 1023 1111111111 • • • • • • • • • • • • • • • • • • • • 512 1000000000 511 0 1 1 1 1 1 1 11 1 • • • • • • • • 0 0000000000 VRB MSB LSB The following table shows the output state for the combination of TESTMODE, LINV, and MlNV states. TABLE 2. TEST MODE LlNV MlNV D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 1 0 0 P P P P P P P P P P 1 1 0 N N N N N N N N N P 1 0 1 P P P P P P P P P N 1 1 1 N N N N N N N N N N 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 NOTE: P: Forward-phase output; N: Inverted output. 10 HI3300 Application Circuit 1 When not using self-bias and the internal bias circuits and supplying the reference voltage from an external source. 1V 2V AVDD AVDD AVSS 1.0V SIGNAL INPUT AVSS AVDD VRT VRTS VRTC VRBC VRMC VRB VRBS BE 37 TSTR AVSS 2.0V AVDD 36 35 34 33 32 31 30 29 28 27 26 25 AVDD 38 VIN OE 23 39 TS CLK 22 40 AVDD AVDD 21 41 AVSS MINV 20 LINV 19 42 CAL AVDD 1 2 3 4 5 6 7 8 9 10 11 12 RESET PULSE AVSS D9 D7 TO 13 D6 48 DVSS D5 TIN 14 DVDD 47 DVDD DVSS RESET 15 D4 46 AVSS D3 AVSS 16 D2 DVSS AVDD 17 45 AVDD D1 DVDD 44 AT D0 AVSS CLOCK PULSE TESTMODE 18 43 AVDD D8 CALIBRATION PULSE CE 24 : 0.1µF DVSS DVDD POWER SUPPLY DECOUPLERS DIGITAL OUTPUT NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Intersil cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 11 HI3300 Application Circuit 2 When not using self-bias circuit, using only the internal bias circuit, and supplying the reference voltage from an external source. AVDD 1V 2V AVDD AVSS 1.0V SIGNAL INPUT AVSS AVDD VRT VRTS VRTC VRBC VRMC VRB VRBS BE 37 TSTR AVSS 2.0V AVDD 36 35 34 33 32 31 30 29 28 27 26 25 AVDD 38 VIN OE 23 39 TS CLK 22 40 AVDD AVDD 21 41 AVSS MINV 20 LINV 19 42 CAL AVDD 1 2 3 4 5 6 7 8 9 10 11 12 RESET PULSE AVSS D9 D7 TO 13 D6 48 DVSS D5 TIN 14 DVDD 47 DVDD DVSS RESET 15 D4 46 AVSS D3 AVSS 16 D2 DVSS AVDD 17 45 AVDD D1 DVDD 44 AT D0 AVSS CLOCK PULSE TESTMODE 18 43 AVDD D8 CALIBRATION PULSE CE 24 : 0.1µF DVSS DVDD DIGITAL OUTPUT NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Intersil cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 12 HI3300 Application Circuit 3 When not using self bias circuit, using only the internal bias circuit, and supplying the reference voltage from an external source. AVDD AVDD AVSS 1.0V SIGNAL INPUT AVSS AVDD VRT VRTS VRTC VRBC VRMC VRB VRBS BE 37 TSTR AVSS 2.0V AVDD 36 35 34 33 32 31 30 29 28 27 26 25 AVDD 38 VIN OE 23 39 TS CLK 22 40 AVDD AVDD 21 41 AVSS MINV 20 LINV 19 42 CAL AVDD 1 2 3 4 5 6 7 8 9 10 11 12 RESET PULSE AVSS D9 D7 TO 13 D6 48 DVSS D5 TIN 14 DVDD 47 DVDD DVSS RESET 15 D4 46 AVSS D3 AVSS 16 D2 DVSS AVDD 17 45 AVDD D1 DVDD 44 AT D0 AVSS CLOCK PULSE TESTMODE 18 43 AVDD D8 CALIBRATION PULSE CE 24 : 0.1µF DVSS DVDD DIGITAL OUTPUT NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Intersil cannot assume responsibility for any problems arising out of these use of the circuits or for any infringement of third party patent and other right due to same. 13 HI3300 Calibration Function Activating Startup Calibration As shown in the Figure 3, startup calibration must be activated after the supply voltage has risen and stabilized (full scale of 90% or more). After activation, startup calibration is performed for an interval of about 33,000 clocks. Therefore, care should be taken as the output data during this interval (about 2.3ms at 14.3MHz) cannot be used. To achieve superior linearity, the HI3300 has a built-in calibration circuit. Startup calibration must be activated when the power supply and reference voltage have risen and stabilized. Care should be taken as only the upper five bits may be output in the worst case if startup calibration is not activated. Calibration Pulse Supply Startup calibration can be activated either at the rise of the RESET pin (Pin 15) or at the fall of the CE pin (Pin 24). The startup calibration activation method for each case is shown in Figure 3. The IC’s operating status with changes due to fluctuations in the supply voltage and ambient temperature during use can be constantly monitored and then compensated appropriately by inputting a pulse at regular intervals to the CAL pin (Pin 41). Figure 4 shows the timing chart. B. WHEN USING CE A. WHEN USING RESET [V] [V] AVDD VRT VRT VRB VRB 0 0 [t] H RESET CE AVDD 3 3 RESET L [t] H L H H CE L STARTUP CALIBRATION L STARTUP CALIBRATION 33,000 CLK 33,000 CLK FIGURE 3. STARTUP CALIBRATION ACTIVATION METHODS 10ns OR MORE 7CLOCK CLK 1CLOCK OR MORE CAL D0 TO D9 N-3 N-2 N-1 FIGURE 4. CALIBRATION TIMING CHART 14 N N +5 HI3300 Calibration starts when the fall of the pulse input to the CAL pin (Pin 41) is detected at the clock rise. At this time, the comparator is used in an exclusive manner for a four clock interval. So, the output data holds the immediately previous data for a four clock interval after seven clocks from the rise of the clock where the fall of the calibration pulse was detected, and then the data during this interval is missing. Therefore, the effects of this function can be avoided by inputting a sync or other signal as the calibration pulse so that calibration is performed outside of the interval of the actually used video signal. An input example is shown below. Input ever H Sync INPUT CLK CAL Input ever V Sync INPUT CLK RESET CAL Latch-up Board Ensure that the AVDD and DVDD pins share the same power supply on a board to prevent latch-up which may be caused by power-ON time lag. To obtain full-expected performance from this IC, be sure that the mounting board has a large ground pattern for lower impedance. It is recommended that the IC be mounted on a board without using a socket to evaluate its characteristics adequately. 15 HI3300 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D Q48.7x7-S D1 48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES E E1 e MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.056 0.066 1.40 1.70 - A1 0.000 0.007 0.00 0.20 - B 0.006 0.010 0.15 0.26 5 D 0.347 0.362 8.80 9.20 2 D1 0.272 0.279 6.90 7.10 3, 4 E 0.347 0.362 8.80 9.20 2 E1 0.272 0.279 6.90 7.10 3, 4 L 0.012 0.027 0.30 0.70 N 48 48 e 0.020 BSC 0.500 BSC 6 Rev. 1 4/95 PIN 1 NOTES: -H- SEATING PLANE A 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . 0.10 0.004 -C- 0.24 M B 3. Dimensions D1 and E1 to be determined at datum plane -H- . 4. Dimensions D1 and E1 do not include mold protrusion. 5. Dimension B does not include dambar protrusion. 6. “N” is the number of terminal positions. A1 0o-10o L 0.107/0.177 0.004/0.007 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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