A8724 Datasheet

A8724
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: December 10, 2012
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A8724
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
Features and Benefits
Description
▪ Wide battery voltage range: 1.5 to 11 V
▪ Low quiescent current draw (1 μA max in shutdown mode)
▪ Flexible current limit:
▫ External resistor sets default current (0.7 to 1.5 A)
▫ Optional single-wire current limit programming through
CHARGE pin
▪ Rugged and compact design:
▫ Integrated 55 V DMOS switch
▫ No feedback resistors
▫ ISET open/short protection
▫ Open diode/secondary winding protection
▫ 3 mm × 3 mm footprint
▪ Charge Complete indication
▪ Flexible IGBT driver with separate sink and source
The A8724 provides a robust Xenon photoflash solution for a
wide range of cameras. Its wide battery voltage specifications
allow designers to use a common device for camera using 2 or 4
cell Alkaline batteries as well as 1 or 2 cell Lithium ion batteries.
Its 55V rated integrated power switch provides ample design
margin, even for the 2 cell Lithium ion battery designs.
Applications
▪ Digital and film camera flash
▪ Digital video camera flash
Package: 10-contact TDFN (suffix EJ)
The A8724 detects the output voltage on the primary side
and it eliminates the external feedback resistors. If the output
diode or the secondary winding are disconnected, it prevents
the output capacitor from being overcharged.
The A8724 features a flexible current limit scheme. The current
limit is set by an external resistor at ISET, allowing designers
to optimize the camera performance. The A8724 is protected
against open circuit and short circuit condition on the ISET pin.
Once the current limit is set, it can be optionally programmed as
a percentage of the set current through a single wire interface,
through the CHARGE pin.
The A8724 features an integrated flexible IGBT gate driver,
with independent source and sink pins.
The A8724 is available in a 10-contact 3 mm × 3 mm TDFN
package. This small, low profile (0.75 mm) package is ideal
for space-constrained applications. It is lead (Pb) free, with
100% matte-tin leadframe plating.
Approximate size
Typical Applications
1 : 10
1 : 10
Battery Input +
1.5 to 11 V
3 to 5.5 V VIN
Battery Input +
1.5 to 11 V
C1
COUT
VBAT
3 to 5.5 V VIN
VOUT Detect
SW
C2
VOUT Detect
SW
C2
Control
Block
ISW sense
Decoder
ON
DONE
ON/
OFF
CHARGE
20 kΩ
GND
Figure 1a. Current set by RSET
ISW sense
DONE
DONE
RSET
IGBTSRC
OFF
IGBT DRV
VIN
100 kΩ
ILIM
Setting
Decoder
VIN
IGBT Driver
TRIGGER
A8724-DS, Rev. 2
ISET
DONE
RSET
OFF
Block
VIN
100 kΩ
ILIM
Setting
COUT
VBAT
Control
ISET
C1
ON/
OFF
ON CHARGE
TRIGGER
VIN
IGBT Driver
IGBTSINK
20 kΩ
GND
Figure 1b. Current programmed by CHARGE pin
IGBTSRC
IGBTSINK
IGBT DRV
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
Selection Guide
Part Number
A8724EEJTR-T
Package
Packing
10-contact TDFN
Tape and reel, 1500 pieces per reel
*Contact Allegro for additional ordering information.
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
V
SW Pin
VSW
–0.3 to 55
VBAT Pin
VBAT
–0.3 to 12
VIN Pin
VIN
–0.3 to 6.0
V
–0.6 to VIN + 0.3
V
–40 to 85
ºC
Remaining Pins
VI
Care should be taken to limit the current when
–0.6 V is applied to these pins.
Operating Ambient Temperature
TA
Range E
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Value
Units
45
ºC/W
Storage Temperature
Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
On 4-layer PCB based on JEDEC standard
*Additional thermal information available on the Allegro website
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
Functional Block Diagram
VIN
VBAT
ISET
SW
VSW – VBAT
DCM
Detector
toff(max)
ISET Buffer
VDSref
Control Logic
DMOS
13 μs
HmL
Triggered Timer
OCP
S
Q
R
Q
ton(max)
13 μs
Decoder
Enable
S
Q
R
Q
DONE
CHARGE
VIN
IGBT Driver
IGBTSRC
TRIGGER
IGBTSINK
GND
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
ELECTRICAL CHARACTERISTICS Valid at VIN = VBAT = 3.6 V, RSET = 22.6 kΩ, TA = 25°C except
guaranteed from −40°C to 85°C ambient, unless otherwise specified
Characteristics
VIN Voltage Range1
VBAT Pin Voltage Range1
UVLO Enable Threshold
UVLO Hysteresis
Supply Current
Symbol
Min
Typ
Max
Unit
VIN
3
–
5.5
V
VBAT
1.5
–
11
V
2.55
2.65
2.80
V
–
150
–
mV
Shutdown (CHARGE = 0 V, TRIGGER = 0 V)
–
0.01
1
μA
Charging done (CHARGE = VIN, DONE = 0 V)
–
10
50
μA
VINUV
VIN rising through threshold
VINUVhys
IIN
VBAT Pin Supply Current
Test Conditions
indicates specifications
IBAT
Charging (CHARGE = VIN, TRIGGER = 0 V)
–
2
–
mA
Shutdown (CHARGE = 0 V, TRIGGER = 0 V)
–
0.01
1
μA
Charging done (CHARGE = VIN, DONE = 0 V)
–
–
1
μA
Charging (CHARGE = VIN, TRIGGER = 0 V)
–
–
50
μA
Current Limits
Switch Current Limit
ILIM / ISET Current Ratio
ISET Pin Voltage While Charging
Switch Current Limit (ILIM
Programming Input on CHARGE Pin)
Switch On-Resistance
Switch Leakage
Current1
TRIGGER and CHARGE Input
Current
1.35
1.5
1.65
A
ILIM / ISET
ILIM
100% setting
CHARGE = high, 100% setting
–
27.8
–
kA/A
VSET
CHARGE = high, 100% setting
–
1.2
–
V
ISWlim1
Default setting
–
100
–
%
ISWlim2
One pulse applied to CHARGE pin
–
93
–
%
ISWlim3
Two pulses applied to CHARGE pin
–
86
–
%
ISWlim4
Three pulses applied to CHARGE pin
–
79
–
%
ISWlim5
Four pulses applied to CHARGE pin
–
71
–
%
ISWlim6
Five pulses applied to CHARGE pin
–
64
–
%
ISWlim7
Six pulses applied to CHARGE pin
–
57
–
%
ISWlim8
Seven pulses applied to CHARGE pin
–
50
–
%
RDS(on)
ISW = 800 mA
–
0.35
–
Ω
VSW = 11 V, in shutdown
–
–
1
μA
VCHARGE = VTRIGGER = VIN
–
36
–
μA
ISWlk
ICHARGE,
ITRIGGER
TRIGGER and CHARGE Input
Voltage High1
VCHARGE(H),
Over VIN supply range
VTRIGGER(H)
1.2
–
–
V
TRIGGER and CHARGE Input
Voltage Low1
VCHARGE(L),
Over VIN supply range
VTRIGGER(L)
–
–
0.4
V
Continued on the next page…
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
ELECTRICAL CHARACTERISTICS (continued) Valid at VIN = VBAT = 3.6 V, RSET = 22.6 kΩ, TA = 25°C except
indicates
specifications guaranteed from −40°C to 85°C ambient, unless otherwise specified
Characteristics
Symbol
Min
Typ
Max
Unit
Initial pulse
15
–
–
μs
Subsequent pulses
0.2
–
–
μs
tILIM(L)
0.2
–
–
μs
tILIM(SU)
–
45
–
μs
Switch-Off Timeout
toff
–
13
–
μs
Switch-On Timeout
ton
–
13
–
μs
ILIM Programming High Time at
CHARGE Pin2
ILIM Programming Low Time at
CHARGE Pin2
Total ILIM Setup Time at
CHARGE Pin2
tILIM(H)init
Test Conditions
tILIM(H)
¯N̄¯Ē¯ Output Leakage Current1
D̄¯Ō
IDONElk
¯N̄¯Ē¯ Output Low Voltage1
D̄¯Ō
VDONEL
Output Comparator Trip Voltage1
Output Comparator Overdrive
VOUTTRIP
VOUTOV
dV/dt Threshold of ZVS Comparator
dV/dt
–
–
1
μA
¯N̄¯Ē¯ pin
32 μA into D̄¯Ō
–
–
100
mV
Measured as VSW – VBAT
31
31.5
32
V
200 ns pulse width (90% to 90% points)
–
200
400
mV
Measured at SW node
–
20
–
V/μs
–
6
–
Ω
IGBT Driver
IBGTSRC Resistance to VIN
RIGBTSRC
VIGBTSRC = 1.8 V
IBGTSNK Resistance to GND
RIGBTSNK
VIGBTSNK = 1.8 V
Propagation Delay (Rising)3
tdr
Propagation Delay (Falling)3
tdf
Output Rise
Time3
tr
Output Fall Time3
IGBTSRC and IGBTSNK connected together,
measurement taken at pin; RGATE = 12 Ω,
CLOAD = 6500 pF
tf
–
24
–
Ω
–
16
–
ns
–
50
–
ns
–
80
–
ns
–
320
–
ns
1Specification
over the range TA = –40°C to 85°C guaranteed by design and characterization.
figure 6 timing diagram for further explanation.
3See figure 2 timing diagram for further explanation.
2See
TRIGGER
50%
50%
tdr
IGBTSRC,
IGBTSINK
tr
tdf
90%
10%
tf
90%
10%
IGBTSRC and IGBTSINK connected together
Figure 2. IGBT Drive Timing Definition
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
Operation Timing Diagram
VIN
UVLO
CHARGE
SW
Target VOUT
VOUT
DONE
T2
T1
T3
TRIGGER
IGBTDRV
A
B
C
D
E
F
Explanation of Events
A: Start charging by pulling CHARGE to high, provided that VIN is above UVLO level.
B: Charging stops when VOUT reaches the target voltage.
C: Start a new charging process with a low-to-high transition at the CHARGE pin.
D: Pull CHARGE to low to put the controller in low-power standby mode.
E: Charging does not start, because VIN is below UVLO level when CHARGE goes high.
F: After VIN goes above UVLO , another low-to-high transition at the CHARGE pin is required to
start the charging.
T1, T2, T3 (Trigger instances): IGBT driver output pulled high whenever the TRIGGER pin is at
logic high. It is recommended to avoid applying any trigger pulses during charging.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
Pin-out Diagram
VIN
1
IGBTSRC
2
10 ISET
PAD
9
DONE
IGBTSINK
3
8
CHARGE
TRIGGER
4
7
VBAT
GND
5
6
SW
(Top View)
Terminal List Table
Number
Name
Function
1
VIN
Input voltage. Connect to 3 to 5.5 V bias supply. Decouple VIN voltage with
0.1 μF ceramic capacitor placed close to this pin.
2
IGBTSRC
IGBT gate drive source output.
3
IGBTSINK
IGBT gate drive sink output.
4
TRIGGER
IGBT trigger input.
5
GND
Ground connection.
6
SW
7
VBAT
8
CHARGE
Charge enable and current limit serial programming pin. Set this pin low to
shut down the chip.
9
¯N̄¯Ē¯
D̄¯Ō
Open collector output, pulls low when output reaches target value and
CHARGE is high. Goes high during charging or whenever CHARGE is low.
10
ISET
Connect an external resistor to GND to set default peak switch current limit.
–
PAD
Exposed pad for enhanced thermal dissipation. Connect to ground plane.
Drain connection of internal DMOS switch. Connect to transformer primary
winding.
Battery voltage.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
Characteristic Performance
IGBTSRC and IGBTSINK connected together and IGBT Drive waveforms
are measured at pin with R-C load (12 Ω, 6800 pF).
IGBT Drive Performance
tr
Rising Signal
VIN
Symbol
C1
C2
C3
t
Conditions
Parameter
VTRIGGER
VGATE
VIN
time
Parameter
tDr
tr
CLOAD
Rgate
Units/Division
1V
1V
1V
50 ns
Value
16 ns
81.5 ns
6.8 nF
12 Ω
C2,C3
VGATE
C1
VTRIGGER
t
tf
Falling Signal
VIN
Symbol
C1
C2
C3
t
Conditions
Parameter
VTRIGGER
VGATE
VIN
time
Parameter
tDr
tr
CLOAD
Rgate
Units/Division
1V
1V
1V
50 ns
Value
46 ns
342 ns
6.8 nF
12 Ω
VGATE
C2,C3
VTRIGGER
C1
t
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
Charge Time versus Battery Voltage
Transformer LP = 12.8 μH, N = 10.25, VIN = 3.6 V, COUT = 100 μF, RISET = 22.6 kΩ, , TA ≈ 25°C
Time (s)
10
9
ILIM
Step
ILIM
(A)
8
8
0.75
7
7
0.85
6
5
4
3
2
6
0.95
5
1.1
4
1.2
3
1.3
2
1.4
1
1.5
1
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
VBAT (V)
Output voltage is sensed from the primary side winding when the switch turns off. This
duration, toff , has to be long enough (>200 ns) in order to obtain an accurate measurement
(see Final Output Voltage versus Secondary Side Conduction Time chart).
Final Output Voltage versus Secondary Side Conduction Time
Transformer LP = 12.8 μH, N = 10.25, VIN = 3.6 V, COUT = 100 μF, RISET = 22.6 kΩ, , TA ≈ 25°C
328
327
VOUT (V)
326
325
324
323
322
250
300
350
400
450
500
550
toff (ns)
The value of toff depends on ISWlim, primary inductance, LPrimary , and turns ratio,
N, as given by: toff = (ISWlim × LPrimary × N) / VOUT .
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
Final Output Voltage versus Battery Voltage
Transformer LP = 12.8 μH, N = 10.25, VIN = 3.6 V, COUT = 100 μF, RISET = 22.6 kΩ, , TA ≈ 25°C
328
ILIM
Step
327
8
7
VOUT (V)
326
6
5
325
4
324
3
2
323
1
322
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
VBAT (V)
Efficiency versus Battery Voltage
Transformer LP = 12.8 μH, N = 10.25, VIN = 3.6 V, COUT = 100 μF, RISET = 22.6 kΩ, , TA ≈ 25°C
86
84
82
Efficiency (%)
A8724
80
ILIM
Step
78
8
76
7
74
6
72
5
70
4
68
3
66
2
64
1
62
60
58
56
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
VBAT (V)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
Average Input Current versus Battery Voltage
Transformer LP = 12.8 μH, N = 10.25, VIN = 3.6 V, RISET = 22.6 kΩ, , TA ≈ 25°C
0.6
0.5
IIN(av) (A)
A8724
0.4
0.3
0.2
ILIM
Step
1
ILIM
(A)
1.5
2
1.4
3
1.3
4
1.2
5
1.1
6
0.95
7
0.85
8
0.75
0.1
1
2
3
4
5
6
7
8
9
10
11
VBAT (V)
Note: Peak switch current is limited by maximum on-time and di/dt of transformer
primary current; therefore, average current drops at very low battery voltage.
ILIM versus ILIM Steps at Various VIN
Transformer LP = 12.8 μH, N = 10.25, VIN = 3.6 V, COUT = 100 μF, RISET = 22.6 kΩ, , TA ≈ 25°C
1.7
1.6
1.5
1.4
VIN (V)
1.3
1.2
3.0
3.6
1.1
5.0
1.0
0.9
0.8
0.7
1
2
3
4
5
6
7
8
ILIM Step
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A8724
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
VOUT Charging at Various VBAT
VIN = 3.6 V, COUT = 100 μF, ISWlim = 1.2 A
VOUT
VOUT
IIN
IIN
VBAT = 11 V. C1, VOUT 100 V/div; C4, IIN(av) 200 mA/div; Time 500 ms/div.
VBAT = 7.2 V. C1, VOUT 100 V/div; C4, IIN(av) 200 mA/div; Time 500 ms/div.
VOUT
VOUT
IIN
IIN
VBAT = 3.6 V. C1, VOUT 100 V/div, C4; IIN(av) 200 mA/div; Time 1s/div.
VBAT = 2 V. C1, VOUT 100 V/div; C4, IIN(av) 200 mA/div; Time 1s/div.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A8724
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
Functional Description
Overview
The A8724 integrates a flyback converter and an IGBT gate
driver to provide a compact solution for Xenon flash applications.
The charging operation of the A8724 is started by a low-to-high
signal on the CHARGE pin, provided that VIN is above VUVLO
level. It is strongly recommended to keep the CHARGE pin at
logic low during power-up. After VIN exceeds the UVLO level, a
low-to-high transition on the CHARGE pin is required to start the
charging.
Toggling the CHARGE pin reinitiates the charging operation.
The A8724 implements an adaptive off-time, toff, control. After
the switch is turned off, a sensing circuit tracks the flyback voltage at the SW node. A proprietary dV/dt detection circuit is used
to allow minimum-voltage switching, even if the SW voltage
does not drop to zero volts. This enables fast-charging to start
earlier, thereby reducing the overall charging time.
The A8724 senses output voltage indirectly on the primary side.
The flyback converter stops switching when output voltage
reaches:
VOUT = K × N – Vd ,
where:
K = 31.5 typically,
Vd is the forward drop of the output diode (around 2 V), and
N is transformer turns ratio.
Switch On-Time and Off-Time Control
The A8724 implements an adaptive on-time/off-time control. Ontime duration, ton , is equal to ton = ISWlim × LP / VBAT. Off-time
duration, toff , depends on the operating conditions during switch
off-time. The A8724 applies its two charging modes, Fast Charging mode and Timer mode, according to those conditions.
Timer Mode and Fast Charging Mode
The A8724 achieves fast charging times and high efficiency by
operating in discontinuous conduction mode (DCM) through
most of the charging process The relationship of Timer mode and
Fast Charging mode is shown in figure 3.
The IC operates in Timer mode when beginning to charge a completely discharged photoflash capacitor, usually when the output
voltage, VOUT, is less than approximately 15 to 20 V. Timer mode
is a fixed period, 13 μs, off-time control. One advantage of having Timer mode is that it limits the initial battery current surge
and thus acts as a “soft-start.” A time-expanded view of a Timer
mode interval is shown in figure 4.
During Fast-Charging mode, when VOUT is high enough (over
50 V), true zero-voltage switching (ZVS) is achieved. This
further improves efficiency as well as reduces switching noise. A
ZVS interval is shown in figure 5.
Switch Current Limit Setting The peak switch current limit is
set through a resistor RSET connected between the ISET pin and
VOUT
Timer Mode
Fast Charging Mode
VBAT
IIN
Figure 3. Timer mode and Fast Charging mode: t = 200 ms/div;
VOUT = 50 V/div; VBAT = 1 V/div.; IIN = 100 mA/div., VBAT = 3.6 V;
COUT = 20 μF / 330 V; and ISWlim ≈ 0.75 A.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
GND. The value of RSET can be between 22.6 and 48 kΩ, setting
the peak switch current from 1.5 to 0.7 A. Select the value for the
RSET resistor as:
RSET = 1.2 × 27800 / ILIM ,
where:
VOUT
VSW
ILIM is the target current limit, in A,
RSET is in Ω.
The resistor sets the 100% current level, ILIM, which can be programmed by applying pulses on the CHARGE pin.
The peak current limit can be programmed to eight different levels, from 100% to 50%, with a 7% decrement per programming
step on charge pin. An internal digital circuit decodes the input
clock signals, which sets the switch current limit. This flexible
scheme allows the user to operate the A8724 according to different battery input voltages. The battery life can be effectively
extended by setting a lower current limit at low battery voltages.
Figure 6 shows the ILIM clock timing scheme protocol. The
total ILIM setup time, tILIM(SU) , denotes the time needed for the
decoder circuit to receive ILIM inputs and set ISWLIM , and has a
typical duration of 45 μs (minimum 40 μs).
Figure 7 shows the timing definition of the primary current
limiting circuit. At the end of the setup period, tILIM(SU) , primary
current starts to ramp up to the set ISWLIM. The ISWLIM setting
remains in effect as long as the CHARGE pin is high. To reset the
ILIM decoder, pull the CHARGE pin low before clocking in the
new setting.
After the first start-up or an ILIM decoder reset, each new current
limit can be set by sending a burst of pulses to the CHARGE pin.
The first rising edge starts the ILIM decoder, and up to 8 rising edges will be counted to set the ISWLIM level. The first pulse
width, tILIM1(H), must be at least 15 μs long. Subsequent pulses
(up to 7 more) can be as short as 0.2 μs. The last low-to-high
edge must arrive within 40 μs from the first edge. The CHARGE
pin will stay high afterwards.
ISW
Figure 4. Expanded view of Timer Mode, VBAT = 3.6 V, ISWlim = 1.2 A.
C2, VSW = 2 V/div; C3, VOUT = 50 V/div; C4, ISW = 500 mA/div;
Time = 2 μs/div.
VSW
VOUT
ISW
Figure 5. Zero-Voltage Switching (ZVS) VBAT = 3.6 V, ISWlim = 1.2 A.
C2, VSW = 2 V/ div; C3, VOUT = 50 V; C4, ISW = 500 mA/div;
Time = 0.5 μs/div.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
tILIM(H) ≥ 0.2 μs
tILIM(L) ≥ 0.2 μs
Clock input at
CHARGE pin
tILIM(H) =
first pulse width
tILIM(SU) =
ILIM setup time
First rising edge
0 μs
Subsequent rising edges
(0 to 7)
15 μs
Switching
starts
40 μs
Figure 6. ILIM Program Timing Definition
Start ILIM counter
Reset ILIM counter
CHARGE
4 rising edges
within tILIM(SU)
ISWLIM = 1.05 A
ISW
Switching
starts
0 μs
15 μs
Switching
stops
40 μs
Figure 7. Current Limit Programming Example (Iswlim4 selected)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
A8724
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
Smart Current Limit (Optional)
Current limit reduction with VBAT The switch peak current
limit can be varied according to the battery voltage, as shown in
figure 8.
For example, ISET current is normally set to 54 μA (ILIM = 1.5
A). When the battery voltage drops below 2.5 V, a BL (batterylow) signal from external controller goes high. A resistor connecting from BL to ISET pin then injects 15 μA into RSET. This
effectively reduces ISET current to 39 μA (for ILIM = 1.08 A).
IGBT Driver Application
The integrated IGBT driver is used to drive external flash trigger
IGBT. Separate IGBTSRC and IGBTSNK pins allow the user to
adjust IGBT turn-on and turn-off rise times. IGBT drive timing is
defined when these pins are connected together supplying a load
comprising 12 Ω resistor and a 6500 pF capacitor. These pins can
be connected together to use a single resistor drive.
Open Secondary Protection
The A8724 is protected against open secondary winding or
secondary diode. When a secondary diode or winding is open, the
energy stored in the transformer during on-time generates voltage at the SW pin greater than VOUTTRIP +VBAT. Internal DMOS
clamp the voltage and dissipate energy for one cycle. Internal
switch stops switching and the D̄¯Ō¯N̄¯Ē¯ pin is pulled low as shown
in figure 9.
VCHARGE
VDONE
VSW
ISW
Figure 8. Optional Smart Current Limit configuration
Figure 9. Operation under open diode fault (ISWlim = 1.5 A, VBAT = 3.6 V,
¯N̄¯Ē¯
Lprimary = 12.8 μH). C1, VCHARGE, 5 V/div; C2, VSW 10 V/div; C3, D̄¯Ō
5 V/div; C4, ISW 500 mA/div; Time, 10 μs/div.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
Application Information
toff = (ISWlim / N) × LS /VOUT
Transformer Design
1. The transformer turns ratio, N, determines the output voltage:
N = NS / NP
VOUT = 31.5 × N – Vd ,
where 31.5 is the typical value of VOUTTRIP , and Vd is the forward drop of the output diode.
2. The primary inductance, LPrimary , determines the on-time of
the switch:
ton = (–LP rimary/ R ) × ln (1 – ISWlim × R /VIN) ,
where R is the total resistance in the primary current path (including RSWDS(on) and the DC resistance of the transformer).
If VIN is much larger than ISWlim × R, then ton can be approximated by:
ton = ISWlim × LP /VIN .
3. The secondary inductance, LS, determines the off-time of the
switch. Given:
LS / LPrimary = N × N , then
ton
= (ISWlim × LPrimary × N) /VOUT .
The minimum pulse width for toff determines what is the minimum LPrimary required for the transformer. For example, if
ISWlim = 0.7 A, N = 10, and VOUT = 315 V, then LPrimary must be
at least 9 μH in order to keep toff at 200 ns or longer. These relationships are illustrated in figure 10.
In general, choosing a transformer with a larger LPrimary results in
higher efficiency (because a larger LPrimary means lower switch
frequency and hence lower switching loss). But transformers with
a larger LPrimary also require more windings and larger magnetic
cores. Therefore, a trade-off must be made between transformer
size and efficiency.
Leakage Inductance and Secondary Capacitance
The transformer design should minimize the leakage inductance
to ensure the turn-off voltage spike at the SW node does not
exceed the 55 V limit. An achievable minimum leakage inductance for this application, however, is usually compromised by
an increase in parasitic capacitance. Furthermore, the transformer
secondary capacitance should be minimized. Any secondary
toff
VSW
ISW
Vr
tf
VIN
VIN
VSW
ISW
tneg
Figure 10. Transformer Selection Relationships
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17
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
capacitance is multiplied by N2 when reflected to the primary,
leading to high initial current swings when the switch turns on,
and to reduced efficiency.
Input Capacitor Selection
Ceramic capacitors with X5R or X7R dielectrics are recommended for the input capacitor, C1. During initial timer mode the
device operates with 13 μs off-time. A typical input section for a
photoflash module with input filter inductor, or a test setup with
long connecting wires is shown in figure 11. The resonant period
caused by input filter inductor and capacitor should be at least
2 times greater or smaller than the 13 μs timer period, to reduce
input ripple current during this period. Effect of input capacitor is
shown in figures 12 and 13.
The resonant period is given by:
Tres = 2 ×
× (LIN × C1)½
It is recommended to use at least 4.7 μF / 6.3 V to decouple the
battery input, VBAT, at the primary of the transformer. Decouple
the VIN pin using a 0.1 μF / 6.3 V bypass capacitor.
VOUT
VBAT
IBAT
Figure 12. Input current waveforms with Li+ battery connected by 5-in. wire
and decoupled by 4.7 μF capacitor. C1, VOUT 100 V/div; C3, VBAT
2 V/div; C4, IBAT 500 mA/div; Time, 50 ms/div.
VOUT
VBAT
IBAT
LIN
+
VBAT
C1
A8724
Figure 13. Input current waveforms with Li+ battery connected through
10 μH inductor and 4.7 μF capacitor. C1, VOUT 100 V/div; C3, VBAT 2 V/div;
C4, IBAT 200 mA/div; Time, 50 ms/div.
VOUT
Figure 11. Typical input section with input inductance
(inductance, LIN, may be an input filter inductor or
inductance due to long wires in test setup)
VBAT
IBAT
Figure 14. Input current waveforms with Li+ battery connected through
10 μH inductor and 10 μF capacitor. C1, VOUT 100 V/div; C3, VBAT 2 V/div;
C4, IBAT 200 mA/div; Time, 50 ms/div.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
A8724
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
Output Diode Selection
Choose the rectifying diode(s), D1, to have small parasitic capacitance (short reverse recovery time) while satisfying the reverse
voltage and forward current requirements. The peak reverse
voltage of the diode, VD_Peak , occurs when the internal MOSFET
switch is closed. It can be calculated as:
VD_Peak = VOUT + N × VBAT
The peak current of the rectifying diode, ID_Peak, is calculated
as:
ID_Peak = IPrimary_Peak / N
Layout Guidelines
Key to a good layout for the photoflash capacitor charger circuit
is to keep the parasitics minimized on the power switch loop
(transformer primary side) and the rectifier loop (secondary side).
Use short, thick traces for connections to the transformer primary
¯ signal trace and other
and SW pin. It is important that the D̄¯¯ Ō¯¯N̄¯Ē
signal traces be routed away from the transformer and other
switching traces, in order to minimize noise pickup. In addition,
high voltage isolation rules must be followed carefully to avoid
breakdown failure of the circuit board.
Avoid locating the ground plane underneath transformer secondary and diode to minimize parasitic capacitance.
For low threshold logic (<1.3 V) add 1 nF capacitors across the
CHARGE and TRIGGER pins to GND to avoid malfunction due
to noise. Refer to the figures on the next page for recommended
layout.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
19
A8724
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
Recommended Layout
VIN
VBAT
D1
T1
+
C2
1
9
8
4
VBAT
SW
DONE
CHARGE
IGBTSRC
PAD
IGBTSINK
ISET
TRIGGER
GND
Xenon+
R1
150 kΩ
T2
7
VIN
Schematic
COUT
100 μF
C1
C3
22 nF
630 V
6
2
RIGBTSRC
Q1
3
10
Xenon
Trigger
RIGBTSINK
Xenon–
RSET
5
Top side
Bottom side
Top components
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
20
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
Package EJ 10-Contact TDFN
with Exposed Thermal Pad
0.30
3.00 ±0.15
0.85
0.50
10
10
3.00 ±0.15
1.65
3.10
A
1
2
1
11X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
C
C
For Reference Only; Not for tooling use
(Reference DWG 2860)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
2
0.40 ±0.10
+0.10
1.65 –0.15
B
10
+0.10
2.38 –0.15
PCB Layout Reference View
0.75 ±0.05
0.5 BSC
1
2.38
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference
IPC7351 SON50P300X300X80-11WEED3M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21
Photoflash Capacitor Charger with Primary Side Sensing,
Flexible Current Limit, and 55 V Power DMOS Switch
A8724
Revision History
Revision
Revision Date
Rev. 2
April 19, 2012
Description of Revision
Miscellaneous format changes
Copyright ©2008-2012, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
22
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