HS-6564RH S I GN D ES W NE at F O R or D E H nter c D e R N 7 C /ts ME 564 or t COM ee HS-6 al Supp rsil.com E R S ic .inte NOT chn r Te or w w w u o 8K SI L tact con -INTER 8 1-88 ® September 1997 Features Radiation Hardened x 8, 16K x 4 CMOS RAM Module Pinout • Radiation Hardened EPI CMOS - Total Dose 1 x 105 RAD (Si) - Transient Upset > 1 x 108 RAD (Si)/s - Latch-Up Free to > 1 x 1012 RAD (Si)/s • Low Power Standby 4.4mW Maximum • Low Power Operation 308mW/MHz Maximum • Data Retention 3.0V Minimum • TTL Compatible In/Out • Three State Outputs • Fast Access Time 250ns Maximum • Military Temperature Range -55oC to +125oC • On Chip Address Registers • Organizable 8K x 8 or 16K x 4 • 40 Pin DIP Pinout 2.000" x 0.900" HS5-6564RH 40 PIN CERAMIC MODULE INTERNAL PACKAGE CODE “HSQ” TOP VIEW 39 Q0 D4 3 38 D0 Q5 4 D5 5 37 Q1 36 D1 A0 6 35 A6 A1 7 34 A7 A2 8 33 A9 E3 9 32 E1 31 W1 30 W1* W2 11 The HS-6564RH is a radiation hardened 64K bit, synchronous CMOS RAM module. It consists of 16 HS-6504RH 4K x 1 radiation hardened CMOS RAMs, in leadless carriers, mounted on a ceramic substrate. The individual RAMs are fabricated using the Intersil radiation hardened guard ring, self-aligned silicon gate technology. The HS-6564RH is configured as an extra wide, standard length 40 pin DIP. The memory appears to the system as an array of 16 4K x 1 static RAMs. The array is organized as two 8K by 4 blocks of RAM sharing only the address bus. The data inputs, data outputs, chip enables and write enables are seperate for each block of RAM. This allows the user to organize the HS-6564RH RAM as either an 8K by 8 or a 16K by 4 array. This 64K memory provides a unique blend of low power CMOS semiconductor technology and advanced packaging techniques. The HS-6564RH is intended for use in radiation environments where a large amount of RAM is needed, and where power consumption and board space are prime concerns. On-chip latches are provided for addresses, data input and data output allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance for use in expanded memory arrays. The guaranteed low voltage data retention characteristics allow easy implementation of non-volatile readswrite memory by using very small batteries mounted directly on the memory circuit board. Functional Diagram Q4 2 *W2 10 Description A W1 E1 40 VDD* *GND 1 E4 12 29 E2 A11 13 A10 14 28 A3 A9 15 27 A2 26 A5 D6 16 25 D2 Q6 17 24 Q2 D7 18 23 D3 Q7 19 22 Q3 21 GND* *VDD 20 * Pins 20 and 40 (VDD) are internally connected. Similarly pins 1 and 21 (Ground) are connected. The user is advised to connect both VDD pins and both Ground pins to the board busses. This will improve power distribution across the array and will enhance decoupling. Pin 10 is internally connected to pin 11, and pin 30 is connected to pin 31. For those users wishing to preserve board compatibility with possible future RAM arrays, we recommend connections to the write lines be made at pins 11 and 31, leaving pins 10 and 30 free for future expansion. 12 A W EDQ E2 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 W2 E3 E4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 8-449 File Number 3032.1 Specifications HS-6564RH Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3.0V to +7.0V Input or Output Voltage Applied . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC Typical Derating Factor . . . . . . . . . . 48mA/MHz Increase in IDDOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θja θjc 40 Pin Ceramic Module Package . . . . . . TBD TBD Maximum Package Power Dissipation at +125oC 40 Pin Ceramic Module Package . . . . . . . . . . . . . . . . . . . . . .TBD Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53,336 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Supply Voltage Range . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Standby Supply Current SYMBOL IDDSB CONDITIONS MIN MAX UNITS IO = 0, VI = GND or VDD - 1600 µA Operating Supply Current (8K x 8) (Note 1) IDDOP1 f = 1MHz, IO = 0 VI = VDD or GND - 56 mA Operating Supply Current (16K x 4) (Note 1) IDDOP2 f = 1MHz, IO = 0 VI = VDD or GND - 28 mA Data Retention Supply Current IDDDR IO = 0, VDD = 3.0 VI = VDD or GND - 1200 µA Data Retention Supply Current VDDDR 3.0 - V Address Input Leakage IIA GND ≤ VI ≤ VDD -20 +20 µA Data Input Leakage (8K x 8) IID1 GND ≤ VI ≤ VDD -3 +3 µA Data Input Leakage (16K x 4) IID2 GND ≤ VI ≤ VDD -5 +5 µA Enable Input Leakage (8K x 8) IIE1 GND ≤ VI ≤ VDD -10 +10 µA Enable Input Leakage (16K x 4) IIE2 GND ≤ VI ≤ VDD -5 +5 µA Write Enable Input Leakage (Each) IIW GND ≤ VI ≤ VDD -10 +10 µA Output Leakage (8K x 8) IOZ1 GND ≤ VO ≤ VDD -20 +20 µA Output Leakage (16K x 4) IOZ2 GND ≤ VO ≤ VDD -40 +40 µA Input Low Voltage VIL - 0.8 V Input High Level (Except E and W) VIH1 VDD -1.5 - V Input High Level (E and W) VIH2 VDD -1.0 - V Output Low Voltage VOL IOL = 2.0mA - 0.4 V Output High Voltage VOH IOH = -1.0mA 2.4 - V NOTES: 1. Operating supply current is proportional to operating frequency. IDDOP is specified at an operating frequency of 1MHz indicating repetitive accessing at a 1µs rate. Operating at slower rates will decrease IDDOP proportionally. 8-450 Specifications HS-6564RH TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Chip Enable Access Time TELQV Note 1 - 350 ns Address Access Time (TAVQV = TELQV + TAVEL) TAVQV Note 1 - 400 ns Chip Enable Low TELEH Note 1 350 - ns Chip Enable High TEHEL Note 1 130 - ns Address Setup Time TAVEL Note 1 50 - ns Address Hold Time TELAX Note 1 50 - ns Write Enable Low TWLWH Note 1 150 - ns Write Enable Setup Time TWLEH Note 1 250 - ns Early Write Setup Time TWLEL Note 1 10 - ns Early Write Hold Time TELWX Note 1 100 - ns Data Setup Time TDVWL Note 1 10 - ns Early Write Data Setup Time TDVEL Note 1 90 - ns Data Hold Time TWLDX Note 1 100 - ns Early Write Data Hold Time TELDX Note 1 100 - ns Early Write Pulse Hold Time TELWH Note 1 250 - ns MIN MAX UNITS NOTE: 1. Inputs TRISE = TFALL ≤ 20ns: Outputs : CLOAD = 50pF. All timing measurements at 1/2 VDD. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Guaranteed, but not tested) LIMITS PARAMETER Address Input Capacitance SYMBOL CONDITIONS CIA f = 1MHz, VI = VDD or GND - 200 pF Data Input Capacitance (8K x 8) CID1 f = 1MHz, VI = VDD or GND - 50 pF Data Input Capacitance (16K x 4) CID2 f = 1MHz, VI = VDD or GND - 100 pF Enable Input Capacitance (8K x 8) CIE1 f = 1MHz, VI = VDD or GND - 160 pF Enable Input Capacitance (16K x 4) CIE2 f = 1MHz, VI = VDD or GND - 80 pF Write Enable Input Capacitance (Each) CIW f = 1MHz, VI = VDD or GND - 100 pF Output Capacitance (8K x 8) CO1 f = 1MHz, VO = VDD or GND - 50 pF Output Capacitance (16K x 4) CO2 f = 1MHz, VO = VDD or GND - 100 pF - 75 ns Output Enable Time TELQX 8-451 Specifications HS-6564RH TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Guaranteed, but not tested) (Continued) LIMITS PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Output Disable Time TEHQZ - 75 ns Data Valid to Write (Read-Modify-Write) TQVWL 100 - ns Read or Write Cycle Time TELEL 480 - ns NOTE: 1. Inputs: TRISE = TFALL ≤ 20ns. Outputs: CLOAD = 50pF. All timing measurements at 1/2 VDD. TABLE 4. POST RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: The post irradiation test conditions and limits are the same as those listed in Tables 1 and 2. TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER SYMBOL DELTA LIMITS Output Low Voltage VOL ± 0.08V Output High Voltage VOH ± 0.48V II ± 0.20µA Input Leakage Current NOTE: Circuits are Burned-in as HS-6504RH discrete units, see HS-6504RH for approppiate burn-in delta information. TABLE 6. APPLICABLE SUBGROUPS NOTE: Quality Conformance Inspection (QCI) applies to the individual HS-6564RH devices, not to the assembled module. See HS-6504RH for further information. 8-452 HS-6564RH Timing Waveforms READ CYCLE TELEL TAVEL TAVEL TELAX ADD VALID A NEXT ADD TEHEL TEHEL TELEH E TELQV Q W HIGH-Z TEHQZ TELQX HIGH-Z HIGH TIME REFERENCE -1 0 1 2 3 4 5 TRUTH TABLE INPUTS TIME REFERENCE E -1 H 0 W OUTPUT Q A FUNCTION X X Z Memory Disabled H V Z Cycle Begins, Addresses are Latched 1 L H X X Output Enabled 2 L H X V Output Valid H X V Read Accomplished X X Z Prepare for Next Cycle (Same as -1) H V Z Cycle Ends, Next Cycle Begins (Same as 0) 3 4 5 H The address information is latched in the on chip registers on the falling edge of E (T = 0). Minimum address set up and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1) the output becomes enabled but data is not valid until during time (T = 2). W must remain high until after time (T = 2). After the output data has been read, E may return high (T = 3). This will disable the output buffer and ready the RAM for the next memory cycle (T = 4). 8-453 HS-6564RH Timing Waveforms (Continued) EARLY WRITE CYCLE TELAX TAVEL TAVEL NEXT ADD ADD VALID A TELEL TELEH TEHEL TEHEL E TELWH TWLEL TWLEL W TELDX TDVEL TDVEL NEXT DATA DATA VALID D HIGH-Z HIGH-Z Q TIME REFERENCE TRUTH TABLE INPUTS TIME REFERENCE E W A D OUTPUT Q -1 H X X X Z L V V Z Cycle Begins, Addresses are Latched L X X X Z Write in Progress Internally X X X Z Write Complete H X X X Z Prepare for Next Cycle (Same as -1) L V V Z Cycle Ends, Next Cycle Begins (Same as 0) 0 1 2 3 4 The early write cycle is the only cycle where the output is guaranteed not to become active. On the falling edge of E (T = 0), the addresses, the write signal, and the data input are latched in on chip registers. The logic value of W at the time E falls determines the state of the output buffer for the cycle. Since W is low when E falls, the output buffer is latched into FUNCTION Memory Disabled the high impedance state and will remain in that state until E returns high (T = 2). For this cycle, the data input is latched by E going low; therefore data set up and hold times should be referenced to E. When E (T = 2) returns to the high state the output buffer disables and all signals are unlatched. The device is now ready for the next cycle. 8-454 HS-6564RH Timing Waveforms (Continued) READ MODIFY WRITE CYCLE TELAX TAVEL TAVEL NEXT DATA ADD VALID A TEHEL TEHEL E TWLEH TWLWH TWHEL TWHEL W TQVWL TDVWL TWLDX DATA VALID D TELQV Q TEHQZ TELQX HIGH-Z HIGH-Z VALID DATA OUTPUT TIME REFERENCE -1 0 1 2 3 4 5 6 7 TRUTH TABLE INPUTS TIME REFERENCE E W A D OUTPUT Q -1 H X X X Z H V X Z Cycle Begins, Addresses are Latched 1 L H X X X Output Enabled 2 L H X X V Output Valid, Read and Modify Time 3 L X V V Write Begins, Data is Latched 4 L X X X V Write in Progress Internally X X X V Write Complete 0 5 6 7 H FUNCTION Memory Disabled X X X Z Prepare for Next Cycle (Same as -1) H V X Z Cycle Ends, Next Cycle Begins (Same as 0) The read modify write cycle begins as all other cycles on the falling edge of E (T = 0). The W line should be high at (T = 0) in order to latch the output buffers in the active state. During (T = 1) the output will be active but not valid until (T = 2). On the falling edge of the W (T = 3) the data present at the output and input are latched. The W signal also latches itself on its low going edge. All input signals excluding E have been latched and have no further effect on the RAM. The rising edge of E (T = 5) completes the write portion of the cycle and unlatches all inputs and output. The output goes to a high impedane and the RAM is ready for the next cycle. NOTE: In the above descriptions the numbers in parenthesis (T = n) refers to the respective timing diagrams. The numbers are located on the time reference line below each diagram. The timing diagrams shown are only examples and are not the only valid method of operation. 8-455 HS-6564RH Organization Guide mode, use the chip enables as if there were only two, E1 and E2. In the 16K x 4 mode, all chip enables must be treated separately. Transitions between chip enables must be treated with the same timing constraints that apply to any one chip enable. All chip enables must be high at least one chip enable high time (TEHEL) before any chip enable can fall. More than one chip enable low simultaneously, for devices whose outputs are tied common either internally or externally, is an illegal input condition and must be avoid. To Organize 8K x 8: Connect: E1 with E3 E2 with E4 W1 with W2 (Pins 9 + 32) (Pins 12 + 29) (Pins 11 + 31) To Organize 16K x 4: Connect: Q0 with Q4 D0 with D4 Q1 with Q5 D1 with D5 D2 with D6 Q2 with Q6 D3 with D7 Q3 with Q7 Optional W1 may be common with W2 (Pins 2 + 39) (Pins 3 + 38) (Pins 4 + 37) (Pins 5 + 36) (Pins 16 + 25) (Pins 17 + 24) (Pins 18 + 23) (Pins 19 + 22) (Pins 11 + 31) Printed Circuit Board Mounting: The leadless chip carrier packages used in the HS-6564RH have conductive lids. These lids are electrically floating, not connected to VDD or GND. The designer should be aware of the possibility that the carriers on the bottom side could short conductors below if pressed completely down against the surface of the circuit board. The pins on the package are designed with a standoff feature to help prevent the leadless carriers from touching the circuit board surface. Concerns for Proper Operation of Chip Enables: The transition between blocks of RAM requires a change in the chip enable being used. When operating in the 8K x 8 HS-6504RH (One of Sixteen) LSB A8 A7 A6 A0 A1 A2 A 6 LATCHED ADDRESS REGISTER A GATED ROW DECODER 6 L 64 64 x 64 MATRIX G 64 D D LATCH L W D LATCH G Q A D L LATCH D LATCH L Q A Q Q L E GATED COLUMN DECODER AND DATA I/O L Q 6 6 A A LATCHED ADDRESS REGISTER LSB A11 A5 A4 A3 A9 A10 8-456 ALL LINES ACTIVE HIGH-POSITIVE LOGIC THREE-STATE BUFFERS: A HIGH OUTPUT ACTIVE CONTROL AND DATA LATCHES: L LOW Q=D Q LATCHES ON RISING EDGE OF L ADDRESS LATCHES: LATCH ON RISING EDGE OF E GATED DECODERS: GATE ON RISING EDGE OF G HS-6564RH Board Size Tradeoffs Printed circuit board real estate is a costly commodity. Actual board costs depend on layout tolerances, density, complexity, number of layers, choice of board material, and other factors. The following table compares board space for 16 standard DIP 4K RAMs to the HS-6564RH RAM array. Both fine line, close tolerance layout and standard “easy” layout board sizes are shown in the comparison. We urge you to contact your local Intersil office of sales representative for accurate pricing allowing cost tradeoff analysis. In your cost analysis, also consider the advantages of a lighter, smaller overall package for your system. Con sider how much more valuable your system will be when the memory array size is decreased to about 1/6 of normal size. 64K ARRAY OR 16 4K RAMs ON A PC BOARD vs. THE HS-6564RH CIRCUIT SUBSTRATE PACKAGE SIZE 18 Pin DIP Standard Two Sided PCB 12 to 15 Square Inches 18 Pin DIP Fine Line or Multilayer 9 to 11 Square Inches PCB 18 Pin Leadless Carrier Multilayer Alumina Substrate 3 to 5 Square Inches HS-6564RH Two Sided Mounting Multilayer Alumina Substrate 2 Square Inches Low Voltage Data Retention DATA RETENTION MODE INTERSIL CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. Chip Enable (E) must be held high during data retention; within VDD +0.3V to VDD - 0.3V. DATA RETENTION MODE VDD 2. All other inputs should be held either high (at CMOS VDD) or at ground to minimize IDDDR. E 3. Inputs which are held high (e.g. E) must be kept between VDD +0.3V and 70% of VDD during the power up and power down transitions. 4.5V VDD ≥ 3.0V 4.5V TEHEL VDD +0.3V 4. The RAM can begin operation one TEHEL after VDD reaches the minimum operating voltage (4.5 volts). Burn-In/Irradiation Circuits Intersil - Space Level Product Flow HS4-6504RH LCCs are fully tested and processed through the Intersil space level (-Q) product flow (see page 8-91) and are assembled onto a ceramic substrate for the HS56564RH module. Temperature Cycle - 10 Cycles Serialization Electrical Tests Subgroups 1, 7, 9; Read and Record Subgroup 1 only Electrical Tests Subgroups 3, 8B, 11; Read and Record Subgroup 3 only Electrical Tests Subgroups 2, 8A, 10; Read and Record Subgroups 2 only Gross Leak Method 1014, 100% Fine Lead Method 1014, 100% Customer Source Inspection (Note 1) External Visual Inspection Method 2009 Data package Generation (Note 3) NOTES: 1. These steps are optional, and should be listed on the purchase order if required. 2. This data comes from the testing and processing of the HS5-6504RH LCC’s. 3. Data package contains: Wafer Lot Acceptance Report (includes SEM report) (Note 2) Assembly Attributes (post seal) X-Ray Report and Film (Note 2) Test Attributes (includes Group A) Test Variables Data Shippable Serial Number List Radiation Testing Certificate of Conformance (Note 2) 8-457