® RT3601EA Signal Phase PWM Controller with Integrated Driver for IMVP8 Mobile CPU Core Power Supply General Description Features The RT3601EA is an IMVP8 compliant CPU power controller with 1 embedded driver. The RT3601EA adopts G-NAVP TM (Green Native AVP) which is Richtek's proprietary topology derived from finite DC gain of EA amplifier with current mode control, making it easy to set the droop to meet all Intel CPU requirements of AVP (Adaptive Voltage Positioning). Based on the G-NAVPTM topology, the RT3601EA also features a quick response mechanism for optimized AVP performance during load transient. The RT3601EA supports mode transition function with various operating states. A serial VID (SVID) interface is built in the RT3601EA to communicate with Intel IMVP8 compliant CPU. The RT3601EA supports VID on-the-fly function with three different slew rates : Fast, Slow and Decay. By utilizing the G-NAVPTM topology, the operating frequency of the RT3601EA varies with VID, load and input voltage to further enhance the efficiency even in CCM. Moreover, the G-NAVPTM with CCRCOT (Constant Current Ripple COT) technology provides superior output voltage ripple over the entire input/output range. The built-in high accuracy DAC converts the SVID code ranging from 0.25V to 1.52V with 5mV per step. The RT3601EA integrates a high accuracy ADC for platform setting functions, such as quick response trigger level. Besides, the setting function also supposes this two rails address exchange. The RT3601EA provides VR ready output signals. It also features complete fault protection functions including overvoltage (OV), negative voltage (NV), over-current (OC) and under-voltage lockout (UVLO). The RT3601EA is available in the WQFN-28L 4x4 small foot print package. Intel IMVP8 Serial VID Interface Compatible Power Management States Single Phase with 1 Embedded MOSFET Drvier PWM Controller G-NAVP TM (Green Native Adaptive Voltage Positioning) Topology 0.5% DAC Accuracy Differential Remote Voltage Sensing Built-in ADC for Platform Programming Accurate Current Balance System Thermal Compensated AVP Diode Emulation Mode at Light Load Condition for Multiple or Single Phase Operation Fast Transient Response VR Ready Indicator Thermal Throttling Current Monitor Output OVP, OCP, NVP, UVLO Slew Rate Setting/Address Flip Function Rail Address Flexibility DVID Enhancement Applications IMVP8 Intel Core Supply Notebook/ Desktop Computer/ Servers Multi-phase CPU Core Supply AVP Step-Down Converter Simplified Application Circuit RT3601EA To PCH PGOOD PWM Driver MOSFET VCORE VR_HOT To CPU VCLK VDIO PHASE MOSFET VCORE ALERT Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT3601EA Pin Configuration Ordering Information (TOP VIEW) RT3601EA SET1 SET2 SET3 VSEN FB COMP RGND Package Type QW : WQFN-28L 4x4 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) 28 27 26 25 24 23 22 VCC EN VR_HOT VDIO ALERT VCLK VR_READY Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. 20 19 18 17 16 15 GND 29 ISENN ISENP PSYS IMON VREF TSEN DRVEN 8 9 10 11 12 13 14 Suitable for use in SnPb or Pb-free soldering processes. Marking Information WQFN-28L 4x4 3H= : Product Code 3H=YM DNN 21 2 3 4 5 6 7 BOOT UGATE PHASE LGATE PVCC VIN PWM 1 YMDNN : Date Code Functional Pin Description Pin No Pin Name Pin Function 1 VCC Controller Power Supply. Connect this pin to 5V and place a decoupling capacitor 2.2F at least. The decoupling capacitor is as close PWM controller as possible. 2 EN VR Enable Control Input. 3 VR_HOT Thermal Monitor Output, this Pin is Active Low. 4 VDIO VR and CPU Data Transmission Interface. 5 ALERT SVID Alert. (Active low) 6 VCLK Synchronous Clock from the CPU. 7 VR_READY VR Ready Indicator. 8 BOOT Bootstrap Supply for High-Side Gate MOSFET Driver. 9 UGATE High-Side Driver Output. Connect the pin to the gate of high-side MOSFET. 10 PHASE Switch Node of High-Side Driver. Connect the pin to high-side MOSFET source together with the low-side MOSFET drain and inductor. 11 LGATE Low-Side Driver Output. This pin drives the gate of low-side MOSFET. 12 PVCC Driver Power Supply Input. Connect this pin to GND by a minimum 2.2F ceramic Capacitor. 13 VIN VIN Input Pin. Connect a low pass filter to this pin to set on-time. 14 PWM PWM Outputs. 15 DRVEN 16 TSEN 17 VREF External Driver Enable Control. Connecting to driver enable pin. Thermal Sense Input. Platform can use this to set BOOT voltage and DVID threshold. Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the output voltage of IMON pin. Between this pin and GND must be placed a exact 0.47F capacitor and 3.9 resistor. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Pin No Pin Name Pin Function 18 IMON Current Monitor Output. This pin outputs a voltage proportional to the output current. 19 PSYS System Input Power Monitor. 20 ISENP Positive Current Sense Input. 21 ISENN Negative Current Sense Input. 22 RGND Return Ground. This pin is the negative node of the differential remote voltage sensing. 23 COMP Compensation. This pin is error amplifier output pin. 24 FB Negative Input of the Error Amplifier. This pin is for output voltage feedback to controller. 25 VSEN 26 SET3 27 SET2 SET1 29 (Exposed Pad) GND 1st Platform Setting. Platform can use this pin to set ICCMAX,AI Gain, PSYS function and DVID width. Moreover, SETI pin features a special function for users to confirm the soldering condition of the controller under zero VBOOT condition. Connect the SETI pin to 5V and turn on the EN pin, if the soldering is good, both rails will output to 1.05V. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. VCC VSEN EN VR_HOT ALERT VDIO VCLK TSEN PSYS SET2 SET3 SET1 Functional Block Diagram VR_READY 28 VR Voltage Sense Input. This pin is connected to the terminal of VR output voltage. 3rd Platform Setting. Platform can use this pin to set QRTH, QRWIDTH, IPSK, anti-overshoot threshold. 2nd Platform Setting. Platform can use this pin to set switching frequency, zero load-line, anti-overshoot function, VR address and OCS. MUX UVLO IMONI GND ADC ADC SVID Interface Configuration Registers Control Logic From Control Logic RGND DAC Soft-Start & Slew Rate Control FB VSET ERROR AMP QRTH QRWIDTH OCS AI TONSET IMAX ADDR OLL ANTIOVS OCP DVID_TH Offset Cancellation + - + + COMP PWM CMP - QR QRWIDTH AI ISENP ISENN Loop Control Protection Logic DRVEN TON GEN/ Driver Interface PWM PVCC BOOT TONSET + Driver RAMP - IMON + IMONI OCS/OCP_TH OC To Protection Logic UGATE PHASE LGATE - VSEN VINR OV/UV/NV VREFI VIN + - VREF Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT3601EA Operation The RT3601EA adopts G-NAVPTM (Green Native AVP) which is Richtek's proprietary topology derived from finite DC gain of EA amplifier with current mode control, making it easy to set the droop to meet all Intel CPU requirements of AVP (Adaptive Voltage Positioning). Current Balance The G-NAVPTM controller is one type of current mode constant on-time control with DC offset cancellation. The approach can not only improve DC offset problem for increasing system accuracy but also provide fast transient response. When current feedback signal reaches COMP signal, the RT3601EA generates an on-time width to achieve PWM modulation. Offset Cancellation TON GEN/Driver Interface PWMx Generate the sequentially according to the phase control signal from the Loop Control/Protection Logic. Pulse width is determined by current balance result and pin setting. Once quick response mechanism is triggered, VR will allow all PWM to turn on at the same time. PWM status is also controlled by Protection Logic. Different protections may cause different PWM status (Both High-Z or LG turnon). SVID Interface/Configuration Registers/Control Logic The interface receives the SVID signal from CPU and sends the relative signals to Loop Control/Protection Logic for loop control to execute the action by CPU. The registers save the pin setting data from ADC output. The Control Logic controls the ADC timing, generates the digital code of the VID for VSEN voltage. Loop Control/Protection Logic Each phase current sense signal is sent to the current balance circuit which adjusts the on-time of each phase to optimize current sharing. Cancel the current/voltage ripple issue to get the accurate VSEN. UVLO Detect the DVD and VCC voltage and issue POR signal as they are high enough. DAC Generate an analog signal according to the digital code generated by Control Logic. Soft-Start & Slew Rate Control Control the Dynamic VID slew rate of VSET according to the SetVID fast or SetVID slow. Error Amp Error amplifier generates COMP signal by the difference between VSET and FB. PWM CMP The PWM comparator compares Ramp signal COMP signal and current feedback signal to generate a signal for TON trigger. IMON Filter IMON Filter is used for average sum current signal by analog RC filter. It controls the power on sequence, the protection behavior, and the operational phase number. MUX and ADC The MUX supports the inputs from SET1, SET2, SET3, IMON, TSEN. The ADC converts these analog signals to digital codes for reporting or performance adjustment. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Table 1. VR12.5 VID Code Table VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 0 0 0 0 0 0 1 01 0.25 0 0 0 0 0 0 1 0 02 0.255 0 0 0 0 0 0 1 1 03 0.26 0 0 0 0 0 1 0 0 04 0.265 0 0 0 0 0 1 0 1 05 0.27 0 0 0 0 0 1 1 0 06 0.275 0 0 0 0 0 1 1 1 07 0.28 0 0 0 0 1 0 0 0 08 0.285 0 0 0 0 1 0 0 1 09 0.29 0 0 0 0 1 0 1 0 0A 0.295 0 0 0 0 1 0 1 1 0B 0.3 0 0 0 0 1 1 0 0 0C 0.305 0 0 0 0 1 1 0 1 0D 0.31 0 0 0 0 1 1 1 0 0E 0.315 0 0 0 0 1 1 1 1 0F 0.32 0 0 0 1 0 0 0 0 10 0.325 0 0 0 1 0 0 0 1 11 0.33 0 0 0 1 0 0 1 0 12 0.335 0 0 0 1 0 0 1 1 13 0.34 0 0 0 1 0 1 0 0 14 0.345 0 0 0 1 0 1 0 1 15 0.35 0 0 0 1 0 1 1 0 16 0.355 0 0 0 1 0 1 1 1 17 0.36 0 0 0 1 1 0 0 0 18 0.365 0 0 0 1 1 0 0 1 19 0.37 0 0 0 1 1 0 1 0 1A 0.375 0 0 0 1 1 0 1 1 1B 0.38 0 0 0 1 1 1 0 0 1C 0.385 0 0 0 1 1 1 0 1 1D 0.39 0 0 0 1 1 1 1 0 1E 0.395 0 0 0 1 1 1 1 1 1F 0.4 0 0 1 0 0 0 0 0 20 0.405 0 0 1 0 0 0 0 1 21 0.41 0 0 1 0 0 0 1 0 22 0.415 0 0 1 0 0 0 1 1 23 0.42 0 0 1 0 0 1 0 0 24 0.425 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT3601EA VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 0 1 0 0 1 0 1 25 0.43 0 0 1 0 0 1 1 0 26 0.435 0 0 1 0 0 1 1 1 27 0.44 0 0 1 0 1 0 0 0 28 0.445 0 0 1 0 1 0 0 1 29 0.45 0 0 1 0 1 0 1 0 2A 0.455 0 0 1 0 1 0 1 1 2B 0.46 0 0 1 0 1 1 0 0 2C 0.465 0 0 1 0 1 1 0 1 2D 0.47 0 0 1 0 1 1 1 0 2E 0.475 0 0 1 0 1 1 1 1 2F 0.48 0 0 1 1 0 0 0 0 30 0.485 0 0 1 1 0 0 0 1 31 0.49 0 0 1 1 0 0 1 0 32 0.495 0 0 1 1 0 0 1 1 33 0.5 0 0 1 1 0 1 0 0 34 0.505 0 0 1 1 0 1 0 1 35 0.51 0 0 1 1 0 1 1 0 36 0.515 0 0 1 1 0 1 1 1 37 0.52 0 0 1 1 1 0 0 0 38 0.525 0 0 1 1 1 0 0 1 39 0.53 0 0 1 1 1 0 1 0 3A 0.535 0 0 1 1 1 0 1 1 3B 0.54 0 0 1 1 1 1 0 0 3C 0.545 0 0 1 1 1 1 0 1 3D 0.55 0 0 1 1 1 1 1 0 3E 0.555 0 0 1 1 1 1 1 1 3F 0.56 0 1 0 0 0 0 0 0 40 0.565 0 1 0 0 0 0 0 1 41 0.57 0 1 0 0 0 0 1 0 42 0.575 0 1 0 0 0 0 1 1 43 0.58 0 1 0 0 0 1 0 0 44 0.585 0 1 0 0 0 1 0 1 45 0.59 0 1 0 0 0 1 1 0 46 0.595 0 1 0 0 0 1 1 1 47 0.6 0 1 0 0 1 0 0 0 48 0.605 0 1 0 0 1 0 0 1 49 0.61 Copyright © 2016 Richtek Technology Corporation. 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DS3601EA-00 June 2016 RT3601EA VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 1 0 0 1 0 1 0 4A 0.615 0 1 0 0 1 0 1 1 4B 0.62 0 1 0 0 1 1 0 0 4C 0.625 0 1 0 0 1 1 0 1 4D 0.63 0 1 0 0 1 1 1 0 4E 0.635 0 1 0 0 1 1 1 1 4F 0.64 0 1 0 1 0 0 0 0 50 0.645 0 1 0 1 0 0 0 1 51 0.65 0 1 0 1 0 0 1 0 52 0.655 0 1 0 1 0 0 1 1 53 0.66 0 1 0 1 0 1 0 0 54 0.665 0 1 0 1 0 1 0 1 55 0.67 0 1 0 1 0 1 1 0 56 0.675 0 1 0 1 0 1 1 1 57 0.68 0 1 0 1 1 0 0 0 58 0.685 0 1 0 1 1 0 0 1 59 0.69 0 1 0 1 1 0 1 0 5A 0.695 0 1 0 1 1 0 1 1 5B 0.7 0 1 0 1 1 1 0 0 5C 0.705 0 1 0 1 1 1 0 1 5D 0.71 0 1 0 1 1 1 1 0 5E 0.715 0 1 0 1 1 1 1 1 5F 0.72 0 1 1 0 0 0 0 0 60 0.725 0 1 1 0 0 0 0 1 61 0.73 0 1 1 0 0 0 1 0 62 0.735 0 1 1 0 0 0 1 1 63 0.74 0 1 1 0 0 1 0 0 64 0.745 0 1 1 0 0 1 0 1 65 0.75 0 1 1 0 0 1 1 0 66 0.755 0 1 1 0 0 1 1 1 67 0.76 0 1 1 0 1 0 0 0 68 0.765 0 1 1 0 1 0 0 1 69 0.77 0 1 1 0 1 0 1 0 6A 0.775 0 1 1 0 1 0 1 1 6B 0.78 0 1 1 0 1 1 0 0 6C 0.785 0 1 1 0 1 1 0 1 6D 0.79 0 1 1 0 1 1 1 0 6E 0.795 Copyright © 2016 Richtek Technology Corporation. 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DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT3601EA VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 1 1 0 1 1 1 1 6F 0.8 0 1 1 1 0 0 0 0 70 0.805 0 1 1 1 0 0 0 1 71 0.81 0 1 1 1 0 0 1 0 72 0.815 0 1 1 1 0 0 1 1 73 0.82 0 1 1 1 0 1 0 0 74 0.825 0 1 1 1 0 1 0 1 75 0.83 0 1 1 1 0 1 1 0 76 0.835 0 1 1 1 0 1 1 1 77 0.84 0 1 1 1 1 0 0 0 78 0.845 0 1 1 1 1 0 0 1 79 0.85 0 1 1 1 1 0 1 0 7A 0.855 0 1 1 1 1 0 1 1 7B 0.86 0 1 1 1 1 1 0 0 7C 0.865 0 1 1 1 1 1 0 1 7D 0.87 0 1 1 1 1 1 1 0 7E 0.875 0 1 1 1 1 1 1 1 7F 0.88 1 0 0 0 0 0 0 0 80 0.885 1 0 0 0 0 0 0 1 81 0.89 1 0 0 0 0 0 1 0 82 0.895 1 0 0 0 0 0 1 1 83 0.9 1 0 0 0 0 1 0 0 84 0.905 1 0 0 0 0 1 0 1 85 0.91 1 0 0 0 0 1 1 0 86 0.915 1 0 0 0 0 1 1 1 87 0.92 1 0 0 0 1 0 0 0 88 0.925 1 0 0 0 1 0 0 1 89 0.93 1 0 0 0 1 0 1 0 8A 0.935 1 0 0 0 1 0 1 1 8B 0.94 1 0 0 0 1 1 0 0 8C 0.945 1 0 0 0 1 1 0 1 8D 0.95 1 0 0 0 1 1 1 0 8E 0.955 1 0 0 0 1 1 1 1 8F 0.96 1 0 0 1 0 0 0 0 90 0.965 1 0 0 1 0 0 0 1 91 0.97 1 0 0 1 0 0 1 0 92 0.975 1 0 0 1 0 0 1 1 93 0.98 Copyright © 2016 Richtek Technology Corporation. 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DS3601EA-00 June 2016 RT3601EA VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 1 0 0 1 0 1 0 0 94 0.985 1 0 0 1 0 1 0 1 95 0.99 1 0 0 1 0 1 1 0 96 0.995 1 0 0 1 0 1 1 1 97 1 1 0 0 1 1 0 0 0 98 1.005 1 0 0 1 1 0 0 1 99 1.01 1 0 0 1 1 0 1 0 9A 1.015 1 0 0 1 1 0 1 1 9B 1.02 1 0 0 1 1 1 0 0 9C 1.025 1 0 0 1 1 1 0 1 9D 1.03 1 0 0 1 1 1 1 0 9E 1.035 1 0 0 1 1 1 1 1 9F 1.04 1 0 1 0 0 0 0 0 A0 1.045 1 0 1 0 0 0 0 1 A1 1.05 1 0 1 0 0 0 1 0 A2 1.055 1 0 1 0 0 0 1 1 A3 1.06 1 0 1 0 0 1 0 0 A4 1.065 1 0 1 0 0 1 0 1 A5 1.07 1 0 1 0 0 1 1 0 A6 1.075 1 0 1 0 0 1 1 1 A7 1.08 1 0 1 0 1 0 0 0 A8 1.085 1 0 1 0 1 0 0 1 A9 1.09 1 0 1 0 1 0 1 0 AA 1.095 1 0 1 0 1 0 1 1 AB 1.1 1 0 1 0 1 1 0 0 AC 1.105 1 0 1 0 1 1 0 1 AD 1.11 1 0 1 0 1 1 1 0 AE 1.115 1 0 1 0 1 1 1 1 AF 1.12 1 0 1 1 0 0 0 0 B0 1.125 1 0 1 1 0 0 0 1 B1 1.13 1 0 1 1 0 0 1 0 B2 1.135 1 0 1 1 0 0 1 1 B3 1.14 1 0 1 1 0 1 0 0 B4 1.145 1 0 1 1 0 1 0 1 B5 1.15 1 0 1 1 0 1 1 0 B6 1.155 1 0 1 1 0 1 1 1 B7 1.16 1 0 1 1 1 0 0 0 B8 1.165 Copyright © 2016 Richtek Technology Corporation. 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DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT3601EA VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 1 0 1 1 1 0 0 1 B9 1.17 1 0 1 1 1 0 1 0 BA 1.175 1 0 1 1 1 0 1 1 BB 1.18 1 0 1 1 1 1 0 0 BC 1.185 1 0 1 1 1 1 0 1 BD 1.19 1 0 1 1 1 1 1 0 BE 1.195 1 0 1 1 1 1 1 1 BF 1.2 1 1 0 0 0 0 0 0 C0 1.205 1 1 0 0 0 0 0 1 C1 1.21 1 1 0 0 0 0 1 0 C2 1.215 1 1 0 0 0 0 1 1 C3 1.22 1 1 0 0 0 1 0 0 C4 1.225 1 1 0 0 0 1 0 1 C5 1.23 1 1 0 0 0 1 1 0 C6 1.235 1 1 0 0 0 1 1 1 C7 1.24 1 1 0 0 1 0 0 0 C8 1.245 1 1 0 0 1 0 0 1 C9 1.25 1 1 0 0 1 0 1 0 CA 1.255 1 1 0 0 1 0 1 1 CB 1.26 1 1 0 0 1 1 0 0 CC 1.265 1 1 0 0 1 1 0 1 CD 1.27 1 1 0 0 1 1 1 0 CE 1.275 1 1 0 0 1 1 1 1 CF 1.28 1 1 0 1 0 0 0 0 D0 1.285 1 1 0 1 0 0 0 1 D1 1.29 1 1 0 1 0 0 1 0 D2 1.295 1 1 0 1 0 0 1 1 D3 1.3 1 1 0 1 0 1 0 0 D4 1.305 1 1 0 1 0 1 0 1 D5 1.31 1 1 0 1 0 1 1 0 D6 1.315 1 1 0 1 0 1 1 1 D7 1.32 1 1 0 1 1 0 0 0 D8 1.325 1 1 0 1 1 0 0 1 D9 1.33 1 1 0 1 1 0 1 0 DA 1.335 1 1 0 1 1 0 1 1 DB 1.34 1 1 0 1 1 1 0 0 DC 1.345 1 1 0 1 1 1 0 1 DD 1.35 Copyright © 2016 Richtek Technology Corporation. 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DS3601EA-00 June 2016 RT3601EA VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 1 1 0 1 1 1 1 0 DE 1.355 1 1 0 1 1 1 1 1 DF 1.36 1 1 1 0 0 0 0 0 E0 1.365 1 1 1 0 0 0 0 1 E1 1.37 1 1 1 0 0 0 1 0 E2 1.375 1 1 1 0 0 0 1 1 E3 1.38 1 1 1 0 0 1 0 0 E4 1.385 1 1 1 0 0 1 0 1 E5 1.39 1 1 1 0 0 1 1 0 E6 1.395 1 1 1 0 0 1 1 1 E7 1.4 1 1 1 0 1 0 0 0 E8 1.405 1 1 1 0 1 0 0 1 E9 1.41 1 1 1 0 1 0 1 0 EA 1.415 1 1 1 0 1 0 1 1 EB 1.42 1 1 1 0 1 1 0 0 EC 1.425 1 1 1 0 1 1 0 1 ED 1.43 1 1 1 0 1 1 1 0 EE 1.435 1 1 1 0 1 1 1 1 EF 1.44 1 1 1 1 0 0 0 0 F0 1.445 1 1 1 1 0 0 0 1 F1 1.45 1 1 1 1 0 0 1 0 F2 1.455 1 1 1 1 0 0 1 1 F3 1.46 1 1 1 1 0 1 0 0 F4 1.465 1 1 1 1 0 1 0 1 F5 1.47 1 1 1 1 0 1 1 0 F6 1.475 1 1 1 1 0 1 1 1 F7 1.48 1 1 1 1 1 0 0 0 F8 1.485 1 1 1 1 1 0 0 1 F9 1.49 1 1 1 1 1 0 1 0 FA 1.495 1 1 1 1 1 0 1 1 FB 1.5 1 1 1 1 1 1 0 0 FC 1.505 1 1 1 1 1 1 0 1 FD 1.51 1 1 1 1 1 1 1 0 FE 1.515 1 1 1 1 1 1 1 1 FF 1.52 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT3601EA Absolute Maximum Ratings (Note 1) VCC to GND ------------------------------------------------------------------------------------------- −0.3V to 6.5V RGND to GND ----------------------------------------------------------------------------------------- −0.3V to 0.3V VIN to GND --------------------------------------------------------------------------------------------- −0.3V to 28V PVCC to GND ----------------------------------------------------------------------------------------- −0.3V to 6.5V BOOT to PHASE ------------------------------------------------------------------------------------- −0.3V to 6.5V PHASE to GND DC -------------------------------------------------------------------------------------------------------- −0.3V to 30V <20ns --------------------------------------------------------------------------------------------------- −10V to 35V LGATE to GND DC -------------------------------------------------------------------------------------------------------- −0.3V to (VCC+ 0.3V) <20ns --------------------------------------------------------------------------------------------------- −2V to (VCC+ 0.3V) UGATE to GND DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V) <20ns --------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V) Other Pins ---------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V) Power Dissipation, PD @ TA = 25°C WQFN-28L 4x4 --------------------------------------------------------------------------------------- 3.5W Package Thermal Resistance (Note 2) WQFN-28L 4x4, θJA ---------------------------------------------------------------------------------- 28.5°C/W WQFN-28L 4x4, θJC --------------------------------------------------------------------------------- 7°C/W Junction Temperature -------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Model) ------------------------------------------------------------------------- 1.5kV Recommended Operating Conditions (Note 4) Supply Voltage, VIN --------------------------------------------------------------------------------- 4.5V to 26V Supply Voltage, VCC, PVCC ---------------------------------------------------------------------- 4.5V to 5.5V Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 4.5 5 5.5 V Supply Input Supply Voltage VCC Supply Current IVCC EN = 1.05V, No Switching -- 5 -- Supply Current at PS4 IVCC_PS4 EN = 1.05V, No Switching -- 0.1 -- Shutdown Current ISHDN VEN = 0 -- -- 5 Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 mA A is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Parameter Symbol Test Conditions Min Typ Max Unit 0.5% 8 10 0 0 0 0.5% 8 10 % of VID Reference and DAC DAC Accuracy VFB VDAC = 0.75V 1.52V VDAC = 0.5V 0.745V VDAC = 0.25V 0.495V SR Set VID Fast Set VID Slow, set slow = 1/2 Fast 30 15 33.75 16.875 45 22.5 mV/s RL = 47k(Note 5) CLOAD = 5pF (Note 5) 70 -3 80 5 -- --3 dB MHz mV -- 5 -- V/s 0.3 -- 3.6 V -- 5 -- mA 0.4 -- 0.4 mV 1 -- -- M 2.085 2.15 2.215 k 40 -- 40 mV mV Slew Rate Dynamic VID Slew Rate EA Amplifier DC Gain Gain-Bandwidth Product Input Offset ADC GBW VEAOFS Slew Rate SREA CLOAD = 10pF (Gain= 4, RF = 47k, VOUT =0.5V to -3V) Output Voltage Range VCOMP RL = 47k Max Source/Sink Current IOUTEA VCOMP = 2V Current Sensing Amplifier Input Offset Voltage VOSCS Impedance at Positive Input RISENxP VDAC = 1.1V, 40mV < ISENP – ISENN < 40mV Current Sensing Resistor RCS VISENP VISENN = 10mV Input Range VISEN_IN VDAC = 1.1V, ISENP – ISENN On-Time Setting TON VIN = 19V, VDAC = 1.3V, TON = 160ns -- 160 -- ns Minimum Off time TOFF VDAC = 1V -- 165 -- ns VUVLO Falling edge 3.86 4.06 4.26 V VUVLO Rising edge hysteresis -- 190 -- mV TON Setting Protections Under-Voltage Lockout Threshold Over-Voltage Protection Threshold VOV VDAC < 1V EN Threshold mV mV VDAC 350 VDAC 300 mV VNV 100 50 -- mV VIH 0.7 -- -- V VIL -- -- 0.3 V 1 -- 1 A Respect to VDAC voltage Leakage Current of EN Copyright © 2016 Richtek Technology Corporation. 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DS3601EA-00 June 2016 VDAC + 400 1400 VDAC 400 Under-Voltage Protection VUV Threshold Negative Voltage Protection Threshold EN and VR_REDAY Respect to VDAC voltage VDAC VDAC + + 300 350 1300 1350 mV is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT3601EA Parameter PGOOD Pull Low Voltage Symbol Test Conditions VPGOOD IVR_Ready = 10mA VIH Respect to INTEL Spec. with 50mV hysteresis Min Typ Max Unit -- -- 0.13 V 0.65 -- -- -- -- 0.45 1 -- 1 A -- -- 0.13 V 0.595 0.6 0.605 V Serial VID and VR_HOT VCLK, VDIO Leakage Current of VCLK, VDIO, ALERT VIL ILEAK_IN V and VR_HOT IVDIO = 10mA VDIO, ALERT and VR_HOT Pull Low Voltage IALERT = 10mA IVR_HOT = 10mA VREF VREF VREF ADC Digital IMON Set Update Period TSEN Threshold for Tmp_Zone[7] Transition TSEN Threshold for Tmp_Zone[6] Transition TSEN Threshold for Tmp_Zone[5] Transition TSEN Threshold for Tmp_Zone[4] Transition TSEN Threshold for Tmp_Zone[3] Transition TSEN Threshold for Tmp_Zone[2] Transition TSEN Threshold for Tmp_Zone[1] Transition TSEN Threshold for Tmp_Zone[0] Transition Update Period VIMON VIMON_INI = 0.8V, Auxiliary rail VIMON VIMON_INI = 0.4V, Main rail (Note 5) -- 255 -- --- 255 125 --- 100C -- 1.092 -- 97C -- 1.132 -- 94C -- 1.176 -- 91C -- 1.226 -- 88C -- 1.283 -- 85C -- 1.346 -- 82C -- 1.418 -- 75C -- 1.624 -- (Note 5) -- 100 -- RPWMsr -- 30 -- RPWMsk -- 10 -- VIMON TIMON Decimal VTSEN Ttsen s V s PWM Driving Capability PWM_x Driver On-Resistance UGATEx Drive Source RUGATEsr VBOOT VPHASE Forced to 5V -- 1.7 -- UGATEx Drive Sink RUGATEsk VBOOT VPHASE Forced to 5V -- 1.4 -- LGATEx Drive Source RLGATEsr ISource = 100mA -- 1.6 -- LGATEx Drive Sink RLGATEsk ISink = 100mA -- 1.1 -- Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Parameter Symbol Dead-Time Internal Boost Diode Resistance RBOOT Test Conditions From LGATE Falling to UGATE Rising From UGATE Falling to LGATE Rising PVCC to BOOTx, IBOOT = 10mA Min Typ Max Unit 30 ns 20 -- 40 80 Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guarantee by design. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 www.richtek.com 16 VREF R8 R7 26.1k Copyright © 2016 Richtek Technology Corporation. All rights reserved. VSS_SENSE VCC_SENSE C7 Optional C6 Optional Enable To CPU VCCIO R15 0 565 390 C3 0.47µF VIN R11 3.01k R12 R4 R3 28k VREF R22 NC R16 3.9 R20 85 R19 75 C8 Optional 47k 47pF R18 10k C5 58K C2 0.22µF R6 8.87k R5 215 C1 2.2µF R24 10k R23 C4 270pF R21 170 R17 R10 2k R14 2.1k 1.2 R9 18.7 R13 36 5V R2 22 VCC IMON VREF COMP 24 FB 22 RGND 23 7 VR_READY 3 VR_HOT 6 VCLK 4 VDIO 5 ALERT 2 EN 25 VSEN 18 17 13 VIN 9 8 12 14 GND TSEN DRVEN ISENN RNTC2 100k R37 48.7k NC NC C16 2.2µF R39 8.87k R38 113 5V VIN R36 1.24k C9 0.1µF R28 0 R27 0 R26 2.2 R25 0 29 (Exposed Pad) 16 15 21 ISENP 20 PWM PHASE 10 11 LGATE UGATE BOOT PVCC RT3601EA PSYS SET3 27 SET2 28 SET1 26 1 R1 (Optional) 19 R35 53.6k C11 3.3nF R29 1 VREF R30 768 C10 10µF x 3 R31 845 RNTC1 4.7k R32 4.7k C12 0.47µF L1 0.22µH C13 C14 C15 22µF x 18 R33 100 LOAD VCORE_OUT R34 100 VSS_SENSE VCC_SENSE RT3601EA Typical Application Circuit Using Embedded MOSFET Driver is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 DS3601EA-00 June 2016 VREF Copyright © 2016 Richtek Technology Corporation. All rights reserved. VSS_SENSE VCC_SENSE C7 Optional C6 Optional Enable To CPU VCCIO R20 85 R17 R19 75 C8 Optional 47k 47pF R18 10k C5 58k C2 0.22µF R6 8.87k R5 215 C1 2.2µF R23 10k R24 C4 270pF R21 170 3.9 1.2 R10 2k R14 2.1k 22 R9 18.7 VREF R2 R13 36 R22 NC R16 R15 C3 0.47µF VIN 0 565 R8 R7 26.1k R11 3.01k R12 390 R4 R3 28k 5V SET3 VCC IMON VREF COMP 24 FB 22 RGND 23 7 VR_READY 3 VR_HOT 6 VCLK 4 VDIO 5 ALERT 2 EN 25 VSEN 18 17 13 VIN C9 1µF GND TSEN DRVEN ISENN 5V R27 R26 5V RNTC2 100k R37 48.7k R39 8.87k R38 113 R36 1.24k 0 0 VREF C10 2.2 0.1µF R35 53.6k PHASE PWM R28 LGATE EN RT9610C 29 (Exposed Pad) 16 15 21 BOOT C17 2.2µF PGND UGATE VCC NC NC NC NC R25 0 DRVEN DRVEN 14 8 9 10 11 12 ISENP 20 PWM BOOT UGATE PHASE LGATE PVCC RT3601EA PSYS 27 SET2 28 SET1 26 1 R1 (Optional) 19 VIN C12 3.3nF R29 1 R30 768 C11 10µF x 3 R31 845 RNTC1 4.7k R32 4.7k C13 0.47µF L1 0.22µH C14 C15 C16 22µF x 18 R33 100 LOAD VCORE_OUT R34 100 VSS_SENSE VCC_SENSE RT3601EA Using External MOSFET Driver is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT3601EA Typical Operating Characteristics VR Power On from EN CORE VR Power Off from EN V CORE (400mV/Div) V CORE (400mV/Div) PGOOD (1V/Div) UGATE1 (20V/Div) PGOOD (1V/Div) UGATE (20V/Div) EN (1V/Div) EN (1V/Div) VIN = 19V, No Load, VID = 1.05V VIN = 19V, No Load, VID = 1.05V Time (500μs/Div) Time (50μs/Div) CORE VR OCP CORE VR OVP V CORE (400mV/Div) V CORE (500mV/Div) PGOOD (1V/Div) PGOOD (1V/Div) UGATE (20V/Div) UGATE (20V/Div) I LOAD (40A/Div) LGATE (6V/Div) VIN = 19V, VID = 0.9V VIN = 19V, VID = 0.9V Time (100μs/Div) Time (50μs/Div) CORE VR Dynamic VID Up CORE VR Dynamic VID Down V CORE V CORE VCLK VCLK (1V/Div) V CORE (200mV/Div) VDIO (1V/Div) ALERT (1V/Div) VCLK VCLK (1V/Div) VDIO ALERT VIN = 19V, VID = 0.6V to 0.9VSlew Rate = Slow, ILOAD = 5A Time (10μs/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 V CORE (200mV/Div) VDIO (1V/Div) VDIO ALERT ALERT VIN = 19V, (1V/Div) VID = 0.9V to 0.6VSlew Rate = Slow, ILOAD = 5A Time (10μs/Div) is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA CORE VR Dynamic VID Up CORE VR Mode Transient V CORE V CORE VCLK VCLK VLCK (1V/Div) UGATE (20V/Div) VCLK (1V/Div) V CORE (200mV/Div) VDIO (1V/Div) VDIO UGATE LGATE LGATE (6V/Div) V CORE (20mV/Div) ALERT ALERT VIN = 19V, (1V/Div) VID = 0.6V to 0.9VSlew Rate = Fast, ILOAD = 5A Time (10μs/Div) VIN = 19V, VID = 0.9V, PS0 to PS2, ILOAD = 1A Time (50μs/Div) CORE VR Thermal Monitioring CORE VR Mode Transient V CORE VCLK VLCK (1V/Div) UGATE1 VTSEN (500mV/Div) UGATE (20V/Div) LGATE1 LGATE (6V/Div) V CORE (20mV/Div) VR_HOT (1V/Div) VIN = 19V, VID = 0.9V, PS2 to PS0, ILOAD = 1A VIN = 19V, VTSEN Sweep from 1V to 2V Time (5ms/Div) Time (50μs/Div) ∆VIMON_CORE vs. Load Current 0.5 ∆VIMON_CORE (V) 0.4 0.3 0.2 0.1 0.0 0 5 10 15 20 25 30 Load Current (A) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT3601EA Applications Information The RT3601EA is a single phase synchronous Buck controller, designed to meet Intel IMVP8 compatible CPUs specification with a serial SVID control interface. The controller uses an ADC to implement all kinds of settings to save total pin number for easy use and increasing PCB space utilization. The RT3601EA is used in notebooks, desktop computers and servers. General loop Function G-NAVPTM Control Mode The RT3601EA adopts the G-NAVPTM controller, which is a current mode constant on-time control with DC offset cancellation. The approach can not only improve DC offset problem for increasing system accuracy but also provide fast transient response. When current feedback signal reaches comp signal, the RT3601EA generates an ontime width to achieve PWM modulation. Figure 1 shows the basic G-NAVPTM behavior waveforms in continuous conduct mode (CCM). Diode Emulation Mode (DEM) As well-known, the dominate power loss is switching related loss during light load, hence VR needs to be operated in asynchronous mode (or called discontinuous conduct mode, DCM) to reduce switching related loss since switching frequency is dependent on loading in the asynchronous mode. The RT3601EA can operate in diode emulation mode (DEM) to improve light load efficiency. In DEM operation, the behavior of low-side MOSFET(s) needs to work like a diode, that is, the low-side MOSFET(s) will be turned on when the phase voltage is a negative value, i.e. the inductor current follows from Source to Drain of low-side MOSFET(s). And the low-side MOSFET(s) will be turned off when phase voltage is a positive value, i.e. reversed current is not allowed. Figure 2 shows the control behavior in DEM. Figure 3 shows the G-NAVPTM operation in DEM to illustrate the control behaviors. When the load decreases, the discharge time of output capacitors increases during UGATE and LGATE are turned off. Hence, the switching frequency and switching loss will be reduced to improve efficiency in light load condition. Current feedback signal Comp signal PWM Figure 1 (a). G-NAVPTM Behavior Waveforms in CCM in Steady State Current feedback signal Comp signal PWM Figure 1 (b). G-NAVPTM Behavior Waveforms in CCM in Load Transient. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Inductor current Phase node UGATE LGATE Figure 2. Diode Emulation Mode (DEM) in Steady State Inductor current signal Output capacitor discharge slope COMP signal UGATE LGATE Inductor current signal Output capacitor discharge slope COMP signal UGATE LGATE Figure 3. G-NAVPTM Operation in DEM. (a) : The load is lighter, output capacitor discharge slope is smaller and the switching frequency is lower. (b) : The load is increasing, output capacitor discharge slope is increased and switching frequency is increased, too. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT3601EA Multi-Function Pin Setting Mechanism For reducing total pin number of package, SET [1:3] pins adopt the multi-function pin setting mechanism in the RT3601EA. Figure 4 illustrates this operating mechanism for SET [1:3]. The voltage at VREF pin will be pulled up to 3.2V after power ready (POR). First, external voltage divider is used to set the Function1, and then internal current source 80μA is used to set the Function2. The setting voltage of Function1 and Function2 can be represented as R2 3.2V R1 R2 VFunction2 80 Α R1 R2 R1 R2 Connecting a R3 resistor from the SET[1:3] pin to the middle node of voltage divider can help to fine tune the set voltage of Function 2, which does not affect the set voltage of Function1. The Figure 5 shows the setting method and the set voltage of Function 1 and Function2 can be represented as : R2 3.2V R1 R2 80 Α R3 R1 R2 R1 R2 VFunction1 VFunction2 Function 2 <5:0> VFunction1 Function 1 <5:0> 80µA ADC VREF All function setting will be done within 500μs after power ready (POR), and the voltage at VREF pin will be fixed to 0.6V after all function setting over. Function 1 Register If VFunction1 and VFunction2 are determined, R1 and R2 can be calculated as follows : 3.2V VFunction2 80 Α VFunction1 R1 VFunction1 R2 3.2V VFunction1 R1 SET[1:3] R3 R2 Function 2 Register R1 Function 2 <5:0> Function 1 <5:0> 80µA ADC Function 2 <5:0> Function 1 <5:0> VREF 80µA Function 1 Register ADC Function 1 Register R1 SETx R2 Function 2 Register Function 2 <5:0> Function 1 <5:0> R1 SET[1:3] VREF Function 2 Register R3 R2 Figure 5. Multi-Function Pin Setting Mechanism with a R3 Resistor to Fine Tune the Set Voltage of Function2 80µA ADC VREF Function 1 Register R1 SETx Function 2 Register R2 Figure 4. Multi-Function Pin Setting Mechanism for SET [1:3] Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Figure 6 shows operating mechanism for TSEN pins. There is only voltage divider Function to program VR. The internal current source is used to thermal sensing. The Function for program VR can be represented as VFunction1 R2 3.2V R1 R2 Function <5:0> 80µA ADC VREF DVID_TH and VBOOT Setting Register RNTC R1 R3 R2 TSEN Thermal Sense Figure 6. Multi-Function Pin Setting Mechanism for TSEN TSEN and VR_HOT The VR_HOT signal is an open-drain signal which is used for VR thermal protection. When the sensed voltage in each TSEN pin is less than 1.092, the VR_HOT signal will be pulled-low to notify CPU that the thermal protection needs to work. According to Intel VR definition, VR_HOT signal needs acting if VR power chain temperature exceeds 100°C. Placing an NTC thermistor at the hottest area in the VR power chain and its connection is shown in Figure 7, to design the TSEN network so that VTSEN = 1.092V at 100°C. The resistance accuracy of TSEN network is recommended to be 1% or higher. VTSEN 80 Α (RNTC //R3) + (R1//R2) VDDIO Power Ready (POR) Detection During start-up, the RT3601EA detects the voltage at the voltage input pins : VCC and EN. When VCC> 4.45V, the RT3601EA recognizes the power state of system to be ready (POR = high) and waits for enable command at the EN pin. After POR = high and VEN > 0.7V, the RT3601EA enters start-up sequence. If VCC drops below low threshold (POR = low), the RT3601EA enters power down sequence and all functions will be disabled. Normally, connecting system voltage VTT (1.05V) to the EN pin is recommended. 2ms (max) after the chip has been enabled, the SVID circuitry will be ready. All the protection latches (OVP, OCP, UVP) will be cleared only by VCC. The condition of VEN = low will not clear these latches. Figure 8 and Figure 9 show the POR detection and the timing chart for POR process, respectively. Under-Voltage Lockout (UVLO) During normal operation, if the voltage at the VCC pin drops below POR threshold 3.86V (min), the VR triggers UVLO. The UVLO protection forces all high-side MOSFETs and low-side MOSFETs off by shutting down internal PWM logic drivers. VCC 5V 3.86V EN VTT 1.05V Chip Enable CP - Figure 8. POR Detection POR EN VREF 80µA RNTC 2ms SVID Invalid Valid Invalid R1 Figure 9. Timing Chart for POR Process + POR - + 0.7V CP VCC VR_HOT TSEN + R3 R2 1.092V Figure 7. VR_HOT Circuit Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT3601EA Switching Frequency Setting The RT3601EA is one kind of constant on-time control. The patented CCRCOT (Constant Current Ripple COT) technology can generate an adaptive on-time with input voltage and VID code to obtain a constant current ripple, so that the output voltage ripple can be controlled nearly like a constant as different input and output voltages change. The Ton equation can be classified as below two regions. VDAC 0.9 TON 26.2 VDAC 15n k TON (VIN 0.9) 0.3 < VDAC 0.9 TON 23.6 15n k TON (VIN VDAC ) where kTON is a coefficient which can be selected by SET2, as shown in Table 3. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 24 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Table 2. SET1 Pin Setting for ICCMAX and AI Gain VSET1 VREF R2 R1 R2 Min Typical Max Unit 3.75 25 46.25 mV 2 (OCP = 6x) 54.25 75 95.75 mV 4 (OCP = 6x) 104.75 125 145.25 mV 6 (OCP = 6x) 155.25 175 194.75 mV 8 (OCP = 6x) 205.75 225 244.25 mV 10 (OCP = 4x) 256.25 275 293.75 mV 12 (OCP = 4x) 306.75 325 343.25 mV 14 (OCP = 4x) 357.25 375 392.75 mV 407.75 425 442.25 mV 458.25 475 491.75 mV 20 (OCP = 3x) 508.75 525 541.25 mV 22 (OCP = 3x) 559.25 575 590.75 mV 24 (OCP = 3x) 609.75 625 640.25 mV 26 (OCP = 2x) 660.25 675 689.75 mV 28 (OCP = 2x) 710.75 725 739.25 mV 30 (OCP = 2x) 761.25 775 788.75 mV 32 (OCP = 2x) 811.75 825 838.25 mV 2 (OCP = 6x) 862.25 875 887.75 mV 4 (OCP = 6x) 912.75 925 937.25 mV 6 (OCP = 6x) 963.25 975 986.75 mV 8 (OCP = 6x) 1013.75 1025 1036.25 mV 10 (OCP = 4x) 1064.25 1075 1085.75 mV 12 (OCP = 4x) 1114.75 1125 1135.25 mV 14 (OCP = 4x) 1165.25 1175 1184.75 mV 1215.75 1225 1234.25 mV 1266.25 1275 1283.75 mV 20 (OCP = 3x) 1316.75 1325 1333.25 mV 22 (OCP = 3x) 1367.25 1375 1382.75 mV 24 (OCP = 3x) 1417.75 1425 1432.25 mV 26 (OCP = 2x) 1468.25 1475 1481.75 mV 28 (OCP = 2x) 1518.75 1525 1531.25 mV 30 (OCP = 2x) 1569.25 1575 1580.75 mV 32 (OCP = 2x) AI Gain 20 80 ICCMAX (A) 16 (OCP = 4x) 18 (OCP = 3x) 16 (OCP = 4x) 18 (OCP = 3x) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 25 RT3601EA Table 3. SET2 Pin Setting for kTON and OCS VSET2 VREF R2 R1 R2 Min Typical Max Unit 3.75 25 46.25 mV 54.25 75 95.75 mV 104.75 125 145.25 mV 155.25 175 194.75 mV 180 205.75 225 244.25 mV 120 256.25 275 293.75 mV 306.75 325 343.25 mV 357.25 375 392.75 mV 180 407.75 425 442.25 mV 120 458.25 475 491.75 mV 508.75 525 541.25 mV 559.25 575 590.75 mV 180 609.75 625 640.25 mV 120 660.25 675 689.75 mV 710.75 725 739.25 mV 761.25 775 788.75 mV 180 811.75 825 838.25 mV 120 862.25 875 887.75 mV 912.75 925 937.25 mV 963.25 975 986.75 mV 180 1013.75 1025 1036.25 mV 120 1064.25 1075 1085.75 mV 1114.75 1125 1135.25 mV 1165.25 1175 1184.75 mV 180 1215.75 1225 1234.25 mV 120 1266.25 1275 1283.75 mV 1316.75 1325 1333.25 mV 1367.25 1375 1382.75 mV 180 1417.75 1425 1432.25 mV 120 1468.25 1475 1481.75 mV 1518.75 1525 1531.25 mV 1569.25 1575 1580.75 mV Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 26 TONSET (kTON) OCS (%) 120 15 13 12 11 10 9 8 7 140 160 140 160 140 160 140 160 140 160 140 160 140 160 140 160 180 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA For better efficiency of the given load range, the maximum switching frequency is suggested to be : FSW(MAX) VID1 IccTDC DCR RON_LS,max RLL VIN(MAX) IccTDC RON_LS,max RON_HS,max TON TD TON,VAR IccTDC RON_LS,max TD where FSW(MAX) is the maximum switching frequency, VID1 is the typical VID of application, VIN(MAX) is the maximum application input voltage, IccTDC is the thermal design current of application. The RON_HS,max is the maximum equivalent high-side RDS(ON), RON_LS,max is the maximum equivalent low-side RDS(ON). TD is the summation of the high-side MOSFET delay time and the rising time, TON, VAR is the TON variation value. DCR is the inductor DCR, and RLL is the loadline setting. In addition, Richtek provides a Microsoft Excel-based spreadsheet to help design the RTON for RT3601EA. When load increases, on-time keeps constant. The offtime width will be reduced so that loading can load more power from input terminal to regulate output voltage. Hence, the loading current usually increases in case the switching frequency also increases. Higher switching frequency operation can reduce power components' size and PCB space, trading off the whole efficiency since switching related loss increases, vice versa. IMON RIMON GM + RCS LX DCR Rx Cx ISENP ISENN - VREF Figure 10. Lossless Current Sense Method for Single Phase VCORE R x Cx = Lx DCR IOUT x RLL IOUT IOUT Expected load transient waveform VCORE R x Cx < Current Sense In the RT3601EA, the current signal is used for load-line setting and over-current protection (OCP). The inductor current sense method adopts the lossless current sensing for allowing high efficiency as illustrated in Figure 10. If RC network time constant matches inductor time constant Lx/DCR, an expected load transient waveform can be designed. If RxCx network time constant is larger than inductor time constant Lx/DCR, VCORE waveform has a sluggish droop during load transient. If RxCx network is smaller than inductor time constant Lx/DCR, a worst VCORE waveform will sag to create an undershooting to fail the specification. Figure 11 shows the variety RxCx constant corresponding to the output waveforms. VCORE ILx Lx DCR IOUT x RLL IOUT IOUT Undershoot created in VCORE VCORE R x Cx > Lx DCR IOUT x RLL IOUT IOUT Sluggish droop Figure 11. All Kind of RxCx Constants Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 27 RT3601EA Thermal Compensation for Current Sense Next, let Since the copper wire of inductor has a positive temperature coefficient. And hence, temperature compensation is necessary for the lossless inductor current sense. For single phase thermal compensation, Figure 12. shows a not only simple but also effective way to compensate temperature variation. An NTC thermistor is put in the current sensing network and it can be used to compensate DCR variation due to temperature is changed. VCORE ILx LX DCR RX CX Rs GM VIMON IMON + RCS RIMON ISENxP m LX DCR C X Then R RP RNTC RP m R X RS NTC R X RS R R R NTC P NTC RP Step1 : Given the two system temperature TR and TH at which are compensated. Step2 : Two equations can be listed as R (T ) RP R (T ) RP m(TR ) R X RS NTC R R X RS NTC R RNTC (TR ) RP RNTC (TR ) RP Rp RNTC ISENxN - VREF R (T ) RP m(TH ) R X RS NTC H RNTC (TH ) RP RNTC (TH ) RP R X RS R NTC (TH ) RP Step3 : Usually RP is set to equal to RNTC (TR). And hence, there are two equations and two unknowns, RX and RS can be found out. Current Monitor, IMON Figure 12. Thermal Compensation method for Single Phase The current sense network equation is as follows : ILX DCR VIMON VIMON VREF RS RP //RNTC RX RS RP //RNTC RIMON RCS Usually, RP is set equal to RNTC ( 25°C). RS is selected to linearize the NTC’s temperature characteristic. For a given NTC, design is to get RX and RS to compensate the temperature variation of the sense resistor. Let REQU RS RP //RNTC According to current sense network, the corresponding equation is represented as follows : RT3601EA includes a current monitor (IMON) function which can be used to detect over-current protection and maximum processor current ICCMAX, and also sets a part of current gain in the load-line setting. It produces an analog voltage proportional to output current between the IMON and VREF pins. Load-Line (Droop) Setting The G-NAVPTM topology can set load-line (droop) via the current loop and voltage loop, the load-line is a slope between load current ICC and output voltage Vsen as shown in Figure 13. Figure 14 shows the voltage control and current loop. By using both loops, the load-line (droop) can be set easily. The load-line set equation is : k i DCR R k i DCR OUT 2 RCS AI RLL 2 (m ) AV R2 R2 R1 R1 where ROUT = RCS R RX LX C X EQU DCR REQU R X Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 28 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA VCOEE C2 C1 Load line slope = -RLL R2 - R1 RLL x ICC + VID ICC Figure 13. Load-Line (Droop) VSEN Differential Remote Sense Setting R2 Voltage Loop TON Generator - R1 + + - IL LX CX RX VID ki/2 - + DCR ISENP + GM RCS ISENN 1 Figure 15. Type I compensator ROUT 1 IMONA Current Loop VREF The VR provides differential remote-sense inputs to eliminate the effects of voltage drops along the PC board traces, CPU internal power routes and socket contacts for Main and AUXI rails. The CPU contains on-die sense pins, V CC_SENSE and V SS_SENSE . Connect RGND to VSS_SENSE and connect FB to VCC_SENSE with a resistor to build the negative input path of the error amplifier as shown in Figure 16. The VDAC and the precision voltage reference are referred to RGND for accurate remote sensing. RIMON CPU VCC_SENSE VOUT Compensator Design The compensator of RT3601EA doesn't need a complex type II or type III compensator to optimize control loop performance. It can adopt a simple type I compensator (one pole, one zero) in the G-NAVPTM topology to achieve constant output impedance design for Intel IMVP8 ACLL specification. The one pole one zero compensator is shown as Figure 15. The transfer function of compensator should be design as following transfer function to achieve constant output impedance, i.e. Zo(s) = load-line slope in the entire frequency range : FB EA + VID + Figure 14. Voltage Loop and Current Loop RGND R1 COUT R2 CPU VSS_SENSE Figure 16. Remote Sensing Circuit Maximum Processor Current Setting, ICCMAX The maximum processor current ICCMAX can be set by SET1 pin. ICCMAX register is set by an external voltage divider with the multi-function mechanism. Table 2 shows the ICCMAX setting on SET1 pin. s 1 AI fsw GCON (S) RLL 1 s ESR where AI is current loop gain, RLL is load-line, fSW is switching frequency and ωESR is a pole that should be located at 1/(COUT x ESR). Then, the C1 and C2 should be designed as follows : C ESR 1 C1 = C2 = OUT R1 fSW R2 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 29 RT3601EA Table 4. SET1 Pin Setting for PSYS and DVID_Width VSET1 = 80μA x R1 x R2 R1 + R2 PSYS DVID_Width (s) Min Typical Max Unit 5.5 100 194.5 mV Enable 5.36 209.5 300 390.5 mV Enable 4.69 413.5 500 586.5 mV Enable 2.68 617.5 700 782.5 mV Enable 2.01 821.5 900 978.5 mV Disable 5.36 1025.5 1100 1174.5 mV Disable 4.69 1229.5 1300 1370.5 mV Disable 2.68 1433.5 1500 1566.5 mV Disable 2.01 Table 5. TSEN Setting for DVID_TH and VBOOT VTSEN VREF R2 R1 R2 DVID_TH (mV) VBOOT (V) Min Typical Max Unit 4 50 96 mV 105 150 195 mV 206 250 294 mV 307 350 393 mV 1.35 408 450 492 mV 0 509 550 591 mV 610 650 690 mV 711 750 789 mV 1.35 812 850 888 mV 0 913 950 987 mV 1014 1050 1086 mV 1115 1150 1185 mV 1.35 1216 1250 1284 mV 0 1317 1350 1383 mV 1418 1450 1482 mV 1519 1550 1581 mV 0 15 30 60 Disable 1.05 1.2 1.05 1.2 1.05 1.2 1.05 1.2 1.35 Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 30 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Dynamic VID (DVID) Compensation When VID transition event occurs, a charge current will be generated in the loop to cause DVID performance is deteriorated by this induced charge current, the phenomenon is called droop effect. The droop effect is shown in Figure 17. When VID up transition occurs, the output capacitor will be charged by inductor current. Since current signal is sensed in inductor, an induced charge current will appear in control loop. The induced charge current will produce a voltage drop in R1 to cause output voltage to have a droop effect. Due to this, VID transition performance will be deteriorated. The RT3601EA provides a DVID compensation function. By the DVID compensation to cancel the real induced charge current signal and the virtual charge current signal is defined in Figure 18. Figure 19 shows the operation of cancelling droop effect. A virtual charge current signal is established first and then VID signal plus virtual charge current signal to be generated on the FB pin. Hence, an induced charge current signal flows to R1 and is cancelled to reduce droop effect. DVID_Width DVID_Threshold Charge current L VIN Q1 Gate Driver CO1 Q2 CO2 RESR Figure 18. Definition of Virtual Charge Current Signal CPU Ai Induced charge current signal C2 R2 CCRCOT VIN VID tON Output voltage C1 COMP + R1 EA + IDROOP VID VID Transition Figure 17. Droop Effect in VID transition Charge current VIN L Q1 Gate Driver CO1 Q2 CO2 RESR Ai Induced charge current signal Output voltage CPU C2 C1 R2 CCRCOT COMP - VIN VID tON + IDROOP R1 EA + Virtual Charge Current + DVID Event Slew Rate Control VID VID Transition Virtual Charge Current Generator Figure 19. DVID Compensation Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 31 RT3601EA Table 4 and Table 5 show the DVID width, DVID threshold, PSYS function and VBOOT on SET1 and TSEN. For example, 15mV DVID threshold and 2.68μs DVID width are designed (VBOOT set as 1.05V, PSYS function is disable) . According to the Table 4 adn Table 5, the DVID threshold set voltage should be between 0.1286V and 0.1316V and DVID width set voltage should be between 0.1351V to 0.1651V. Please note that a high accuracy resistor is needed for this setting, <1% error tolerance is recommended. Ramp Compensation The G-NAVPTM topology is one type of ripple based control that has fast transient response and can lower BOM cost. However, ripple based control usually has no good noise immunity. The RT3601EA provides the ramp compensation to increase noise immunity and reduce jitter at the switching node. Figure 20 shows the ramp compensation. Noise Margin w/o ramp compensation IMON-VREF VCOMP Noise Margin w/ ramp compensation QR Width VCORE QR Threshold PWM1 PWM2 Load Figure 21. Quick Response Mechanism The output voltage signal behavior needs to be detected so that QR mechanism can be trigged. The output voltage signal is via a remote sense line to connect at the VSEN pin which is shown in Figure 22. The QR mechanism needs to set QR width and QR threshold. Both definitions are shown in Figure 21. A proper QR mechanism set can meet different applications. The SET3 pin can set QR threshold and QR width by an external voltage divider with the multifunction mechanism. Table 6 shows the QR_TH and QR_WIDTH on the SET3 pin. IMON-VREF VCOMP Figure 20. Ramp Compensation Quick Response (QR) Mechanism QR Pulse Generation Circuit +- + COM VSEN QR threshold + - Figure 22. Simplified QR Trigger schematic When the transient load step-up becomes quite large, it is difficult for loop response to meet the energy transfer. Hence, that output voltage generate undershoot to fail specification. The RT3601EA has Quick Response (QR) mechanism being able to improve this issue. It adopts a nonlinear control mechanism which can disable interleaving function and simultaneously turn on all UGATE one pulse at instantaneous step-up transient load to restrain the output voltage drooping. Figure 21 shows the QR behavior. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 32 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Table 6. SET3 Pin Setting for QR Threshold and QR Width VSET3 VREF R2 R1 R2 QR_TH (mV) Min Typical Max Unit 3.75 25 46.25 mV 54.25 104.75 75 125 95.75 145.25 mV mV 155.25 205.75 175 225 194.75 244.25 mV mV 256.25 275 293.75 mV 306.75 325 343.25 mV PS0 PS1 QR_WIDTH (% of On-Time) 160% Disable Disable 130% 100% 70% 160% 10 10 130% 100% 357.25 375 392.75 mV 70% 407.75 458.25 425 475 442.25 491.75 mV mV 160% 130% 508.75 559.25 525 575 541.25 590.75 mV mV 609.75 660.25 625 675 640.25 689.75 mV mV 710.75 725 739.25 mV 761.25 775 788.75 mV 70% 811.75 862.25 825 875 838.25 887.75 mV mV 160% 130% 912.75 925 937.25 mV 963.25 1013.75 975 1025 986.75 1036.25 mV mV 1064.25 1075 1085.75 mV 1114.75 1125 1135.25 mV 1165.25 1215.75 1175 1225 1184.75 1234.25 mV mV 1266.25 1316.75 1275 1325 1283.75 1333.25 mV mV 1367.25 1417.75 1375 1425 1382.75 1432.25 mV mV 1468.25 1475 1481.75 mV 1518.75 1569.25 1525 1575 1531.25 1580.75 mV mV 15 20 25 15 20 25 100% 70% 160% 130% 100% 100% 70% 160% 30 30 130% 100% 70% 160% 35 35 130% 100% 70% 160% 40 40 130% 100% 70% Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 33 RT3601EA For example, 20mV QR threshold and 0.7 x TON QR width are set. According to Table 6, the set voltage should be between 0.7607V and 0.7907V. Please note that a high accuracy resistor is needed for this setting accuracy, <1% error tolerance is recommended. Zero Load-Line Setting and Anti-overshoot function The SET2 pin can be enabled/disabled zero load-line function and can be enabled/disabled anti-overshoot function. Table 7 and Table 8 show the zero load-line function, anti-overshoot function, IPSK and anti-overshoot threshold on SET2 pin and SET3 pin. When DVID slew rate increases, loop response is difficult to meet energy transfer so that output voltage generates overshoot to fail specification. The RT3601EA has antiovershoot function being able to help improve this issue. The VR will turn off low-side MOSFET when output voltage ramps up to the target VID (ALERT signal be pulled low). This function also can improve the overshoot during the load transient condition. When anti-overshoot function is triggered, the UGATE and LGATE signal will be masked to reduce the overshoot amplitude. Table 7. SET2 Pin Setting for Anti-Overshoot and Zero Load-Line VSET2 80μA R1 R2 R1 R2 VR Zero Load-Line Address Min Typical Max Unit 4.5 50 95.5 mV 106.5 150 193.5 mV 208.5 250 291.5 mV 310.5 350 389.5 mV 412.5 450 487.5 mV 514.5 550 585.5 mV 616.5 650 683.5 mV 718.5 750 781.5 mV 820.5 850 879.5 mV 922.5 950 977.5 mV 1024.5 1050 1075.5 mV 1126.5 1150 1173.5 mV 1228.5 1250 1271.5 mV 1330.5 1350 1369.5 mV 1432.5 1450 1467.5 mV 1534.5 1550 1565.5 mV Disable 00 Enable Disable 01 Enable Disable 02 Enable Disable 03 Enable ANTIOVS Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 34 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Table 8. SET3 Pin Setting for IPSK and ANTIOVS_TH VSET3 80μA R1 R2 R1 R2 IPSK ANTIOVS_TH(mV) Min Typical Max Unit 4.5 50 95.5 mV 106.5 150 193.5 mV 208.5 250 291.5 mV 310.5 350 389.5 mV 40 412.5 450 487.5 mV 10 514.5 550 585.5 mV 616.5 650 683.5 mV 718.5 750 781.5 mV 40 820.5 850 879.5 mV 10 922.5 950 977.5 mV 1024.5 1050 1075.5 mV 1126.5 1150 1173.5 mV 40 1228.5 1250 1271.5 mV 10 1330.5 1350 1369.5 mV 1432.5 1450 1467.5 mV 1534.5 1550 1565.5 mV 10 150mV / Avgain 100mV / Avgain 50V / Avgain 0mV / Avgain 20 30 20 30 20 30 20 30 40 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 35 RT3601EA Over-Current Protection Under-Voltage Protection The RT3601EA has dual OCP mechanism. One is named SUM-OCP, the other is called per phase OC. The over current protection (OCP) forces high-side MOSFET and low-side MOSFET off by shutting down internal PWM logic drivers. RT3601EA provides SUM-OCP which is 160% of IMON_04. IMON_04 is the current that makes VIMON − VREF = 0.4. When output current is higher than the SUM-OCP threshold, SUM-OCP is latched with a 40μs delay time to prevent false trigger. Besides, the SUM-OCP function is masked when dynamic VID transient occurs and after dynamic VID transition, SUM-OCP is masked for 80μs. The other one is SPIKE-OCP which should trip when the output current exceeds per phase OC threshold during first DVID. Per phase OC threshold is dependent on IMAX level as shown in Table 2. When output current is higher than the per phase OC threshold, SPIKE-OCP is latched with a 0.5μs delay time to prevent false trigger. When the VSEN pin voltage is 350mV less than VID, UVP will be latched. When UVP latched, the both UGATEx and LGATEx are pulled low. A 3μs delay is used in UVP detection circuit to prevent false trigger. Besides, the UVP function is masked when dynamic VID transient occurs and after dynamic VID transition, UVP is masked for 80μs. Design Step : RT3601EA Excel based design tool is available. Users can contact your Richtek representative to get the spreadsheet. Three main design procedures of RT3601EA design, first step is loop design, second step is pin setting design, and the last step is protection settings. The following design example is to explain RT3601EA design procedure : Specification Input Voltage 19V No. of Phase 1 Normal VID 1.3V ICCMAX 22A Load-Line 6m Fast Slew Rate MAX Switching Frequency 33.75mV/s Output Over-Voltage Protection There are two conditions for OVP. Oneis when VSEN is respect to VID voltage. The other is when VSEN is lower limit to 1V. For VSEN is respect to VID voltage, OVP condition is detected when VSEN pin is 350mV more than VID. For VSEN is lower limit to 1V, OVP is occurred when VSEN is higher than 1V. When OVP is detected, the highside gate voltage UGATEx is pulled low and the low-side gate voltage LGATEx is pulled high. OVP is latched with a 0.5us delay- to prevent false trigger. 600kHz The output filter requirements of VRTB specification are as follows : Output Inductor : 0.22μH/0.875mΩ Negative Voltage Protection Output Ceramic Capacitor : 396μF (18pcs) Since the OVP latch continuously turns on all low-side MOSFETs of the VR, the VR will suffer negative output voltage. When the VSEN detects a voltage below −0.05V after triggering OVP, the VR triggers NVP to turn off all low-side MOSFETs of the VR while the high-side MOSFETs remain off. After triggering NVP, if the output voltage rises above 0V, the OVP latch restarts to turn on all low-side MOSFETs. Therefore, the output voltage may bounce between 0V and −0.05V due to OVP latch and NVP triggering. The NVP function will be active only after OVP is triggered. Loop Design : Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 36 On time setting: Using the specification, then can get that TON is 160ns. The kTON parameter can be calculated after the on-time is decided. TON 26.2μ VDAC 15n k TON (VIN 0.9) is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA 22A. The PSYS function is decided to Enable and DVID width is set to 5.36μs. By using the information, the two equation can be listed by using multi-function pin setting mechanism : Choosing the nearest on-time setting kTON = 13 Current sensor adopts lossless RC filter to sense current signal in DCR. For getting an expected load transient waveform RXCX time constant needs to match LX/DCR. CX = 0.47μF, RNTC = 4.7kΩ and RP = 4.7kΩ are set, then 3.2 REQU RS RP //RNTC 80μ R RX LX C X EQU DCR REQU R X R1 = 3.01kΩ and R2 = 2.13kΩ. By using the design tool, RS and RX can be determined, are equal to 845Ω and 768Ω, respectively. IMON resistor network design : RIMON ∆VIMON 2.15k 58k REQU ICCMAX DCR R X REQU Load-line design : 6mΩ droop is requirement, because DCR and ki are decided to 0.875mΩ and 80, respectively (ki = AI Gain). The voltage loop Av gain is also can be determined by following equation : RLL ki DCR AI 2 AV R2 R1 R2 225.22mV R1 R2 80μ SET3 resistor network design : From above designs, the QR_TH is set to 20mV and QR width is designed as 0.7 x TON. The IPSK is set to 100mV/Avgain and ANTIOVS_TH is set to 20mV. By using the information, the two equation can be listed by using multi-function pin setting mechanism : R2 775.75mV R1 R2 C1 1 270pF R1 π FSW 3.2 C2 COUT ESR 47pF R2 80μ Pin Setting Design : R1 R2 150.14mV R1 R2 R1 = 26.66kΩ and R2 = 2.01kΩ. Typical compensator design can use the following equations to design C1 and C2 values For Intel platform, in order to induce the band width to enhance transient performance to meet Intel's criterion, the zero location can be designed close to 1/10 of the switching frequency or less than the 1/10 of switching frequency. R1 R2 100.09mV R1 R2 SET2 resistor network design : From above designs, parameters of kTON is 13. The OCP threshold is designed as 1.2 x ICCMAX. The zero load-line function is decided to disable and anti-overshoot is decided to enable. The VR address is set to 0. By using the information, the two equation can be listed by using multi-function pin setting mechanism: 3.2 R1 = 10kΩ is usually decided and here R2 is chosen to 47kΩ. R2 1326.29mV R1 R2 R1 R2 550.53mV R1 R2 R1 = 28.38kΩ and R2 = 9.08kΩ. TSEN resistor network design : The DIVD threshold is 30mV and the Boot voltage is set to 0V. By using the information, the equation can be shown as below : 3.2 R2 450.44mV R1 R2 SET1 resistor network design: From above designs, parameter of AI Gain is 80. The ICCMAX is designed as Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3601EA-00 June 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 37 RT3601EA OVP/UVP protections: When the VSEN pin voltage is 350mV higher than VID, the OVP will be latched. When the VSEN pin voltage is 350mV lower than VID, the UVP will be latched. TSEN and VR_HOT design : Using the following equation to calculate related resistances for VR_HOT setting. VTSEN 80μ (R3 //RNTC ) (R1 //R2 ) NTC thermistor RNTC (25°C) = 100kΩ and its β = 4485. When temperature is 100°C, the RNTC (90°C) = 6.75kΩ. According to TSEN pins for multi-function mechanism, three equations can be got as following for Main VR rail : VTSEN (25oC) 80μ (R3 //RNTC (25oC) ) (R1 //R2 ) 1.624V VTSEN (90oC) 80μ (R3 //RNTC (100oC) ) (R1 //R2 ) 1.092V 3.2 R2 450.44mV R1 R2 R1 = 54.83kΩ, R2 = 8.98kΩ and R3 = 48.7kΩ. The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 23 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 5.0 Maximum Power Dissipation (W)1 Protection Settings : Four-Layer PCB 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 23. Derating Curve of Maximum Power Dissipation Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-28L 4x4 package, the thermal resistance, θJA, is 28.5°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (28.5°C/W) = 3.5W for WQFN-28L 4x4 package Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 38 is a registered trademark of Richtek Technology Corporation. DS3601EA-00 June 2016 RT3601EA Outline Dimension D2 D SEE DETAIL A L 1 E E2 e Symbol A3 2 2 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 3.900 4.100 0.154 0.161 D2 2.350 2.450 0.093 0.096 E 3.900 4.100 0.154 0.161 E2 2.350 2.450 0.093 0.096 e L 1 DETAIL A Pin #1 ID and Tie Bar Mark Options b A A1 1 0.400 0.350 0.016 0.450 0.014 0.018 W-Type 28L QFN 4x4 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS3601EA-00 June 2016 www.richtek.com 39