Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W5x7.35
35 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP 0.4mm Pitch)
Rev 0, 11/14
0.400
X
Y
2.14±0.030
G
F
35x0.265±0.035
E
D
2.88 ±0.030
C
B
0.240
A
(4X)
0.10
1
TOP VIEW
2
3
4
5
0.005
PIN 1 (A1 CORNER)
0.275
0.265
BOTTOM VIEW
Z
0.240
0.05 Z
PACKAGE OUTLINE
SEATING PLANE
3
0.290
2
0.265±0.035
0.10
0.05
0.400
4
6 NSMD
0.200±0.030
RECOMMENDED LAND PATTERN
0.500±0.050
SIDE VIEW
NOTES:
1. Dimensions and tolerance per ASME Y 14.5M - 1994.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z .
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
5. All dimensions are in millimeters.
6. NSMD refers to non-solder mask defined pad design per Intersil Techbrief TB451.
1
ZXY
Z